qla_mr.c 90 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483
  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/delay.h>
  9. #include <linux/pci.h>
  10. #include <linux/ratelimit.h>
  11. #include <linux/vmalloc.h>
  12. #include <scsi/scsi_tcq.h>
  13. #include <linux/utsname.h>
  14. /* QLAFX00 specific Mailbox implementation functions */
  15. /*
  16. * qlafx00_mailbox_command
  17. * Issue mailbox command and waits for completion.
  18. *
  19. * Input:
  20. * ha = adapter block pointer.
  21. * mcp = driver internal mbx struct pointer.
  22. *
  23. * Output:
  24. * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
  25. *
  26. * Returns:
  27. * 0 : QLA_SUCCESS = cmd performed success
  28. * 1 : QLA_FUNCTION_FAILED (error encountered)
  29. * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
  30. *
  31. * Context:
  32. * Kernel context.
  33. */
  34. static int
  35. qlafx00_mailbox_command(scsi_qla_host_t *vha, struct mbx_cmd_32 *mcp)
  36. {
  37. int rval;
  38. unsigned long flags = 0;
  39. device_reg_t __iomem *reg;
  40. uint8_t abort_active;
  41. uint8_t io_lock_on;
  42. uint16_t command = 0;
  43. uint32_t *iptr;
  44. uint32_t __iomem *optr;
  45. uint32_t cnt;
  46. uint32_t mboxes;
  47. unsigned long wait_time;
  48. struct qla_hw_data *ha = vha->hw;
  49. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  50. if (ha->pdev->error_state > pci_channel_io_frozen) {
  51. ql_log(ql_log_warn, vha, 0x115c,
  52. "error_state is greater than pci_channel_io_frozen, "
  53. "exiting.\n");
  54. return QLA_FUNCTION_TIMEOUT;
  55. }
  56. if (vha->device_flags & DFLG_DEV_FAILED) {
  57. ql_log(ql_log_warn, vha, 0x115f,
  58. "Device in failed state, exiting.\n");
  59. return QLA_FUNCTION_TIMEOUT;
  60. }
  61. reg = ha->iobase;
  62. io_lock_on = base_vha->flags.init_done;
  63. rval = QLA_SUCCESS;
  64. abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  65. if (ha->flags.pci_channel_io_perm_failure) {
  66. ql_log(ql_log_warn, vha, 0x1175,
  67. "Perm failure on EEH timeout MBX, exiting.\n");
  68. return QLA_FUNCTION_TIMEOUT;
  69. }
  70. if (ha->flags.isp82xx_fw_hung) {
  71. /* Setting Link-Down error */
  72. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  73. ql_log(ql_log_warn, vha, 0x1176,
  74. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  75. rval = QLA_FUNCTION_FAILED;
  76. goto premature_exit;
  77. }
  78. /*
  79. * Wait for active mailbox commands to finish by waiting at most tov
  80. * seconds. This is to serialize actual issuing of mailbox cmds during
  81. * non ISP abort time.
  82. */
  83. if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
  84. /* Timeout occurred. Return error. */
  85. ql_log(ql_log_warn, vha, 0x1177,
  86. "Cmd access timeout, cmd=0x%x, Exiting.\n",
  87. mcp->mb[0]);
  88. return QLA_FUNCTION_TIMEOUT;
  89. }
  90. ha->flags.mbox_busy = 1;
  91. /* Save mailbox command for debug */
  92. ha->mcp32 = mcp;
  93. ql_dbg(ql_dbg_mbx, vha, 0x1178,
  94. "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
  95. spin_lock_irqsave(&ha->hardware_lock, flags);
  96. /* Load mailbox registers. */
  97. optr = (uint32_t __iomem *)&reg->ispfx00.mailbox0;
  98. iptr = mcp->mb;
  99. command = mcp->mb[0];
  100. mboxes = mcp->out_mb;
  101. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  102. if (mboxes & BIT_0)
  103. WRT_REG_DWORD(optr, *iptr);
  104. mboxes >>= 1;
  105. optr++;
  106. iptr++;
  107. }
  108. /* Issue set host interrupt command to send cmd out. */
  109. ha->flags.mbox_int = 0;
  110. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  111. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1172,
  112. (uint8_t *)mcp->mb, 16);
  113. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1173,
  114. ((uint8_t *)mcp->mb + 0x10), 16);
  115. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1174,
  116. ((uint8_t *)mcp->mb + 0x20), 8);
  117. /* Unlock mbx registers and wait for interrupt */
  118. ql_dbg(ql_dbg_mbx, vha, 0x1179,
  119. "Going to unlock irq & waiting for interrupts. "
  120. "jiffies=%lx.\n", jiffies);
  121. /* Wait for mbx cmd completion until timeout */
  122. if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
  123. set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  124. QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
  125. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  126. wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ);
  127. } else {
  128. ql_dbg(ql_dbg_mbx, vha, 0x112c,
  129. "Cmd=%x Polling Mode.\n", command);
  130. QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
  131. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  132. wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
  133. while (!ha->flags.mbox_int) {
  134. if (time_after(jiffies, wait_time))
  135. break;
  136. /* Check for pending interrupts. */
  137. qla2x00_poll(ha->rsp_q_map[0]);
  138. if (!ha->flags.mbox_int &&
  139. !(IS_QLA2200(ha) &&
  140. command == MBC_LOAD_RISC_RAM_EXTENDED))
  141. usleep_range(10000, 11000);
  142. } /* while */
  143. ql_dbg(ql_dbg_mbx, vha, 0x112d,
  144. "Waited %d sec.\n",
  145. (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
  146. }
  147. /* Check whether we timed out */
  148. if (ha->flags.mbox_int) {
  149. uint32_t *iptr2;
  150. ql_dbg(ql_dbg_mbx, vha, 0x112e,
  151. "Cmd=%x completed.\n", command);
  152. /* Got interrupt. Clear the flag. */
  153. ha->flags.mbox_int = 0;
  154. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  155. if (ha->mailbox_out32[0] != MBS_COMMAND_COMPLETE)
  156. rval = QLA_FUNCTION_FAILED;
  157. /* Load return mailbox registers. */
  158. iptr2 = mcp->mb;
  159. iptr = (uint32_t *)&ha->mailbox_out32[0];
  160. mboxes = mcp->in_mb;
  161. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  162. if (mboxes & BIT_0)
  163. *iptr2 = *iptr;
  164. mboxes >>= 1;
  165. iptr2++;
  166. iptr++;
  167. }
  168. } else {
  169. rval = QLA_FUNCTION_TIMEOUT;
  170. }
  171. ha->flags.mbox_busy = 0;
  172. /* Clean up */
  173. ha->mcp32 = NULL;
  174. if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
  175. ql_dbg(ql_dbg_mbx, vha, 0x113a,
  176. "checking for additional resp interrupt.\n");
  177. /* polling mode for non isp_abort commands. */
  178. qla2x00_poll(ha->rsp_q_map[0]);
  179. }
  180. if (rval == QLA_FUNCTION_TIMEOUT &&
  181. mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
  182. if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
  183. ha->flags.eeh_busy) {
  184. /* not in dpc. schedule it for dpc to take over. */
  185. ql_dbg(ql_dbg_mbx, vha, 0x115d,
  186. "Timeout, schedule isp_abort_needed.\n");
  187. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  188. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  189. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  190. ql_log(ql_log_info, base_vha, 0x115e,
  191. "Mailbox cmd timeout occurred, cmd=0x%x, "
  192. "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
  193. "abort.\n", command, mcp->mb[0],
  194. ha->flags.eeh_busy);
  195. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  196. qla2xxx_wake_dpc(vha);
  197. }
  198. } else if (!abort_active) {
  199. /* call abort directly since we are in the DPC thread */
  200. ql_dbg(ql_dbg_mbx, vha, 0x1160,
  201. "Timeout, calling abort_isp.\n");
  202. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  203. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  204. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  205. ql_log(ql_log_info, base_vha, 0x1161,
  206. "Mailbox cmd timeout occurred, cmd=0x%x, "
  207. "mb[0]=0x%x. Scheduling ISP abort ",
  208. command, mcp->mb[0]);
  209. set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  210. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  211. if (ha->isp_ops->abort_isp(vha)) {
  212. /* Failed. retry later. */
  213. set_bit(ISP_ABORT_NEEDED,
  214. &vha->dpc_flags);
  215. }
  216. clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  217. ql_dbg(ql_dbg_mbx, vha, 0x1162,
  218. "Finished abort_isp.\n");
  219. }
  220. }
  221. }
  222. premature_exit:
  223. /* Allow next mbx cmd to come in. */
  224. complete(&ha->mbx_cmd_comp);
  225. if (rval) {
  226. ql_log(ql_log_warn, base_vha, 0x1163,
  227. "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, "
  228. "mb[3]=%x, cmd=%x ****.\n",
  229. mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
  230. } else {
  231. ql_dbg(ql_dbg_mbx, base_vha, 0x1164, "Done %s.\n", __func__);
  232. }
  233. return rval;
  234. }
  235. /*
  236. * qlafx00_driver_shutdown
  237. * Indicate a driver shutdown to firmware.
  238. *
  239. * Input:
  240. * ha = adapter block pointer.
  241. *
  242. * Returns:
  243. * local function return status code.
  244. *
  245. * Context:
  246. * Kernel context.
  247. */
  248. static int
  249. qlafx00_driver_shutdown(scsi_qla_host_t *vha, int tmo)
  250. {
  251. int rval;
  252. struct mbx_cmd_32 mc;
  253. struct mbx_cmd_32 *mcp = &mc;
  254. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1166,
  255. "Entered %s.\n", __func__);
  256. mcp->mb[0] = MBC_MR_DRV_SHUTDOWN;
  257. mcp->out_mb = MBX_0;
  258. mcp->in_mb = MBX_0;
  259. if (tmo)
  260. mcp->tov = tmo;
  261. else
  262. mcp->tov = MBX_TOV_SECONDS;
  263. mcp->flags = 0;
  264. rval = qlafx00_mailbox_command(vha, mcp);
  265. if (rval != QLA_SUCCESS) {
  266. ql_dbg(ql_dbg_mbx, vha, 0x1167,
  267. "Failed=%x.\n", rval);
  268. } else {
  269. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1168,
  270. "Done %s.\n", __func__);
  271. }
  272. return rval;
  273. }
  274. /*
  275. * qlafx00_get_firmware_state
  276. * Get adapter firmware state.
  277. *
  278. * Input:
  279. * ha = adapter block pointer.
  280. * TARGET_QUEUE_LOCK must be released.
  281. * ADAPTER_STATE_LOCK must be released.
  282. *
  283. * Returns:
  284. * qla7xxx local function return status code.
  285. *
  286. * Context:
  287. * Kernel context.
  288. */
  289. static int
  290. qlafx00_get_firmware_state(scsi_qla_host_t *vha, uint32_t *states)
  291. {
  292. int rval;
  293. struct mbx_cmd_32 mc;
  294. struct mbx_cmd_32 *mcp = &mc;
  295. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1169,
  296. "Entered %s.\n", __func__);
  297. mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
  298. mcp->out_mb = MBX_0;
  299. mcp->in_mb = MBX_1|MBX_0;
  300. mcp->tov = MBX_TOV_SECONDS;
  301. mcp->flags = 0;
  302. rval = qlafx00_mailbox_command(vha, mcp);
  303. /* Return firmware states. */
  304. states[0] = mcp->mb[1];
  305. if (rval != QLA_SUCCESS) {
  306. ql_dbg(ql_dbg_mbx, vha, 0x116a,
  307. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  308. } else {
  309. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116b,
  310. "Done %s.\n", __func__);
  311. }
  312. return rval;
  313. }
  314. /*
  315. * qlafx00_init_firmware
  316. * Initialize adapter firmware.
  317. *
  318. * Input:
  319. * ha = adapter block pointer.
  320. * dptr = Initialization control block pointer.
  321. * size = size of initialization control block.
  322. * TARGET_QUEUE_LOCK must be released.
  323. * ADAPTER_STATE_LOCK must be released.
  324. *
  325. * Returns:
  326. * qlafx00 local function return status code.
  327. *
  328. * Context:
  329. * Kernel context.
  330. */
  331. int
  332. qlafx00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
  333. {
  334. int rval;
  335. struct mbx_cmd_32 mc;
  336. struct mbx_cmd_32 *mcp = &mc;
  337. struct qla_hw_data *ha = vha->hw;
  338. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116c,
  339. "Entered %s.\n", __func__);
  340. mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
  341. mcp->mb[1] = 0;
  342. mcp->mb[2] = MSD(ha->init_cb_dma);
  343. mcp->mb[3] = LSD(ha->init_cb_dma);
  344. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  345. mcp->in_mb = MBX_0;
  346. mcp->buf_size = size;
  347. mcp->flags = MBX_DMA_OUT;
  348. mcp->tov = MBX_TOV_SECONDS;
  349. rval = qlafx00_mailbox_command(vha, mcp);
  350. if (rval != QLA_SUCCESS) {
  351. ql_dbg(ql_dbg_mbx, vha, 0x116d,
  352. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  353. } else {
  354. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116e,
  355. "Done %s.\n", __func__);
  356. }
  357. return rval;
  358. }
  359. /*
  360. * qlafx00_mbx_reg_test
  361. */
  362. static int
  363. qlafx00_mbx_reg_test(scsi_qla_host_t *vha)
  364. {
  365. int rval;
  366. struct mbx_cmd_32 mc;
  367. struct mbx_cmd_32 *mcp = &mc;
  368. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116f,
  369. "Entered %s.\n", __func__);
  370. mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
  371. mcp->mb[1] = 0xAAAA;
  372. mcp->mb[2] = 0x5555;
  373. mcp->mb[3] = 0xAA55;
  374. mcp->mb[4] = 0x55AA;
  375. mcp->mb[5] = 0xA5A5;
  376. mcp->mb[6] = 0x5A5A;
  377. mcp->mb[7] = 0x2525;
  378. mcp->mb[8] = 0xBBBB;
  379. mcp->mb[9] = 0x6666;
  380. mcp->mb[10] = 0xBB66;
  381. mcp->mb[11] = 0x66BB;
  382. mcp->mb[12] = 0xB6B6;
  383. mcp->mb[13] = 0x6B6B;
  384. mcp->mb[14] = 0x3636;
  385. mcp->mb[15] = 0xCCCC;
  386. mcp->out_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  387. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  388. mcp->in_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  389. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  390. mcp->buf_size = 0;
  391. mcp->flags = MBX_DMA_OUT;
  392. mcp->tov = MBX_TOV_SECONDS;
  393. rval = qlafx00_mailbox_command(vha, mcp);
  394. if (rval == QLA_SUCCESS) {
  395. if (mcp->mb[17] != 0xAAAA || mcp->mb[18] != 0x5555 ||
  396. mcp->mb[19] != 0xAA55 || mcp->mb[20] != 0x55AA)
  397. rval = QLA_FUNCTION_FAILED;
  398. if (mcp->mb[21] != 0xA5A5 || mcp->mb[22] != 0x5A5A ||
  399. mcp->mb[23] != 0x2525 || mcp->mb[24] != 0xBBBB)
  400. rval = QLA_FUNCTION_FAILED;
  401. if (mcp->mb[25] != 0x6666 || mcp->mb[26] != 0xBB66 ||
  402. mcp->mb[27] != 0x66BB || mcp->mb[28] != 0xB6B6)
  403. rval = QLA_FUNCTION_FAILED;
  404. if (mcp->mb[29] != 0x6B6B || mcp->mb[30] != 0x3636 ||
  405. mcp->mb[31] != 0xCCCC)
  406. rval = QLA_FUNCTION_FAILED;
  407. }
  408. if (rval != QLA_SUCCESS) {
  409. ql_dbg(ql_dbg_mbx, vha, 0x1170,
  410. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  411. } else {
  412. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1171,
  413. "Done %s.\n", __func__);
  414. }
  415. return rval;
  416. }
  417. /**
  418. * qlafx00_pci_config() - Setup ISPFx00 PCI configuration registers.
  419. * @ha: HA context
  420. *
  421. * Returns 0 on success.
  422. */
  423. int
  424. qlafx00_pci_config(scsi_qla_host_t *vha)
  425. {
  426. uint16_t w;
  427. struct qla_hw_data *ha = vha->hw;
  428. pci_set_master(ha->pdev);
  429. pci_try_set_mwi(ha->pdev);
  430. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  431. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  432. w &= ~PCI_COMMAND_INTX_DISABLE;
  433. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  434. /* PCIe -- adjust Maximum Read Request Size (2048). */
  435. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  436. pcie_set_readrq(ha->pdev, 2048);
  437. ha->chip_revision = ha->pdev->revision;
  438. return QLA_SUCCESS;
  439. }
  440. /**
  441. * qlafx00_warm_reset() - Perform warm reset of iSA(CPUs being reset on SOC).
  442. * @ha: HA context
  443. *
  444. */
  445. static inline void
  446. qlafx00_soc_cpu_reset(scsi_qla_host_t *vha)
  447. {
  448. unsigned long flags = 0;
  449. struct qla_hw_data *ha = vha->hw;
  450. int i, core;
  451. uint32_t cnt;
  452. /* Set all 4 cores in reset */
  453. for (i = 0; i < 4; i++) {
  454. QLAFX00_SET_HBA_SOC_REG(ha,
  455. (SOC_SW_RST_CONTROL_REG_CORE0 + 8*i), (0xF01));
  456. }
  457. /* Set all 4 core Clock gating control */
  458. for (i = 0; i < 4; i++) {
  459. QLAFX00_SET_HBA_SOC_REG(ha,
  460. (SOC_SW_RST_CONTROL_REG_CORE0 + 4 + 8*i), (0x01010101));
  461. }
  462. /* Reset all units in Fabric */
  463. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x11F0101));
  464. /* Reset all interrupt control registers */
  465. for (i = 0; i < 115; i++) {
  466. QLAFX00_SET_HBA_SOC_REG(ha,
  467. (SOC_INTERRUPT_SOURCE_I_CONTROL_REG + 4*i), (0x0));
  468. }
  469. /* Reset Timers control registers. per core */
  470. for (core = 0; core < 4; core++)
  471. for (i = 0; i < 8; i++)
  472. QLAFX00_SET_HBA_SOC_REG(ha,
  473. (SOC_CORE_TIMER_REG + 0x100*core + 4*i), (0x0));
  474. /* Reset per core IRQ ack register */
  475. for (core = 0; core < 4; core++)
  476. QLAFX00_SET_HBA_SOC_REG(ha,
  477. (SOC_IRQ_ACK_REG + 0x100*core), (0x3FF));
  478. /* Set Fabric control and config to defaults */
  479. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONTROL_REG, (0x2));
  480. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONFIG_REG, (0x3));
  481. spin_lock_irqsave(&ha->hardware_lock, flags);
  482. /* Kick in Fabric units */
  483. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x0));
  484. /* Kick in Core0 to start boot process */
  485. QLAFX00_SET_HBA_SOC_REG(ha, SOC_SW_RST_CONTROL_REG_CORE0, (0xF00));
  486. /* Wait 10secs for soft-reset to complete. */
  487. for (cnt = 10; cnt; cnt--) {
  488. msleep(1000);
  489. barrier();
  490. }
  491. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  492. }
  493. /**
  494. * qlafx00_soft_reset() - Soft Reset ISPFx00.
  495. * @ha: HA context
  496. *
  497. * Returns 0 on success.
  498. */
  499. void
  500. qlafx00_soft_reset(scsi_qla_host_t *vha)
  501. {
  502. struct qla_hw_data *ha = vha->hw;
  503. if (unlikely(pci_channel_offline(ha->pdev) &&
  504. ha->flags.pci_channel_io_perm_failure))
  505. return;
  506. ha->isp_ops->disable_intrs(ha);
  507. qlafx00_soc_cpu_reset(vha);
  508. ha->isp_ops->enable_intrs(ha);
  509. }
  510. /**
  511. * qlafx00_chip_diag() - Test ISPFx00 for proper operation.
  512. * @ha: HA context
  513. *
  514. * Returns 0 on success.
  515. */
  516. int
  517. qlafx00_chip_diag(scsi_qla_host_t *vha)
  518. {
  519. int rval = 0;
  520. struct qla_hw_data *ha = vha->hw;
  521. struct req_que *req = ha->req_q_map[0];
  522. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
  523. rval = qlafx00_mbx_reg_test(vha);
  524. if (rval) {
  525. ql_log(ql_log_warn, vha, 0x1165,
  526. "Failed mailbox send register test\n");
  527. } else {
  528. /* Flag a successful rval */
  529. rval = QLA_SUCCESS;
  530. }
  531. return rval;
  532. }
  533. void
  534. qlafx00_config_rings(struct scsi_qla_host *vha)
  535. {
  536. struct qla_hw_data *ha = vha->hw;
  537. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  538. struct init_cb_fx *icb;
  539. struct req_que *req = ha->req_q_map[0];
  540. struct rsp_que *rsp = ha->rsp_q_map[0];
  541. /* Setup ring parameters in initialization control block. */
  542. icb = (struct init_cb_fx *)ha->init_cb;
  543. icb->request_q_outpointer = __constant_cpu_to_le16(0);
  544. icb->response_q_inpointer = __constant_cpu_to_le16(0);
  545. icb->request_q_length = cpu_to_le16(req->length);
  546. icb->response_q_length = cpu_to_le16(rsp->length);
  547. icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  548. icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  549. icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  550. icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  551. WRT_REG_DWORD(&reg->req_q_in, 0);
  552. WRT_REG_DWORD(&reg->req_q_out, 0);
  553. WRT_REG_DWORD(&reg->rsp_q_in, 0);
  554. WRT_REG_DWORD(&reg->rsp_q_out, 0);
  555. /* PCI posting */
  556. RD_REG_DWORD(&reg->rsp_q_out);
  557. }
  558. char *
  559. qlafx00_pci_info_str(struct scsi_qla_host *vha, char *str)
  560. {
  561. struct qla_hw_data *ha = vha->hw;
  562. int pcie_reg;
  563. pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
  564. if (pcie_reg) {
  565. strcpy(str, "PCIe iSA");
  566. return str;
  567. }
  568. return str;
  569. }
  570. char *
  571. qlafx00_fw_version_str(struct scsi_qla_host *vha, char *str)
  572. {
  573. struct qla_hw_data *ha = vha->hw;
  574. sprintf(str, "%s", ha->mr.fw_version);
  575. return str;
  576. }
  577. void
  578. qlafx00_enable_intrs(struct qla_hw_data *ha)
  579. {
  580. unsigned long flags = 0;
  581. spin_lock_irqsave(&ha->hardware_lock, flags);
  582. ha->interrupts_on = 1;
  583. QLAFX00_ENABLE_ICNTRL_REG(ha);
  584. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  585. }
  586. void
  587. qlafx00_disable_intrs(struct qla_hw_data *ha)
  588. {
  589. unsigned long flags = 0;
  590. spin_lock_irqsave(&ha->hardware_lock, flags);
  591. ha->interrupts_on = 0;
  592. QLAFX00_DISABLE_ICNTRL_REG(ha);
  593. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  594. }
  595. static void
  596. qlafx00_tmf_iocb_timeout(void *data)
  597. {
  598. srb_t *sp = (srb_t *)data;
  599. struct srb_iocb *tmf = &sp->u.iocb_cmd;
  600. tmf->u.tmf.comp_status = cpu_to_le16((uint16_t)CS_TIMEOUT);
  601. complete(&tmf->u.tmf.comp);
  602. }
  603. static void
  604. qlafx00_tmf_sp_done(void *data, void *ptr, int res)
  605. {
  606. srb_t *sp = (srb_t *)ptr;
  607. struct srb_iocb *tmf = &sp->u.iocb_cmd;
  608. complete(&tmf->u.tmf.comp);
  609. }
  610. static int
  611. qlafx00_async_tm_cmd(fc_port_t *fcport, uint32_t flags,
  612. uint32_t lun, uint32_t tag)
  613. {
  614. scsi_qla_host_t *vha = fcport->vha;
  615. struct srb_iocb *tm_iocb;
  616. srb_t *sp;
  617. int rval = QLA_FUNCTION_FAILED;
  618. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  619. if (!sp)
  620. goto done;
  621. tm_iocb = &sp->u.iocb_cmd;
  622. sp->type = SRB_TM_CMD;
  623. sp->name = "tmf";
  624. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
  625. tm_iocb->u.tmf.flags = flags;
  626. tm_iocb->u.tmf.lun = lun;
  627. tm_iocb->u.tmf.data = tag;
  628. sp->done = qlafx00_tmf_sp_done;
  629. tm_iocb->timeout = qlafx00_tmf_iocb_timeout;
  630. init_completion(&tm_iocb->u.tmf.comp);
  631. rval = qla2x00_start_sp(sp);
  632. if (rval != QLA_SUCCESS)
  633. goto done_free_sp;
  634. ql_dbg(ql_dbg_async, vha, 0x507b,
  635. "Task management command issued target_id=%x\n",
  636. fcport->tgt_id);
  637. wait_for_completion(&tm_iocb->u.tmf.comp);
  638. rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
  639. QLA_SUCCESS : QLA_FUNCTION_FAILED;
  640. done_free_sp:
  641. sp->free(vha, sp);
  642. done:
  643. return rval;
  644. }
  645. int
  646. qlafx00_abort_target(fc_port_t *fcport, unsigned int l, int tag)
  647. {
  648. return qlafx00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
  649. }
  650. int
  651. qlafx00_lun_reset(fc_port_t *fcport, unsigned int l, int tag)
  652. {
  653. return qlafx00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
  654. }
  655. int
  656. qlafx00_iospace_config(struct qla_hw_data *ha)
  657. {
  658. if (pci_request_selected_regions(ha->pdev, ha->bars,
  659. QLA2XXX_DRIVER_NAME)) {
  660. ql_log_pci(ql_log_fatal, ha->pdev, 0x014e,
  661. "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
  662. pci_name(ha->pdev));
  663. goto iospace_error_exit;
  664. }
  665. /* Use MMIO operations for all accesses. */
  666. if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
  667. ql_log_pci(ql_log_warn, ha->pdev, 0x014f,
  668. "Invalid pci I/O region size (%s).\n",
  669. pci_name(ha->pdev));
  670. goto iospace_error_exit;
  671. }
  672. if (pci_resource_len(ha->pdev, 0) < BAR0_LEN_FX00) {
  673. ql_log_pci(ql_log_warn, ha->pdev, 0x0127,
  674. "Invalid PCI mem BAR0 region size (%s), aborting\n",
  675. pci_name(ha->pdev));
  676. goto iospace_error_exit;
  677. }
  678. ha->cregbase =
  679. ioremap_nocache(pci_resource_start(ha->pdev, 0), BAR0_LEN_FX00);
  680. if (!ha->cregbase) {
  681. ql_log_pci(ql_log_fatal, ha->pdev, 0x0128,
  682. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  683. goto iospace_error_exit;
  684. }
  685. if (!(pci_resource_flags(ha->pdev, 2) & IORESOURCE_MEM)) {
  686. ql_log_pci(ql_log_warn, ha->pdev, 0x0129,
  687. "region #2 not an MMIO resource (%s), aborting\n",
  688. pci_name(ha->pdev));
  689. goto iospace_error_exit;
  690. }
  691. if (pci_resource_len(ha->pdev, 2) < BAR2_LEN_FX00) {
  692. ql_log_pci(ql_log_warn, ha->pdev, 0x012a,
  693. "Invalid PCI mem BAR2 region size (%s), aborting\n",
  694. pci_name(ha->pdev));
  695. goto iospace_error_exit;
  696. }
  697. ha->iobase =
  698. ioremap_nocache(pci_resource_start(ha->pdev, 2), BAR2_LEN_FX00);
  699. if (!ha->iobase) {
  700. ql_log_pci(ql_log_fatal, ha->pdev, 0x012b,
  701. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  702. goto iospace_error_exit;
  703. }
  704. /* Determine queue resources */
  705. ha->max_req_queues = ha->max_rsp_queues = 1;
  706. ql_log_pci(ql_log_info, ha->pdev, 0x012c,
  707. "Bars 0x%x, iobase0 0x%p, iobase2 0x%p\n",
  708. ha->bars, ha->cregbase, ha->iobase);
  709. return 0;
  710. iospace_error_exit:
  711. return -ENOMEM;
  712. }
  713. static void
  714. qlafx00_save_queue_ptrs(struct scsi_qla_host *vha)
  715. {
  716. struct qla_hw_data *ha = vha->hw;
  717. struct req_que *req = ha->req_q_map[0];
  718. struct rsp_que *rsp = ha->rsp_q_map[0];
  719. req->length_fx00 = req->length;
  720. req->ring_fx00 = req->ring;
  721. req->dma_fx00 = req->dma;
  722. rsp->length_fx00 = rsp->length;
  723. rsp->ring_fx00 = rsp->ring;
  724. rsp->dma_fx00 = rsp->dma;
  725. ql_dbg(ql_dbg_init, vha, 0x012d,
  726. "req: %p, ring_fx00: %p, length_fx00: 0x%x,"
  727. "req->dma_fx00: 0x%llx\n", req, req->ring_fx00,
  728. req->length_fx00, (u64)req->dma_fx00);
  729. ql_dbg(ql_dbg_init, vha, 0x012e,
  730. "rsp: %p, ring_fx00: %p, length_fx00: 0x%x,"
  731. "rsp->dma_fx00: 0x%llx\n", rsp, rsp->ring_fx00,
  732. rsp->length_fx00, (u64)rsp->dma_fx00);
  733. }
  734. static int
  735. qlafx00_config_queues(struct scsi_qla_host *vha)
  736. {
  737. struct qla_hw_data *ha = vha->hw;
  738. struct req_que *req = ha->req_q_map[0];
  739. struct rsp_que *rsp = ha->rsp_q_map[0];
  740. dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2);
  741. req->length = ha->req_que_len;
  742. req->ring = (void *)ha->iobase + ha->req_que_off;
  743. req->dma = bar2_hdl + ha->req_que_off;
  744. if ((!req->ring) || (req->length == 0)) {
  745. ql_log_pci(ql_log_info, ha->pdev, 0x012f,
  746. "Unable to allocate memory for req_ring\n");
  747. return QLA_FUNCTION_FAILED;
  748. }
  749. ql_dbg(ql_dbg_init, vha, 0x0130,
  750. "req: %p req_ring pointer %p req len 0x%x "
  751. "req off 0x%x\n, req->dma: 0x%llx",
  752. req, req->ring, req->length,
  753. ha->req_que_off, (u64)req->dma);
  754. rsp->length = ha->rsp_que_len;
  755. rsp->ring = (void *)ha->iobase + ha->rsp_que_off;
  756. rsp->dma = bar2_hdl + ha->rsp_que_off;
  757. if ((!rsp->ring) || (rsp->length == 0)) {
  758. ql_log_pci(ql_log_info, ha->pdev, 0x0131,
  759. "Unable to allocate memory for rsp_ring\n");
  760. return QLA_FUNCTION_FAILED;
  761. }
  762. ql_dbg(ql_dbg_init, vha, 0x0132,
  763. "rsp: %p rsp_ring pointer %p rsp len 0x%x "
  764. "rsp off 0x%x, rsp->dma: 0x%llx\n",
  765. rsp, rsp->ring, rsp->length,
  766. ha->rsp_que_off, (u64)rsp->dma);
  767. return QLA_SUCCESS;
  768. }
  769. static int
  770. qlafx00_init_fw_ready(scsi_qla_host_t *vha)
  771. {
  772. int rval = 0;
  773. unsigned long wtime;
  774. uint16_t wait_time; /* Wait time */
  775. struct qla_hw_data *ha = vha->hw;
  776. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  777. uint32_t aenmbx, aenmbx7 = 0;
  778. uint32_t state[5];
  779. bool done = false;
  780. /* 30 seconds wait - Adjust if required */
  781. wait_time = 30;
  782. /* wait time before firmware ready */
  783. wtime = jiffies + (wait_time * HZ);
  784. do {
  785. aenmbx = RD_REG_DWORD(&reg->aenmailbox0);
  786. barrier();
  787. ql_dbg(ql_dbg_mbx, vha, 0x0133,
  788. "aenmbx: 0x%x\n", aenmbx);
  789. switch (aenmbx) {
  790. case MBA_FW_NOT_STARTED:
  791. case MBA_FW_STARTING:
  792. break;
  793. case MBA_SYSTEM_ERR:
  794. case MBA_REQ_TRANSFER_ERR:
  795. case MBA_RSP_TRANSFER_ERR:
  796. case MBA_FW_INIT_FAILURE:
  797. qlafx00_soft_reset(vha);
  798. break;
  799. case MBA_FW_RESTART_CMPLT:
  800. /* Set the mbx and rqstq intr code */
  801. aenmbx7 = RD_REG_DWORD(&reg->aenmailbox7);
  802. ha->mbx_intr_code = MSW(aenmbx7);
  803. ha->rqstq_intr_code = LSW(aenmbx7);
  804. ha->req_que_off = RD_REG_DWORD(&reg->aenmailbox1);
  805. ha->rsp_que_off = RD_REG_DWORD(&reg->aenmailbox3);
  806. ha->req_que_len = RD_REG_DWORD(&reg->aenmailbox5);
  807. ha->rsp_que_len = RD_REG_DWORD(&reg->aenmailbox6);
  808. WRT_REG_DWORD(&reg->aenmailbox0, 0);
  809. RD_REG_DWORD_RELAXED(&reg->aenmailbox0);
  810. ql_dbg(ql_dbg_init, vha, 0x0134,
  811. "f/w returned mbx_intr_code: 0x%x, "
  812. "rqstq_intr_code: 0x%x\n",
  813. ha->mbx_intr_code, ha->rqstq_intr_code);
  814. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  815. rval = QLA_SUCCESS;
  816. done = true;
  817. break;
  818. default:
  819. /* If fw is apparently not ready. In order to continue,
  820. * we might need to issue Mbox cmd, but the problem is
  821. * that the DoorBell vector values that come with the
  822. * 8060 AEN are most likely gone by now (and thus no
  823. * bell would be rung on the fw side when mbox cmd is
  824. * issued). We have to therefore grab the 8060 AEN
  825. * shadow regs (filled in by FW when the last 8060
  826. * AEN was being posted).
  827. * Do the following to determine what is needed in
  828. * order to get the FW ready:
  829. * 1. reload the 8060 AEN values from the shadow regs
  830. * 2. clear int status to get rid of possible pending
  831. * interrupts
  832. * 3. issue Get FW State Mbox cmd to determine fw state
  833. * Set the mbx and rqstq intr code from Shadow Regs
  834. */
  835. aenmbx7 = RD_REG_DWORD(&reg->initval7);
  836. ha->mbx_intr_code = MSW(aenmbx7);
  837. ha->rqstq_intr_code = LSW(aenmbx7);
  838. ha->req_que_off = RD_REG_DWORD(&reg->initval1);
  839. ha->rsp_que_off = RD_REG_DWORD(&reg->initval3);
  840. ha->req_que_len = RD_REG_DWORD(&reg->initval5);
  841. ha->rsp_que_len = RD_REG_DWORD(&reg->initval6);
  842. ql_dbg(ql_dbg_init, vha, 0x0135,
  843. "f/w returned mbx_intr_code: 0x%x, "
  844. "rqstq_intr_code: 0x%x\n",
  845. ha->mbx_intr_code, ha->rqstq_intr_code);
  846. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  847. /* Get the FW state */
  848. rval = qlafx00_get_firmware_state(vha, state);
  849. if (rval != QLA_SUCCESS) {
  850. /* Retry if timer has not expired */
  851. break;
  852. }
  853. if (state[0] == FSTATE_FX00_CONFIG_WAIT) {
  854. /* Firmware is waiting to be
  855. * initialized by driver
  856. */
  857. rval = QLA_SUCCESS;
  858. done = true;
  859. break;
  860. }
  861. /* Issue driver shutdown and wait until f/w recovers.
  862. * Driver should continue to poll until 8060 AEN is
  863. * received indicating firmware recovery.
  864. */
  865. ql_dbg(ql_dbg_init, vha, 0x0136,
  866. "Sending Driver shutdown fw_state 0x%x\n",
  867. state[0]);
  868. rval = qlafx00_driver_shutdown(vha, 10);
  869. if (rval != QLA_SUCCESS) {
  870. rval = QLA_FUNCTION_FAILED;
  871. break;
  872. }
  873. msleep(500);
  874. wtime = jiffies + (wait_time * HZ);
  875. break;
  876. }
  877. if (!done) {
  878. if (time_after_eq(jiffies, wtime)) {
  879. ql_dbg(ql_dbg_init, vha, 0x0137,
  880. "Init f/w failed: aen[7]: 0x%x\n",
  881. RD_REG_DWORD(&reg->aenmailbox7));
  882. rval = QLA_FUNCTION_FAILED;
  883. done = true;
  884. break;
  885. }
  886. /* Delay for a while */
  887. msleep(500);
  888. }
  889. } while (!done);
  890. if (rval)
  891. ql_dbg(ql_dbg_init, vha, 0x0138,
  892. "%s **** FAILED ****.\n", __func__);
  893. else
  894. ql_dbg(ql_dbg_init, vha, 0x0139,
  895. "%s **** SUCCESS ****.\n", __func__);
  896. return rval;
  897. }
  898. /*
  899. * qlafx00_fw_ready() - Waits for firmware ready.
  900. * @ha: HA context
  901. *
  902. * Returns 0 on success.
  903. */
  904. int
  905. qlafx00_fw_ready(scsi_qla_host_t *vha)
  906. {
  907. int rval;
  908. unsigned long wtime;
  909. uint16_t wait_time; /* Wait time if loop is coming ready */
  910. uint32_t state[5];
  911. rval = QLA_SUCCESS;
  912. wait_time = 10;
  913. /* wait time before firmware ready */
  914. wtime = jiffies + (wait_time * HZ);
  915. /* Wait for ISP to finish init */
  916. if (!vha->flags.init_done)
  917. ql_dbg(ql_dbg_init, vha, 0x013a,
  918. "Waiting for init to complete...\n");
  919. do {
  920. rval = qlafx00_get_firmware_state(vha, state);
  921. if (rval == QLA_SUCCESS) {
  922. if (state[0] == FSTATE_FX00_INITIALIZED) {
  923. ql_dbg(ql_dbg_init, vha, 0x013b,
  924. "fw_state=%x\n", state[0]);
  925. rval = QLA_SUCCESS;
  926. break;
  927. }
  928. }
  929. rval = QLA_FUNCTION_FAILED;
  930. if (time_after_eq(jiffies, wtime))
  931. break;
  932. /* Delay for a while */
  933. msleep(500);
  934. ql_dbg(ql_dbg_init, vha, 0x013c,
  935. "fw_state=%x curr time=%lx.\n", state[0], jiffies);
  936. } while (1);
  937. if (rval)
  938. ql_dbg(ql_dbg_init, vha, 0x013d,
  939. "Firmware ready **** FAILED ****.\n");
  940. else
  941. ql_dbg(ql_dbg_init, vha, 0x013e,
  942. "Firmware ready **** SUCCESS ****.\n");
  943. return rval;
  944. }
  945. static int
  946. qlafx00_find_all_targets(scsi_qla_host_t *vha,
  947. struct list_head *new_fcports)
  948. {
  949. int rval;
  950. uint16_t tgt_id;
  951. fc_port_t *fcport, *new_fcport;
  952. int found;
  953. struct qla_hw_data *ha = vha->hw;
  954. rval = QLA_SUCCESS;
  955. if (!test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
  956. return QLA_FUNCTION_FAILED;
  957. if ((atomic_read(&vha->loop_down_timer) ||
  958. STATE_TRANSITION(vha))) {
  959. atomic_set(&vha->loop_down_timer, 0);
  960. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  961. return QLA_FUNCTION_FAILED;
  962. }
  963. ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088,
  964. "Listing Target bit map...\n");
  965. ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha,
  966. 0x2089, (uint8_t *)ha->gid_list, 32);
  967. /* Allocate temporary rmtport for any new rmtports discovered. */
  968. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  969. if (new_fcport == NULL)
  970. return QLA_MEMORY_ALLOC_FAILED;
  971. for_each_set_bit(tgt_id, (void *)ha->gid_list,
  972. QLAFX00_TGT_NODE_LIST_SIZE) {
  973. /* Send get target node info */
  974. new_fcport->tgt_id = tgt_id;
  975. rval = qlafx00_fx_disc(vha, new_fcport,
  976. FXDISC_GET_TGT_NODE_INFO);
  977. if (rval != QLA_SUCCESS) {
  978. ql_log(ql_log_warn, vha, 0x208a,
  979. "Target info scan failed -- assuming zero-entry "
  980. "result...\n");
  981. continue;
  982. }
  983. /* Locate matching device in database. */
  984. found = 0;
  985. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  986. if (memcmp(new_fcport->port_name,
  987. fcport->port_name, WWN_SIZE))
  988. continue;
  989. found++;
  990. /*
  991. * If tgt_id is same and state FCS_ONLINE, nothing
  992. * changed.
  993. */
  994. if (fcport->tgt_id == new_fcport->tgt_id &&
  995. atomic_read(&fcport->state) == FCS_ONLINE)
  996. break;
  997. /*
  998. * Tgt ID changed or device was marked to be updated.
  999. */
  1000. ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x208b,
  1001. "TGT-ID Change(%s): Present tgt id: "
  1002. "0x%x state: 0x%x "
  1003. "wwnn = %llx wwpn = %llx.\n",
  1004. __func__, fcport->tgt_id,
  1005. atomic_read(&fcport->state),
  1006. (unsigned long long)wwn_to_u64(fcport->node_name),
  1007. (unsigned long long)wwn_to_u64(fcport->port_name));
  1008. ql_log(ql_log_info, vha, 0x208c,
  1009. "TGT-ID Announce(%s): Discovered tgt "
  1010. "id 0x%x wwnn = %llx "
  1011. "wwpn = %llx.\n", __func__, new_fcport->tgt_id,
  1012. (unsigned long long)
  1013. wwn_to_u64(new_fcport->node_name),
  1014. (unsigned long long)
  1015. wwn_to_u64(new_fcport->port_name));
  1016. if (atomic_read(&fcport->state) != FCS_ONLINE) {
  1017. fcport->old_tgt_id = fcport->tgt_id;
  1018. fcport->tgt_id = new_fcport->tgt_id;
  1019. ql_log(ql_log_info, vha, 0x208d,
  1020. "TGT-ID: New fcport Added: %p\n", fcport);
  1021. qla2x00_update_fcport(vha, fcport);
  1022. } else {
  1023. ql_log(ql_log_info, vha, 0x208e,
  1024. " Existing TGT-ID %x did not get "
  1025. " offline event from firmware.\n",
  1026. fcport->old_tgt_id);
  1027. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1028. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1029. kfree(new_fcport);
  1030. return rval;
  1031. }
  1032. break;
  1033. }
  1034. if (found)
  1035. continue;
  1036. /* If device was not in our fcports list, then add it. */
  1037. list_add_tail(&new_fcport->list, new_fcports);
  1038. /* Allocate a new replacement fcport. */
  1039. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  1040. if (new_fcport == NULL)
  1041. return QLA_MEMORY_ALLOC_FAILED;
  1042. }
  1043. kfree(new_fcport);
  1044. return rval;
  1045. }
  1046. /*
  1047. * qlafx00_configure_all_targets
  1048. * Setup target devices with node ID's.
  1049. *
  1050. * Input:
  1051. * ha = adapter block pointer.
  1052. *
  1053. * Returns:
  1054. * 0 = success.
  1055. * BIT_0 = error
  1056. */
  1057. static int
  1058. qlafx00_configure_all_targets(scsi_qla_host_t *vha)
  1059. {
  1060. int rval;
  1061. fc_port_t *fcport, *rmptemp;
  1062. LIST_HEAD(new_fcports);
  1063. rval = qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
  1064. FXDISC_GET_TGT_NODE_LIST);
  1065. if (rval != QLA_SUCCESS) {
  1066. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1067. return rval;
  1068. }
  1069. rval = qlafx00_find_all_targets(vha, &new_fcports);
  1070. if (rval != QLA_SUCCESS) {
  1071. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1072. return rval;
  1073. }
  1074. /*
  1075. * Delete all previous devices marked lost.
  1076. */
  1077. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1078. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  1079. break;
  1080. if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
  1081. if (fcport->port_type != FCT_INITIATOR)
  1082. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1083. }
  1084. }
  1085. /*
  1086. * Add the new devices to our devices list.
  1087. */
  1088. list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
  1089. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  1090. break;
  1091. qla2x00_update_fcport(vha, fcport);
  1092. list_move_tail(&fcport->list, &vha->vp_fcports);
  1093. ql_log(ql_log_info, vha, 0x208f,
  1094. "Attach new target id 0x%x wwnn = %llx "
  1095. "wwpn = %llx.\n",
  1096. fcport->tgt_id,
  1097. (unsigned long long)wwn_to_u64(fcport->node_name),
  1098. (unsigned long long)wwn_to_u64(fcport->port_name));
  1099. }
  1100. /* Free all new device structures not processed. */
  1101. list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
  1102. list_del(&fcport->list);
  1103. kfree(fcport);
  1104. }
  1105. return rval;
  1106. }
  1107. /*
  1108. * qlafx00_configure_devices
  1109. * Updates Fibre Channel Device Database with what is actually on loop.
  1110. *
  1111. * Input:
  1112. * ha = adapter block pointer.
  1113. *
  1114. * Returns:
  1115. * 0 = success.
  1116. * 1 = error.
  1117. * 2 = database was full and device was not configured.
  1118. */
  1119. int
  1120. qlafx00_configure_devices(scsi_qla_host_t *vha)
  1121. {
  1122. int rval;
  1123. unsigned long flags, save_flags;
  1124. rval = QLA_SUCCESS;
  1125. save_flags = flags = vha->dpc_flags;
  1126. ql_dbg(ql_dbg_disc, vha, 0x2090,
  1127. "Configure devices -- dpc flags =0x%lx\n", flags);
  1128. rval = qlafx00_configure_all_targets(vha);
  1129. if (rval == QLA_SUCCESS) {
  1130. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  1131. rval = QLA_FUNCTION_FAILED;
  1132. } else {
  1133. atomic_set(&vha->loop_state, LOOP_READY);
  1134. ql_log(ql_log_info, vha, 0x2091,
  1135. "Device Ready\n");
  1136. }
  1137. }
  1138. if (rval) {
  1139. ql_dbg(ql_dbg_disc, vha, 0x2092,
  1140. "%s *** FAILED ***.\n", __func__);
  1141. } else {
  1142. ql_dbg(ql_dbg_disc, vha, 0x2093,
  1143. "%s: exiting normally.\n", __func__);
  1144. }
  1145. return rval;
  1146. }
  1147. static void
  1148. qlafx00_abort_isp_cleanup(scsi_qla_host_t *vha)
  1149. {
  1150. struct qla_hw_data *ha = vha->hw;
  1151. fc_port_t *fcport;
  1152. vha->flags.online = 0;
  1153. ha->flags.chip_reset_done = 0;
  1154. ha->mr.fw_hbt_en = 0;
  1155. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1156. vha->qla_stats.total_isp_aborts++;
  1157. ql_log(ql_log_info, vha, 0x013f,
  1158. "Performing ISP error recovery - ha = %p.\n", ha);
  1159. ha->isp_ops->reset_chip(vha);
  1160. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  1161. atomic_set(&vha->loop_state, LOOP_DOWN);
  1162. atomic_set(&vha->loop_down_timer,
  1163. QLAFX00_LOOP_DOWN_TIME);
  1164. } else {
  1165. if (!atomic_read(&vha->loop_down_timer))
  1166. atomic_set(&vha->loop_down_timer,
  1167. QLAFX00_LOOP_DOWN_TIME);
  1168. }
  1169. /* Clear all async request states across all VPs. */
  1170. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1171. fcport->flags = 0;
  1172. if (atomic_read(&fcport->state) == FCS_ONLINE)
  1173. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  1174. }
  1175. if (!ha->flags.eeh_busy) {
  1176. /* Requeue all commands in outstanding command list. */
  1177. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  1178. }
  1179. qla2x00_free_irqs(vha);
  1180. set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1181. /* Clear the Interrupts */
  1182. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1183. ql_log(ql_log_info, vha, 0x0140,
  1184. "%s Done done - ha=%p.\n", __func__, ha);
  1185. }
  1186. /**
  1187. * qlafx00_init_response_q_entries() - Initializes response queue entries.
  1188. * @ha: HA context
  1189. *
  1190. * Beginning of request ring has initialization control block already built
  1191. * by nvram config routine.
  1192. *
  1193. * Returns 0 on success.
  1194. */
  1195. void
  1196. qlafx00_init_response_q_entries(struct rsp_que *rsp)
  1197. {
  1198. uint16_t cnt;
  1199. response_t *pkt;
  1200. rsp->ring_ptr = rsp->ring;
  1201. rsp->ring_index = 0;
  1202. rsp->status_srb = NULL;
  1203. pkt = rsp->ring_ptr;
  1204. for (cnt = 0; cnt < rsp->length; cnt++) {
  1205. pkt->signature = RESPONSE_PROCESSED;
  1206. WRT_REG_DWORD((void __iomem *)&pkt->signature,
  1207. RESPONSE_PROCESSED);
  1208. pkt++;
  1209. }
  1210. }
  1211. int
  1212. qlafx00_rescan_isp(scsi_qla_host_t *vha)
  1213. {
  1214. uint32_t status = QLA_FUNCTION_FAILED;
  1215. struct qla_hw_data *ha = vha->hw;
  1216. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  1217. uint32_t aenmbx7;
  1218. qla2x00_request_irqs(ha, ha->rsp_q_map[0]);
  1219. aenmbx7 = RD_REG_DWORD(&reg->aenmailbox7);
  1220. ha->mbx_intr_code = MSW(aenmbx7);
  1221. ha->rqstq_intr_code = LSW(aenmbx7);
  1222. ha->req_que_off = RD_REG_DWORD(&reg->aenmailbox1);
  1223. ha->rsp_que_off = RD_REG_DWORD(&reg->aenmailbox3);
  1224. ha->req_que_len = RD_REG_DWORD(&reg->aenmailbox5);
  1225. ha->rsp_que_len = RD_REG_DWORD(&reg->aenmailbox6);
  1226. ql_dbg(ql_dbg_disc, vha, 0x2094,
  1227. "fw returned mbx_intr_code: 0x%x, rqstq_intr_code: 0x%x "
  1228. " Req que offset 0x%x Rsp que offset 0x%x\n",
  1229. ha->mbx_intr_code, ha->rqstq_intr_code,
  1230. ha->req_que_off, ha->rsp_que_len);
  1231. /* Clear the Interrupts */
  1232. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1233. status = qla2x00_init_rings(vha);
  1234. if (!status) {
  1235. vha->flags.online = 1;
  1236. /* if no cable then assume it's good */
  1237. if ((vha->device_flags & DFLG_NO_CABLE))
  1238. status = 0;
  1239. /* Register system information */
  1240. if (qlafx00_fx_disc(vha,
  1241. &vha->hw->mr.fcport, FXDISC_REG_HOST_INFO))
  1242. ql_dbg(ql_dbg_disc, vha, 0x2095,
  1243. "failed to register host info\n");
  1244. }
  1245. scsi_unblock_requests(vha->host);
  1246. return status;
  1247. }
  1248. void
  1249. qlafx00_timer_routine(scsi_qla_host_t *vha)
  1250. {
  1251. struct qla_hw_data *ha = vha->hw;
  1252. uint32_t fw_heart_beat;
  1253. uint32_t aenmbx0;
  1254. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  1255. /* Check firmware health */
  1256. if (ha->mr.fw_hbt_cnt)
  1257. ha->mr.fw_hbt_cnt--;
  1258. else {
  1259. if ((!ha->flags.mr_reset_hdlr_active) &&
  1260. (!test_bit(UNLOADING, &vha->dpc_flags)) &&
  1261. (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
  1262. (ha->mr.fw_hbt_en)) {
  1263. fw_heart_beat = RD_REG_DWORD(&reg->fwheartbeat);
  1264. if (fw_heart_beat != ha->mr.old_fw_hbt_cnt) {
  1265. ha->mr.old_fw_hbt_cnt = fw_heart_beat;
  1266. ha->mr.fw_hbt_miss_cnt = 0;
  1267. } else {
  1268. ha->mr.fw_hbt_miss_cnt++;
  1269. if (ha->mr.fw_hbt_miss_cnt ==
  1270. QLAFX00_HEARTBEAT_MISS_CNT) {
  1271. set_bit(ISP_ABORT_NEEDED,
  1272. &vha->dpc_flags);
  1273. qla2xxx_wake_dpc(vha);
  1274. ha->mr.fw_hbt_miss_cnt = 0;
  1275. }
  1276. }
  1277. }
  1278. ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
  1279. }
  1280. if (test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags)) {
  1281. /* Reset recovery to be performed in timer routine */
  1282. aenmbx0 = RD_REG_DWORD(&reg->aenmailbox0);
  1283. if (ha->mr.fw_reset_timer_exp) {
  1284. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1285. qla2xxx_wake_dpc(vha);
  1286. ha->mr.fw_reset_timer_exp = 0;
  1287. } else if (aenmbx0 == MBA_FW_RESTART_CMPLT) {
  1288. /* Wake up DPC to rescan the targets */
  1289. set_bit(FX00_TARGET_SCAN, &vha->dpc_flags);
  1290. clear_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1291. qla2xxx_wake_dpc(vha);
  1292. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1293. } else if ((aenmbx0 == MBA_FW_STARTING) &&
  1294. (!ha->mr.fw_hbt_en)) {
  1295. ha->mr.fw_hbt_en = 1;
  1296. } else if (!ha->mr.fw_reset_timer_tick) {
  1297. if (aenmbx0 == ha->mr.old_aenmbx0_state)
  1298. ha->mr.fw_reset_timer_exp = 1;
  1299. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1300. } else if (aenmbx0 == 0xFFFFFFFF) {
  1301. uint32_t data0, data1;
  1302. data0 = QLAFX00_RD_REG(ha,
  1303. QLAFX00_BAR1_BASE_ADDR_REG);
  1304. data1 = QLAFX00_RD_REG(ha,
  1305. QLAFX00_PEX0_WIN0_BASE_ADDR_REG);
  1306. data0 &= 0xffff0000;
  1307. data1 &= 0x0000ffff;
  1308. QLAFX00_WR_REG(ha,
  1309. QLAFX00_PEX0_WIN0_BASE_ADDR_REG,
  1310. (data0 | data1));
  1311. } else if ((aenmbx0 & 0xFF00) == MBA_FW_POLL_STATE) {
  1312. ha->mr.fw_reset_timer_tick =
  1313. QLAFX00_MAX_RESET_INTERVAL;
  1314. } else if (aenmbx0 == MBA_FW_RESET_FCT) {
  1315. ha->mr.fw_reset_timer_tick =
  1316. QLAFX00_MAX_RESET_INTERVAL;
  1317. }
  1318. ha->mr.old_aenmbx0_state = aenmbx0;
  1319. ha->mr.fw_reset_timer_tick--;
  1320. }
  1321. }
  1322. /*
  1323. * qlfx00a_reset_initialize
  1324. * Re-initialize after a iSA device reset.
  1325. *
  1326. * Input:
  1327. * ha = adapter block pointer.
  1328. *
  1329. * Returns:
  1330. * 0 = success
  1331. */
  1332. int
  1333. qlafx00_reset_initialize(scsi_qla_host_t *vha)
  1334. {
  1335. struct qla_hw_data *ha = vha->hw;
  1336. if (vha->device_flags & DFLG_DEV_FAILED) {
  1337. ql_dbg(ql_dbg_init, vha, 0x0142,
  1338. "Device in failed state\n");
  1339. return QLA_SUCCESS;
  1340. }
  1341. ha->flags.mr_reset_hdlr_active = 1;
  1342. if (vha->flags.online) {
  1343. scsi_block_requests(vha->host);
  1344. qlafx00_abort_isp_cleanup(vha);
  1345. }
  1346. ql_log(ql_log_info, vha, 0x0143,
  1347. "(%s): succeeded.\n", __func__);
  1348. ha->flags.mr_reset_hdlr_active = 0;
  1349. return QLA_SUCCESS;
  1350. }
  1351. /*
  1352. * qlafx00_abort_isp
  1353. * Resets ISP and aborts all outstanding commands.
  1354. *
  1355. * Input:
  1356. * ha = adapter block pointer.
  1357. *
  1358. * Returns:
  1359. * 0 = success
  1360. */
  1361. int
  1362. qlafx00_abort_isp(scsi_qla_host_t *vha)
  1363. {
  1364. struct qla_hw_data *ha = vha->hw;
  1365. if (vha->flags.online) {
  1366. if (unlikely(pci_channel_offline(ha->pdev) &&
  1367. ha->flags.pci_channel_io_perm_failure)) {
  1368. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  1369. return QLA_SUCCESS;
  1370. }
  1371. scsi_block_requests(vha->host);
  1372. qlafx00_abort_isp_cleanup(vha);
  1373. } else {
  1374. scsi_block_requests(vha->host);
  1375. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1376. vha->qla_stats.total_isp_aborts++;
  1377. ha->isp_ops->reset_chip(vha);
  1378. set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1379. /* Clear the Interrupts */
  1380. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1381. }
  1382. ql_log(ql_log_info, vha, 0x0145,
  1383. "(%s): succeeded.\n", __func__);
  1384. return QLA_SUCCESS;
  1385. }
  1386. static inline fc_port_t*
  1387. qlafx00_get_fcport(struct scsi_qla_host *vha, int tgt_id)
  1388. {
  1389. fc_port_t *fcport;
  1390. /* Check for matching device in remote port list. */
  1391. fcport = NULL;
  1392. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1393. if (fcport->tgt_id == tgt_id) {
  1394. ql_dbg(ql_dbg_async, vha, 0x5072,
  1395. "Matching fcport(%p) found with TGT-ID: 0x%x "
  1396. "and Remote TGT_ID: 0x%x\n",
  1397. fcport, fcport->tgt_id, tgt_id);
  1398. break;
  1399. }
  1400. }
  1401. return fcport;
  1402. }
  1403. static void
  1404. qlafx00_tgt_detach(struct scsi_qla_host *vha, int tgt_id)
  1405. {
  1406. fc_port_t *fcport;
  1407. ql_log(ql_log_info, vha, 0x5073,
  1408. "Detach TGT-ID: 0x%x\n", tgt_id);
  1409. fcport = qlafx00_get_fcport(vha, tgt_id);
  1410. if (!fcport)
  1411. return;
  1412. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1413. return;
  1414. }
  1415. int
  1416. qlafx00_process_aen(struct scsi_qla_host *vha, struct qla_work_evt *evt)
  1417. {
  1418. int rval = 0;
  1419. uint32_t aen_code, aen_data;
  1420. aen_code = FCH_EVT_VENDOR_UNIQUE;
  1421. aen_data = evt->u.aenfx.evtcode;
  1422. switch (evt->u.aenfx.evtcode) {
  1423. case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
  1424. if (evt->u.aenfx.mbx[1] == 0) {
  1425. if (evt->u.aenfx.mbx[2] == 1) {
  1426. if (!vha->flags.fw_tgt_reported)
  1427. vha->flags.fw_tgt_reported = 1;
  1428. atomic_set(&vha->loop_down_timer, 0);
  1429. atomic_set(&vha->loop_state, LOOP_UP);
  1430. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1431. qla2xxx_wake_dpc(vha);
  1432. } else if (evt->u.aenfx.mbx[2] == 2) {
  1433. qlafx00_tgt_detach(vha, evt->u.aenfx.mbx[3]);
  1434. }
  1435. } else if (evt->u.aenfx.mbx[1] == 0xffff) {
  1436. if (evt->u.aenfx.mbx[2] == 1) {
  1437. if (!vha->flags.fw_tgt_reported)
  1438. vha->flags.fw_tgt_reported = 1;
  1439. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1440. } else if (evt->u.aenfx.mbx[2] == 2) {
  1441. vha->device_flags |= DFLG_NO_CABLE;
  1442. qla2x00_mark_all_devices_lost(vha, 1);
  1443. }
  1444. }
  1445. break;
  1446. case QLAFX00_MBA_LINK_UP:
  1447. aen_code = FCH_EVT_LINKUP;
  1448. aen_data = 0;
  1449. break;
  1450. case QLAFX00_MBA_LINK_DOWN:
  1451. aen_code = FCH_EVT_LINKDOWN;
  1452. aen_data = 0;
  1453. break;
  1454. }
  1455. fc_host_post_event(vha->host, fc_get_event_number(),
  1456. aen_code, aen_data);
  1457. return rval;
  1458. }
  1459. static void
  1460. qlafx00_update_host_attr(scsi_qla_host_t *vha, struct port_info_data *pinfo)
  1461. {
  1462. u64 port_name = 0, node_name = 0;
  1463. port_name = (unsigned long long)wwn_to_u64(pinfo->port_name);
  1464. node_name = (unsigned long long)wwn_to_u64(pinfo->node_name);
  1465. fc_host_node_name(vha->host) = node_name;
  1466. fc_host_port_name(vha->host) = port_name;
  1467. if (!pinfo->port_type)
  1468. vha->hw->current_topology = ISP_CFG_F;
  1469. if (pinfo->link_status == QLAFX00_LINK_STATUS_UP)
  1470. atomic_set(&vha->loop_state, LOOP_READY);
  1471. else if (pinfo->link_status == QLAFX00_LINK_STATUS_DOWN)
  1472. atomic_set(&vha->loop_state, LOOP_DOWN);
  1473. vha->hw->link_data_rate = (uint16_t)pinfo->link_config;
  1474. }
  1475. static void
  1476. qla2x00_fxdisc_iocb_timeout(void *data)
  1477. {
  1478. srb_t *sp = (srb_t *)data;
  1479. struct srb_iocb *lio = &sp->u.iocb_cmd;
  1480. complete(&lio->u.fxiocb.fxiocb_comp);
  1481. }
  1482. static void
  1483. qla2x00_fxdisc_sp_done(void *data, void *ptr, int res)
  1484. {
  1485. srb_t *sp = (srb_t *)ptr;
  1486. struct srb_iocb *lio = &sp->u.iocb_cmd;
  1487. complete(&lio->u.fxiocb.fxiocb_comp);
  1488. }
  1489. int
  1490. qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
  1491. {
  1492. srb_t *sp;
  1493. struct srb_iocb *fdisc;
  1494. int rval = QLA_FUNCTION_FAILED;
  1495. struct qla_hw_data *ha = vha->hw;
  1496. struct host_system_info *phost_info;
  1497. struct register_host_info *preg_hsi;
  1498. struct new_utsname *p_sysid = NULL;
  1499. struct timeval tv;
  1500. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  1501. if (!sp)
  1502. goto done;
  1503. fdisc = &sp->u.iocb_cmd;
  1504. switch (fx_type) {
  1505. case FXDISC_GET_CONFIG_INFO:
  1506. fdisc->u.fxiocb.flags =
  1507. SRB_FXDISC_RESP_DMA_VALID;
  1508. fdisc->u.fxiocb.rsp_len = sizeof(struct config_info_data);
  1509. break;
  1510. case FXDISC_GET_PORT_INFO:
  1511. fdisc->u.fxiocb.flags =
  1512. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1513. fdisc->u.fxiocb.rsp_len = QLAFX00_PORT_DATA_INFO;
  1514. fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->port_id);
  1515. break;
  1516. case FXDISC_GET_TGT_NODE_INFO:
  1517. fdisc->u.fxiocb.flags =
  1518. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1519. fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_INFO;
  1520. fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->tgt_id);
  1521. break;
  1522. case FXDISC_GET_TGT_NODE_LIST:
  1523. fdisc->u.fxiocb.flags =
  1524. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1525. fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_LIST_SIZE;
  1526. break;
  1527. case FXDISC_REG_HOST_INFO:
  1528. fdisc->u.fxiocb.flags = SRB_FXDISC_REQ_DMA_VALID;
  1529. fdisc->u.fxiocb.req_len = sizeof(struct register_host_info);
  1530. p_sysid = utsname();
  1531. if (!p_sysid) {
  1532. ql_log(ql_log_warn, vha, 0x303c,
  1533. "Not able to get the system informtion\n");
  1534. goto done_free_sp;
  1535. }
  1536. break;
  1537. default:
  1538. break;
  1539. }
  1540. if (fdisc->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
  1541. fdisc->u.fxiocb.req_addr = dma_alloc_coherent(&ha->pdev->dev,
  1542. fdisc->u.fxiocb.req_len,
  1543. &fdisc->u.fxiocb.req_dma_handle, GFP_KERNEL);
  1544. if (!fdisc->u.fxiocb.req_addr)
  1545. goto done_free_sp;
  1546. if (fx_type == FXDISC_REG_HOST_INFO) {
  1547. preg_hsi = (struct register_host_info *)
  1548. fdisc->u.fxiocb.req_addr;
  1549. phost_info = &preg_hsi->hsi;
  1550. memset(preg_hsi, 0, sizeof(struct register_host_info));
  1551. phost_info->os_type = OS_TYPE_LINUX;
  1552. strncpy(phost_info->sysname,
  1553. p_sysid->sysname, SYSNAME_LENGTH);
  1554. strncpy(phost_info->nodename,
  1555. p_sysid->nodename, NODENAME_LENGTH);
  1556. strncpy(phost_info->release,
  1557. p_sysid->release, RELEASE_LENGTH);
  1558. strncpy(phost_info->version,
  1559. p_sysid->version, VERSION_LENGTH);
  1560. strncpy(phost_info->machine,
  1561. p_sysid->machine, MACHINE_LENGTH);
  1562. strncpy(phost_info->domainname,
  1563. p_sysid->domainname, DOMNAME_LENGTH);
  1564. strncpy(phost_info->hostdriver,
  1565. QLA2XXX_VERSION, VERSION_LENGTH);
  1566. do_gettimeofday(&tv);
  1567. preg_hsi->utc = (uint64_t)tv.tv_sec;
  1568. ql_dbg(ql_dbg_init, vha, 0x0149,
  1569. "ISP%04X: Host registration with firmware\n",
  1570. ha->pdev->device);
  1571. ql_dbg(ql_dbg_init, vha, 0x014a,
  1572. "os_type = '%d', sysname = '%s', nodname = '%s'\n",
  1573. phost_info->os_type,
  1574. phost_info->sysname,
  1575. phost_info->nodename);
  1576. ql_dbg(ql_dbg_init, vha, 0x014b,
  1577. "release = '%s', version = '%s'\n",
  1578. phost_info->release,
  1579. phost_info->version);
  1580. ql_dbg(ql_dbg_init, vha, 0x014c,
  1581. "machine = '%s' "
  1582. "domainname = '%s', hostdriver = '%s'\n",
  1583. phost_info->machine,
  1584. phost_info->domainname,
  1585. phost_info->hostdriver);
  1586. ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d,
  1587. (uint8_t *)phost_info,
  1588. sizeof(struct host_system_info));
  1589. }
  1590. }
  1591. if (fdisc->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
  1592. fdisc->u.fxiocb.rsp_addr = dma_alloc_coherent(&ha->pdev->dev,
  1593. fdisc->u.fxiocb.rsp_len,
  1594. &fdisc->u.fxiocb.rsp_dma_handle, GFP_KERNEL);
  1595. if (!fdisc->u.fxiocb.rsp_addr)
  1596. goto done_unmap_req;
  1597. }
  1598. sp->type = SRB_FXIOCB_DCMD;
  1599. sp->name = "fxdisc";
  1600. qla2x00_init_timer(sp, FXDISC_TIMEOUT);
  1601. fdisc->timeout = qla2x00_fxdisc_iocb_timeout;
  1602. fdisc->u.fxiocb.req_func_type = cpu_to_le16(fx_type);
  1603. sp->done = qla2x00_fxdisc_sp_done;
  1604. rval = qla2x00_start_sp(sp);
  1605. if (rval != QLA_SUCCESS)
  1606. goto done_unmap_dma;
  1607. wait_for_completion(&fdisc->u.fxiocb.fxiocb_comp);
  1608. if (fx_type == FXDISC_GET_CONFIG_INFO) {
  1609. struct config_info_data *pinfo =
  1610. (struct config_info_data *) fdisc->u.fxiocb.rsp_addr;
  1611. memcpy(&vha->hw->mr.product_name, pinfo->product_name,
  1612. sizeof(vha->hw->mr.product_name));
  1613. memcpy(&vha->hw->mr.symbolic_name, pinfo->symbolic_name,
  1614. sizeof(vha->hw->mr.symbolic_name));
  1615. memcpy(&vha->hw->mr.serial_num, pinfo->serial_num,
  1616. sizeof(vha->hw->mr.serial_num));
  1617. memcpy(&vha->hw->mr.hw_version, pinfo->hw_version,
  1618. sizeof(vha->hw->mr.hw_version));
  1619. memcpy(&vha->hw->mr.fw_version, pinfo->fw_version,
  1620. sizeof(vha->hw->mr.fw_version));
  1621. strim(vha->hw->mr.fw_version);
  1622. memcpy(&vha->hw->mr.uboot_version, pinfo->uboot_version,
  1623. sizeof(vha->hw->mr.uboot_version));
  1624. memcpy(&vha->hw->mr.fru_serial_num, pinfo->fru_serial_num,
  1625. sizeof(vha->hw->mr.fru_serial_num));
  1626. } else if (fx_type == FXDISC_GET_PORT_INFO) {
  1627. struct port_info_data *pinfo =
  1628. (struct port_info_data *) fdisc->u.fxiocb.rsp_addr;
  1629. memcpy(vha->node_name, pinfo->node_name, WWN_SIZE);
  1630. memcpy(vha->port_name, pinfo->port_name, WWN_SIZE);
  1631. vha->d_id.b.domain = pinfo->port_id[0];
  1632. vha->d_id.b.area = pinfo->port_id[1];
  1633. vha->d_id.b.al_pa = pinfo->port_id[2];
  1634. qlafx00_update_host_attr(vha, pinfo);
  1635. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141,
  1636. (uint8_t *)pinfo, 16);
  1637. } else if (fx_type == FXDISC_GET_TGT_NODE_INFO) {
  1638. struct qlafx00_tgt_node_info *pinfo =
  1639. (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
  1640. memcpy(fcport->node_name, pinfo->tgt_node_wwnn, WWN_SIZE);
  1641. memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE);
  1642. fcport->port_type = FCT_TARGET;
  1643. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144,
  1644. (uint8_t *)pinfo, 16);
  1645. } else if (fx_type == FXDISC_GET_TGT_NODE_LIST) {
  1646. struct qlafx00_tgt_node_info *pinfo =
  1647. (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
  1648. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146,
  1649. (uint8_t *)pinfo, 16);
  1650. memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE);
  1651. }
  1652. rval = le32_to_cpu(fdisc->u.fxiocb.result);
  1653. done_unmap_dma:
  1654. if (fdisc->u.fxiocb.rsp_addr)
  1655. dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.rsp_len,
  1656. fdisc->u.fxiocb.rsp_addr, fdisc->u.fxiocb.rsp_dma_handle);
  1657. done_unmap_req:
  1658. if (fdisc->u.fxiocb.req_addr)
  1659. dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.req_len,
  1660. fdisc->u.fxiocb.req_addr, fdisc->u.fxiocb.req_dma_handle);
  1661. done_free_sp:
  1662. sp->free(vha, sp);
  1663. done:
  1664. return rval;
  1665. }
  1666. static void
  1667. qlafx00_abort_iocb_timeout(void *data)
  1668. {
  1669. srb_t *sp = (srb_t *)data;
  1670. struct srb_iocb *abt = &sp->u.iocb_cmd;
  1671. abt->u.abt.comp_status = cpu_to_le16((uint16_t)CS_TIMEOUT);
  1672. complete(&abt->u.abt.comp);
  1673. }
  1674. static void
  1675. qlafx00_abort_sp_done(void *data, void *ptr, int res)
  1676. {
  1677. srb_t *sp = (srb_t *)ptr;
  1678. struct srb_iocb *abt = &sp->u.iocb_cmd;
  1679. complete(&abt->u.abt.comp);
  1680. }
  1681. static int
  1682. qlafx00_async_abt_cmd(srb_t *cmd_sp)
  1683. {
  1684. scsi_qla_host_t *vha = cmd_sp->fcport->vha;
  1685. fc_port_t *fcport = cmd_sp->fcport;
  1686. struct srb_iocb *abt_iocb;
  1687. srb_t *sp;
  1688. int rval = QLA_FUNCTION_FAILED;
  1689. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  1690. if (!sp)
  1691. goto done;
  1692. abt_iocb = &sp->u.iocb_cmd;
  1693. sp->type = SRB_ABT_CMD;
  1694. sp->name = "abort";
  1695. qla2x00_init_timer(sp, FXDISC_TIMEOUT);
  1696. abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
  1697. sp->done = qlafx00_abort_sp_done;
  1698. abt_iocb->timeout = qlafx00_abort_iocb_timeout;
  1699. init_completion(&abt_iocb->u.abt.comp);
  1700. rval = qla2x00_start_sp(sp);
  1701. if (rval != QLA_SUCCESS)
  1702. goto done_free_sp;
  1703. ql_dbg(ql_dbg_async, vha, 0x507c,
  1704. "Abort command issued - hdl=%x, target_id=%x\n",
  1705. cmd_sp->handle, fcport->tgt_id);
  1706. wait_for_completion(&abt_iocb->u.abt.comp);
  1707. rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
  1708. QLA_SUCCESS : QLA_FUNCTION_FAILED;
  1709. done_free_sp:
  1710. sp->free(vha, sp);
  1711. done:
  1712. return rval;
  1713. }
  1714. int
  1715. qlafx00_abort_command(srb_t *sp)
  1716. {
  1717. unsigned long flags = 0;
  1718. uint32_t handle;
  1719. fc_port_t *fcport = sp->fcport;
  1720. struct scsi_qla_host *vha = fcport->vha;
  1721. struct qla_hw_data *ha = vha->hw;
  1722. struct req_que *req = vha->req;
  1723. spin_lock_irqsave(&ha->hardware_lock, flags);
  1724. for (handle = 1; handle < DEFAULT_OUTSTANDING_COMMANDS; handle++) {
  1725. if (req->outstanding_cmds[handle] == sp)
  1726. break;
  1727. }
  1728. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1729. if (handle == DEFAULT_OUTSTANDING_COMMANDS) {
  1730. /* Command not found. */
  1731. return QLA_FUNCTION_FAILED;
  1732. }
  1733. return qlafx00_async_abt_cmd(sp);
  1734. }
  1735. /*
  1736. * qlafx00_initialize_adapter
  1737. * Initialize board.
  1738. *
  1739. * Input:
  1740. * ha = adapter block pointer.
  1741. *
  1742. * Returns:
  1743. * 0 = success
  1744. */
  1745. int
  1746. qlafx00_initialize_adapter(scsi_qla_host_t *vha)
  1747. {
  1748. int rval;
  1749. struct qla_hw_data *ha = vha->hw;
  1750. /* Clear adapter flags. */
  1751. vha->flags.online = 0;
  1752. ha->flags.chip_reset_done = 0;
  1753. vha->flags.reset_active = 0;
  1754. ha->flags.pci_channel_io_perm_failure = 0;
  1755. ha->flags.eeh_busy = 0;
  1756. ha->thermal_support = 0;
  1757. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  1758. atomic_set(&vha->loop_state, LOOP_DOWN);
  1759. vha->device_flags = DFLG_NO_CABLE;
  1760. vha->dpc_flags = 0;
  1761. vha->flags.management_server_logged_in = 0;
  1762. vha->marker_needed = 0;
  1763. ha->isp_abort_cnt = 0;
  1764. ha->beacon_blink_led = 0;
  1765. set_bit(0, ha->req_qid_map);
  1766. set_bit(0, ha->rsp_qid_map);
  1767. ql_dbg(ql_dbg_init, vha, 0x0147,
  1768. "Configuring PCI space...\n");
  1769. rval = ha->isp_ops->pci_config(vha);
  1770. if (rval) {
  1771. ql_log(ql_log_warn, vha, 0x0148,
  1772. "Unable to configure PCI space.\n");
  1773. return rval;
  1774. }
  1775. rval = qlafx00_init_fw_ready(vha);
  1776. if (rval != QLA_SUCCESS)
  1777. return rval;
  1778. qlafx00_save_queue_ptrs(vha);
  1779. rval = qlafx00_config_queues(vha);
  1780. if (rval != QLA_SUCCESS)
  1781. return rval;
  1782. /*
  1783. * Allocate the array of outstanding commands
  1784. * now that we know the firmware resources.
  1785. */
  1786. rval = qla2x00_alloc_outstanding_cmds(ha, vha->req);
  1787. if (rval != QLA_SUCCESS)
  1788. return rval;
  1789. rval = qla2x00_init_rings(vha);
  1790. ha->flags.chip_reset_done = 1;
  1791. return rval;
  1792. }
  1793. uint32_t
  1794. qlafx00_fw_state_show(struct device *dev, struct device_attribute *attr,
  1795. char *buf)
  1796. {
  1797. scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
  1798. int rval = QLA_FUNCTION_FAILED;
  1799. uint32_t state[1];
  1800. if (qla2x00_reset_active(vha))
  1801. ql_log(ql_log_warn, vha, 0x70ce,
  1802. "ISP reset active.\n");
  1803. else if (!vha->hw->flags.eeh_busy) {
  1804. rval = qlafx00_get_firmware_state(vha, state);
  1805. }
  1806. if (rval != QLA_SUCCESS)
  1807. memset(state, -1, sizeof(state));
  1808. return state[0];
  1809. }
  1810. void
  1811. qlafx00_get_host_speed(struct Scsi_Host *shost)
  1812. {
  1813. struct qla_hw_data *ha = ((struct scsi_qla_host *)
  1814. (shost_priv(shost)))->hw;
  1815. u32 speed = FC_PORTSPEED_UNKNOWN;
  1816. switch (ha->link_data_rate) {
  1817. case QLAFX00_PORT_SPEED_2G:
  1818. speed = FC_PORTSPEED_2GBIT;
  1819. break;
  1820. case QLAFX00_PORT_SPEED_4G:
  1821. speed = FC_PORTSPEED_4GBIT;
  1822. break;
  1823. case QLAFX00_PORT_SPEED_8G:
  1824. speed = FC_PORTSPEED_8GBIT;
  1825. break;
  1826. case QLAFX00_PORT_SPEED_10G:
  1827. speed = FC_PORTSPEED_10GBIT;
  1828. break;
  1829. }
  1830. fc_host_speed(shost) = speed;
  1831. }
  1832. /** QLAFX00 specific ISR implementation functions */
  1833. static inline void
  1834. qlafx00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1835. uint32_t sense_len, struct rsp_que *rsp, int res)
  1836. {
  1837. struct scsi_qla_host *vha = sp->fcport->vha;
  1838. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1839. uint32_t track_sense_len;
  1840. SET_FW_SENSE_LEN(sp, sense_len);
  1841. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1842. sense_len = SCSI_SENSE_BUFFERSIZE;
  1843. SET_CMD_SENSE_LEN(sp, sense_len);
  1844. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1845. track_sense_len = sense_len;
  1846. if (sense_len > par_sense_len)
  1847. sense_len = par_sense_len;
  1848. memcpy(cp->sense_buffer, sense_data, sense_len);
  1849. SET_FW_SENSE_LEN(sp, GET_FW_SENSE_LEN(sp) - sense_len);
  1850. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1851. track_sense_len -= sense_len;
  1852. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1853. ql_dbg(ql_dbg_io, vha, 0x304d,
  1854. "sense_len=0x%x par_sense_len=0x%x track_sense_len=0x%x.\n",
  1855. sense_len, par_sense_len, track_sense_len);
  1856. if (GET_FW_SENSE_LEN(sp) > 0) {
  1857. rsp->status_srb = sp;
  1858. cp->result = res;
  1859. }
  1860. if (sense_len) {
  1861. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x3039,
  1862. "Check condition Sense data, nexus%ld:%d:%d cmd=%p.\n",
  1863. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1864. cp);
  1865. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3049,
  1866. cp->sense_buffer, sense_len);
  1867. }
  1868. }
  1869. static void
  1870. qlafx00_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1871. struct tsk_mgmt_entry_fx00 *pkt, srb_t *sp,
  1872. __le16 sstatus, __le16 cpstatus)
  1873. {
  1874. struct srb_iocb *tmf;
  1875. tmf = &sp->u.iocb_cmd;
  1876. if (cpstatus != cpu_to_le16((uint16_t)CS_COMPLETE) ||
  1877. (sstatus & cpu_to_le16((uint16_t)SS_RESPONSE_INFO_LEN_VALID)))
  1878. cpstatus = cpu_to_le16((uint16_t)CS_INCOMPLETE);
  1879. tmf->u.tmf.comp_status = cpstatus;
  1880. sp->done(vha, sp, 0);
  1881. }
  1882. static void
  1883. qlafx00_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1884. struct abort_iocb_entry_fx00 *pkt)
  1885. {
  1886. const char func[] = "ABT_IOCB";
  1887. srb_t *sp;
  1888. struct srb_iocb *abt;
  1889. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1890. if (!sp)
  1891. return;
  1892. abt = &sp->u.iocb_cmd;
  1893. abt->u.abt.comp_status = pkt->tgt_id_sts;
  1894. sp->done(vha, sp, 0);
  1895. }
  1896. static void
  1897. qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1898. struct ioctl_iocb_entry_fx00 *pkt)
  1899. {
  1900. const char func[] = "IOSB_IOCB";
  1901. srb_t *sp;
  1902. struct fc_bsg_job *bsg_job;
  1903. struct srb_iocb *iocb_job;
  1904. int res;
  1905. struct qla_mt_iocb_rsp_fx00 fstatus;
  1906. uint8_t *fw_sts_ptr;
  1907. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1908. if (!sp)
  1909. return;
  1910. if (sp->type == SRB_FXIOCB_DCMD) {
  1911. iocb_job = &sp->u.iocb_cmd;
  1912. iocb_job->u.fxiocb.seq_number = pkt->seq_no;
  1913. iocb_job->u.fxiocb.fw_flags = pkt->fw_iotcl_flags;
  1914. iocb_job->u.fxiocb.result = pkt->status;
  1915. if (iocb_job->u.fxiocb.flags & SRB_FXDISC_RSP_DWRD_VALID)
  1916. iocb_job->u.fxiocb.req_data =
  1917. pkt->dataword_r;
  1918. } else {
  1919. bsg_job = sp->u.bsg_job;
  1920. memset(&fstatus, 0, sizeof(struct qla_mt_iocb_rsp_fx00));
  1921. fstatus.reserved_1 = pkt->reserved_0;
  1922. fstatus.func_type = pkt->comp_func_num;
  1923. fstatus.ioctl_flags = pkt->fw_iotcl_flags;
  1924. fstatus.ioctl_data = pkt->dataword_r;
  1925. fstatus.adapid = pkt->adapid;
  1926. fstatus.adapid_hi = pkt->adapid_hi;
  1927. fstatus.reserved_2 = pkt->reserved_1;
  1928. fstatus.res_count = pkt->residuallen;
  1929. fstatus.status = pkt->status;
  1930. fstatus.seq_number = pkt->seq_no;
  1931. memcpy(fstatus.reserved_3,
  1932. pkt->reserved_2, 20 * sizeof(uint8_t));
  1933. fw_sts_ptr = ((uint8_t *)bsg_job->req->sense) +
  1934. sizeof(struct fc_bsg_reply);
  1935. memcpy(fw_sts_ptr, (uint8_t *)&fstatus,
  1936. sizeof(struct qla_mt_iocb_rsp_fx00));
  1937. bsg_job->reply_len = sizeof(struct fc_bsg_reply) +
  1938. sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t);
  1939. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  1940. sp->fcport->vha, 0x5080,
  1941. (uint8_t *)pkt, sizeof(struct ioctl_iocb_entry_fx00));
  1942. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  1943. sp->fcport->vha, 0x5074,
  1944. (uint8_t *)fw_sts_ptr, sizeof(struct qla_mt_iocb_rsp_fx00));
  1945. res = bsg_job->reply->result = DID_OK << 16;
  1946. bsg_job->reply->reply_payload_rcv_len =
  1947. bsg_job->reply_payload.payload_len;
  1948. }
  1949. sp->done(vha, sp, res);
  1950. }
  1951. /**
  1952. * qlafx00_status_entry() - Process a Status IOCB entry.
  1953. * @ha: SCSI driver HA context
  1954. * @pkt: Entry pointer
  1955. */
  1956. static void
  1957. qlafx00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1958. {
  1959. srb_t *sp;
  1960. fc_port_t *fcport;
  1961. struct scsi_cmnd *cp;
  1962. struct sts_entry_fx00 *sts;
  1963. __le16 comp_status;
  1964. __le16 scsi_status;
  1965. uint16_t ox_id;
  1966. __le16 lscsi_status;
  1967. int32_t resid;
  1968. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1969. fw_resid_len;
  1970. uint8_t *rsp_info = NULL, *sense_data = NULL;
  1971. struct qla_hw_data *ha = vha->hw;
  1972. uint32_t hindex, handle;
  1973. uint16_t que;
  1974. struct req_que *req;
  1975. int logit = 1;
  1976. int res = 0;
  1977. sts = (struct sts_entry_fx00 *) pkt;
  1978. comp_status = sts->comp_status;
  1979. scsi_status = sts->scsi_status & cpu_to_le16((uint16_t)SS_MASK);
  1980. hindex = sts->handle;
  1981. handle = LSW(hindex);
  1982. que = MSW(hindex);
  1983. req = ha->req_q_map[que];
  1984. /* Validate handle. */
  1985. if (handle < req->num_outstanding_cmds)
  1986. sp = req->outstanding_cmds[handle];
  1987. else
  1988. sp = NULL;
  1989. if (sp == NULL) {
  1990. ql_dbg(ql_dbg_io, vha, 0x3034,
  1991. "Invalid status handle (0x%x).\n", handle);
  1992. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1993. qla2xxx_wake_dpc(vha);
  1994. return;
  1995. }
  1996. if (sp->type == SRB_TM_CMD) {
  1997. req->outstanding_cmds[handle] = NULL;
  1998. qlafx00_tm_iocb_entry(vha, req, pkt, sp,
  1999. scsi_status, comp_status);
  2000. return;
  2001. }
  2002. /* Fast path completion. */
  2003. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  2004. qla2x00_do_host_ramp_up(vha);
  2005. qla2x00_process_completed_request(vha, req, handle);
  2006. return;
  2007. }
  2008. req->outstanding_cmds[handle] = NULL;
  2009. cp = GET_CMD_SP(sp);
  2010. if (cp == NULL) {
  2011. ql_dbg(ql_dbg_io, vha, 0x3048,
  2012. "Command already returned (0x%x/%p).\n",
  2013. handle, sp);
  2014. return;
  2015. }
  2016. lscsi_status = scsi_status & cpu_to_le16((uint16_t)STATUS_MASK);
  2017. fcport = sp->fcport;
  2018. ox_id = 0;
  2019. sense_len = par_sense_len = rsp_info_len = resid_len =
  2020. fw_resid_len = 0;
  2021. if (scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID))
  2022. sense_len = sts->sense_len;
  2023. if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
  2024. | (uint16_t)SS_RESIDUAL_OVER)))
  2025. resid_len = le32_to_cpu(sts->residual_len);
  2026. if (comp_status == cpu_to_le16((uint16_t)CS_DATA_UNDERRUN))
  2027. fw_resid_len = le32_to_cpu(sts->residual_len);
  2028. rsp_info = sense_data = sts->data;
  2029. par_sense_len = sizeof(sts->data);
  2030. /* Check for overrun. */
  2031. if (comp_status == CS_COMPLETE &&
  2032. scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_OVER))
  2033. comp_status = cpu_to_le16((uint16_t)CS_DATA_OVERRUN);
  2034. /*
  2035. * Based on Host and scsi status generate status code for Linux
  2036. */
  2037. switch (le16_to_cpu(comp_status)) {
  2038. case CS_COMPLETE:
  2039. case CS_QUEUE_FULL:
  2040. if (scsi_status == 0) {
  2041. res = DID_OK << 16;
  2042. break;
  2043. }
  2044. if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
  2045. | (uint16_t)SS_RESIDUAL_OVER))) {
  2046. resid = resid_len;
  2047. scsi_set_resid(cp, resid);
  2048. if (!lscsi_status &&
  2049. ((unsigned)(scsi_bufflen(cp) - resid) <
  2050. cp->underflow)) {
  2051. ql_dbg(ql_dbg_io, fcport->vha, 0x3050,
  2052. "Mid-layer underflow "
  2053. "detected (0x%x of 0x%x bytes).\n",
  2054. resid, scsi_bufflen(cp));
  2055. res = DID_ERROR << 16;
  2056. break;
  2057. }
  2058. }
  2059. res = DID_OK << 16 | le16_to_cpu(lscsi_status);
  2060. if (lscsi_status ==
  2061. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
  2062. ql_dbg(ql_dbg_io, fcport->vha, 0x3051,
  2063. "QUEUE FULL detected.\n");
  2064. break;
  2065. }
  2066. logit = 0;
  2067. if (lscsi_status != cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
  2068. break;
  2069. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2070. if (!(scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
  2071. break;
  2072. qlafx00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  2073. rsp, res);
  2074. break;
  2075. case CS_DATA_UNDERRUN:
  2076. /* Use F/W calculated residual length. */
  2077. if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2078. resid = fw_resid_len;
  2079. else
  2080. resid = resid_len;
  2081. scsi_set_resid(cp, resid);
  2082. if (scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_UNDER)) {
  2083. if ((IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2084. && fw_resid_len != resid_len) {
  2085. ql_dbg(ql_dbg_io, fcport->vha, 0x3052,
  2086. "Dropped frame(s) detected "
  2087. "(0x%x of 0x%x bytes).\n",
  2088. resid, scsi_bufflen(cp));
  2089. res = DID_ERROR << 16 |
  2090. le16_to_cpu(lscsi_status);
  2091. goto check_scsi_status;
  2092. }
  2093. if (!lscsi_status &&
  2094. ((unsigned)(scsi_bufflen(cp) - resid) <
  2095. cp->underflow)) {
  2096. ql_dbg(ql_dbg_io, fcport->vha, 0x3053,
  2097. "Mid-layer underflow "
  2098. "detected (0x%x of 0x%x bytes, "
  2099. "cp->underflow: 0x%x).\n",
  2100. resid, scsi_bufflen(cp), cp->underflow);
  2101. res = DID_ERROR << 16;
  2102. break;
  2103. }
  2104. } else if (lscsi_status !=
  2105. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL) &&
  2106. lscsi_status != cpu_to_le16((uint16_t)SAM_STAT_BUSY)) {
  2107. /*
  2108. * scsi status of task set and busy are considered
  2109. * to be task not completed.
  2110. */
  2111. ql_dbg(ql_dbg_io, fcport->vha, 0x3054,
  2112. "Dropped frame(s) detected (0x%x "
  2113. "of 0x%x bytes).\n", resid,
  2114. scsi_bufflen(cp));
  2115. res = DID_ERROR << 16 | le16_to_cpu(lscsi_status);
  2116. goto check_scsi_status;
  2117. } else {
  2118. ql_dbg(ql_dbg_io, fcport->vha, 0x3055,
  2119. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  2120. scsi_status, lscsi_status);
  2121. }
  2122. res = DID_OK << 16 | le16_to_cpu(lscsi_status);
  2123. logit = 0;
  2124. check_scsi_status:
  2125. /*
  2126. * Check to see if SCSI Status is non zero. If so report SCSI
  2127. * Status.
  2128. */
  2129. if (lscsi_status != 0) {
  2130. if (lscsi_status ==
  2131. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
  2132. ql_dbg(ql_dbg_io, fcport->vha, 0x3056,
  2133. "QUEUE FULL detected.\n");
  2134. logit = 1;
  2135. break;
  2136. }
  2137. if (lscsi_status !=
  2138. cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
  2139. break;
  2140. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2141. if (!(scsi_status &
  2142. cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
  2143. break;
  2144. qlafx00_handle_sense(sp, sense_data, par_sense_len,
  2145. sense_len, rsp, res);
  2146. }
  2147. break;
  2148. case CS_PORT_LOGGED_OUT:
  2149. case CS_PORT_CONFIG_CHG:
  2150. case CS_PORT_BUSY:
  2151. case CS_INCOMPLETE:
  2152. case CS_PORT_UNAVAILABLE:
  2153. case CS_TIMEOUT:
  2154. case CS_RESET:
  2155. /*
  2156. * We are going to have the fc class block the rport
  2157. * while we try to recover so instruct the mid layer
  2158. * to requeue until the class decides how to handle this.
  2159. */
  2160. res = DID_TRANSPORT_DISRUPTED << 16;
  2161. ql_dbg(ql_dbg_io, fcport->vha, 0x3057,
  2162. "Port down status: port-state=0x%x.\n",
  2163. atomic_read(&fcport->state));
  2164. if (atomic_read(&fcport->state) == FCS_ONLINE)
  2165. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  2166. break;
  2167. case CS_ABORTED:
  2168. res = DID_RESET << 16;
  2169. break;
  2170. default:
  2171. res = DID_ERROR << 16;
  2172. break;
  2173. }
  2174. if (logit)
  2175. ql_dbg(ql_dbg_io, fcport->vha, 0x3058,
  2176. "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%d "
  2177. "tgt_id: 0x%x lscsi_status: 0x%x cdb=%10phN len=0x%x "
  2178. "rsp_info=0x%x resid=0x%x fw_resid=0x%x sense_len=0x%x, "
  2179. "par_sense_len=0x%x, rsp_info_len=0x%x\n",
  2180. comp_status, scsi_status, res, vha->host_no,
  2181. cp->device->id, cp->device->lun, fcport->tgt_id,
  2182. lscsi_status, cp->cmnd, scsi_bufflen(cp),
  2183. rsp_info_len, resid_len, fw_resid_len, sense_len,
  2184. par_sense_len, rsp_info_len);
  2185. if (!res)
  2186. qla2x00_do_host_ramp_up(vha);
  2187. if (rsp->status_srb == NULL)
  2188. sp->done(ha, sp, res);
  2189. }
  2190. /**
  2191. * qlafx00_status_cont_entry() - Process a Status Continuations entry.
  2192. * @ha: SCSI driver HA context
  2193. * @pkt: Entry pointer
  2194. *
  2195. * Extended sense data.
  2196. */
  2197. static void
  2198. qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  2199. {
  2200. uint8_t sense_sz = 0;
  2201. struct qla_hw_data *ha = rsp->hw;
  2202. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  2203. srb_t *sp = rsp->status_srb;
  2204. struct scsi_cmnd *cp;
  2205. uint32_t sense_len;
  2206. uint8_t *sense_ptr;
  2207. if (!sp) {
  2208. ql_dbg(ql_dbg_io, vha, 0x3037,
  2209. "no SP, sp = %p\n", sp);
  2210. return;
  2211. }
  2212. if (!GET_FW_SENSE_LEN(sp)) {
  2213. ql_dbg(ql_dbg_io, vha, 0x304b,
  2214. "no fw sense data, sp = %p\n", sp);
  2215. return;
  2216. }
  2217. cp = GET_CMD_SP(sp);
  2218. if (cp == NULL) {
  2219. ql_log(ql_log_warn, vha, 0x303b,
  2220. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  2221. rsp->status_srb = NULL;
  2222. return;
  2223. }
  2224. if (!GET_CMD_SENSE_LEN(sp)) {
  2225. ql_dbg(ql_dbg_io, vha, 0x304c,
  2226. "no sense data, sp = %p\n", sp);
  2227. } else {
  2228. sense_len = GET_CMD_SENSE_LEN(sp);
  2229. sense_ptr = GET_CMD_SENSE_PTR(sp);
  2230. ql_dbg(ql_dbg_io, vha, 0x304f,
  2231. "sp=%p sense_len=0x%x sense_ptr=%p.\n",
  2232. sp, sense_len, sense_ptr);
  2233. if (sense_len > sizeof(pkt->data))
  2234. sense_sz = sizeof(pkt->data);
  2235. else
  2236. sense_sz = sense_len;
  2237. /* Move sense data. */
  2238. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e,
  2239. (uint8_t *)pkt, sizeof(sts_cont_entry_t));
  2240. memcpy(sense_ptr, pkt->data, sense_sz);
  2241. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a,
  2242. sense_ptr, sense_sz);
  2243. sense_len -= sense_sz;
  2244. sense_ptr += sense_sz;
  2245. SET_CMD_SENSE_PTR(sp, sense_ptr);
  2246. SET_CMD_SENSE_LEN(sp, sense_len);
  2247. }
  2248. sense_len = GET_FW_SENSE_LEN(sp);
  2249. sense_len = (sense_len > sizeof(pkt->data)) ?
  2250. (sense_len - sizeof(pkt->data)) : 0;
  2251. SET_FW_SENSE_LEN(sp, sense_len);
  2252. /* Place command on done queue. */
  2253. if (sense_len == 0) {
  2254. rsp->status_srb = NULL;
  2255. sp->done(ha, sp, cp->result);
  2256. }
  2257. }
  2258. /**
  2259. * qlafx00_multistatus_entry() - Process Multi response queue entries.
  2260. * @ha: SCSI driver HA context
  2261. */
  2262. static void
  2263. qlafx00_multistatus_entry(struct scsi_qla_host *vha,
  2264. struct rsp_que *rsp, void *pkt)
  2265. {
  2266. srb_t *sp;
  2267. struct multi_sts_entry_fx00 *stsmfx;
  2268. struct qla_hw_data *ha = vha->hw;
  2269. uint32_t handle, hindex, handle_count, i;
  2270. uint16_t que;
  2271. struct req_que *req;
  2272. __le32 *handle_ptr;
  2273. stsmfx = (struct multi_sts_entry_fx00 *) pkt;
  2274. handle_count = stsmfx->handle_count;
  2275. if (handle_count > MAX_HANDLE_COUNT) {
  2276. ql_dbg(ql_dbg_io, vha, 0x3035,
  2277. "Invalid handle count (0x%x).\n", handle_count);
  2278. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2279. qla2xxx_wake_dpc(vha);
  2280. return;
  2281. }
  2282. handle_ptr = &stsmfx->handles[0];
  2283. for (i = 0; i < handle_count; i++) {
  2284. hindex = le32_to_cpu(*handle_ptr);
  2285. handle = LSW(hindex);
  2286. que = MSW(hindex);
  2287. req = ha->req_q_map[que];
  2288. /* Validate handle. */
  2289. if (handle < req->num_outstanding_cmds)
  2290. sp = req->outstanding_cmds[handle];
  2291. else
  2292. sp = NULL;
  2293. if (sp == NULL) {
  2294. ql_dbg(ql_dbg_io, vha, 0x3044,
  2295. "Invalid status handle (0x%x).\n", handle);
  2296. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2297. qla2xxx_wake_dpc(vha);
  2298. return;
  2299. }
  2300. qla2x00_process_completed_request(vha, req, handle);
  2301. handle_ptr++;
  2302. }
  2303. }
  2304. /**
  2305. * qlafx00_error_entry() - Process an error entry.
  2306. * @ha: SCSI driver HA context
  2307. * @pkt: Entry pointer
  2308. */
  2309. static void
  2310. qlafx00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp,
  2311. struct sts_entry_fx00 *pkt, uint8_t estatus, uint8_t etype)
  2312. {
  2313. srb_t *sp;
  2314. struct qla_hw_data *ha = vha->hw;
  2315. const char func[] = "ERROR-IOCB";
  2316. uint16_t que = MSW(pkt->handle);
  2317. struct req_que *req = NULL;
  2318. int res = DID_ERROR << 16;
  2319. ql_dbg(ql_dbg_async, vha, 0x507f,
  2320. "type of error status in response: 0x%x\n", estatus);
  2321. req = ha->req_q_map[que];
  2322. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2323. if (sp) {
  2324. sp->done(ha, sp, res);
  2325. return;
  2326. }
  2327. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2328. qla2xxx_wake_dpc(vha);
  2329. }
  2330. /**
  2331. * qlafx00_process_response_queue() - Process response queue entries.
  2332. * @ha: SCSI driver HA context
  2333. */
  2334. static void
  2335. qlafx00_process_response_queue(struct scsi_qla_host *vha,
  2336. struct rsp_que *rsp)
  2337. {
  2338. struct sts_entry_fx00 *pkt;
  2339. response_t *lptr;
  2340. if (!vha->flags.online)
  2341. return;
  2342. while (RD_REG_DWORD((void __iomem *)&(rsp->ring_ptr->signature)) !=
  2343. RESPONSE_PROCESSED) {
  2344. lptr = rsp->ring_ptr;
  2345. memcpy_fromio(rsp->rsp_pkt, (void __iomem *)lptr,
  2346. sizeof(rsp->rsp_pkt));
  2347. pkt = (struct sts_entry_fx00 *)rsp->rsp_pkt;
  2348. rsp->ring_index++;
  2349. if (rsp->ring_index == rsp->length) {
  2350. rsp->ring_index = 0;
  2351. rsp->ring_ptr = rsp->ring;
  2352. } else {
  2353. rsp->ring_ptr++;
  2354. }
  2355. if (pkt->entry_status != 0 &&
  2356. pkt->entry_type != IOCTL_IOSB_TYPE_FX00) {
  2357. qlafx00_error_entry(vha, rsp,
  2358. (struct sts_entry_fx00 *)pkt, pkt->entry_status,
  2359. pkt->entry_type);
  2360. goto next_iter;
  2361. continue;
  2362. }
  2363. switch (pkt->entry_type) {
  2364. case STATUS_TYPE_FX00:
  2365. qlafx00_status_entry(vha, rsp, pkt);
  2366. break;
  2367. case STATUS_CONT_TYPE_FX00:
  2368. qlafx00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2369. break;
  2370. case MULTI_STATUS_TYPE_FX00:
  2371. qlafx00_multistatus_entry(vha, rsp, pkt);
  2372. break;
  2373. case ABORT_IOCB_TYPE_FX00:
  2374. qlafx00_abort_iocb_entry(vha, rsp->req,
  2375. (struct abort_iocb_entry_fx00 *)pkt);
  2376. break;
  2377. case IOCTL_IOSB_TYPE_FX00:
  2378. qlafx00_ioctl_iosb_entry(vha, rsp->req,
  2379. (struct ioctl_iocb_entry_fx00 *)pkt);
  2380. break;
  2381. default:
  2382. /* Type Not Supported. */
  2383. ql_dbg(ql_dbg_async, vha, 0x5081,
  2384. "Received unknown response pkt type %x "
  2385. "entry status=%x.\n",
  2386. pkt->entry_type, pkt->entry_status);
  2387. break;
  2388. }
  2389. next_iter:
  2390. WRT_REG_DWORD((void __iomem *)&lptr->signature,
  2391. RESPONSE_PROCESSED);
  2392. wmb();
  2393. }
  2394. /* Adjust ring index */
  2395. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2396. }
  2397. /**
  2398. * qlafx00_async_event() - Process aynchronous events.
  2399. * @ha: SCSI driver HA context
  2400. */
  2401. static void
  2402. qlafx00_async_event(scsi_qla_host_t *vha)
  2403. {
  2404. struct qla_hw_data *ha = vha->hw;
  2405. struct device_reg_fx00 __iomem *reg;
  2406. int data_size = 1;
  2407. reg = &ha->iobase->ispfx00;
  2408. /* Setup to process RIO completion. */
  2409. switch (ha->aenmb[0]) {
  2410. case QLAFX00_MBA_SYSTEM_ERR: /* System Error */
  2411. ql_log(ql_log_warn, vha, 0x5079,
  2412. "ISP System Error - mbx1=%x\n", ha->aenmb[0]);
  2413. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2414. break;
  2415. case QLAFX00_MBA_SHUTDOWN_RQSTD: /* Shutdown requested */
  2416. ql_dbg(ql_dbg_async, vha, 0x5076,
  2417. "Asynchronous FW shutdown requested.\n");
  2418. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2419. qla2xxx_wake_dpc(vha);
  2420. break;
  2421. case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
  2422. ha->aenmb[1] = RD_REG_WORD(&reg->aenmailbox1);
  2423. ha->aenmb[2] = RD_REG_WORD(&reg->aenmailbox2);
  2424. ha->aenmb[3] = RD_REG_WORD(&reg->aenmailbox3);
  2425. ql_dbg(ql_dbg_async, vha, 0x5077,
  2426. "Asynchronous port Update received "
  2427. "aenmb[0]: %x, aenmb[1]: %x, aenmb[2]: %x, aenmb[3]: %x\n",
  2428. ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3]);
  2429. data_size = 4;
  2430. break;
  2431. default:
  2432. ha->aenmb[1] = RD_REG_WORD(&reg->aenmailbox1);
  2433. ha->aenmb[2] = RD_REG_WORD(&reg->aenmailbox2);
  2434. ha->aenmb[3] = RD_REG_WORD(&reg->aenmailbox3);
  2435. ha->aenmb[4] = RD_REG_WORD(&reg->aenmailbox4);
  2436. ha->aenmb[5] = RD_REG_WORD(&reg->aenmailbox5);
  2437. ha->aenmb[6] = RD_REG_WORD(&reg->aenmailbox6);
  2438. ha->aenmb[7] = RD_REG_WORD(&reg->aenmailbox7);
  2439. ql_dbg(ql_dbg_async, vha, 0x5078,
  2440. "AEN:%04x %04x %04x %04x :%04x %04x %04x %04x\n",
  2441. ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3],
  2442. ha->aenmb[4], ha->aenmb[5], ha->aenmb[6], ha->aenmb[7]);
  2443. break;
  2444. }
  2445. qlafx00_post_aenfx_work(vha, ha->aenmb[0],
  2446. (uint32_t *)ha->aenmb, data_size);
  2447. }
  2448. /**
  2449. *
  2450. * qlafx00x_mbx_completion() - Process mailbox command completions.
  2451. * @ha: SCSI driver HA context
  2452. * @mb16: Mailbox16 register
  2453. */
  2454. static void
  2455. qlafx00_mbx_completion(scsi_qla_host_t *vha, uint32_t mb0)
  2456. {
  2457. uint16_t cnt;
  2458. uint16_t __iomem *wptr;
  2459. struct qla_hw_data *ha = vha->hw;
  2460. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  2461. if (!ha->mcp32)
  2462. ql_dbg(ql_dbg_async, vha, 0x507e, "MBX pointer ERROR.\n");
  2463. /* Load return mailbox registers. */
  2464. ha->flags.mbox_int = 1;
  2465. ha->mailbox_out32[0] = mb0;
  2466. wptr = (uint16_t __iomem *)&reg->mailbox17;
  2467. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2468. ha->mailbox_out32[cnt] = RD_REG_WORD(wptr);
  2469. wptr++;
  2470. }
  2471. }
  2472. /**
  2473. * qlafx00_intr_handler() - Process interrupts for the ISPFX00.
  2474. * @irq:
  2475. * @dev_id: SCSI driver HA context
  2476. *
  2477. * Called by system whenever the host adapter generates an interrupt.
  2478. *
  2479. * Returns handled flag.
  2480. */
  2481. irqreturn_t
  2482. qlafx00_intr_handler(int irq, void *dev_id)
  2483. {
  2484. scsi_qla_host_t *vha;
  2485. struct qla_hw_data *ha;
  2486. struct device_reg_fx00 __iomem *reg;
  2487. int status;
  2488. unsigned long iter;
  2489. uint32_t stat;
  2490. uint32_t mb[8];
  2491. struct rsp_que *rsp;
  2492. unsigned long flags;
  2493. uint32_t clr_intr = 0;
  2494. rsp = (struct rsp_que *) dev_id;
  2495. if (!rsp) {
  2496. ql_log(ql_log_info, NULL, 0x507d,
  2497. "%s: NULL response queue pointer.\n", __func__);
  2498. return IRQ_NONE;
  2499. }
  2500. ha = rsp->hw;
  2501. reg = &ha->iobase->ispfx00;
  2502. status = 0;
  2503. if (unlikely(pci_channel_offline(ha->pdev)))
  2504. return IRQ_HANDLED;
  2505. spin_lock_irqsave(&ha->hardware_lock, flags);
  2506. vha = pci_get_drvdata(ha->pdev);
  2507. for (iter = 50; iter--; clr_intr = 0) {
  2508. stat = QLAFX00_RD_INTR_REG(ha);
  2509. if ((stat & QLAFX00_HST_INT_STS_BITS) == 0)
  2510. break;
  2511. switch (stat & QLAFX00_HST_INT_STS_BITS) {
  2512. case QLAFX00_INTR_MB_CMPLT:
  2513. case QLAFX00_INTR_MB_RSP_CMPLT:
  2514. case QLAFX00_INTR_MB_ASYNC_CMPLT:
  2515. case QLAFX00_INTR_ALL_CMPLT:
  2516. mb[0] = RD_REG_WORD(&reg->mailbox16);
  2517. qlafx00_mbx_completion(vha, mb[0]);
  2518. status |= MBX_INTERRUPT;
  2519. clr_intr |= QLAFX00_INTR_MB_CMPLT;
  2520. break;
  2521. case QLAFX00_INTR_ASYNC_CMPLT:
  2522. case QLAFX00_INTR_RSP_ASYNC_CMPLT:
  2523. ha->aenmb[0] = RD_REG_WORD(&reg->aenmailbox0);
  2524. qlafx00_async_event(vha);
  2525. clr_intr |= QLAFX00_INTR_ASYNC_CMPLT;
  2526. break;
  2527. case QLAFX00_INTR_RSP_CMPLT:
  2528. qlafx00_process_response_queue(vha, rsp);
  2529. clr_intr |= QLAFX00_INTR_RSP_CMPLT;
  2530. break;
  2531. default:
  2532. ql_dbg(ql_dbg_async, vha, 0x507a,
  2533. "Unrecognized interrupt type (%d).\n", stat);
  2534. break;
  2535. }
  2536. QLAFX00_CLR_INTR_REG(ha, clr_intr);
  2537. QLAFX00_RD_INTR_REG(ha);
  2538. }
  2539. qla2x00_handle_mbx_completion(ha, status);
  2540. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2541. return IRQ_HANDLED;
  2542. }
  2543. /** QLAFX00 specific IOCB implementation functions */
  2544. static inline cont_a64_entry_t *
  2545. qlafx00_prep_cont_type1_iocb(struct req_que *req,
  2546. cont_a64_entry_t *lcont_pkt)
  2547. {
  2548. cont_a64_entry_t *cont_pkt;
  2549. /* Adjust ring index. */
  2550. req->ring_index++;
  2551. if (req->ring_index == req->length) {
  2552. req->ring_index = 0;
  2553. req->ring_ptr = req->ring;
  2554. } else {
  2555. req->ring_ptr++;
  2556. }
  2557. cont_pkt = (cont_a64_entry_t *)req->ring_ptr;
  2558. /* Load packet defaults. */
  2559. lcont_pkt->entry_type = CONTINUE_A64_TYPE_FX00;
  2560. return cont_pkt;
  2561. }
  2562. static inline void
  2563. qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt,
  2564. uint16_t tot_dsds, struct cmd_type_7_fx00 *lcmd_pkt)
  2565. {
  2566. uint16_t avail_dsds;
  2567. __le32 *cur_dsd;
  2568. scsi_qla_host_t *vha;
  2569. struct scsi_cmnd *cmd;
  2570. struct scatterlist *sg;
  2571. int i, cont;
  2572. struct req_que *req;
  2573. cont_a64_entry_t lcont_pkt;
  2574. cont_a64_entry_t *cont_pkt;
  2575. vha = sp->fcport->vha;
  2576. req = vha->req;
  2577. cmd = GET_CMD_SP(sp);
  2578. cont = 0;
  2579. cont_pkt = NULL;
  2580. /* Update entry type to indicate Command Type 3 IOCB */
  2581. lcmd_pkt->entry_type = FX00_COMMAND_TYPE_7;
  2582. /* No data transfer */
  2583. if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
  2584. lcmd_pkt->byte_count = __constant_cpu_to_le32(0);
  2585. return;
  2586. }
  2587. /* Set transfer direction */
  2588. if (cmd->sc_data_direction == DMA_TO_DEVICE) {
  2589. lcmd_pkt->cntrl_flags = TMF_WRITE_DATA;
  2590. vha->qla_stats.output_bytes += scsi_bufflen(cmd);
  2591. } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) {
  2592. lcmd_pkt->cntrl_flags = TMF_READ_DATA;
  2593. vha->qla_stats.input_bytes += scsi_bufflen(cmd);
  2594. }
  2595. /* One DSD is available in the Command Type 3 IOCB */
  2596. avail_dsds = 1;
  2597. cur_dsd = (__le32 *)&lcmd_pkt->dseg_0_address;
  2598. /* Load data segments */
  2599. scsi_for_each_sg(cmd, sg, tot_dsds, i) {
  2600. dma_addr_t sle_dma;
  2601. /* Allocate additional continuation packets? */
  2602. if (avail_dsds == 0) {
  2603. /*
  2604. * Five DSDs are available in the Continuation
  2605. * Type 1 IOCB.
  2606. */
  2607. memset(&lcont_pkt, 0, REQUEST_ENTRY_SIZE);
  2608. cont_pkt =
  2609. qlafx00_prep_cont_type1_iocb(req, &lcont_pkt);
  2610. cur_dsd = (__le32 *)lcont_pkt.dseg_0_address;
  2611. avail_dsds = 5;
  2612. cont = 1;
  2613. }
  2614. sle_dma = sg_dma_address(sg);
  2615. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2616. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2617. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2618. avail_dsds--;
  2619. if (avail_dsds == 0 && cont == 1) {
  2620. cont = 0;
  2621. memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
  2622. REQUEST_ENTRY_SIZE);
  2623. }
  2624. }
  2625. if (avail_dsds != 0 && cont == 1) {
  2626. memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
  2627. REQUEST_ENTRY_SIZE);
  2628. }
  2629. }
  2630. /**
  2631. * qlafx00_start_scsi() - Send a SCSI command to the ISP
  2632. * @sp: command to send to the ISP
  2633. *
  2634. * Returns non-zero if a failure occurred, else zero.
  2635. */
  2636. int
  2637. qlafx00_start_scsi(srb_t *sp)
  2638. {
  2639. int ret, nseg;
  2640. unsigned long flags;
  2641. uint32_t index;
  2642. uint32_t handle;
  2643. uint16_t cnt;
  2644. uint16_t req_cnt;
  2645. uint16_t tot_dsds;
  2646. struct req_que *req = NULL;
  2647. struct rsp_que *rsp = NULL;
  2648. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  2649. struct scsi_qla_host *vha = sp->fcport->vha;
  2650. struct qla_hw_data *ha = vha->hw;
  2651. struct cmd_type_7_fx00 *cmd_pkt;
  2652. struct cmd_type_7_fx00 lcmd_pkt;
  2653. struct scsi_lun llun;
  2654. char tag[2];
  2655. /* Setup device pointers. */
  2656. ret = 0;
  2657. rsp = ha->rsp_q_map[0];
  2658. req = vha->req;
  2659. /* So we know we haven't pci_map'ed anything yet */
  2660. tot_dsds = 0;
  2661. /* Forcing marker needed for now */
  2662. vha->marker_needed = 0;
  2663. /* Send marker if required */
  2664. if (vha->marker_needed != 0) {
  2665. if (qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL) !=
  2666. QLA_SUCCESS)
  2667. return QLA_FUNCTION_FAILED;
  2668. vha->marker_needed = 0;
  2669. }
  2670. /* Acquire ring specific lock */
  2671. spin_lock_irqsave(&ha->hardware_lock, flags);
  2672. /* Check for room in outstanding command list. */
  2673. handle = req->current_outstanding_cmd;
  2674. for (index = 1; index < req->num_outstanding_cmds; index++) {
  2675. handle++;
  2676. if (handle == req->num_outstanding_cmds)
  2677. handle = 1;
  2678. if (!req->outstanding_cmds[handle])
  2679. break;
  2680. }
  2681. if (index == req->num_outstanding_cmds)
  2682. goto queuing_error;
  2683. /* Map the sg table so we have an accurate count of sg entries needed */
  2684. if (scsi_sg_count(cmd)) {
  2685. nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd),
  2686. scsi_sg_count(cmd), cmd->sc_data_direction);
  2687. if (unlikely(!nseg))
  2688. goto queuing_error;
  2689. } else
  2690. nseg = 0;
  2691. tot_dsds = nseg;
  2692. req_cnt = qla24xx_calc_iocbs(vha, tot_dsds);
  2693. if (req->cnt < (req_cnt + 2)) {
  2694. cnt = RD_REG_DWORD_RELAXED(req->req_q_out);
  2695. if (req->ring_index < cnt)
  2696. req->cnt = cnt - req->ring_index;
  2697. else
  2698. req->cnt = req->length -
  2699. (req->ring_index - cnt);
  2700. if (req->cnt < (req_cnt + 2))
  2701. goto queuing_error;
  2702. }
  2703. /* Build command packet. */
  2704. req->current_outstanding_cmd = handle;
  2705. req->outstanding_cmds[handle] = sp;
  2706. sp->handle = handle;
  2707. cmd->host_scribble = (unsigned char *)(unsigned long)handle;
  2708. req->cnt -= req_cnt;
  2709. cmd_pkt = (struct cmd_type_7_fx00 *)req->ring_ptr;
  2710. memset(&lcmd_pkt, 0, REQUEST_ENTRY_SIZE);
  2711. lcmd_pkt.handle = MAKE_HANDLE(req->id, sp->handle);
  2712. lcmd_pkt.handle_hi = 0;
  2713. lcmd_pkt.dseg_count = cpu_to_le16(tot_dsds);
  2714. lcmd_pkt.tgt_idx = cpu_to_le16(sp->fcport->tgt_id);
  2715. int_to_scsilun(cmd->device->lun, &llun);
  2716. host_to_adap((uint8_t *)&llun, (uint8_t *)&lcmd_pkt.lun,
  2717. sizeof(lcmd_pkt.lun));
  2718. /* Update tagged queuing modifier -- default is TSK_SIMPLE (0). */
  2719. if (scsi_populate_tag_msg(cmd, tag)) {
  2720. switch (tag[0]) {
  2721. case HEAD_OF_QUEUE_TAG:
  2722. lcmd_pkt.task = TSK_HEAD_OF_QUEUE;
  2723. break;
  2724. case ORDERED_QUEUE_TAG:
  2725. lcmd_pkt.task = TSK_ORDERED;
  2726. break;
  2727. }
  2728. }
  2729. /* Load SCSI command packet. */
  2730. host_to_adap(cmd->cmnd, lcmd_pkt.fcp_cdb, sizeof(lcmd_pkt.fcp_cdb));
  2731. lcmd_pkt.byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
  2732. /* Build IOCB segments */
  2733. qlafx00_build_scsi_iocbs(sp, cmd_pkt, tot_dsds, &lcmd_pkt);
  2734. /* Set total data segment count. */
  2735. lcmd_pkt.entry_count = (uint8_t)req_cnt;
  2736. /* Specify response queue number where completion should happen */
  2737. lcmd_pkt.entry_status = (uint8_t) rsp->id;
  2738. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e,
  2739. (uint8_t *)cmd->cmnd, cmd->cmd_len);
  2740. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032,
  2741. (uint8_t *)&lcmd_pkt, REQUEST_ENTRY_SIZE);
  2742. memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE);
  2743. wmb();
  2744. /* Adjust ring index. */
  2745. req->ring_index++;
  2746. if (req->ring_index == req->length) {
  2747. req->ring_index = 0;
  2748. req->ring_ptr = req->ring;
  2749. } else
  2750. req->ring_ptr++;
  2751. sp->flags |= SRB_DMA_VALID;
  2752. /* Set chip new ring index. */
  2753. WRT_REG_DWORD(req->req_q_in, req->ring_index);
  2754. QLAFX00_SET_HST_INTR(ha, ha->rqstq_intr_code);
  2755. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2756. return QLA_SUCCESS;
  2757. queuing_error:
  2758. if (tot_dsds)
  2759. scsi_dma_unmap(cmd);
  2760. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2761. return QLA_FUNCTION_FAILED;
  2762. }
  2763. void
  2764. qlafx00_tm_iocb(srb_t *sp, struct tsk_mgmt_entry_fx00 *ptm_iocb)
  2765. {
  2766. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2767. scsi_qla_host_t *vha = sp->fcport->vha;
  2768. struct req_que *req = vha->req;
  2769. struct tsk_mgmt_entry_fx00 tm_iocb;
  2770. struct scsi_lun llun;
  2771. memset(&tm_iocb, 0, sizeof(struct tsk_mgmt_entry_fx00));
  2772. tm_iocb.entry_type = TSK_MGMT_IOCB_TYPE_FX00;
  2773. tm_iocb.entry_count = 1;
  2774. tm_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
  2775. tm_iocb.handle_hi = 0;
  2776. tm_iocb.timeout = cpu_to_le16(qla2x00_get_async_timeout(vha) + 2);
  2777. tm_iocb.tgt_id = cpu_to_le16(sp->fcport->tgt_id);
  2778. tm_iocb.control_flags = cpu_to_le32(fxio->u.tmf.flags);
  2779. if (tm_iocb.control_flags == cpu_to_le32((uint32_t)TCF_LUN_RESET)) {
  2780. int_to_scsilun(fxio->u.tmf.lun, &llun);
  2781. host_to_adap((uint8_t *)&llun, (uint8_t *)&tm_iocb.lun,
  2782. sizeof(struct scsi_lun));
  2783. }
  2784. memcpy((void *)ptm_iocb, &tm_iocb,
  2785. sizeof(struct tsk_mgmt_entry_fx00));
  2786. wmb();
  2787. }
  2788. void
  2789. qlafx00_abort_iocb(srb_t *sp, struct abort_iocb_entry_fx00 *pabt_iocb)
  2790. {
  2791. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2792. scsi_qla_host_t *vha = sp->fcport->vha;
  2793. struct req_que *req = vha->req;
  2794. struct abort_iocb_entry_fx00 abt_iocb;
  2795. memset(&abt_iocb, 0, sizeof(struct abort_iocb_entry_fx00));
  2796. abt_iocb.entry_type = ABORT_IOCB_TYPE_FX00;
  2797. abt_iocb.entry_count = 1;
  2798. abt_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
  2799. abt_iocb.abort_handle =
  2800. cpu_to_le32(MAKE_HANDLE(req->id, fxio->u.abt.cmd_hndl));
  2801. abt_iocb.tgt_id_sts = cpu_to_le16(sp->fcport->tgt_id);
  2802. abt_iocb.req_que_no = cpu_to_le16(req->id);
  2803. memcpy((void *)pabt_iocb, &abt_iocb,
  2804. sizeof(struct abort_iocb_entry_fx00));
  2805. wmb();
  2806. }
  2807. void
  2808. qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb)
  2809. {
  2810. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2811. struct qla_mt_iocb_rqst_fx00 *piocb_rqst;
  2812. struct fc_bsg_job *bsg_job;
  2813. struct fxdisc_entry_fx00 fx_iocb;
  2814. uint8_t entry_cnt = 1;
  2815. memset(&fx_iocb, 0, sizeof(struct fxdisc_entry_fx00));
  2816. fx_iocb.entry_type = FX00_IOCB_TYPE;
  2817. fx_iocb.handle = cpu_to_le32(sp->handle);
  2818. fx_iocb.entry_count = entry_cnt;
  2819. if (sp->type == SRB_FXIOCB_DCMD) {
  2820. fx_iocb.func_num =
  2821. sp->u.iocb_cmd.u.fxiocb.req_func_type;
  2822. fx_iocb.adapid = fxio->u.fxiocb.adapter_id;
  2823. fx_iocb.adapid_hi = fxio->u.fxiocb.adapter_id_hi;
  2824. fx_iocb.reserved_0 = fxio->u.fxiocb.reserved_0;
  2825. fx_iocb.reserved_1 = fxio->u.fxiocb.reserved_1;
  2826. fx_iocb.dataword_extra = fxio->u.fxiocb.req_data_extra;
  2827. if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
  2828. fx_iocb.req_dsdcnt = cpu_to_le16(1);
  2829. fx_iocb.req_xfrcnt =
  2830. cpu_to_le16(fxio->u.fxiocb.req_len);
  2831. fx_iocb.dseg_rq_address[0] =
  2832. cpu_to_le32(LSD(fxio->u.fxiocb.req_dma_handle));
  2833. fx_iocb.dseg_rq_address[1] =
  2834. cpu_to_le32(MSD(fxio->u.fxiocb.req_dma_handle));
  2835. fx_iocb.dseg_rq_len =
  2836. cpu_to_le32(fxio->u.fxiocb.req_len);
  2837. }
  2838. if (fxio->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
  2839. fx_iocb.rsp_dsdcnt = cpu_to_le16(1);
  2840. fx_iocb.rsp_xfrcnt =
  2841. cpu_to_le16(fxio->u.fxiocb.rsp_len);
  2842. fx_iocb.dseg_rsp_address[0] =
  2843. cpu_to_le32(LSD(fxio->u.fxiocb.rsp_dma_handle));
  2844. fx_iocb.dseg_rsp_address[1] =
  2845. cpu_to_le32(MSD(fxio->u.fxiocb.rsp_dma_handle));
  2846. fx_iocb.dseg_rsp_len =
  2847. cpu_to_le32(fxio->u.fxiocb.rsp_len);
  2848. }
  2849. if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DWRD_VALID) {
  2850. fx_iocb.dataword = fxio->u.fxiocb.req_data;
  2851. }
  2852. fx_iocb.flags = fxio->u.fxiocb.flags;
  2853. } else {
  2854. struct scatterlist *sg;
  2855. bsg_job = sp->u.bsg_job;
  2856. piocb_rqst = (struct qla_mt_iocb_rqst_fx00 *)
  2857. &bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
  2858. fx_iocb.func_num = piocb_rqst->func_type;
  2859. fx_iocb.adapid = piocb_rqst->adapid;
  2860. fx_iocb.adapid_hi = piocb_rqst->adapid_hi;
  2861. fx_iocb.reserved_0 = piocb_rqst->reserved_0;
  2862. fx_iocb.reserved_1 = piocb_rqst->reserved_1;
  2863. fx_iocb.dataword_extra = piocb_rqst->dataword_extra;
  2864. fx_iocb.dataword = piocb_rqst->dataword;
  2865. fx_iocb.req_xfrcnt = piocb_rqst->req_len;
  2866. fx_iocb.rsp_xfrcnt = piocb_rqst->rsp_len;
  2867. if (piocb_rqst->flags & SRB_FXDISC_REQ_DMA_VALID) {
  2868. int avail_dsds, tot_dsds;
  2869. cont_a64_entry_t lcont_pkt;
  2870. cont_a64_entry_t *cont_pkt = NULL;
  2871. __le32 *cur_dsd;
  2872. int index = 0, cont = 0;
  2873. fx_iocb.req_dsdcnt =
  2874. cpu_to_le16(bsg_job->request_payload.sg_cnt);
  2875. tot_dsds =
  2876. bsg_job->request_payload.sg_cnt;
  2877. cur_dsd = (__le32 *)&fx_iocb.dseg_rq_address[0];
  2878. avail_dsds = 1;
  2879. for_each_sg(bsg_job->request_payload.sg_list, sg,
  2880. tot_dsds, index) {
  2881. dma_addr_t sle_dma;
  2882. /* Allocate additional continuation packets? */
  2883. if (avail_dsds == 0) {
  2884. /*
  2885. * Five DSDs are available in the Cont.
  2886. * Type 1 IOCB.
  2887. */
  2888. memset(&lcont_pkt, 0,
  2889. REQUEST_ENTRY_SIZE);
  2890. cont_pkt =
  2891. qlafx00_prep_cont_type1_iocb(
  2892. sp->fcport->vha->req,
  2893. &lcont_pkt);
  2894. cur_dsd = (__le32 *)
  2895. lcont_pkt.dseg_0_address;
  2896. avail_dsds = 5;
  2897. cont = 1;
  2898. entry_cnt++;
  2899. }
  2900. sle_dma = sg_dma_address(sg);
  2901. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2902. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2903. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2904. avail_dsds--;
  2905. if (avail_dsds == 0 && cont == 1) {
  2906. cont = 0;
  2907. memcpy_toio(
  2908. (void __iomem *)cont_pkt,
  2909. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2910. ql_dump_buffer(
  2911. ql_dbg_user + ql_dbg_verbose,
  2912. sp->fcport->vha, 0x3042,
  2913. (uint8_t *)&lcont_pkt,
  2914. REQUEST_ENTRY_SIZE);
  2915. }
  2916. }
  2917. if (avail_dsds != 0 && cont == 1) {
  2918. memcpy_toio((void __iomem *)cont_pkt,
  2919. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2920. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2921. sp->fcport->vha, 0x3043,
  2922. (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
  2923. }
  2924. }
  2925. if (piocb_rqst->flags & SRB_FXDISC_RESP_DMA_VALID) {
  2926. int avail_dsds, tot_dsds;
  2927. cont_a64_entry_t lcont_pkt;
  2928. cont_a64_entry_t *cont_pkt = NULL;
  2929. __le32 *cur_dsd;
  2930. int index = 0, cont = 0;
  2931. fx_iocb.rsp_dsdcnt =
  2932. cpu_to_le16(bsg_job->reply_payload.sg_cnt);
  2933. tot_dsds = bsg_job->reply_payload.sg_cnt;
  2934. cur_dsd = (__le32 *)&fx_iocb.dseg_rsp_address[0];
  2935. avail_dsds = 1;
  2936. for_each_sg(bsg_job->reply_payload.sg_list, sg,
  2937. tot_dsds, index) {
  2938. dma_addr_t sle_dma;
  2939. /* Allocate additional continuation packets? */
  2940. if (avail_dsds == 0) {
  2941. /*
  2942. * Five DSDs are available in the Cont.
  2943. * Type 1 IOCB.
  2944. */
  2945. memset(&lcont_pkt, 0,
  2946. REQUEST_ENTRY_SIZE);
  2947. cont_pkt =
  2948. qlafx00_prep_cont_type1_iocb(
  2949. sp->fcport->vha->req,
  2950. &lcont_pkt);
  2951. cur_dsd = (__le32 *)
  2952. lcont_pkt.dseg_0_address;
  2953. avail_dsds = 5;
  2954. cont = 1;
  2955. entry_cnt++;
  2956. }
  2957. sle_dma = sg_dma_address(sg);
  2958. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2959. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2960. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2961. avail_dsds--;
  2962. if (avail_dsds == 0 && cont == 1) {
  2963. cont = 0;
  2964. memcpy_toio((void __iomem *)cont_pkt,
  2965. &lcont_pkt,
  2966. REQUEST_ENTRY_SIZE);
  2967. ql_dump_buffer(
  2968. ql_dbg_user + ql_dbg_verbose,
  2969. sp->fcport->vha, 0x3045,
  2970. (uint8_t *)&lcont_pkt,
  2971. REQUEST_ENTRY_SIZE);
  2972. }
  2973. }
  2974. if (avail_dsds != 0 && cont == 1) {
  2975. memcpy_toio((void __iomem *)cont_pkt,
  2976. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2977. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2978. sp->fcport->vha, 0x3046,
  2979. (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
  2980. }
  2981. }
  2982. if (piocb_rqst->flags & SRB_FXDISC_REQ_DWRD_VALID)
  2983. fx_iocb.dataword = piocb_rqst->dataword;
  2984. fx_iocb.flags = piocb_rqst->flags;
  2985. fx_iocb.entry_count = entry_cnt;
  2986. }
  2987. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2988. sp->fcport->vha, 0x3047,
  2989. (uint8_t *)&fx_iocb, sizeof(struct fxdisc_entry_fx00));
  2990. memcpy((void *)pfxiocb, &fx_iocb,
  2991. sizeof(struct fxdisc_entry_fx00));
  2992. wmb();
  2993. }