i915_sysfs.c 16 KB

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  1. /*
  2. * Copyright © 2012 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Ben Widawsky <ben@bwidawsk.net>
  25. *
  26. */
  27. #include <linux/device.h>
  28. #include <linux/module.h>
  29. #include <linux/stat.h>
  30. #include <linux/sysfs.h>
  31. #include "intel_drv.h"
  32. #include "i915_drv.h"
  33. #ifdef CONFIG_PM
  34. static u32 calc_residency(struct drm_device *dev, const u32 reg)
  35. {
  36. struct drm_i915_private *dev_priv = dev->dev_private;
  37. u64 raw_time; /* 32b value may overflow during fixed point math */
  38. if (!intel_enable_rc6(dev))
  39. return 0;
  40. raw_time = I915_READ(reg) * 128ULL;
  41. return DIV_ROUND_UP_ULL(raw_time, 100000);
  42. }
  43. static ssize_t
  44. show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
  45. {
  46. struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
  47. return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6(dminor->dev));
  48. }
  49. static ssize_t
  50. show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
  51. {
  52. struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
  53. u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6);
  54. return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
  55. }
  56. static ssize_t
  57. show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
  58. {
  59. struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
  60. u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
  61. if (IS_VALLEYVIEW(dminor->dev))
  62. rc6p_residency = 0;
  63. return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
  64. }
  65. static ssize_t
  66. show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
  67. {
  68. struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
  69. u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
  70. if (IS_VALLEYVIEW(dminor->dev))
  71. rc6pp_residency = 0;
  72. return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
  73. }
  74. static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
  75. static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
  76. static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
  77. static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
  78. static struct attribute *rc6_attrs[] = {
  79. &dev_attr_rc6_enable.attr,
  80. &dev_attr_rc6_residency_ms.attr,
  81. &dev_attr_rc6p_residency_ms.attr,
  82. &dev_attr_rc6pp_residency_ms.attr,
  83. NULL
  84. };
  85. static struct attribute_group rc6_attr_group = {
  86. .name = power_group_name,
  87. .attrs = rc6_attrs
  88. };
  89. #endif
  90. static int l3_access_valid(struct drm_device *dev, loff_t offset)
  91. {
  92. if (!HAS_L3_DPF(dev))
  93. return -EPERM;
  94. if (offset % 4 != 0)
  95. return -EINVAL;
  96. if (offset >= GEN7_L3LOG_SIZE)
  97. return -ENXIO;
  98. return 0;
  99. }
  100. static ssize_t
  101. i915_l3_read(struct file *filp, struct kobject *kobj,
  102. struct bin_attribute *attr, char *buf,
  103. loff_t offset, size_t count)
  104. {
  105. struct device *dev = container_of(kobj, struct device, kobj);
  106. struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
  107. struct drm_device *drm_dev = dminor->dev;
  108. struct drm_i915_private *dev_priv = drm_dev->dev_private;
  109. int slice = (int)(uintptr_t)attr->private;
  110. int ret;
  111. count = round_down(count, 4);
  112. ret = l3_access_valid(drm_dev, offset);
  113. if (ret)
  114. return ret;
  115. count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count);
  116. ret = i915_mutex_lock_interruptible(drm_dev);
  117. if (ret)
  118. return ret;
  119. if (dev_priv->l3_parity.remap_info[slice])
  120. memcpy(buf,
  121. dev_priv->l3_parity.remap_info[slice] + (offset/4),
  122. count);
  123. else
  124. memset(buf, 0, count);
  125. mutex_unlock(&drm_dev->struct_mutex);
  126. return count;
  127. }
  128. static ssize_t
  129. i915_l3_write(struct file *filp, struct kobject *kobj,
  130. struct bin_attribute *attr, char *buf,
  131. loff_t offset, size_t count)
  132. {
  133. struct device *dev = container_of(kobj, struct device, kobj);
  134. struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
  135. struct drm_device *drm_dev = dminor->dev;
  136. struct drm_i915_private *dev_priv = drm_dev->dev_private;
  137. struct i915_hw_context *ctx;
  138. u32 *temp = NULL; /* Just here to make handling failures easy */
  139. int slice = (int)(uintptr_t)attr->private;
  140. int ret;
  141. ret = l3_access_valid(drm_dev, offset);
  142. if (ret)
  143. return ret;
  144. if (dev_priv->hw_contexts_disabled)
  145. return -ENXIO;
  146. ret = i915_mutex_lock_interruptible(drm_dev);
  147. if (ret)
  148. return ret;
  149. if (!dev_priv->l3_parity.remap_info[slice]) {
  150. temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
  151. if (!temp) {
  152. mutex_unlock(&drm_dev->struct_mutex);
  153. return -ENOMEM;
  154. }
  155. }
  156. ret = i915_gpu_idle(drm_dev);
  157. if (ret) {
  158. kfree(temp);
  159. mutex_unlock(&drm_dev->struct_mutex);
  160. return ret;
  161. }
  162. /* TODO: Ideally we really want a GPU reset here to make sure errors
  163. * aren't propagated. Since I cannot find a stable way to reset the GPU
  164. * at this point it is left as a TODO.
  165. */
  166. if (temp)
  167. dev_priv->l3_parity.remap_info[slice] = temp;
  168. memcpy(dev_priv->l3_parity.remap_info[slice] + (offset/4), buf, count);
  169. /* NB: We defer the remapping until we switch to the context */
  170. list_for_each_entry(ctx, &dev_priv->context_list, link)
  171. ctx->remap_slice |= (1<<slice);
  172. mutex_unlock(&drm_dev->struct_mutex);
  173. return count;
  174. }
  175. static struct bin_attribute dpf_attrs = {
  176. .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
  177. .size = GEN7_L3LOG_SIZE,
  178. .read = i915_l3_read,
  179. .write = i915_l3_write,
  180. .mmap = NULL,
  181. .private = (void *)0
  182. };
  183. static struct bin_attribute dpf_attrs_1 = {
  184. .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)},
  185. .size = GEN7_L3LOG_SIZE,
  186. .read = i915_l3_read,
  187. .write = i915_l3_write,
  188. .mmap = NULL,
  189. .private = (void *)1
  190. };
  191. static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
  192. struct device_attribute *attr, char *buf)
  193. {
  194. struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
  195. struct drm_device *dev = minor->dev;
  196. struct drm_i915_private *dev_priv = dev->dev_private;
  197. int ret;
  198. mutex_lock(&dev_priv->rps.hw_lock);
  199. if (IS_VALLEYVIEW(dev_priv->dev)) {
  200. u32 freq;
  201. freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
  202. ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff);
  203. } else {
  204. ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
  205. }
  206. mutex_unlock(&dev_priv->rps.hw_lock);
  207. return snprintf(buf, PAGE_SIZE, "%d\n", ret);
  208. }
  209. static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
  210. struct device_attribute *attr, char *buf)
  211. {
  212. struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
  213. struct drm_device *dev = minor->dev;
  214. struct drm_i915_private *dev_priv = dev->dev_private;
  215. return snprintf(buf, PAGE_SIZE, "%d\n",
  216. vlv_gpu_freq(dev_priv->mem_freq,
  217. dev_priv->rps.rpe_delay));
  218. }
  219. static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
  220. {
  221. struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
  222. struct drm_device *dev = minor->dev;
  223. struct drm_i915_private *dev_priv = dev->dev_private;
  224. int ret;
  225. mutex_lock(&dev_priv->rps.hw_lock);
  226. if (IS_VALLEYVIEW(dev_priv->dev))
  227. ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.max_delay);
  228. else
  229. ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
  230. mutex_unlock(&dev_priv->rps.hw_lock);
  231. return snprintf(buf, PAGE_SIZE, "%d\n", ret);
  232. }
  233. static ssize_t gt_max_freq_mhz_store(struct device *kdev,
  234. struct device_attribute *attr,
  235. const char *buf, size_t count)
  236. {
  237. struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
  238. struct drm_device *dev = minor->dev;
  239. struct drm_i915_private *dev_priv = dev->dev_private;
  240. u32 val, rp_state_cap, hw_max, hw_min, non_oc_max;
  241. ssize_t ret;
  242. ret = kstrtou32(buf, 0, &val);
  243. if (ret)
  244. return ret;
  245. mutex_lock(&dev_priv->rps.hw_lock);
  246. if (IS_VALLEYVIEW(dev_priv->dev)) {
  247. val = vlv_freq_opcode(dev_priv->mem_freq, val);
  248. hw_max = valleyview_rps_max_freq(dev_priv);
  249. hw_min = valleyview_rps_min_freq(dev_priv);
  250. non_oc_max = hw_max;
  251. } else {
  252. val /= GT_FREQUENCY_MULTIPLIER;
  253. rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  254. hw_max = dev_priv->rps.hw_max;
  255. non_oc_max = (rp_state_cap & 0xff);
  256. hw_min = ((rp_state_cap & 0xff0000) >> 16);
  257. }
  258. if (val < hw_min || val > hw_max ||
  259. val < dev_priv->rps.min_delay) {
  260. mutex_unlock(&dev_priv->rps.hw_lock);
  261. return -EINVAL;
  262. }
  263. if (val > non_oc_max)
  264. DRM_DEBUG("User requested overclocking to %d\n",
  265. val * GT_FREQUENCY_MULTIPLIER);
  266. if (dev_priv->rps.cur_delay > val) {
  267. if (IS_VALLEYVIEW(dev_priv->dev))
  268. valleyview_set_rps(dev_priv->dev, val);
  269. else
  270. gen6_set_rps(dev_priv->dev, val);
  271. }
  272. dev_priv->rps.max_delay = val;
  273. mutex_unlock(&dev_priv->rps.hw_lock);
  274. return count;
  275. }
  276. static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
  277. {
  278. struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
  279. struct drm_device *dev = minor->dev;
  280. struct drm_i915_private *dev_priv = dev->dev_private;
  281. int ret;
  282. mutex_lock(&dev_priv->rps.hw_lock);
  283. if (IS_VALLEYVIEW(dev_priv->dev))
  284. ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.min_delay);
  285. else
  286. ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
  287. mutex_unlock(&dev_priv->rps.hw_lock);
  288. return snprintf(buf, PAGE_SIZE, "%d\n", ret);
  289. }
  290. static ssize_t gt_min_freq_mhz_store(struct device *kdev,
  291. struct device_attribute *attr,
  292. const char *buf, size_t count)
  293. {
  294. struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
  295. struct drm_device *dev = minor->dev;
  296. struct drm_i915_private *dev_priv = dev->dev_private;
  297. u32 val, rp_state_cap, hw_max, hw_min;
  298. ssize_t ret;
  299. ret = kstrtou32(buf, 0, &val);
  300. if (ret)
  301. return ret;
  302. mutex_lock(&dev_priv->rps.hw_lock);
  303. if (IS_VALLEYVIEW(dev)) {
  304. val = vlv_freq_opcode(dev_priv->mem_freq, val);
  305. hw_max = valleyview_rps_max_freq(dev_priv);
  306. hw_min = valleyview_rps_min_freq(dev_priv);
  307. } else {
  308. val /= GT_FREQUENCY_MULTIPLIER;
  309. rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  310. hw_max = dev_priv->rps.hw_max;
  311. hw_min = ((rp_state_cap & 0xff0000) >> 16);
  312. }
  313. if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) {
  314. mutex_unlock(&dev_priv->rps.hw_lock);
  315. return -EINVAL;
  316. }
  317. if (dev_priv->rps.cur_delay < val) {
  318. if (IS_VALLEYVIEW(dev))
  319. valleyview_set_rps(dev, val);
  320. else
  321. gen6_set_rps(dev_priv->dev, val);
  322. }
  323. dev_priv->rps.min_delay = val;
  324. mutex_unlock(&dev_priv->rps.hw_lock);
  325. return count;
  326. }
  327. static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
  328. static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
  329. static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
  330. static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL);
  331. static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
  332. static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
  333. static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
  334. static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
  335. /* For now we have a static number of RP states */
  336. static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
  337. {
  338. struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
  339. struct drm_device *dev = minor->dev;
  340. struct drm_i915_private *dev_priv = dev->dev_private;
  341. u32 val, rp_state_cap;
  342. ssize_t ret;
  343. ret = mutex_lock_interruptible(&dev->struct_mutex);
  344. if (ret)
  345. return ret;
  346. rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  347. mutex_unlock(&dev->struct_mutex);
  348. if (attr == &dev_attr_gt_RP0_freq_mhz) {
  349. val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
  350. } else if (attr == &dev_attr_gt_RP1_freq_mhz) {
  351. val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
  352. } else if (attr == &dev_attr_gt_RPn_freq_mhz) {
  353. val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
  354. } else {
  355. BUG();
  356. }
  357. return snprintf(buf, PAGE_SIZE, "%d\n", val);
  358. }
  359. static const struct attribute *gen6_attrs[] = {
  360. &dev_attr_gt_cur_freq_mhz.attr,
  361. &dev_attr_gt_max_freq_mhz.attr,
  362. &dev_attr_gt_min_freq_mhz.attr,
  363. &dev_attr_gt_RP0_freq_mhz.attr,
  364. &dev_attr_gt_RP1_freq_mhz.attr,
  365. &dev_attr_gt_RPn_freq_mhz.attr,
  366. NULL,
  367. };
  368. static const struct attribute *vlv_attrs[] = {
  369. &dev_attr_gt_cur_freq_mhz.attr,
  370. &dev_attr_gt_max_freq_mhz.attr,
  371. &dev_attr_gt_min_freq_mhz.attr,
  372. &dev_attr_vlv_rpe_freq_mhz.attr,
  373. NULL,
  374. };
  375. static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
  376. struct bin_attribute *attr, char *buf,
  377. loff_t off, size_t count)
  378. {
  379. struct device *kdev = container_of(kobj, struct device, kobj);
  380. struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
  381. struct drm_device *dev = minor->dev;
  382. struct i915_error_state_file_priv error_priv;
  383. struct drm_i915_error_state_buf error_str;
  384. ssize_t ret_count = 0;
  385. int ret;
  386. memset(&error_priv, 0, sizeof(error_priv));
  387. ret = i915_error_state_buf_init(&error_str, count, off);
  388. if (ret)
  389. return ret;
  390. error_priv.dev = dev;
  391. i915_error_state_get(dev, &error_priv);
  392. ret = i915_error_state_to_str(&error_str, &error_priv);
  393. if (ret)
  394. goto out;
  395. ret_count = count < error_str.bytes ? count : error_str.bytes;
  396. memcpy(buf, error_str.buf, ret_count);
  397. out:
  398. i915_error_state_put(&error_priv);
  399. i915_error_state_buf_release(&error_str);
  400. return ret ?: ret_count;
  401. }
  402. static ssize_t error_state_write(struct file *file, struct kobject *kobj,
  403. struct bin_attribute *attr, char *buf,
  404. loff_t off, size_t count)
  405. {
  406. struct device *kdev = container_of(kobj, struct device, kobj);
  407. struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
  408. struct drm_device *dev = minor->dev;
  409. int ret;
  410. DRM_DEBUG_DRIVER("Resetting error state\n");
  411. ret = mutex_lock_interruptible(&dev->struct_mutex);
  412. if (ret)
  413. return ret;
  414. i915_destroy_error_state(dev);
  415. mutex_unlock(&dev->struct_mutex);
  416. return count;
  417. }
  418. static struct bin_attribute error_state_attr = {
  419. .attr.name = "error",
  420. .attr.mode = S_IRUSR | S_IWUSR,
  421. .size = 0,
  422. .read = error_state_read,
  423. .write = error_state_write,
  424. };
  425. void i915_setup_sysfs(struct drm_device *dev)
  426. {
  427. int ret;
  428. #ifdef CONFIG_PM
  429. if (INTEL_INFO(dev)->gen >= 6) {
  430. ret = sysfs_merge_group(&dev->primary->kdev.kobj,
  431. &rc6_attr_group);
  432. if (ret)
  433. DRM_ERROR("RC6 residency sysfs setup failed\n");
  434. }
  435. #endif
  436. if (HAS_L3_DPF(dev)) {
  437. ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs);
  438. if (ret)
  439. DRM_ERROR("l3 parity sysfs setup failed\n");
  440. if (NUM_L3_SLICES(dev) > 1) {
  441. ret = device_create_bin_file(&dev->primary->kdev,
  442. &dpf_attrs_1);
  443. if (ret)
  444. DRM_ERROR("l3 parity slice 1 setup failed\n");
  445. }
  446. }
  447. ret = 0;
  448. if (IS_VALLEYVIEW(dev))
  449. ret = sysfs_create_files(&dev->primary->kdev.kobj, vlv_attrs);
  450. else if (INTEL_INFO(dev)->gen >= 6)
  451. ret = sysfs_create_files(&dev->primary->kdev.kobj, gen6_attrs);
  452. if (ret)
  453. DRM_ERROR("RPS sysfs setup failed\n");
  454. ret = sysfs_create_bin_file(&dev->primary->kdev.kobj,
  455. &error_state_attr);
  456. if (ret)
  457. DRM_ERROR("error_state sysfs setup failed\n");
  458. }
  459. void i915_teardown_sysfs(struct drm_device *dev)
  460. {
  461. sysfs_remove_bin_file(&dev->primary->kdev.kobj, &error_state_attr);
  462. if (IS_VALLEYVIEW(dev))
  463. sysfs_remove_files(&dev->primary->kdev.kobj, vlv_attrs);
  464. else
  465. sysfs_remove_files(&dev->primary->kdev.kobj, gen6_attrs);
  466. device_remove_bin_file(&dev->primary->kdev, &dpf_attrs_1);
  467. device_remove_bin_file(&dev->primary->kdev, &dpf_attrs);
  468. #ifdef CONFIG_PM
  469. sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group);
  470. #endif
  471. }