at91sam9g45.dtsi 9.1 KB

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  1. /*
  2. * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
  3. * applies to AT91SAM9G45, AT91SAM9M10,
  4. * AT91SAM9G46, AT91SAM9M11 SoC
  5. *
  6. * Copyright (C) 2011 Atmel,
  7. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9G45 family SoC";
  14. compatible = "atmel,at91sam9g45";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. serial4 = &usart3;
  22. gpio0 = &pioA;
  23. gpio1 = &pioB;
  24. gpio2 = &pioC;
  25. gpio3 = &pioD;
  26. gpio4 = &pioE;
  27. tcb0 = &tcb0;
  28. tcb1 = &tcb1;
  29. i2c0 = &i2c0;
  30. i2c1 = &i2c1;
  31. };
  32. cpus {
  33. cpu@0 {
  34. compatible = "arm,arm926ejs";
  35. };
  36. };
  37. memory {
  38. reg = <0x70000000 0x10000000>;
  39. };
  40. ahb {
  41. compatible = "simple-bus";
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. ranges;
  45. apb {
  46. compatible = "simple-bus";
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. ranges;
  50. aic: interrupt-controller@fffff000 {
  51. #interrupt-cells = <3>;
  52. compatible = "atmel,at91rm9200-aic";
  53. interrupt-controller;
  54. reg = <0xfffff000 0x200>;
  55. atmel,external-irqs = <31>;
  56. };
  57. ramc0: ramc@ffffe400 {
  58. compatible = "atmel,at91sam9g45-ddramc";
  59. reg = <0xffffe400 0x200
  60. 0xffffe600 0x200>;
  61. };
  62. pmc: pmc@fffffc00 {
  63. compatible = "atmel,at91rm9200-pmc";
  64. reg = <0xfffffc00 0x100>;
  65. };
  66. rstc@fffffd00 {
  67. compatible = "atmel,at91sam9g45-rstc";
  68. reg = <0xfffffd00 0x10>;
  69. };
  70. pit: timer@fffffd30 {
  71. compatible = "atmel,at91sam9260-pit";
  72. reg = <0xfffffd30 0xf>;
  73. interrupts = <1 4 7>;
  74. };
  75. shdwc@fffffd10 {
  76. compatible = "atmel,at91sam9rl-shdwc";
  77. reg = <0xfffffd10 0x10>;
  78. };
  79. tcb0: timer@fff7c000 {
  80. compatible = "atmel,at91rm9200-tcb";
  81. reg = <0xfff7c000 0x100>;
  82. interrupts = <18 4 0>;
  83. };
  84. tcb1: timer@fffd4000 {
  85. compatible = "atmel,at91rm9200-tcb";
  86. reg = <0xfffd4000 0x100>;
  87. interrupts = <18 4 0>;
  88. };
  89. dma: dma-controller@ffffec00 {
  90. compatible = "atmel,at91sam9g45-dma";
  91. reg = <0xffffec00 0x200>;
  92. interrupts = <21 4 0>;
  93. };
  94. pinctrl@fffff200 {
  95. #address-cells = <1>;
  96. #size-cells = <1>;
  97. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  98. ranges = <0xfffff200 0xfffff200 0xa00>;
  99. atmel,mux-mask = <
  100. /* A B */
  101. 0xffffffff 0xffc003ff /* pioA */
  102. 0xffffffff 0x800f8f00 /* pioB */
  103. 0xffffffff 0x00000e00 /* pioC */
  104. 0xffffffff 0xff0c1381 /* pioD */
  105. 0xffffffff 0x81ffff81 /* pioE */
  106. >;
  107. /* shared pinctrl settings */
  108. dbgu {
  109. pinctrl_dbgu: dbgu-0 {
  110. atmel,pins =
  111. <1 12 0x1 0x0 /* PB12 periph A */
  112. 1 13 0x1 0x0>; /* PB13 periph A */
  113. };
  114. };
  115. uart0 {
  116. pinctrl_uart0: uart0-0 {
  117. atmel,pins =
  118. <1 19 0x1 0x1 /* PB19 periph A with pullup */
  119. 1 18 0x1 0x0>; /* PB18 periph A */
  120. };
  121. pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
  122. atmel,pins =
  123. <1 17 0x2 0x0 /* PB17 periph B */
  124. 1 15 0x2 0x0>; /* PB15 periph B */
  125. };
  126. };
  127. uart1 {
  128. pinctrl_uart1: uart1-0 {
  129. atmel,pins =
  130. <1 4 0x1 0x1 /* PB4 periph A with pullup */
  131. 1 5 0x1 0x0>; /* PB5 periph A */
  132. };
  133. pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
  134. atmel,pins =
  135. <3 16 0x1 0x0 /* PD16 periph A */
  136. 3 17 0x1 0x0>; /* PD17 periph A */
  137. };
  138. };
  139. uart2 {
  140. pinctrl_uart2: uart2-0 {
  141. atmel,pins =
  142. <1 6 0x1 0x1 /* PB6 periph A with pullup */
  143. 1 7 0x1 0x0>; /* PB7 periph A */
  144. };
  145. pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
  146. atmel,pins =
  147. <2 9 0x2 0x0 /* PC9 periph B */
  148. 2 11 0x2 0x0>; /* PC11 periph B */
  149. };
  150. };
  151. uart3 {
  152. pinctrl_uart3: uart3-0 {
  153. atmel,pins =
  154. <1 8 0x1 0x1 /* PB9 periph A with pullup */
  155. 1 9 0x1 0x0>; /* PB8 periph A */
  156. };
  157. pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
  158. atmel,pins =
  159. <0 23 0x2 0x0 /* PA23 periph B */
  160. 0 24 0x2 0x0>; /* PA24 periph B */
  161. };
  162. };
  163. nand {
  164. pinctrl_nand: nand-0 {
  165. atmel,pins =
  166. <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/
  167. 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
  168. };
  169. };
  170. pioA: gpio@fffff200 {
  171. compatible = "atmel,at91rm9200-gpio";
  172. reg = <0xfffff200 0x200>;
  173. interrupts = <2 4 1>;
  174. #gpio-cells = <2>;
  175. gpio-controller;
  176. interrupt-controller;
  177. #interrupt-cells = <2>;
  178. };
  179. pioB: gpio@fffff400 {
  180. compatible = "atmel,at91rm9200-gpio";
  181. reg = <0xfffff400 0x200>;
  182. interrupts = <3 4 1>;
  183. #gpio-cells = <2>;
  184. gpio-controller;
  185. interrupt-controller;
  186. #interrupt-cells = <2>;
  187. };
  188. pioC: gpio@fffff600 {
  189. compatible = "atmel,at91rm9200-gpio";
  190. reg = <0xfffff600 0x200>;
  191. interrupts = <4 4 1>;
  192. #gpio-cells = <2>;
  193. gpio-controller;
  194. interrupt-controller;
  195. #interrupt-cells = <2>;
  196. };
  197. pioD: gpio@fffff800 {
  198. compatible = "atmel,at91rm9200-gpio";
  199. reg = <0xfffff800 0x200>;
  200. interrupts = <5 4 1>;
  201. #gpio-cells = <2>;
  202. gpio-controller;
  203. interrupt-controller;
  204. #interrupt-cells = <2>;
  205. };
  206. pioE: gpio@fffffa00 {
  207. compatible = "atmel,at91rm9200-gpio";
  208. reg = <0xfffffa00 0x200>;
  209. interrupts = <5 4 1>;
  210. #gpio-cells = <2>;
  211. gpio-controller;
  212. interrupt-controller;
  213. #interrupt-cells = <2>;
  214. };
  215. };
  216. dbgu: serial@ffffee00 {
  217. compatible = "atmel,at91sam9260-usart";
  218. reg = <0xffffee00 0x200>;
  219. interrupts = <1 4 7>;
  220. pinctrl-names = "default";
  221. pinctrl-0 = <&pinctrl_dbgu>;
  222. status = "disabled";
  223. };
  224. usart0: serial@fff8c000 {
  225. compatible = "atmel,at91sam9260-usart";
  226. reg = <0xfff8c000 0x200>;
  227. interrupts = <7 4 5>;
  228. atmel,use-dma-rx;
  229. atmel,use-dma-tx;
  230. pinctrl-names = "default";
  231. pinctrl-0 = <&pinctrl_uart0>;
  232. status = "disabled";
  233. };
  234. usart1: serial@fff90000 {
  235. compatible = "atmel,at91sam9260-usart";
  236. reg = <0xfff90000 0x200>;
  237. interrupts = <8 4 5>;
  238. atmel,use-dma-rx;
  239. atmel,use-dma-tx;
  240. pinctrl-names = "default";
  241. pinctrl-0 = <&pinctrl_uart1>;
  242. status = "disabled";
  243. };
  244. usart2: serial@fff94000 {
  245. compatible = "atmel,at91sam9260-usart";
  246. reg = <0xfff94000 0x200>;
  247. interrupts = <9 4 5>;
  248. atmel,use-dma-rx;
  249. atmel,use-dma-tx;
  250. pinctrl-names = "default";
  251. pinctrl-0 = <&pinctrl_uart2>;
  252. status = "disabled";
  253. };
  254. usart3: serial@fff98000 {
  255. compatible = "atmel,at91sam9260-usart";
  256. reg = <0xfff98000 0x200>;
  257. interrupts = <10 4 5>;
  258. atmel,use-dma-rx;
  259. atmel,use-dma-tx;
  260. pinctrl-names = "default";
  261. pinctrl-0 = <&pinctrl_uart3>;
  262. status = "disabled";
  263. };
  264. macb0: ethernet@fffbc000 {
  265. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  266. reg = <0xfffbc000 0x100>;
  267. interrupts = <25 4 3>;
  268. status = "disabled";
  269. };
  270. i2c0: i2c@fff84000 {
  271. compatible = "atmel,at91sam9g10-i2c";
  272. reg = <0xfff84000 0x100>;
  273. interrupts = <12 4 6>;
  274. #address-cells = <1>;
  275. #size-cells = <0>;
  276. status = "disabled";
  277. };
  278. i2c1: i2c@fff88000 {
  279. compatible = "atmel,at91sam9g10-i2c";
  280. reg = <0xfff88000 0x100>;
  281. interrupts = <13 4 6>;
  282. #address-cells = <1>;
  283. #size-cells = <0>;
  284. status = "disabled";
  285. };
  286. adc0: adc@fffb0000 {
  287. compatible = "atmel,at91sam9260-adc";
  288. reg = <0xfffb0000 0x100>;
  289. interrupts = <20 4 0>;
  290. atmel,adc-use-external-triggers;
  291. atmel,adc-channels-used = <0xff>;
  292. atmel,adc-vref = <3300>;
  293. atmel,adc-num-channels = <8>;
  294. atmel,adc-startup-time = <40>;
  295. atmel,adc-channel-base = <0x30>;
  296. atmel,adc-drdy-mask = <0x10000>;
  297. atmel,adc-status-register = <0x1c>;
  298. atmel,adc-trigger-register = <0x08>;
  299. trigger@0 {
  300. trigger-name = "external-rising";
  301. trigger-value = <0x1>;
  302. trigger-external;
  303. };
  304. trigger@1 {
  305. trigger-name = "external-falling";
  306. trigger-value = <0x2>;
  307. trigger-external;
  308. };
  309. trigger@2 {
  310. trigger-name = "external-any";
  311. trigger-value = <0x3>;
  312. trigger-external;
  313. };
  314. trigger@3 {
  315. trigger-name = "continuous";
  316. trigger-value = <0x6>;
  317. };
  318. };
  319. };
  320. nand0: nand@40000000 {
  321. compatible = "atmel,at91rm9200-nand";
  322. #address-cells = <1>;
  323. #size-cells = <1>;
  324. reg = <0x40000000 0x10000000
  325. 0xffffe200 0x200
  326. >;
  327. atmel,nand-addr-offset = <21>;
  328. atmel,nand-cmd-offset = <22>;
  329. pinctrl-names = "default";
  330. pinctrl-0 = <&pinctrl_nand>;
  331. gpios = <&pioC 8 0
  332. &pioC 14 0
  333. 0
  334. >;
  335. status = "disabled";
  336. };
  337. usb0: ohci@00700000 {
  338. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  339. reg = <0x00700000 0x100000>;
  340. interrupts = <22 4 2>;
  341. status = "disabled";
  342. };
  343. usb1: ehci@00800000 {
  344. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  345. reg = <0x00800000 0x100000>;
  346. interrupts = <22 4 2>;
  347. status = "disabled";
  348. };
  349. };
  350. i2c@0 {
  351. compatible = "i2c-gpio";
  352. gpios = <&pioA 20 0 /* sda */
  353. &pioA 21 0 /* scl */
  354. >;
  355. i2c-gpio,sda-open-drain;
  356. i2c-gpio,scl-open-drain;
  357. i2c-gpio,delay-us = <5>; /* ~100 kHz */
  358. #address-cells = <1>;
  359. #size-cells = <0>;
  360. status = "disabled";
  361. };
  362. };