wa.c 19 KB

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  1. /*
  2. Broadcom B43 wireless driver
  3. PHY workarounds.
  4. Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
  5. Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; either version 2 of the License, or
  9. (at your option) any later version.
  10. This program is distributed in the hope that it will be useful,
  11. but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. GNU General Public License for more details.
  14. You should have received a copy of the GNU General Public License
  15. along with this program; see the file COPYING. If not, write to
  16. the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  17. Boston, MA 02110-1301, USA.
  18. */
  19. #include "b43.h"
  20. #include "main.h"
  21. #include "tables.h"
  22. #include "phy_common.h"
  23. #include "wa.h"
  24. static void b43_wa_papd(struct b43_wldev *dev)
  25. {
  26. u16 backup;
  27. backup = b43_ofdmtab_read16(dev, B43_OFDMTAB_PWRDYN2, 0);
  28. b43_ofdmtab_write16(dev, B43_OFDMTAB_PWRDYN2, 0, 7);
  29. b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_APHY, 0, 0);
  30. b43_dummy_transmission(dev);
  31. b43_ofdmtab_write16(dev, B43_OFDMTAB_PWRDYN2, 0, backup);
  32. }
  33. static void b43_wa_auxclipthr(struct b43_wldev *dev)
  34. {
  35. b43_phy_write(dev, B43_PHY_OFDM(0x8E), 0x3800);
  36. }
  37. static void b43_wa_afcdac(struct b43_wldev *dev)
  38. {
  39. b43_phy_write(dev, 0x0035, 0x03FF);
  40. b43_phy_write(dev, 0x0036, 0x0400);
  41. }
  42. static void b43_wa_txdc_offset(struct b43_wldev *dev)
  43. {
  44. b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 0, 0x0051);
  45. }
  46. void b43_wa_initgains(struct b43_wldev *dev)
  47. {
  48. struct b43_phy *phy = &dev->phy;
  49. b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9);
  50. b43_phy_write(dev, B43_PHY_LPFGAINCTL,
  51. b43_phy_read(dev, B43_PHY_LPFGAINCTL) & 0xFF0F);
  52. if (phy->rev <= 2)
  53. b43_ofdmtab_write16(dev, B43_OFDMTAB_LPFGAIN, 0, 0x1FBF);
  54. b43_radio_write16(dev, 0x0002, 0x1FBF);
  55. b43_phy_write(dev, 0x0024, 0x4680);
  56. b43_phy_write(dev, 0x0020, 0x0003);
  57. b43_phy_write(dev, 0x001D, 0x0F40);
  58. b43_phy_write(dev, 0x001F, 0x1C00);
  59. if (phy->rev <= 3)
  60. b43_phy_write(dev, 0x002A,
  61. (b43_phy_read(dev, 0x002A) & 0x00FF) | 0x0400);
  62. else if (phy->rev == 5) {
  63. b43_phy_write(dev, 0x002A,
  64. (b43_phy_read(dev, 0x002A) & 0x00FF) | 0x1A00);
  65. b43_phy_write(dev, 0x00CC, 0x2121);
  66. }
  67. if (phy->rev >= 3)
  68. b43_phy_write(dev, 0x00BA, 0x3ED5);
  69. }
  70. static void b43_wa_divider(struct b43_wldev *dev)
  71. {
  72. b43_phy_write(dev, 0x002B, b43_phy_read(dev, 0x002B) & ~0x0100);
  73. b43_phy_write(dev, 0x008E, 0x58C1);
  74. }
  75. static void b43_wa_gt(struct b43_wldev *dev) /* Gain table. */
  76. {
  77. if (dev->phy.rev <= 2) {
  78. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 0, 15);
  79. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 1, 31);
  80. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 2, 42);
  81. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 3, 48);
  82. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 4, 58);
  83. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 0, 19);
  84. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 1, 19);
  85. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 2, 19);
  86. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 3, 19);
  87. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 4, 21);
  88. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 5, 21);
  89. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 6, 25);
  90. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 0, 3);
  91. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 1, 3);
  92. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 2, 7);
  93. } else {
  94. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 0, 19);
  95. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 1, 19);
  96. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 2, 19);
  97. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 3, 19);
  98. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 4, 21);
  99. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 5, 21);
  100. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 6, 25);
  101. }
  102. }
  103. static void b43_wa_rssi_lt(struct b43_wldev *dev) /* RSSI lookup table */
  104. {
  105. int i;
  106. if (0 /* FIXME: For APHY.rev=2 this might be needed */) {
  107. for (i = 0; i < 8; i++)
  108. b43_ofdmtab_write16(dev, B43_OFDMTAB_RSSI, i, i + 8);
  109. for (i = 8; i < 16; i++)
  110. b43_ofdmtab_write16(dev, B43_OFDMTAB_RSSI, i, i - 8);
  111. } else {
  112. for (i = 0; i < 64; i++)
  113. b43_ofdmtab_write16(dev, B43_OFDMTAB_RSSI, i, i);
  114. }
  115. }
  116. static void b43_wa_analog(struct b43_wldev *dev)
  117. {
  118. struct b43_phy *phy = &dev->phy;
  119. u16 ofdmrev;
  120. ofdmrev = b43_phy_read(dev, B43_PHY_VERSION_OFDM) & B43_PHYVER_VERSION;
  121. if (ofdmrev > 2) {
  122. if (phy->type == B43_PHYTYPE_A)
  123. b43_phy_write(dev, B43_PHY_PWRDOWN, 0x1808);
  124. else
  125. b43_phy_write(dev, B43_PHY_PWRDOWN, 0x1000);
  126. } else {
  127. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 3, 0x1044);
  128. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 4, 0x7201);
  129. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 6, 0x0040);
  130. }
  131. }
  132. static void b43_wa_dac(struct b43_wldev *dev)
  133. {
  134. if (dev->phy.analog == 1)
  135. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1,
  136. (b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 1) & ~0x0034) | 0x0008);
  137. else
  138. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1,
  139. (b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 1) & ~0x0078) | 0x0010);
  140. }
  141. static void b43_wa_fft(struct b43_wldev *dev) /* Fine frequency table */
  142. {
  143. int i;
  144. if (dev->phy.type == B43_PHYTYPE_A)
  145. for (i = 0; i < B43_TAB_FINEFREQA_SIZE; i++)
  146. b43_ofdmtab_write16(dev, B43_OFDMTAB_DACRFPABB, i, b43_tab_finefreqa[i]);
  147. else
  148. for (i = 0; i < B43_TAB_FINEFREQG_SIZE; i++)
  149. b43_ofdmtab_write16(dev, B43_OFDMTAB_DACRFPABB, i, b43_tab_finefreqg[i]);
  150. }
  151. static void b43_wa_nft(struct b43_wldev *dev) /* Noise figure table */
  152. {
  153. struct b43_phy *phy = &dev->phy;
  154. int i;
  155. if (phy->type == B43_PHYTYPE_A) {
  156. if (phy->rev == 2)
  157. for (i = 0; i < B43_TAB_NOISEA2_SIZE; i++)
  158. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noisea2[i]);
  159. else
  160. for (i = 0; i < B43_TAB_NOISEA3_SIZE; i++)
  161. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noisea3[i]);
  162. } else {
  163. if (phy->rev == 1)
  164. for (i = 0; i < B43_TAB_NOISEG1_SIZE; i++)
  165. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noiseg1[i]);
  166. else
  167. for (i = 0; i < B43_TAB_NOISEG2_SIZE; i++)
  168. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noiseg2[i]);
  169. }
  170. }
  171. static void b43_wa_rt(struct b43_wldev *dev) /* Rotor table */
  172. {
  173. int i;
  174. for (i = 0; i < B43_TAB_ROTOR_SIZE; i++)
  175. b43_ofdmtab_write32(dev, B43_OFDMTAB_ROTOR, i, b43_tab_rotor[i]);
  176. }
  177. static void b43_write_null_nst(struct b43_wldev *dev)
  178. {
  179. int i;
  180. for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
  181. b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE, i, 0);
  182. }
  183. static void b43_write_nst(struct b43_wldev *dev, const u16 *nst)
  184. {
  185. int i;
  186. for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
  187. b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE, i, nst[i]);
  188. }
  189. static void b43_wa_nst(struct b43_wldev *dev) /* Noise scale table */
  190. {
  191. struct b43_phy *phy = &dev->phy;
  192. if (phy->type == B43_PHYTYPE_A) {
  193. if (phy->rev <= 1)
  194. b43_write_null_nst(dev);
  195. else if (phy->rev == 2)
  196. b43_write_nst(dev, b43_tab_noisescalea2);
  197. else if (phy->rev == 3)
  198. b43_write_nst(dev, b43_tab_noisescalea3);
  199. else
  200. b43_write_nst(dev, b43_tab_noisescaleg3);
  201. } else {
  202. if (phy->rev >= 6) {
  203. if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN)
  204. b43_write_nst(dev, b43_tab_noisescaleg3);
  205. else
  206. b43_write_nst(dev, b43_tab_noisescaleg2);
  207. } else {
  208. b43_write_nst(dev, b43_tab_noisescaleg1);
  209. }
  210. }
  211. }
  212. static void b43_wa_art(struct b43_wldev *dev) /* ADV retard table */
  213. {
  214. int i;
  215. for (i = 0; i < B43_TAB_RETARD_SIZE; i++)
  216. b43_ofdmtab_write32(dev, B43_OFDMTAB_ADVRETARD,
  217. i, b43_tab_retard[i]);
  218. }
  219. static void b43_wa_txlna_gain(struct b43_wldev *dev)
  220. {
  221. b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 13, 0x0000);
  222. }
  223. static void b43_wa_crs_reset(struct b43_wldev *dev)
  224. {
  225. b43_phy_write(dev, 0x002C, 0x0064);
  226. }
  227. static void b43_wa_2060txlna_gain(struct b43_wldev *dev)
  228. {
  229. b43_hf_write(dev, b43_hf_read(dev) |
  230. B43_HF_2060W);
  231. }
  232. static void b43_wa_lms(struct b43_wldev *dev)
  233. {
  234. b43_phy_write(dev, 0x0055,
  235. (b43_phy_read(dev, 0x0055) & 0xFFC0) | 0x0004);
  236. }
  237. static void b43_wa_mixedsignal(struct b43_wldev *dev)
  238. {
  239. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1, 3);
  240. }
  241. static void b43_wa_msst(struct b43_wldev *dev) /* Min sigma square table */
  242. {
  243. struct b43_phy *phy = &dev->phy;
  244. int i;
  245. const u16 *tab;
  246. if (phy->type == B43_PHYTYPE_A) {
  247. tab = b43_tab_sigmasqr1;
  248. } else if (phy->type == B43_PHYTYPE_G) {
  249. tab = b43_tab_sigmasqr2;
  250. } else {
  251. B43_WARN_ON(1);
  252. return;
  253. }
  254. for (i = 0; i < B43_TAB_SIGMASQR_SIZE; i++) {
  255. b43_ofdmtab_write16(dev, B43_OFDMTAB_MINSIGSQ,
  256. i, tab[i]);
  257. }
  258. }
  259. static void b43_wa_iqadc(struct b43_wldev *dev)
  260. {
  261. if (dev->phy.analog == 4)
  262. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 0,
  263. b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 0) & ~0xF000);
  264. }
  265. static void b43_wa_crs_ed(struct b43_wldev *dev)
  266. {
  267. struct b43_phy *phy = &dev->phy;
  268. if (phy->rev == 1) {
  269. b43_phy_write(dev, B43_PHY_CRSTHRES1_R1, 0x4F19);
  270. } else if (phy->rev == 2) {
  271. b43_phy_write(dev, B43_PHY_CRSTHRES1, 0x1861);
  272. b43_phy_write(dev, B43_PHY_CRSTHRES2, 0x0271);
  273. b43_phy_set(dev, B43_PHY_ANTDWELL, 0x0800);
  274. } else {
  275. b43_phy_write(dev, B43_PHY_CRSTHRES1, 0x0098);
  276. b43_phy_write(dev, B43_PHY_CRSTHRES2, 0x0070);
  277. b43_phy_write(dev, B43_PHY_OFDM(0xC9), 0x0080);
  278. b43_phy_set(dev, B43_PHY_ANTDWELL, 0x0800);
  279. }
  280. }
  281. static void b43_wa_crs_thr(struct b43_wldev *dev)
  282. {
  283. b43_phy_write(dev, B43_PHY_CRS0,
  284. (b43_phy_read(dev, B43_PHY_CRS0) & ~0x03C0) | 0xD000);
  285. }
  286. static void b43_wa_crs_blank(struct b43_wldev *dev)
  287. {
  288. b43_phy_write(dev, B43_PHY_OFDM(0x2C), 0x005A);
  289. }
  290. static void b43_wa_cck_shiftbits(struct b43_wldev *dev)
  291. {
  292. b43_phy_write(dev, B43_PHY_CCKSHIFTBITS, 0x0026);
  293. }
  294. static void b43_wa_wrssi_offset(struct b43_wldev *dev)
  295. {
  296. int i;
  297. if (dev->phy.rev == 1) {
  298. for (i = 0; i < 16; i++) {
  299. b43_ofdmtab_write16(dev, B43_OFDMTAB_WRSSI_R1,
  300. i, 0x0020);
  301. }
  302. } else {
  303. for (i = 0; i < 32; i++) {
  304. b43_ofdmtab_write16(dev, B43_OFDMTAB_WRSSI,
  305. i, 0x0820);
  306. }
  307. }
  308. }
  309. static void b43_wa_txpuoff_rxpuon(struct b43_wldev *dev)
  310. {
  311. b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_0F, 2, 15);
  312. b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_0F, 3, 20);
  313. }
  314. static void b43_wa_altagc(struct b43_wldev *dev)
  315. {
  316. struct b43_phy *phy = &dev->phy;
  317. if (phy->rev == 1) {
  318. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 254);
  319. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 1, 13);
  320. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 2, 19);
  321. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 3, 25);
  322. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 0, 0x2710);
  323. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 1, 0x9B83);
  324. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 2, 0x9B83);
  325. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 3, 0x0F8D);
  326. b43_phy_write(dev, B43_PHY_LMS, 4);
  327. } else {
  328. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0, 254);
  329. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 1, 13);
  330. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 2, 19);
  331. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 3, 25);
  332. }
  333. b43_phy_write(dev, B43_PHY_CCKSHIFTBITS_WA,
  334. (b43_phy_read(dev, B43_PHY_CCKSHIFTBITS_WA) & ~0xFF00) | 0x5700);
  335. b43_phy_write(dev, B43_PHY_OFDM(0x1A),
  336. (b43_phy_read(dev, B43_PHY_OFDM(0x1A)) & ~0x007F) | 0x000F);
  337. b43_phy_write(dev, B43_PHY_OFDM(0x1A),
  338. (b43_phy_read(dev, B43_PHY_OFDM(0x1A)) & ~0x3F80) | 0x2B80);
  339. b43_phy_write(dev, B43_PHY_ANTWRSETT,
  340. (b43_phy_read(dev, B43_PHY_ANTWRSETT) & 0xF0FF) | 0x0300);
  341. b43_radio_write16(dev, 0x7A,
  342. b43_radio_read16(dev, 0x7A) | 0x0008);
  343. b43_phy_write(dev, B43_PHY_N1P1GAIN,
  344. (b43_phy_read(dev, B43_PHY_N1P1GAIN) & ~0x000F) | 0x0008);
  345. b43_phy_write(dev, B43_PHY_P1P2GAIN,
  346. (b43_phy_read(dev, B43_PHY_P1P2GAIN) & ~0x0F00) | 0x0600);
  347. b43_phy_write(dev, B43_PHY_N1N2GAIN,
  348. (b43_phy_read(dev, B43_PHY_N1N2GAIN) & ~0x0F00) | 0x0700);
  349. b43_phy_write(dev, B43_PHY_N1P1GAIN,
  350. (b43_phy_read(dev, B43_PHY_N1P1GAIN) & ~0x0F00) | 0x0100);
  351. if (phy->rev == 1) {
  352. b43_phy_write(dev, B43_PHY_N1N2GAIN,
  353. (b43_phy_read(dev, B43_PHY_N1N2GAIN)
  354. & ~0x000F) | 0x0007);
  355. }
  356. b43_phy_write(dev, B43_PHY_OFDM(0x88),
  357. (b43_phy_read(dev, B43_PHY_OFDM(0x88)) & ~0x00FF) | 0x001C);
  358. b43_phy_write(dev, B43_PHY_OFDM(0x88),
  359. (b43_phy_read(dev, B43_PHY_OFDM(0x88)) & ~0x3F00) | 0x0200);
  360. b43_phy_write(dev, B43_PHY_OFDM(0x96),
  361. (b43_phy_read(dev, B43_PHY_OFDM(0x96)) & ~0x00FF) | 0x001C);
  362. b43_phy_write(dev, B43_PHY_OFDM(0x89),
  363. (b43_phy_read(dev, B43_PHY_OFDM(0x89)) & ~0x00FF) | 0x0020);
  364. b43_phy_write(dev, B43_PHY_OFDM(0x89),
  365. (b43_phy_read(dev, B43_PHY_OFDM(0x89)) & ~0x3F00) | 0x0200);
  366. b43_phy_write(dev, B43_PHY_OFDM(0x82),
  367. (b43_phy_read(dev, B43_PHY_OFDM(0x82)) & ~0x00FF) | 0x002E);
  368. b43_phy_write(dev, B43_PHY_OFDM(0x96),
  369. (b43_phy_read(dev, B43_PHY_OFDM(0x96)) & ~0xFF00) | 0x1A00);
  370. b43_phy_write(dev, B43_PHY_OFDM(0x81),
  371. (b43_phy_read(dev, B43_PHY_OFDM(0x81)) & ~0x00FF) | 0x0028);
  372. b43_phy_write(dev, B43_PHY_OFDM(0x81),
  373. (b43_phy_read(dev, B43_PHY_OFDM(0x81)) & ~0xFF00) | 0x2C00);
  374. if (phy->rev == 1) {
  375. b43_phy_write(dev, B43_PHY_PEAK_COUNT, 0x092B);
  376. b43_phy_write(dev, B43_PHY_OFDM(0x1B),
  377. (b43_phy_read(dev, B43_PHY_OFDM(0x1B)) & ~0x001E) | 0x0002);
  378. } else {
  379. b43_phy_write(dev, B43_PHY_OFDM(0x1B),
  380. b43_phy_read(dev, B43_PHY_OFDM(0x1B)) & ~0x001E);
  381. b43_phy_write(dev, B43_PHY_OFDM(0x1F), 0x287A);
  382. b43_phy_write(dev, B43_PHY_LPFGAINCTL,
  383. (b43_phy_read(dev, B43_PHY_LPFGAINCTL) & ~0x000F) | 0x0004);
  384. if (phy->rev >= 6) {
  385. b43_phy_write(dev, B43_PHY_OFDM(0x22), 0x287A);
  386. b43_phy_write(dev, B43_PHY_LPFGAINCTL,
  387. (b43_phy_read(dev, B43_PHY_LPFGAINCTL) & ~0xF000) | 0x3000);
  388. }
  389. }
  390. b43_phy_write(dev, B43_PHY_DIVSRCHIDX,
  391. (b43_phy_read(dev, B43_PHY_DIVSRCHIDX) & 0x8080) | 0x7874);
  392. b43_phy_write(dev, B43_PHY_OFDM(0x8E), 0x1C00);
  393. if (phy->rev == 1) {
  394. b43_phy_write(dev, B43_PHY_DIVP1P2GAIN,
  395. (b43_phy_read(dev, B43_PHY_DIVP1P2GAIN) & ~0x0F00) | 0x0600);
  396. b43_phy_write(dev, B43_PHY_OFDM(0x8B), 0x005E);
  397. b43_phy_write(dev, B43_PHY_ANTWRSETT,
  398. (b43_phy_read(dev, B43_PHY_ANTWRSETT) & ~0x00FF) | 0x001E);
  399. b43_phy_write(dev, B43_PHY_OFDM(0x8D), 0x0002);
  400. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 0, 0);
  401. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 1, 7);
  402. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 2, 16);
  403. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 3, 28);
  404. } else {
  405. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 0, 0);
  406. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 1, 7);
  407. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 2, 16);
  408. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 3, 28);
  409. }
  410. if (phy->rev >= 6) {
  411. b43_phy_write(dev, B43_PHY_OFDM(0x26),
  412. b43_phy_read(dev, B43_PHY_OFDM(0x26)) & ~0x0003);
  413. b43_phy_write(dev, B43_PHY_OFDM(0x26),
  414. b43_phy_read(dev, B43_PHY_OFDM(0x26)) & ~0x1000);
  415. }
  416. b43_phy_read(dev, B43_PHY_VERSION_OFDM); /* Dummy read */
  417. }
  418. static void b43_wa_tr_ltov(struct b43_wldev *dev) /* TR Lookup Table Original Values */
  419. {
  420. b43_gtab_write(dev, B43_GTAB_ORIGTR, 0, 0xC480);
  421. }
  422. static void b43_wa_cpll_nonpilot(struct b43_wldev *dev)
  423. {
  424. b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_11, 0, 0);
  425. b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_11, 1, 0);
  426. }
  427. static void b43_wa_rssi_adc(struct b43_wldev *dev)
  428. {
  429. if (dev->phy.analog == 4)
  430. b43_phy_write(dev, 0x00DC, 0x7454);
  431. }
  432. static void b43_wa_boards_a(struct b43_wldev *dev)
  433. {
  434. struct ssb_bus *bus = dev->dev->bus;
  435. if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
  436. bus->boardinfo.type == SSB_BOARD_BU4306 &&
  437. bus->boardinfo.rev < 0x30) {
  438. b43_phy_write(dev, 0x0010, 0xE000);
  439. b43_phy_write(dev, 0x0013, 0x0140);
  440. b43_phy_write(dev, 0x0014, 0x0280);
  441. } else {
  442. if (bus->boardinfo.type == SSB_BOARD_MP4318 &&
  443. bus->boardinfo.rev < 0x20) {
  444. b43_phy_write(dev, 0x0013, 0x0210);
  445. b43_phy_write(dev, 0x0014, 0x0840);
  446. } else {
  447. b43_phy_write(dev, 0x0013, 0x0140);
  448. b43_phy_write(dev, 0x0014, 0x0280);
  449. }
  450. if (dev->phy.rev <= 4)
  451. b43_phy_write(dev, 0x0010, 0xE000);
  452. else
  453. b43_phy_write(dev, 0x0010, 0x2000);
  454. b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 1, 0x0039);
  455. b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_APHY, 7, 0x0040);
  456. }
  457. }
  458. static void b43_wa_boards_g(struct b43_wldev *dev)
  459. {
  460. struct ssb_bus *bus = dev->dev->bus;
  461. struct b43_phy *phy = &dev->phy;
  462. if (bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM ||
  463. bus->boardinfo.type != SSB_BOARD_BU4306 ||
  464. bus->boardinfo.rev != 0x17) {
  465. if (phy->rev < 2) {
  466. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 1, 0x0002);
  467. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 2, 0x0001);
  468. } else {
  469. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 1, 0x0002);
  470. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 2, 0x0001);
  471. if ((bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
  472. (phy->rev >= 7)) {
  473. b43_phy_write(dev, B43_PHY_EXTG(0x11),
  474. b43_phy_read(dev, B43_PHY_EXTG(0x11)) & 0xF7FF);
  475. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0020, 0x0001);
  476. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0021, 0x0001);
  477. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0022, 0x0001);
  478. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0023, 0x0000);
  479. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0000, 0x0000);
  480. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0003, 0x0002);
  481. }
  482. }
  483. }
  484. if (bus->sprom.boardflags_lo & B43_BFL_FEM) {
  485. b43_phy_write(dev, B43_PHY_GTABCTL, 0x3120);
  486. b43_phy_write(dev, B43_PHY_GTABDATA, 0xC480);
  487. }
  488. }
  489. void b43_wa_all(struct b43_wldev *dev)
  490. {
  491. struct b43_phy *phy = &dev->phy;
  492. if (phy->type == B43_PHYTYPE_A) {
  493. switch (phy->rev) {
  494. case 2:
  495. b43_wa_papd(dev);
  496. b43_wa_auxclipthr(dev);
  497. b43_wa_afcdac(dev);
  498. b43_wa_txdc_offset(dev);
  499. b43_wa_initgains(dev);
  500. b43_wa_divider(dev);
  501. b43_wa_gt(dev);
  502. b43_wa_rssi_lt(dev);
  503. b43_wa_analog(dev);
  504. b43_wa_dac(dev);
  505. b43_wa_fft(dev);
  506. b43_wa_nft(dev);
  507. b43_wa_rt(dev);
  508. b43_wa_nst(dev);
  509. b43_wa_art(dev);
  510. b43_wa_txlna_gain(dev);
  511. b43_wa_crs_reset(dev);
  512. b43_wa_2060txlna_gain(dev);
  513. b43_wa_lms(dev);
  514. break;
  515. case 3:
  516. b43_wa_papd(dev);
  517. b43_wa_mixedsignal(dev);
  518. b43_wa_rssi_lt(dev);
  519. b43_wa_txdc_offset(dev);
  520. b43_wa_initgains(dev);
  521. b43_wa_dac(dev);
  522. b43_wa_nft(dev);
  523. b43_wa_nst(dev);
  524. b43_wa_msst(dev);
  525. b43_wa_analog(dev);
  526. b43_wa_gt(dev);
  527. b43_wa_txpuoff_rxpuon(dev);
  528. b43_wa_txlna_gain(dev);
  529. break;
  530. case 5:
  531. b43_wa_iqadc(dev);
  532. case 6:
  533. b43_wa_papd(dev);
  534. b43_wa_rssi_lt(dev);
  535. b43_wa_txdc_offset(dev);
  536. b43_wa_initgains(dev);
  537. b43_wa_dac(dev);
  538. b43_wa_nft(dev);
  539. b43_wa_nst(dev);
  540. b43_wa_msst(dev);
  541. b43_wa_analog(dev);
  542. b43_wa_gt(dev);
  543. b43_wa_txpuoff_rxpuon(dev);
  544. b43_wa_txlna_gain(dev);
  545. break;
  546. case 7:
  547. b43_wa_iqadc(dev);
  548. b43_wa_papd(dev);
  549. b43_wa_rssi_lt(dev);
  550. b43_wa_txdc_offset(dev);
  551. b43_wa_initgains(dev);
  552. b43_wa_dac(dev);
  553. b43_wa_nft(dev);
  554. b43_wa_nst(dev);
  555. b43_wa_msst(dev);
  556. b43_wa_analog(dev);
  557. b43_wa_gt(dev);
  558. b43_wa_txpuoff_rxpuon(dev);
  559. b43_wa_txlna_gain(dev);
  560. b43_wa_rssi_adc(dev);
  561. default:
  562. B43_WARN_ON(1);
  563. }
  564. b43_wa_boards_a(dev);
  565. } else if (phy->type == B43_PHYTYPE_G) {
  566. switch (phy->rev) {
  567. case 1://XXX review rev1
  568. b43_wa_crs_ed(dev);
  569. b43_wa_crs_thr(dev);
  570. b43_wa_crs_blank(dev);
  571. b43_wa_cck_shiftbits(dev);
  572. b43_wa_fft(dev);
  573. b43_wa_nft(dev);
  574. b43_wa_rt(dev);
  575. b43_wa_nst(dev);
  576. b43_wa_art(dev);
  577. b43_wa_wrssi_offset(dev);
  578. b43_wa_altagc(dev);
  579. break;
  580. case 2:
  581. case 6:
  582. case 7:
  583. case 8:
  584. case 9:
  585. b43_wa_tr_ltov(dev);
  586. b43_wa_crs_ed(dev);
  587. b43_wa_rssi_lt(dev);
  588. b43_wa_nft(dev);
  589. b43_wa_nst(dev);
  590. b43_wa_msst(dev);
  591. b43_wa_wrssi_offset(dev);
  592. b43_wa_altagc(dev);
  593. b43_wa_analog(dev);
  594. b43_wa_txpuoff_rxpuon(dev);
  595. break;
  596. default:
  597. B43_WARN_ON(1);
  598. }
  599. b43_wa_boards_g(dev);
  600. } else { /* No N PHY support so far */
  601. B43_WARN_ON(1);
  602. }
  603. b43_wa_cpll_nonpilot(dev);
  604. }