intel_ddi.c 41 KB

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  1. /*
  2. * Copyright © 2012 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eugeni Dodonov <eugeni.dodonov@intel.com>
  25. *
  26. */
  27. #include "i915_drv.h"
  28. #include "intel_drv.h"
  29. /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  30. * them for both DP and FDI transports, allowing those ports to
  31. * automatically adapt to HDMI connections as well
  32. */
  33. static const u32 hsw_ddi_translations_dp[] = {
  34. 0x00FFFFFF, 0x0006000E, /* DP parameters */
  35. 0x00D75FFF, 0x0005000A,
  36. 0x00C30FFF, 0x00040006,
  37. 0x80AAAFFF, 0x000B0000,
  38. 0x00FFFFFF, 0x0005000A,
  39. 0x00D75FFF, 0x000C0004,
  40. 0x80C30FFF, 0x000B0000,
  41. 0x00FFFFFF, 0x00040006,
  42. 0x80D75FFF, 0x000B0000,
  43. };
  44. static const u32 hsw_ddi_translations_fdi[] = {
  45. 0x00FFFFFF, 0x0007000E, /* FDI parameters */
  46. 0x00D75FFF, 0x000F000A,
  47. 0x00C30FFF, 0x00060006,
  48. 0x00AAAFFF, 0x001E0000,
  49. 0x00FFFFFF, 0x000F000A,
  50. 0x00D75FFF, 0x00160004,
  51. 0x00C30FFF, 0x001E0000,
  52. 0x00FFFFFF, 0x00060006,
  53. 0x00D75FFF, 0x001E0000,
  54. };
  55. static const u32 hsw_ddi_translations_hdmi[] = {
  56. /* Idx NT mV diff T mV diff db */
  57. 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */
  58. 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */
  59. 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */
  60. 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */
  61. 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */
  62. 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */
  63. 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */
  64. 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */
  65. 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */
  66. 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */
  67. 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */
  68. 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */
  69. };
  70. static const u32 bdw_ddi_translations_dp[] = {
  71. 0x00FFFFFF, 0x0007000E, /* DP parameters */
  72. 0x00D75FFF, 0x000E000A,
  73. 0x00BEFFFF, 0x00140006,
  74. 0x00FFFFFF, 0x000E000A,
  75. 0x00D75FFF, 0x00180004,
  76. 0x80CB2FFF, 0x001B0002,
  77. 0x00F7DFFF, 0x00180004,
  78. 0x80D75FFF, 0x001B0002,
  79. 0x80FFFFFF, 0x001B0002,
  80. 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
  81. };
  82. static const u32 bdw_ddi_translations_fdi[] = {
  83. 0x00FFFFFF, 0x0001000E, /* FDI parameters */
  84. 0x00D75FFF, 0x0004000A,
  85. 0x00C30FFF, 0x00070006,
  86. 0x00AAAFFF, 0x000C0000,
  87. 0x00FFFFFF, 0x0004000A,
  88. 0x00D75FFF, 0x00090004,
  89. 0x00C30FFF, 0x000C0000,
  90. 0x00FFFFFF, 0x00070006,
  91. 0x00D75FFF, 0x000C0000,
  92. 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
  93. };
  94. enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
  95. {
  96. struct drm_encoder *encoder = &intel_encoder->base;
  97. int type = intel_encoder->type;
  98. if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
  99. type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
  100. struct intel_digital_port *intel_dig_port =
  101. enc_to_dig_port(encoder);
  102. return intel_dig_port->port;
  103. } else if (type == INTEL_OUTPUT_ANALOG) {
  104. return PORT_E;
  105. } else {
  106. DRM_ERROR("Invalid DDI encoder type %d\n", type);
  107. BUG();
  108. }
  109. }
  110. /*
  111. * Starting with Haswell, DDI port buffers must be programmed with correct
  112. * values in advance. The buffer values are different for FDI and DP modes,
  113. * but the HDMI/DVI fields are shared among those. So we program the DDI
  114. * in either FDI or DP modes only, as HDMI connections will work with both
  115. * of those
  116. */
  117. static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
  118. {
  119. struct drm_i915_private *dev_priv = dev->dev_private;
  120. u32 reg;
  121. int i;
  122. int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
  123. const u32 *ddi_translations_fdi;
  124. const u32 *ddi_translations_dp;
  125. const u32 *ddi_translations;
  126. if (IS_BROADWELL(dev)) {
  127. ddi_translations_fdi = bdw_ddi_translations_fdi;
  128. ddi_translations_dp = bdw_ddi_translations_dp;
  129. } else if (IS_HASWELL(dev)) {
  130. ddi_translations_fdi = hsw_ddi_translations_fdi;
  131. ddi_translations_dp = hsw_ddi_translations_dp;
  132. } else {
  133. WARN(1, "ddi translation table missing\n");
  134. ddi_translations_fdi = bdw_ddi_translations_fdi;
  135. ddi_translations_dp = bdw_ddi_translations_dp;
  136. }
  137. ddi_translations = ((port == PORT_E) ?
  138. ddi_translations_fdi :
  139. ddi_translations_dp);
  140. for (i = 0, reg = DDI_BUF_TRANS(port);
  141. i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
  142. I915_WRITE(reg, ddi_translations[i]);
  143. reg += 4;
  144. }
  145. /* Entry 9 is for HDMI: */
  146. for (i = 0; i < 2; i++) {
  147. I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]);
  148. reg += 4;
  149. }
  150. }
  151. /* Program DDI buffers translations for DP. By default, program ports A-D in DP
  152. * mode and port E for FDI.
  153. */
  154. void intel_prepare_ddi(struct drm_device *dev)
  155. {
  156. int port;
  157. if (!HAS_DDI(dev))
  158. return;
  159. for (port = PORT_A; port <= PORT_E; port++)
  160. intel_prepare_ddi_buffers(dev, port);
  161. }
  162. static const long hsw_ddi_buf_ctl_values[] = {
  163. DDI_BUF_EMP_400MV_0DB_HSW,
  164. DDI_BUF_EMP_400MV_3_5DB_HSW,
  165. DDI_BUF_EMP_400MV_6DB_HSW,
  166. DDI_BUF_EMP_400MV_9_5DB_HSW,
  167. DDI_BUF_EMP_600MV_0DB_HSW,
  168. DDI_BUF_EMP_600MV_3_5DB_HSW,
  169. DDI_BUF_EMP_600MV_6DB_HSW,
  170. DDI_BUF_EMP_800MV_0DB_HSW,
  171. DDI_BUF_EMP_800MV_3_5DB_HSW
  172. };
  173. static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
  174. enum port port)
  175. {
  176. uint32_t reg = DDI_BUF_CTL(port);
  177. int i;
  178. for (i = 0; i < 8; i++) {
  179. udelay(1);
  180. if (I915_READ(reg) & DDI_BUF_IS_IDLE)
  181. return;
  182. }
  183. DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
  184. }
  185. /* Starting with Haswell, different DDI ports can work in FDI mode for
  186. * connection to the PCH-located connectors. For this, it is necessary to train
  187. * both the DDI port and PCH receiver for the desired DDI buffer settings.
  188. *
  189. * The recommended port to work in FDI mode is DDI E, which we use here. Also,
  190. * please note that when FDI mode is active on DDI E, it shares 2 lines with
  191. * DDI A (which is used for eDP)
  192. */
  193. void hsw_fdi_link_train(struct drm_crtc *crtc)
  194. {
  195. struct drm_device *dev = crtc->dev;
  196. struct drm_i915_private *dev_priv = dev->dev_private;
  197. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  198. u32 temp, i, rx_ctl_val;
  199. /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
  200. * mode set "sequence for CRT port" document:
  201. * - TP1 to TP2 time with the default value
  202. * - FDI delay to 90h
  203. *
  204. * WaFDIAutoLinkSetTimingOverrride:hsw
  205. */
  206. I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
  207. FDI_RX_PWRDN_LANE0_VAL(2) |
  208. FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  209. /* Enable the PCH Receiver FDI PLL */
  210. rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
  211. FDI_RX_PLL_ENABLE |
  212. FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  213. I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
  214. POSTING_READ(_FDI_RXA_CTL);
  215. udelay(220);
  216. /* Switch from Rawclk to PCDclk */
  217. rx_ctl_val |= FDI_PCDCLK;
  218. I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
  219. /* Configure Port Clock Select */
  220. I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
  221. /* Start the training iterating through available voltages and emphasis,
  222. * testing each value twice. */
  223. for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
  224. /* Configure DP_TP_CTL with auto-training */
  225. I915_WRITE(DP_TP_CTL(PORT_E),
  226. DP_TP_CTL_FDI_AUTOTRAIN |
  227. DP_TP_CTL_ENHANCED_FRAME_ENABLE |
  228. DP_TP_CTL_LINK_TRAIN_PAT1 |
  229. DP_TP_CTL_ENABLE);
  230. /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
  231. * DDI E does not support port reversal, the functionality is
  232. * achieved on the PCH side in FDI_RX_CTL, so no need to set the
  233. * port reversal bit */
  234. I915_WRITE(DDI_BUF_CTL(PORT_E),
  235. DDI_BUF_CTL_ENABLE |
  236. ((intel_crtc->config.fdi_lanes - 1) << 1) |
  237. hsw_ddi_buf_ctl_values[i / 2]);
  238. POSTING_READ(DDI_BUF_CTL(PORT_E));
  239. udelay(600);
  240. /* Program PCH FDI Receiver TU */
  241. I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
  242. /* Enable PCH FDI Receiver with auto-training */
  243. rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
  244. I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
  245. POSTING_READ(_FDI_RXA_CTL);
  246. /* Wait for FDI receiver lane calibration */
  247. udelay(30);
  248. /* Unset FDI_RX_MISC pwrdn lanes */
  249. temp = I915_READ(_FDI_RXA_MISC);
  250. temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
  251. I915_WRITE(_FDI_RXA_MISC, temp);
  252. POSTING_READ(_FDI_RXA_MISC);
  253. /* Wait for FDI auto training time */
  254. udelay(5);
  255. temp = I915_READ(DP_TP_STATUS(PORT_E));
  256. if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
  257. DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
  258. /* Enable normal pixel sending for FDI */
  259. I915_WRITE(DP_TP_CTL(PORT_E),
  260. DP_TP_CTL_FDI_AUTOTRAIN |
  261. DP_TP_CTL_LINK_TRAIN_NORMAL |
  262. DP_TP_CTL_ENHANCED_FRAME_ENABLE |
  263. DP_TP_CTL_ENABLE);
  264. return;
  265. }
  266. temp = I915_READ(DDI_BUF_CTL(PORT_E));
  267. temp &= ~DDI_BUF_CTL_ENABLE;
  268. I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
  269. POSTING_READ(DDI_BUF_CTL(PORT_E));
  270. /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
  271. temp = I915_READ(DP_TP_CTL(PORT_E));
  272. temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
  273. temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
  274. I915_WRITE(DP_TP_CTL(PORT_E), temp);
  275. POSTING_READ(DP_TP_CTL(PORT_E));
  276. intel_wait_ddi_buf_idle(dev_priv, PORT_E);
  277. rx_ctl_val &= ~FDI_RX_ENABLE;
  278. I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
  279. POSTING_READ(_FDI_RXA_CTL);
  280. /* Reset FDI_RX_MISC pwrdn lanes */
  281. temp = I915_READ(_FDI_RXA_MISC);
  282. temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
  283. temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
  284. I915_WRITE(_FDI_RXA_MISC, temp);
  285. POSTING_READ(_FDI_RXA_MISC);
  286. }
  287. DRM_ERROR("FDI link training failed!\n");
  288. }
  289. static void intel_ddi_mode_set(struct intel_encoder *encoder)
  290. {
  291. struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  292. int port = intel_ddi_get_encoder_port(encoder);
  293. int pipe = crtc->pipe;
  294. int type = encoder->type;
  295. struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
  296. DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
  297. port_name(port), pipe_name(pipe));
  298. crtc->eld_vld = false;
  299. if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
  300. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  301. struct intel_digital_port *intel_dig_port =
  302. enc_to_dig_port(&encoder->base);
  303. intel_dp->DP = intel_dig_port->saved_port_bits |
  304. DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
  305. intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
  306. if (intel_dp->has_audio) {
  307. DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
  308. pipe_name(crtc->pipe));
  309. /* write eld */
  310. DRM_DEBUG_DRIVER("DP audio: write eld information\n");
  311. intel_write_eld(&encoder->base, adjusted_mode);
  312. }
  313. } else if (type == INTEL_OUTPUT_HDMI) {
  314. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  315. if (intel_hdmi->has_audio) {
  316. /* Proper support for digital audio needs a new logic
  317. * and a new set of registers, so we leave it for future
  318. * patch bombing.
  319. */
  320. DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
  321. pipe_name(crtc->pipe));
  322. /* write eld */
  323. DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
  324. intel_write_eld(&encoder->base, adjusted_mode);
  325. }
  326. intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
  327. }
  328. }
  329. static struct intel_encoder *
  330. intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
  331. {
  332. struct drm_device *dev = crtc->dev;
  333. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  334. struct intel_encoder *intel_encoder, *ret = NULL;
  335. int num_encoders = 0;
  336. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  337. ret = intel_encoder;
  338. num_encoders++;
  339. }
  340. if (num_encoders != 1)
  341. WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
  342. pipe_name(intel_crtc->pipe));
  343. BUG_ON(ret == NULL);
  344. return ret;
  345. }
  346. void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
  347. {
  348. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  349. struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
  350. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  351. uint32_t val;
  352. switch (intel_crtc->ddi_pll_sel) {
  353. case PORT_CLK_SEL_SPLL:
  354. plls->spll_refcount--;
  355. if (plls->spll_refcount == 0) {
  356. DRM_DEBUG_KMS("Disabling SPLL\n");
  357. val = I915_READ(SPLL_CTL);
  358. WARN_ON(!(val & SPLL_PLL_ENABLE));
  359. I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
  360. POSTING_READ(SPLL_CTL);
  361. }
  362. break;
  363. case PORT_CLK_SEL_WRPLL1:
  364. plls->wrpll1_refcount--;
  365. if (plls->wrpll1_refcount == 0) {
  366. DRM_DEBUG_KMS("Disabling WRPLL 1\n");
  367. val = I915_READ(WRPLL_CTL1);
  368. WARN_ON(!(val & WRPLL_PLL_ENABLE));
  369. I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
  370. POSTING_READ(WRPLL_CTL1);
  371. }
  372. break;
  373. case PORT_CLK_SEL_WRPLL2:
  374. plls->wrpll2_refcount--;
  375. if (plls->wrpll2_refcount == 0) {
  376. DRM_DEBUG_KMS("Disabling WRPLL 2\n");
  377. val = I915_READ(WRPLL_CTL2);
  378. WARN_ON(!(val & WRPLL_PLL_ENABLE));
  379. I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
  380. POSTING_READ(WRPLL_CTL2);
  381. }
  382. break;
  383. }
  384. WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
  385. WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
  386. WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
  387. intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
  388. }
  389. #define LC_FREQ 2700
  390. #define LC_FREQ_2K (LC_FREQ * 2000)
  391. #define P_MIN 2
  392. #define P_MAX 64
  393. #define P_INC 2
  394. /* Constraints for PLL good behavior */
  395. #define REF_MIN 48
  396. #define REF_MAX 400
  397. #define VCO_MIN 2400
  398. #define VCO_MAX 4800
  399. #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
  400. struct wrpll_rnp {
  401. unsigned p, n2, r2;
  402. };
  403. static unsigned wrpll_get_budget_for_freq(int clock)
  404. {
  405. unsigned budget;
  406. switch (clock) {
  407. case 25175000:
  408. case 25200000:
  409. case 27000000:
  410. case 27027000:
  411. case 37762500:
  412. case 37800000:
  413. case 40500000:
  414. case 40541000:
  415. case 54000000:
  416. case 54054000:
  417. case 59341000:
  418. case 59400000:
  419. case 72000000:
  420. case 74176000:
  421. case 74250000:
  422. case 81000000:
  423. case 81081000:
  424. case 89012000:
  425. case 89100000:
  426. case 108000000:
  427. case 108108000:
  428. case 111264000:
  429. case 111375000:
  430. case 148352000:
  431. case 148500000:
  432. case 162000000:
  433. case 162162000:
  434. case 222525000:
  435. case 222750000:
  436. case 296703000:
  437. case 297000000:
  438. budget = 0;
  439. break;
  440. case 233500000:
  441. case 245250000:
  442. case 247750000:
  443. case 253250000:
  444. case 298000000:
  445. budget = 1500;
  446. break;
  447. case 169128000:
  448. case 169500000:
  449. case 179500000:
  450. case 202000000:
  451. budget = 2000;
  452. break;
  453. case 256250000:
  454. case 262500000:
  455. case 270000000:
  456. case 272500000:
  457. case 273750000:
  458. case 280750000:
  459. case 281250000:
  460. case 286000000:
  461. case 291750000:
  462. budget = 4000;
  463. break;
  464. case 267250000:
  465. case 268500000:
  466. budget = 5000;
  467. break;
  468. default:
  469. budget = 1000;
  470. break;
  471. }
  472. return budget;
  473. }
  474. static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
  475. unsigned r2, unsigned n2, unsigned p,
  476. struct wrpll_rnp *best)
  477. {
  478. uint64_t a, b, c, d, diff, diff_best;
  479. /* No best (r,n,p) yet */
  480. if (best->p == 0) {
  481. best->p = p;
  482. best->n2 = n2;
  483. best->r2 = r2;
  484. return;
  485. }
  486. /*
  487. * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
  488. * freq2k.
  489. *
  490. * delta = 1e6 *
  491. * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
  492. * freq2k;
  493. *
  494. * and we would like delta <= budget.
  495. *
  496. * If the discrepancy is above the PPM-based budget, always prefer to
  497. * improve upon the previous solution. However, if you're within the
  498. * budget, try to maximize Ref * VCO, that is N / (P * R^2).
  499. */
  500. a = freq2k * budget * p * r2;
  501. b = freq2k * budget * best->p * best->r2;
  502. diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2));
  503. diff_best = ABS_DIFF((freq2k * best->p * best->r2),
  504. (LC_FREQ_2K * best->n2));
  505. c = 1000000 * diff;
  506. d = 1000000 * diff_best;
  507. if (a < c && b < d) {
  508. /* If both are above the budget, pick the closer */
  509. if (best->p * best->r2 * diff < p * r2 * diff_best) {
  510. best->p = p;
  511. best->n2 = n2;
  512. best->r2 = r2;
  513. }
  514. } else if (a >= c && b < d) {
  515. /* If A is below the threshold but B is above it? Update. */
  516. best->p = p;
  517. best->n2 = n2;
  518. best->r2 = r2;
  519. } else if (a >= c && b >= d) {
  520. /* Both are below the limit, so pick the higher n2/(r2*r2) */
  521. if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
  522. best->p = p;
  523. best->n2 = n2;
  524. best->r2 = r2;
  525. }
  526. }
  527. /* Otherwise a < c && b >= d, do nothing */
  528. }
  529. static void
  530. intel_ddi_calculate_wrpll(int clock /* in Hz */,
  531. unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
  532. {
  533. uint64_t freq2k;
  534. unsigned p, n2, r2;
  535. struct wrpll_rnp best = { 0, 0, 0 };
  536. unsigned budget;
  537. freq2k = clock / 100;
  538. budget = wrpll_get_budget_for_freq(clock);
  539. /* Special case handling for 540 pixel clock: bypass WR PLL entirely
  540. * and directly pass the LC PLL to it. */
  541. if (freq2k == 5400000) {
  542. *n2_out = 2;
  543. *p_out = 1;
  544. *r2_out = 2;
  545. return;
  546. }
  547. /*
  548. * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
  549. * the WR PLL.
  550. *
  551. * We want R so that REF_MIN <= Ref <= REF_MAX.
  552. * Injecting R2 = 2 * R gives:
  553. * REF_MAX * r2 > LC_FREQ * 2 and
  554. * REF_MIN * r2 < LC_FREQ * 2
  555. *
  556. * Which means the desired boundaries for r2 are:
  557. * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
  558. *
  559. */
  560. for (r2 = LC_FREQ * 2 / REF_MAX + 1;
  561. r2 <= LC_FREQ * 2 / REF_MIN;
  562. r2++) {
  563. /*
  564. * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
  565. *
  566. * Once again we want VCO_MIN <= VCO <= VCO_MAX.
  567. * Injecting R2 = 2 * R and N2 = 2 * N, we get:
  568. * VCO_MAX * r2 > n2 * LC_FREQ and
  569. * VCO_MIN * r2 < n2 * LC_FREQ)
  570. *
  571. * Which means the desired boundaries for n2 are:
  572. * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
  573. */
  574. for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
  575. n2 <= VCO_MAX * r2 / LC_FREQ;
  576. n2++) {
  577. for (p = P_MIN; p <= P_MAX; p += P_INC)
  578. wrpll_update_rnp(freq2k, budget,
  579. r2, n2, p, &best);
  580. }
  581. }
  582. *n2_out = best.n2;
  583. *p_out = best.p;
  584. *r2_out = best.r2;
  585. DRM_DEBUG_KMS("WRPLL: %dHz refresh rate with p=%d, n2=%d r2=%d\n",
  586. clock, *p_out, *n2_out, *r2_out);
  587. }
  588. bool intel_ddi_pll_mode_set(struct drm_crtc *crtc)
  589. {
  590. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  591. struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
  592. struct drm_encoder *encoder = &intel_encoder->base;
  593. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  594. struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
  595. int type = intel_encoder->type;
  596. enum pipe pipe = intel_crtc->pipe;
  597. uint32_t reg, val;
  598. int clock = intel_crtc->config.port_clock;
  599. /* TODO: reuse PLLs when possible (compare values) */
  600. intel_ddi_put_crtc_pll(crtc);
  601. if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
  602. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  603. switch (intel_dp->link_bw) {
  604. case DP_LINK_BW_1_62:
  605. intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
  606. break;
  607. case DP_LINK_BW_2_7:
  608. intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
  609. break;
  610. case DP_LINK_BW_5_4:
  611. intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
  612. break;
  613. default:
  614. DRM_ERROR("Link bandwidth %d unsupported\n",
  615. intel_dp->link_bw);
  616. return false;
  617. }
  618. /* We don't need to turn any PLL on because we'll use LCPLL. */
  619. return true;
  620. } else if (type == INTEL_OUTPUT_HDMI) {
  621. unsigned p, n2, r2;
  622. if (plls->wrpll1_refcount == 0) {
  623. DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
  624. pipe_name(pipe));
  625. plls->wrpll1_refcount++;
  626. reg = WRPLL_CTL1;
  627. intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
  628. } else if (plls->wrpll2_refcount == 0) {
  629. DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
  630. pipe_name(pipe));
  631. plls->wrpll2_refcount++;
  632. reg = WRPLL_CTL2;
  633. intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
  634. } else {
  635. DRM_ERROR("No WRPLLs available!\n");
  636. return false;
  637. }
  638. WARN(I915_READ(reg) & WRPLL_PLL_ENABLE,
  639. "WRPLL already enabled\n");
  640. intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
  641. val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
  642. WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
  643. WRPLL_DIVIDER_POST(p);
  644. } else if (type == INTEL_OUTPUT_ANALOG) {
  645. if (plls->spll_refcount == 0) {
  646. DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
  647. pipe_name(pipe));
  648. plls->spll_refcount++;
  649. reg = SPLL_CTL;
  650. intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
  651. } else {
  652. DRM_ERROR("SPLL already in use\n");
  653. return false;
  654. }
  655. WARN(I915_READ(reg) & SPLL_PLL_ENABLE,
  656. "SPLL already enabled\n");
  657. val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
  658. } else {
  659. WARN(1, "Invalid DDI encoder type %d\n", type);
  660. return false;
  661. }
  662. I915_WRITE(reg, val);
  663. udelay(20);
  664. return true;
  665. }
  666. void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
  667. {
  668. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  669. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  670. struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
  671. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  672. int type = intel_encoder->type;
  673. uint32_t temp;
  674. if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
  675. temp = TRANS_MSA_SYNC_CLK;
  676. switch (intel_crtc->config.pipe_bpp) {
  677. case 18:
  678. temp |= TRANS_MSA_6_BPC;
  679. break;
  680. case 24:
  681. temp |= TRANS_MSA_8_BPC;
  682. break;
  683. case 30:
  684. temp |= TRANS_MSA_10_BPC;
  685. break;
  686. case 36:
  687. temp |= TRANS_MSA_12_BPC;
  688. break;
  689. default:
  690. BUG();
  691. }
  692. I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
  693. }
  694. }
  695. void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
  696. {
  697. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  698. struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
  699. struct drm_encoder *encoder = &intel_encoder->base;
  700. struct drm_device *dev = crtc->dev;
  701. struct drm_i915_private *dev_priv = dev->dev_private;
  702. enum pipe pipe = intel_crtc->pipe;
  703. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  704. enum port port = intel_ddi_get_encoder_port(intel_encoder);
  705. int type = intel_encoder->type;
  706. uint32_t temp;
  707. /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
  708. temp = TRANS_DDI_FUNC_ENABLE;
  709. temp |= TRANS_DDI_SELECT_PORT(port);
  710. switch (intel_crtc->config.pipe_bpp) {
  711. case 18:
  712. temp |= TRANS_DDI_BPC_6;
  713. break;
  714. case 24:
  715. temp |= TRANS_DDI_BPC_8;
  716. break;
  717. case 30:
  718. temp |= TRANS_DDI_BPC_10;
  719. break;
  720. case 36:
  721. temp |= TRANS_DDI_BPC_12;
  722. break;
  723. default:
  724. BUG();
  725. }
  726. if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
  727. temp |= TRANS_DDI_PVSYNC;
  728. if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
  729. temp |= TRANS_DDI_PHSYNC;
  730. if (cpu_transcoder == TRANSCODER_EDP) {
  731. switch (pipe) {
  732. case PIPE_A:
  733. /* On Haswell, can only use the always-on power well for
  734. * eDP when not using the panel fitter, and when not
  735. * using motion blur mitigation (which we don't
  736. * support). */
  737. if (IS_HASWELL(dev) && intel_crtc->config.pch_pfit.enabled)
  738. temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
  739. else
  740. temp |= TRANS_DDI_EDP_INPUT_A_ON;
  741. break;
  742. case PIPE_B:
  743. temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
  744. break;
  745. case PIPE_C:
  746. temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
  747. break;
  748. default:
  749. BUG();
  750. break;
  751. }
  752. }
  753. if (type == INTEL_OUTPUT_HDMI) {
  754. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  755. if (intel_hdmi->has_hdmi_sink)
  756. temp |= TRANS_DDI_MODE_SELECT_HDMI;
  757. else
  758. temp |= TRANS_DDI_MODE_SELECT_DVI;
  759. } else if (type == INTEL_OUTPUT_ANALOG) {
  760. temp |= TRANS_DDI_MODE_SELECT_FDI;
  761. temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
  762. } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
  763. type == INTEL_OUTPUT_EDP) {
  764. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  765. temp |= TRANS_DDI_MODE_SELECT_DP_SST;
  766. temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
  767. } else {
  768. WARN(1, "Invalid encoder type %d for pipe %c\n",
  769. intel_encoder->type, pipe_name(pipe));
  770. }
  771. I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
  772. }
  773. void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
  774. enum transcoder cpu_transcoder)
  775. {
  776. uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
  777. uint32_t val = I915_READ(reg);
  778. val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
  779. val |= TRANS_DDI_PORT_NONE;
  780. I915_WRITE(reg, val);
  781. }
  782. bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
  783. {
  784. struct drm_device *dev = intel_connector->base.dev;
  785. struct drm_i915_private *dev_priv = dev->dev_private;
  786. struct intel_encoder *intel_encoder = intel_connector->encoder;
  787. int type = intel_connector->base.connector_type;
  788. enum port port = intel_ddi_get_encoder_port(intel_encoder);
  789. enum pipe pipe = 0;
  790. enum transcoder cpu_transcoder;
  791. uint32_t tmp;
  792. if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
  793. return false;
  794. if (port == PORT_A)
  795. cpu_transcoder = TRANSCODER_EDP;
  796. else
  797. cpu_transcoder = (enum transcoder) pipe;
  798. tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
  799. switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
  800. case TRANS_DDI_MODE_SELECT_HDMI:
  801. case TRANS_DDI_MODE_SELECT_DVI:
  802. return (type == DRM_MODE_CONNECTOR_HDMIA);
  803. case TRANS_DDI_MODE_SELECT_DP_SST:
  804. if (type == DRM_MODE_CONNECTOR_eDP)
  805. return true;
  806. case TRANS_DDI_MODE_SELECT_DP_MST:
  807. return (type == DRM_MODE_CONNECTOR_DisplayPort);
  808. case TRANS_DDI_MODE_SELECT_FDI:
  809. return (type == DRM_MODE_CONNECTOR_VGA);
  810. default:
  811. return false;
  812. }
  813. }
  814. bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
  815. enum pipe *pipe)
  816. {
  817. struct drm_device *dev = encoder->base.dev;
  818. struct drm_i915_private *dev_priv = dev->dev_private;
  819. enum port port = intel_ddi_get_encoder_port(encoder);
  820. u32 tmp;
  821. int i;
  822. tmp = I915_READ(DDI_BUF_CTL(port));
  823. if (!(tmp & DDI_BUF_CTL_ENABLE))
  824. return false;
  825. if (port == PORT_A) {
  826. tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
  827. switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
  828. case TRANS_DDI_EDP_INPUT_A_ON:
  829. case TRANS_DDI_EDP_INPUT_A_ONOFF:
  830. *pipe = PIPE_A;
  831. break;
  832. case TRANS_DDI_EDP_INPUT_B_ONOFF:
  833. *pipe = PIPE_B;
  834. break;
  835. case TRANS_DDI_EDP_INPUT_C_ONOFF:
  836. *pipe = PIPE_C;
  837. break;
  838. }
  839. return true;
  840. } else {
  841. for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
  842. tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
  843. if ((tmp & TRANS_DDI_PORT_MASK)
  844. == TRANS_DDI_SELECT_PORT(port)) {
  845. *pipe = i;
  846. return true;
  847. }
  848. }
  849. }
  850. DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
  851. return false;
  852. }
  853. static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
  854. enum pipe pipe)
  855. {
  856. uint32_t temp, ret;
  857. enum port port = I915_MAX_PORTS;
  858. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  859. pipe);
  860. int i;
  861. if (cpu_transcoder == TRANSCODER_EDP) {
  862. port = PORT_A;
  863. } else {
  864. temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
  865. temp &= TRANS_DDI_PORT_MASK;
  866. for (i = PORT_B; i <= PORT_E; i++)
  867. if (temp == TRANS_DDI_SELECT_PORT(i))
  868. port = i;
  869. }
  870. if (port == I915_MAX_PORTS) {
  871. WARN(1, "Pipe %c enabled on an unknown port\n",
  872. pipe_name(pipe));
  873. ret = PORT_CLK_SEL_NONE;
  874. } else {
  875. ret = I915_READ(PORT_CLK_SEL(port));
  876. DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
  877. "0x%08x\n", pipe_name(pipe), port_name(port),
  878. ret);
  879. }
  880. return ret;
  881. }
  882. void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
  883. {
  884. struct drm_i915_private *dev_priv = dev->dev_private;
  885. enum pipe pipe;
  886. struct intel_crtc *intel_crtc;
  887. for_each_pipe(pipe) {
  888. intel_crtc =
  889. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  890. if (!intel_crtc->active)
  891. continue;
  892. intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
  893. pipe);
  894. switch (intel_crtc->ddi_pll_sel) {
  895. case PORT_CLK_SEL_SPLL:
  896. dev_priv->ddi_plls.spll_refcount++;
  897. break;
  898. case PORT_CLK_SEL_WRPLL1:
  899. dev_priv->ddi_plls.wrpll1_refcount++;
  900. break;
  901. case PORT_CLK_SEL_WRPLL2:
  902. dev_priv->ddi_plls.wrpll2_refcount++;
  903. break;
  904. }
  905. }
  906. }
  907. void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
  908. {
  909. struct drm_crtc *crtc = &intel_crtc->base;
  910. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  911. struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
  912. enum port port = intel_ddi_get_encoder_port(intel_encoder);
  913. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  914. if (cpu_transcoder != TRANSCODER_EDP)
  915. I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
  916. TRANS_CLK_SEL_PORT(port));
  917. }
  918. void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
  919. {
  920. struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
  921. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  922. if (cpu_transcoder != TRANSCODER_EDP)
  923. I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
  924. TRANS_CLK_SEL_DISABLED);
  925. }
  926. static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
  927. {
  928. struct drm_encoder *encoder = &intel_encoder->base;
  929. struct drm_crtc *crtc = encoder->crtc;
  930. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  931. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  932. enum port port = intel_ddi_get_encoder_port(intel_encoder);
  933. int type = intel_encoder->type;
  934. if (type == INTEL_OUTPUT_EDP) {
  935. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  936. ironlake_edp_panel_vdd_on(intel_dp);
  937. ironlake_edp_panel_on(intel_dp);
  938. ironlake_edp_panel_vdd_off(intel_dp, true);
  939. }
  940. WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
  941. I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
  942. if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
  943. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  944. intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
  945. intel_dp_start_link_train(intel_dp);
  946. intel_dp_complete_link_train(intel_dp);
  947. if (port != PORT_A)
  948. intel_dp_stop_link_train(intel_dp);
  949. }
  950. }
  951. static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
  952. {
  953. struct drm_encoder *encoder = &intel_encoder->base;
  954. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  955. enum port port = intel_ddi_get_encoder_port(intel_encoder);
  956. int type = intel_encoder->type;
  957. uint32_t val;
  958. bool wait = false;
  959. val = I915_READ(DDI_BUF_CTL(port));
  960. if (val & DDI_BUF_CTL_ENABLE) {
  961. val &= ~DDI_BUF_CTL_ENABLE;
  962. I915_WRITE(DDI_BUF_CTL(port), val);
  963. wait = true;
  964. }
  965. val = I915_READ(DP_TP_CTL(port));
  966. val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
  967. val |= DP_TP_CTL_LINK_TRAIN_PAT1;
  968. I915_WRITE(DP_TP_CTL(port), val);
  969. if (wait)
  970. intel_wait_ddi_buf_idle(dev_priv, port);
  971. if (type == INTEL_OUTPUT_EDP) {
  972. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  973. ironlake_edp_panel_vdd_on(intel_dp);
  974. ironlake_edp_panel_off(intel_dp);
  975. }
  976. I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
  977. }
  978. static void intel_enable_ddi(struct intel_encoder *intel_encoder)
  979. {
  980. struct drm_encoder *encoder = &intel_encoder->base;
  981. struct drm_crtc *crtc = encoder->crtc;
  982. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  983. int pipe = intel_crtc->pipe;
  984. struct drm_device *dev = encoder->dev;
  985. struct drm_i915_private *dev_priv = dev->dev_private;
  986. enum port port = intel_ddi_get_encoder_port(intel_encoder);
  987. int type = intel_encoder->type;
  988. uint32_t tmp;
  989. if (type == INTEL_OUTPUT_HDMI) {
  990. struct intel_digital_port *intel_dig_port =
  991. enc_to_dig_port(encoder);
  992. /* In HDMI/DVI mode, the port width, and swing/emphasis values
  993. * are ignored so nothing special needs to be done besides
  994. * enabling the port.
  995. */
  996. I915_WRITE(DDI_BUF_CTL(port),
  997. intel_dig_port->saved_port_bits |
  998. DDI_BUF_CTL_ENABLE);
  999. } else if (type == INTEL_OUTPUT_EDP) {
  1000. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  1001. if (port == PORT_A)
  1002. intel_dp_stop_link_train(intel_dp);
  1003. ironlake_edp_backlight_on(intel_dp);
  1004. intel_edp_psr_enable(intel_dp);
  1005. }
  1006. if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
  1007. tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
  1008. tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
  1009. I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
  1010. }
  1011. }
  1012. static void intel_disable_ddi(struct intel_encoder *intel_encoder)
  1013. {
  1014. struct drm_encoder *encoder = &intel_encoder->base;
  1015. struct drm_crtc *crtc = encoder->crtc;
  1016. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1017. int pipe = intel_crtc->pipe;
  1018. int type = intel_encoder->type;
  1019. struct drm_device *dev = encoder->dev;
  1020. struct drm_i915_private *dev_priv = dev->dev_private;
  1021. uint32_t tmp;
  1022. if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
  1023. tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
  1024. tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
  1025. (pipe * 4));
  1026. I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
  1027. }
  1028. if (type == INTEL_OUTPUT_EDP) {
  1029. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  1030. intel_edp_psr_disable(intel_dp);
  1031. ironlake_edp_backlight_off(intel_dp);
  1032. }
  1033. }
  1034. int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
  1035. {
  1036. struct drm_device *dev = dev_priv->dev;
  1037. uint32_t lcpll = I915_READ(LCPLL_CTL);
  1038. uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
  1039. if (lcpll & LCPLL_CD_SOURCE_FCLK) {
  1040. return 800000;
  1041. } else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) {
  1042. return 450000;
  1043. } else if (freq == LCPLL_CLK_FREQ_450) {
  1044. return 450000;
  1045. } else if (IS_HASWELL(dev)) {
  1046. if (IS_ULT(dev))
  1047. return 337500;
  1048. else
  1049. return 540000;
  1050. } else {
  1051. if (freq == LCPLL_CLK_FREQ_54O_BDW)
  1052. return 540000;
  1053. else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
  1054. return 337500;
  1055. else
  1056. return 675000;
  1057. }
  1058. }
  1059. void intel_ddi_pll_init(struct drm_device *dev)
  1060. {
  1061. struct drm_i915_private *dev_priv = dev->dev_private;
  1062. uint32_t val = I915_READ(LCPLL_CTL);
  1063. /* The LCPLL register should be turned on by the BIOS. For now let's
  1064. * just check its state and print errors in case something is wrong.
  1065. * Don't even try to turn it on.
  1066. */
  1067. DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
  1068. intel_ddi_get_cdclk_freq(dev_priv));
  1069. if (val & LCPLL_CD_SOURCE_FCLK)
  1070. DRM_ERROR("CDCLK source is not LCPLL\n");
  1071. if (val & LCPLL_PLL_DISABLE)
  1072. DRM_ERROR("LCPLL is disabled\n");
  1073. }
  1074. void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
  1075. {
  1076. struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  1077. struct intel_dp *intel_dp = &intel_dig_port->dp;
  1078. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  1079. enum port port = intel_dig_port->port;
  1080. uint32_t val;
  1081. bool wait = false;
  1082. if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
  1083. val = I915_READ(DDI_BUF_CTL(port));
  1084. if (val & DDI_BUF_CTL_ENABLE) {
  1085. val &= ~DDI_BUF_CTL_ENABLE;
  1086. I915_WRITE(DDI_BUF_CTL(port), val);
  1087. wait = true;
  1088. }
  1089. val = I915_READ(DP_TP_CTL(port));
  1090. val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
  1091. val |= DP_TP_CTL_LINK_TRAIN_PAT1;
  1092. I915_WRITE(DP_TP_CTL(port), val);
  1093. POSTING_READ(DP_TP_CTL(port));
  1094. if (wait)
  1095. intel_wait_ddi_buf_idle(dev_priv, port);
  1096. }
  1097. val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
  1098. DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
  1099. if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
  1100. val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
  1101. I915_WRITE(DP_TP_CTL(port), val);
  1102. POSTING_READ(DP_TP_CTL(port));
  1103. intel_dp->DP |= DDI_BUF_CTL_ENABLE;
  1104. I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
  1105. POSTING_READ(DDI_BUF_CTL(port));
  1106. udelay(600);
  1107. }
  1108. void intel_ddi_fdi_disable(struct drm_crtc *crtc)
  1109. {
  1110. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  1111. struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
  1112. uint32_t val;
  1113. intel_ddi_post_disable(intel_encoder);
  1114. val = I915_READ(_FDI_RXA_CTL);
  1115. val &= ~FDI_RX_ENABLE;
  1116. I915_WRITE(_FDI_RXA_CTL, val);
  1117. val = I915_READ(_FDI_RXA_MISC);
  1118. val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
  1119. val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
  1120. I915_WRITE(_FDI_RXA_MISC, val);
  1121. val = I915_READ(_FDI_RXA_CTL);
  1122. val &= ~FDI_PCDCLK;
  1123. I915_WRITE(_FDI_RXA_CTL, val);
  1124. val = I915_READ(_FDI_RXA_CTL);
  1125. val &= ~FDI_RX_PLL_ENABLE;
  1126. I915_WRITE(_FDI_RXA_CTL, val);
  1127. }
  1128. static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
  1129. {
  1130. struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
  1131. int type = intel_encoder->type;
  1132. if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
  1133. intel_dp_check_link_status(intel_dp);
  1134. }
  1135. void intel_ddi_get_config(struct intel_encoder *encoder,
  1136. struct intel_crtc_config *pipe_config)
  1137. {
  1138. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  1139. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  1140. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  1141. u32 temp, flags = 0;
  1142. temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
  1143. if (temp & TRANS_DDI_PHSYNC)
  1144. flags |= DRM_MODE_FLAG_PHSYNC;
  1145. else
  1146. flags |= DRM_MODE_FLAG_NHSYNC;
  1147. if (temp & TRANS_DDI_PVSYNC)
  1148. flags |= DRM_MODE_FLAG_PVSYNC;
  1149. else
  1150. flags |= DRM_MODE_FLAG_NVSYNC;
  1151. pipe_config->adjusted_mode.flags |= flags;
  1152. switch (temp & TRANS_DDI_BPC_MASK) {
  1153. case TRANS_DDI_BPC_6:
  1154. pipe_config->pipe_bpp = 18;
  1155. break;
  1156. case TRANS_DDI_BPC_8:
  1157. pipe_config->pipe_bpp = 24;
  1158. break;
  1159. case TRANS_DDI_BPC_10:
  1160. pipe_config->pipe_bpp = 30;
  1161. break;
  1162. case TRANS_DDI_BPC_12:
  1163. pipe_config->pipe_bpp = 36;
  1164. break;
  1165. default:
  1166. break;
  1167. }
  1168. switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
  1169. case TRANS_DDI_MODE_SELECT_HDMI:
  1170. case TRANS_DDI_MODE_SELECT_DVI:
  1171. case TRANS_DDI_MODE_SELECT_FDI:
  1172. break;
  1173. case TRANS_DDI_MODE_SELECT_DP_SST:
  1174. case TRANS_DDI_MODE_SELECT_DP_MST:
  1175. pipe_config->has_dp_encoder = true;
  1176. intel_dp_get_m_n(intel_crtc, pipe_config);
  1177. break;
  1178. default:
  1179. break;
  1180. }
  1181. }
  1182. static void intel_ddi_destroy(struct drm_encoder *encoder)
  1183. {
  1184. /* HDMI has nothing special to destroy, so we can go with this. */
  1185. intel_dp_encoder_destroy(encoder);
  1186. }
  1187. static bool intel_ddi_compute_config(struct intel_encoder *encoder,
  1188. struct intel_crtc_config *pipe_config)
  1189. {
  1190. int type = encoder->type;
  1191. int port = intel_ddi_get_encoder_port(encoder);
  1192. WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
  1193. if (port == PORT_A)
  1194. pipe_config->cpu_transcoder = TRANSCODER_EDP;
  1195. if (type == INTEL_OUTPUT_HDMI)
  1196. return intel_hdmi_compute_config(encoder, pipe_config);
  1197. else
  1198. return intel_dp_compute_config(encoder, pipe_config);
  1199. }
  1200. static const struct drm_encoder_funcs intel_ddi_funcs = {
  1201. .destroy = intel_ddi_destroy,
  1202. };
  1203. static struct intel_connector *
  1204. intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
  1205. {
  1206. struct intel_connector *connector;
  1207. enum port port = intel_dig_port->port;
  1208. connector = kzalloc(sizeof(*connector), GFP_KERNEL);
  1209. if (!connector)
  1210. return NULL;
  1211. intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
  1212. if (!intel_dp_init_connector(intel_dig_port, connector)) {
  1213. kfree(connector);
  1214. return NULL;
  1215. }
  1216. return connector;
  1217. }
  1218. static struct intel_connector *
  1219. intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
  1220. {
  1221. struct intel_connector *connector;
  1222. enum port port = intel_dig_port->port;
  1223. connector = kzalloc(sizeof(*connector), GFP_KERNEL);
  1224. if (!connector)
  1225. return NULL;
  1226. intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
  1227. intel_hdmi_init_connector(intel_dig_port, connector);
  1228. return connector;
  1229. }
  1230. void intel_ddi_init(struct drm_device *dev, enum port port)
  1231. {
  1232. struct drm_i915_private *dev_priv = dev->dev_private;
  1233. struct intel_digital_port *intel_dig_port;
  1234. struct intel_encoder *intel_encoder;
  1235. struct drm_encoder *encoder;
  1236. struct intel_connector *hdmi_connector = NULL;
  1237. struct intel_connector *dp_connector = NULL;
  1238. bool init_hdmi, init_dp;
  1239. init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
  1240. dev_priv->vbt.ddi_port_info[port].supports_hdmi);
  1241. init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
  1242. if (!init_dp && !init_hdmi) {
  1243. DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n",
  1244. port_name(port));
  1245. init_hdmi = true;
  1246. init_dp = true;
  1247. }
  1248. intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
  1249. if (!intel_dig_port)
  1250. return;
  1251. intel_encoder = &intel_dig_port->base;
  1252. encoder = &intel_encoder->base;
  1253. drm_encoder_init(dev, encoder, &intel_ddi_funcs,
  1254. DRM_MODE_ENCODER_TMDS);
  1255. intel_encoder->compute_config = intel_ddi_compute_config;
  1256. intel_encoder->mode_set = intel_ddi_mode_set;
  1257. intel_encoder->enable = intel_enable_ddi;
  1258. intel_encoder->pre_enable = intel_ddi_pre_enable;
  1259. intel_encoder->disable = intel_disable_ddi;
  1260. intel_encoder->post_disable = intel_ddi_post_disable;
  1261. intel_encoder->get_hw_state = intel_ddi_get_hw_state;
  1262. intel_encoder->get_config = intel_ddi_get_config;
  1263. intel_dig_port->port = port;
  1264. intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
  1265. (DDI_BUF_PORT_REVERSAL |
  1266. DDI_A_4_LANES);
  1267. intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
  1268. intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  1269. intel_encoder->cloneable = false;
  1270. intel_encoder->hot_plug = intel_ddi_hot_plug;
  1271. if (init_dp)
  1272. dp_connector = intel_ddi_init_dp_connector(intel_dig_port);
  1273. /* In theory we don't need the encoder->type check, but leave it just in
  1274. * case we have some really bad VBTs... */
  1275. if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi)
  1276. hdmi_connector = intel_ddi_init_hdmi_connector(intel_dig_port);
  1277. if (!dp_connector && !hdmi_connector) {
  1278. drm_encoder_cleanup(encoder);
  1279. kfree(intel_dig_port);
  1280. }
  1281. }