nv50_fbcon.c 7.0 KB

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  1. #include "drmP.h"
  2. #include "nouveau_drv.h"
  3. #include "nouveau_dma.h"
  4. #include "nouveau_fbcon.h"
  5. static void
  6. nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  7. {
  8. struct nouveau_fbcon_par *par = info->par;
  9. struct drm_device *dev = par->dev;
  10. struct drm_nouveau_private *dev_priv = dev->dev_private;
  11. struct nouveau_channel *chan = dev_priv->channel;
  12. uint32_t color = ((uint32_t *) info->pseudo_palette)[rect->color];
  13. if (info->state != FBINFO_STATE_RUNNING)
  14. return;
  15. if (!(info->flags & FBINFO_HWACCEL_DISABLED) &&
  16. RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11)) {
  17. NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
  18. info->flags |= FBINFO_HWACCEL_DISABLED;
  19. }
  20. if (info->flags & FBINFO_HWACCEL_DISABLED) {
  21. cfb_fillrect(info, rect);
  22. return;
  23. }
  24. if (rect->rop != ROP_COPY) {
  25. BEGIN_RING(chan, NvSub2D, 0x02ac, 1);
  26. OUT_RING(chan, 1);
  27. }
  28. BEGIN_RING(chan, NvSub2D, 0x0588, 1);
  29. OUT_RING(chan, color);
  30. BEGIN_RING(chan, NvSub2D, 0x0600, 4);
  31. OUT_RING(chan, rect->dx);
  32. OUT_RING(chan, rect->dy);
  33. OUT_RING(chan, rect->dx + rect->width);
  34. OUT_RING(chan, rect->dy + rect->height);
  35. if (rect->rop != ROP_COPY) {
  36. BEGIN_RING(chan, NvSub2D, 0x02ac, 1);
  37. OUT_RING(chan, 3);
  38. }
  39. FIRE_RING(chan);
  40. }
  41. static void
  42. nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
  43. {
  44. struct nouveau_fbcon_par *par = info->par;
  45. struct drm_device *dev = par->dev;
  46. struct drm_nouveau_private *dev_priv = dev->dev_private;
  47. struct nouveau_channel *chan = dev_priv->channel;
  48. if (info->state != FBINFO_STATE_RUNNING)
  49. return;
  50. if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 12)) {
  51. NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
  52. info->flags |= FBINFO_HWACCEL_DISABLED;
  53. }
  54. if (info->flags & FBINFO_HWACCEL_DISABLED) {
  55. cfb_copyarea(info, region);
  56. return;
  57. }
  58. BEGIN_RING(chan, NvSub2D, 0x0110, 1);
  59. OUT_RING(chan, 0);
  60. BEGIN_RING(chan, NvSub2D, 0x08b0, 4);
  61. OUT_RING(chan, region->dx);
  62. OUT_RING(chan, region->dy);
  63. OUT_RING(chan, region->width);
  64. OUT_RING(chan, region->height);
  65. BEGIN_RING(chan, NvSub2D, 0x08d0, 4);
  66. OUT_RING(chan, 0);
  67. OUT_RING(chan, region->sx);
  68. OUT_RING(chan, 0);
  69. OUT_RING(chan, region->sy);
  70. FIRE_RING(chan);
  71. }
  72. static void
  73. nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
  74. {
  75. struct nouveau_fbcon_par *par = info->par;
  76. struct drm_device *dev = par->dev;
  77. struct drm_nouveau_private *dev_priv = dev->dev_private;
  78. struct nouveau_channel *chan = dev_priv->channel;
  79. uint32_t width, dwords, *data = (uint32_t *)image->data;
  80. uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel));
  81. uint32_t *palette = info->pseudo_palette;
  82. if (info->state != FBINFO_STATE_RUNNING)
  83. return;
  84. if (image->depth != 1) {
  85. cfb_imageblit(info, image);
  86. return;
  87. }
  88. if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 11)) {
  89. NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
  90. info->flags |= FBINFO_HWACCEL_DISABLED;
  91. }
  92. if (info->flags & FBINFO_HWACCEL_DISABLED) {
  93. cfb_imageblit(info, image);
  94. return;
  95. }
  96. width = (image->width + 31) & ~31;
  97. dwords = (width * image->height) >> 5;
  98. BEGIN_RING(chan, NvSub2D, 0x0814, 2);
  99. if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
  100. info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
  101. OUT_RING(chan, palette[image->bg_color] | mask);
  102. OUT_RING(chan, palette[image->fg_color] | mask);
  103. } else {
  104. OUT_RING(chan, image->bg_color);
  105. OUT_RING(chan, image->fg_color);
  106. }
  107. BEGIN_RING(chan, NvSub2D, 0x0838, 2);
  108. OUT_RING(chan, image->width);
  109. OUT_RING(chan, image->height);
  110. BEGIN_RING(chan, NvSub2D, 0x0850, 4);
  111. OUT_RING(chan, 0);
  112. OUT_RING(chan, image->dx);
  113. OUT_RING(chan, 0);
  114. OUT_RING(chan, image->dy);
  115. while (dwords) {
  116. int push = dwords > 2047 ? 2047 : dwords;
  117. if (RING_SPACE(chan, push + 1)) {
  118. NV_ERROR(dev,
  119. "GPU lockup - switching to software fbcon\n");
  120. info->flags |= FBINFO_HWACCEL_DISABLED;
  121. cfb_imageblit(info, image);
  122. return;
  123. }
  124. dwords -= push;
  125. BEGIN_RING(chan, NvSub2D, 0x40000860, push);
  126. OUT_RINGp(chan, data, push);
  127. data += push;
  128. }
  129. FIRE_RING(chan);
  130. }
  131. int
  132. nv50_fbcon_accel_init(struct fb_info *info)
  133. {
  134. struct nouveau_fbcon_par *par = info->par;
  135. struct drm_device *dev = par->dev;
  136. struct drm_nouveau_private *dev_priv = dev->dev_private;
  137. struct nouveau_channel *chan = dev_priv->channel;
  138. struct nouveau_gpuobj *eng2d = NULL;
  139. int ret, format;
  140. switch (info->var.bits_per_pixel) {
  141. case 8:
  142. format = 0xf3;
  143. break;
  144. case 15:
  145. format = 0xf8;
  146. break;
  147. case 16:
  148. format = 0xe8;
  149. break;
  150. case 32:
  151. switch (info->var.transp.length) {
  152. case 0: /* depth 24 */
  153. case 8: /* depth 32, just use 24.. */
  154. format = 0xe6;
  155. break;
  156. case 2: /* depth 30 */
  157. format = 0xd1;
  158. break;
  159. default:
  160. return -EINVAL;
  161. }
  162. break;
  163. default:
  164. return -EINVAL;
  165. }
  166. ret = nouveau_gpuobj_gr_new(dev_priv->channel, 0x502d, &eng2d);
  167. if (ret)
  168. return ret;
  169. ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, Nv2D, eng2d, NULL);
  170. if (ret)
  171. return ret;
  172. ret = RING_SPACE(chan, 59);
  173. if (ret) {
  174. NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
  175. return ret;
  176. }
  177. BEGIN_RING(chan, NvSub2D, 0x0000, 1);
  178. OUT_RING(chan, Nv2D);
  179. BEGIN_RING(chan, NvSub2D, 0x0180, 4);
  180. OUT_RING(chan, NvNotify0);
  181. OUT_RING(chan, chan->vram_handle);
  182. OUT_RING(chan, chan->vram_handle);
  183. OUT_RING(chan, chan->vram_handle);
  184. BEGIN_RING(chan, NvSub2D, 0x0290, 1);
  185. OUT_RING(chan, 0);
  186. BEGIN_RING(chan, NvSub2D, 0x0888, 1);
  187. OUT_RING(chan, 1);
  188. BEGIN_RING(chan, NvSub2D, 0x02ac, 1);
  189. OUT_RING(chan, 3);
  190. BEGIN_RING(chan, NvSub2D, 0x02a0, 1);
  191. OUT_RING(chan, 0x55);
  192. BEGIN_RING(chan, NvSub2D, 0x08c0, 4);
  193. OUT_RING(chan, 0);
  194. OUT_RING(chan, 1);
  195. OUT_RING(chan, 0);
  196. OUT_RING(chan, 1);
  197. BEGIN_RING(chan, NvSub2D, 0x0580, 2);
  198. OUT_RING(chan, 4);
  199. OUT_RING(chan, format);
  200. BEGIN_RING(chan, NvSub2D, 0x02e8, 2);
  201. OUT_RING(chan, 2);
  202. OUT_RING(chan, 1);
  203. BEGIN_RING(chan, NvSub2D, 0x0804, 1);
  204. OUT_RING(chan, format);
  205. BEGIN_RING(chan, NvSub2D, 0x0800, 1);
  206. OUT_RING(chan, 1);
  207. BEGIN_RING(chan, NvSub2D, 0x0808, 3);
  208. OUT_RING(chan, 0);
  209. OUT_RING(chan, 0);
  210. OUT_RING(chan, 0);
  211. BEGIN_RING(chan, NvSub2D, 0x081c, 1);
  212. OUT_RING(chan, 1);
  213. BEGIN_RING(chan, NvSub2D, 0x0840, 4);
  214. OUT_RING(chan, 0);
  215. OUT_RING(chan, 1);
  216. OUT_RING(chan, 0);
  217. OUT_RING(chan, 1);
  218. BEGIN_RING(chan, NvSub2D, 0x0200, 2);
  219. OUT_RING(chan, format);
  220. OUT_RING(chan, 1);
  221. BEGIN_RING(chan, NvSub2D, 0x0214, 5);
  222. OUT_RING(chan, info->fix.line_length);
  223. OUT_RING(chan, info->var.xres_virtual);
  224. OUT_RING(chan, info->var.yres_virtual);
  225. OUT_RING(chan, 0);
  226. OUT_RING(chan, info->fix.smem_start - dev_priv->fb_phys +
  227. dev_priv->vm_vram_base);
  228. BEGIN_RING(chan, NvSub2D, 0x0230, 2);
  229. OUT_RING(chan, format);
  230. OUT_RING(chan, 1);
  231. BEGIN_RING(chan, NvSub2D, 0x0244, 5);
  232. OUT_RING(chan, info->fix.line_length);
  233. OUT_RING(chan, info->var.xres_virtual);
  234. OUT_RING(chan, info->var.yres_virtual);
  235. OUT_RING(chan, 0);
  236. OUT_RING(chan, info->fix.smem_start - dev_priv->fb_phys +
  237. dev_priv->vm_vram_base);
  238. info->fbops->fb_fillrect = nv50_fbcon_fillrect;
  239. info->fbops->fb_copyarea = nv50_fbcon_copyarea;
  240. info->fbops->fb_imageblit = nv50_fbcon_imageblit;
  241. return 0;
  242. }