devices.c 22 KB

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  1. #include <linux/module.h>
  2. #include <linux/kernel.h>
  3. #include <linux/init.h>
  4. #include <linux/platform_device.h>
  5. #include <linux/dma-mapping.h>
  6. #include <linux/spi/pxa2xx_spi.h>
  7. #include <linux/i2c/pxa-i2c.h>
  8. #include <mach/udc.h>
  9. #include <mach/pxa3xx-u2d.h>
  10. #include <mach/pxafb.h>
  11. #include <mach/mmc.h>
  12. #include <mach/irda.h>
  13. #include <mach/irqs.h>
  14. #include <mach/ohci.h>
  15. #include <plat/pxa27x_keypad.h>
  16. #include <mach/camera.h>
  17. #include <mach/audio.h>
  18. #include <mach/hardware.h>
  19. #include <plat/pxa3xx_nand.h>
  20. #include "devices.h"
  21. #include "generic.h"
  22. void __init pxa_register_device(struct platform_device *dev, void *data)
  23. {
  24. int ret;
  25. dev->dev.platform_data = data;
  26. ret = platform_device_register(dev);
  27. if (ret)
  28. dev_err(&dev->dev, "unable to register device: %d\n", ret);
  29. }
  30. static struct resource pxa_resource_pmu = {
  31. .start = IRQ_PMU,
  32. .end = IRQ_PMU,
  33. .flags = IORESOURCE_IRQ,
  34. };
  35. struct platform_device pxa_device_pmu = {
  36. .name = "arm-pmu",
  37. .id = -1,
  38. .resource = &pxa_resource_pmu,
  39. .num_resources = 1,
  40. };
  41. static struct resource pxamci_resources[] = {
  42. [0] = {
  43. .start = 0x41100000,
  44. .end = 0x41100fff,
  45. .flags = IORESOURCE_MEM,
  46. },
  47. [1] = {
  48. .start = IRQ_MMC,
  49. .end = IRQ_MMC,
  50. .flags = IORESOURCE_IRQ,
  51. },
  52. [2] = {
  53. .start = 21,
  54. .end = 21,
  55. .flags = IORESOURCE_DMA,
  56. },
  57. [3] = {
  58. .start = 22,
  59. .end = 22,
  60. .flags = IORESOURCE_DMA,
  61. },
  62. };
  63. static u64 pxamci_dmamask = 0xffffffffUL;
  64. struct platform_device pxa_device_mci = {
  65. .name = "pxa2xx-mci",
  66. .id = 0,
  67. .dev = {
  68. .dma_mask = &pxamci_dmamask,
  69. .coherent_dma_mask = 0xffffffff,
  70. },
  71. .num_resources = ARRAY_SIZE(pxamci_resources),
  72. .resource = pxamci_resources,
  73. };
  74. void __init pxa_set_mci_info(struct pxamci_platform_data *info)
  75. {
  76. pxa_register_device(&pxa_device_mci, info);
  77. }
  78. static struct pxa2xx_udc_mach_info pxa_udc_info = {
  79. .gpio_pullup = -1,
  80. };
  81. void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
  82. {
  83. memcpy(&pxa_udc_info, info, sizeof *info);
  84. }
  85. static struct resource pxa2xx_udc_resources[] = {
  86. [0] = {
  87. .start = 0x40600000,
  88. .end = 0x4060ffff,
  89. .flags = IORESOURCE_MEM,
  90. },
  91. [1] = {
  92. .start = IRQ_USB,
  93. .end = IRQ_USB,
  94. .flags = IORESOURCE_IRQ,
  95. },
  96. };
  97. static u64 udc_dma_mask = ~(u32)0;
  98. struct platform_device pxa25x_device_udc = {
  99. .name = "pxa25x-udc",
  100. .id = -1,
  101. .resource = pxa2xx_udc_resources,
  102. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  103. .dev = {
  104. .platform_data = &pxa_udc_info,
  105. .dma_mask = &udc_dma_mask,
  106. }
  107. };
  108. struct platform_device pxa27x_device_udc = {
  109. .name = "pxa27x-udc",
  110. .id = -1,
  111. .resource = pxa2xx_udc_resources,
  112. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  113. .dev = {
  114. .platform_data = &pxa_udc_info,
  115. .dma_mask = &udc_dma_mask,
  116. }
  117. };
  118. #ifdef CONFIG_PXA3xx
  119. static struct resource pxa3xx_u2d_resources[] = {
  120. [0] = {
  121. .start = 0x54100000,
  122. .end = 0x54100fff,
  123. .flags = IORESOURCE_MEM,
  124. },
  125. [1] = {
  126. .start = IRQ_USB2,
  127. .end = IRQ_USB2,
  128. .flags = IORESOURCE_IRQ,
  129. },
  130. };
  131. struct platform_device pxa3xx_device_u2d = {
  132. .name = "pxa3xx-u2d",
  133. .id = -1,
  134. .resource = pxa3xx_u2d_resources,
  135. .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources),
  136. };
  137. void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
  138. {
  139. pxa_register_device(&pxa3xx_device_u2d, info);
  140. }
  141. #endif /* CONFIG_PXA3xx */
  142. static struct resource pxafb_resources[] = {
  143. [0] = {
  144. .start = 0x44000000,
  145. .end = 0x4400ffff,
  146. .flags = IORESOURCE_MEM,
  147. },
  148. [1] = {
  149. .start = IRQ_LCD,
  150. .end = IRQ_LCD,
  151. .flags = IORESOURCE_IRQ,
  152. },
  153. };
  154. static u64 fb_dma_mask = ~(u64)0;
  155. struct platform_device pxa_device_fb = {
  156. .name = "pxa2xx-fb",
  157. .id = -1,
  158. .dev = {
  159. .dma_mask = &fb_dma_mask,
  160. .coherent_dma_mask = 0xffffffff,
  161. },
  162. .num_resources = ARRAY_SIZE(pxafb_resources),
  163. .resource = pxafb_resources,
  164. };
  165. void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
  166. {
  167. pxa_device_fb.dev.parent = parent;
  168. pxa_register_device(&pxa_device_fb, info);
  169. }
  170. static struct resource pxa_resource_ffuart[] = {
  171. {
  172. .start = 0x40100000,
  173. .end = 0x40100023,
  174. .flags = IORESOURCE_MEM,
  175. }, {
  176. .start = IRQ_FFUART,
  177. .end = IRQ_FFUART,
  178. .flags = IORESOURCE_IRQ,
  179. }
  180. };
  181. struct platform_device pxa_device_ffuart = {
  182. .name = "pxa2xx-uart",
  183. .id = 0,
  184. .resource = pxa_resource_ffuart,
  185. .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
  186. };
  187. void __init pxa_set_ffuart_info(void *info)
  188. {
  189. pxa_register_device(&pxa_device_ffuart, info);
  190. }
  191. static struct resource pxa_resource_btuart[] = {
  192. {
  193. .start = 0x40200000,
  194. .end = 0x40200023,
  195. .flags = IORESOURCE_MEM,
  196. }, {
  197. .start = IRQ_BTUART,
  198. .end = IRQ_BTUART,
  199. .flags = IORESOURCE_IRQ,
  200. }
  201. };
  202. struct platform_device pxa_device_btuart = {
  203. .name = "pxa2xx-uart",
  204. .id = 1,
  205. .resource = pxa_resource_btuart,
  206. .num_resources = ARRAY_SIZE(pxa_resource_btuart),
  207. };
  208. void __init pxa_set_btuart_info(void *info)
  209. {
  210. pxa_register_device(&pxa_device_btuart, info);
  211. }
  212. static struct resource pxa_resource_stuart[] = {
  213. {
  214. .start = 0x40700000,
  215. .end = 0x40700023,
  216. .flags = IORESOURCE_MEM,
  217. }, {
  218. .start = IRQ_STUART,
  219. .end = IRQ_STUART,
  220. .flags = IORESOURCE_IRQ,
  221. }
  222. };
  223. struct platform_device pxa_device_stuart = {
  224. .name = "pxa2xx-uart",
  225. .id = 2,
  226. .resource = pxa_resource_stuart,
  227. .num_resources = ARRAY_SIZE(pxa_resource_stuart),
  228. };
  229. void __init pxa_set_stuart_info(void *info)
  230. {
  231. pxa_register_device(&pxa_device_stuart, info);
  232. }
  233. static struct resource pxa_resource_hwuart[] = {
  234. {
  235. .start = 0x41600000,
  236. .end = 0x4160002F,
  237. .flags = IORESOURCE_MEM,
  238. }, {
  239. .start = IRQ_HWUART,
  240. .end = IRQ_HWUART,
  241. .flags = IORESOURCE_IRQ,
  242. }
  243. };
  244. struct platform_device pxa_device_hwuart = {
  245. .name = "pxa2xx-uart",
  246. .id = 3,
  247. .resource = pxa_resource_hwuart,
  248. .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
  249. };
  250. void __init pxa_set_hwuart_info(void *info)
  251. {
  252. if (cpu_is_pxa255())
  253. pxa_register_device(&pxa_device_hwuart, info);
  254. else
  255. pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
  256. }
  257. static struct resource pxai2c_resources[] = {
  258. {
  259. .start = 0x40301680,
  260. .end = 0x403016a3,
  261. .flags = IORESOURCE_MEM,
  262. }, {
  263. .start = IRQ_I2C,
  264. .end = IRQ_I2C,
  265. .flags = IORESOURCE_IRQ,
  266. },
  267. };
  268. struct platform_device pxa_device_i2c = {
  269. .name = "pxa2xx-i2c",
  270. .id = 0,
  271. .resource = pxai2c_resources,
  272. .num_resources = ARRAY_SIZE(pxai2c_resources),
  273. };
  274. void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
  275. {
  276. pxa_register_device(&pxa_device_i2c, info);
  277. }
  278. #ifdef CONFIG_PXA27x
  279. static struct resource pxa27x_resources_i2c_power[] = {
  280. {
  281. .start = 0x40f00180,
  282. .end = 0x40f001a3,
  283. .flags = IORESOURCE_MEM,
  284. }, {
  285. .start = IRQ_PWRI2C,
  286. .end = IRQ_PWRI2C,
  287. .flags = IORESOURCE_IRQ,
  288. },
  289. };
  290. struct platform_device pxa27x_device_i2c_power = {
  291. .name = "pxa2xx-i2c",
  292. .id = 1,
  293. .resource = pxa27x_resources_i2c_power,
  294. .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
  295. };
  296. #endif
  297. static struct resource pxai2s_resources[] = {
  298. {
  299. .start = 0x40400000,
  300. .end = 0x40400083,
  301. .flags = IORESOURCE_MEM,
  302. }, {
  303. .start = IRQ_I2S,
  304. .end = IRQ_I2S,
  305. .flags = IORESOURCE_IRQ,
  306. },
  307. };
  308. struct platform_device pxa_device_i2s = {
  309. .name = "pxa2xx-i2s",
  310. .id = -1,
  311. .resource = pxai2s_resources,
  312. .num_resources = ARRAY_SIZE(pxai2s_resources),
  313. };
  314. struct platform_device pxa_device_asoc_ssp1 = {
  315. .name = "pxa-ssp-dai",
  316. .id = 0,
  317. };
  318. struct platform_device pxa_device_asoc_ssp2= {
  319. .name = "pxa-ssp-dai",
  320. .id = 1,
  321. };
  322. struct platform_device pxa_device_asoc_ssp3 = {
  323. .name = "pxa-ssp-dai",
  324. .id = 2,
  325. };
  326. struct platform_device pxa_device_asoc_ssp4 = {
  327. .name = "pxa-ssp-dai",
  328. .id = 3,
  329. };
  330. struct platform_device pxa_device_asoc_platform = {
  331. .name = "pxa-pcm-audio",
  332. .id = -1,
  333. };
  334. static u64 pxaficp_dmamask = ~(u32)0;
  335. struct platform_device pxa_device_ficp = {
  336. .name = "pxa2xx-ir",
  337. .id = -1,
  338. .dev = {
  339. .dma_mask = &pxaficp_dmamask,
  340. .coherent_dma_mask = 0xffffffff,
  341. },
  342. };
  343. void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
  344. {
  345. pxa_register_device(&pxa_device_ficp, info);
  346. }
  347. static struct resource pxa_rtc_resources[] = {
  348. [0] = {
  349. .start = 0x40900000,
  350. .end = 0x40900000 + 0x3b,
  351. .flags = IORESOURCE_MEM,
  352. },
  353. [1] = {
  354. .start = IRQ_RTC1Hz,
  355. .end = IRQ_RTC1Hz,
  356. .name = "rtc 1Hz",
  357. .flags = IORESOURCE_IRQ,
  358. },
  359. [2] = {
  360. .start = IRQ_RTCAlrm,
  361. .end = IRQ_RTCAlrm,
  362. .name = "rtc alarm",
  363. .flags = IORESOURCE_IRQ,
  364. },
  365. };
  366. struct platform_device pxa_device_rtc = {
  367. .name = "pxa-rtc",
  368. .id = -1,
  369. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  370. .resource = pxa_rtc_resources,
  371. };
  372. static struct resource sa1100_rtc_resources[] = {
  373. {
  374. .start = IRQ_RTC1Hz,
  375. .end = IRQ_RTC1Hz,
  376. .name = "rtc 1Hz",
  377. .flags = IORESOURCE_IRQ,
  378. }, {
  379. .start = IRQ_RTCAlrm,
  380. .end = IRQ_RTCAlrm,
  381. .name = "rtc alarm",
  382. .flags = IORESOURCE_IRQ,
  383. },
  384. };
  385. struct platform_device sa1100_device_rtc = {
  386. .name = "sa1100-rtc",
  387. .id = -1,
  388. .num_resources = ARRAY_SIZE(sa1100_rtc_resources),
  389. .resource = sa1100_rtc_resources,
  390. };
  391. static struct resource pxa_ac97_resources[] = {
  392. [0] = {
  393. .start = 0x40500000,
  394. .end = 0x40500000 + 0xfff,
  395. .flags = IORESOURCE_MEM,
  396. },
  397. [1] = {
  398. .start = IRQ_AC97,
  399. .end = IRQ_AC97,
  400. .flags = IORESOURCE_IRQ,
  401. },
  402. };
  403. static u64 pxa_ac97_dmamask = 0xffffffffUL;
  404. struct platform_device pxa_device_ac97 = {
  405. .name = "pxa2xx-ac97",
  406. .id = -1,
  407. .dev = {
  408. .dma_mask = &pxa_ac97_dmamask,
  409. .coherent_dma_mask = 0xffffffff,
  410. },
  411. .num_resources = ARRAY_SIZE(pxa_ac97_resources),
  412. .resource = pxa_ac97_resources,
  413. };
  414. void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
  415. {
  416. pxa_register_device(&pxa_device_ac97, ops);
  417. }
  418. #ifdef CONFIG_PXA25x
  419. static struct resource pxa25x_resource_pwm0[] = {
  420. [0] = {
  421. .start = 0x40b00000,
  422. .end = 0x40b0000f,
  423. .flags = IORESOURCE_MEM,
  424. },
  425. };
  426. struct platform_device pxa25x_device_pwm0 = {
  427. .name = "pxa25x-pwm",
  428. .id = 0,
  429. .resource = pxa25x_resource_pwm0,
  430. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
  431. };
  432. static struct resource pxa25x_resource_pwm1[] = {
  433. [0] = {
  434. .start = 0x40c00000,
  435. .end = 0x40c0000f,
  436. .flags = IORESOURCE_MEM,
  437. },
  438. };
  439. struct platform_device pxa25x_device_pwm1 = {
  440. .name = "pxa25x-pwm",
  441. .id = 1,
  442. .resource = pxa25x_resource_pwm1,
  443. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
  444. };
  445. static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
  446. static struct resource pxa25x_resource_ssp[] = {
  447. [0] = {
  448. .start = 0x41000000,
  449. .end = 0x4100001f,
  450. .flags = IORESOURCE_MEM,
  451. },
  452. [1] = {
  453. .start = IRQ_SSP,
  454. .end = IRQ_SSP,
  455. .flags = IORESOURCE_IRQ,
  456. },
  457. [2] = {
  458. /* DRCMR for RX */
  459. .start = 13,
  460. .end = 13,
  461. .flags = IORESOURCE_DMA,
  462. },
  463. [3] = {
  464. /* DRCMR for TX */
  465. .start = 14,
  466. .end = 14,
  467. .flags = IORESOURCE_DMA,
  468. },
  469. };
  470. struct platform_device pxa25x_device_ssp = {
  471. .name = "pxa25x-ssp",
  472. .id = 0,
  473. .dev = {
  474. .dma_mask = &pxa25x_ssp_dma_mask,
  475. .coherent_dma_mask = DMA_BIT_MASK(32),
  476. },
  477. .resource = pxa25x_resource_ssp,
  478. .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
  479. };
  480. static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
  481. static struct resource pxa25x_resource_nssp[] = {
  482. [0] = {
  483. .start = 0x41400000,
  484. .end = 0x4140002f,
  485. .flags = IORESOURCE_MEM,
  486. },
  487. [1] = {
  488. .start = IRQ_NSSP,
  489. .end = IRQ_NSSP,
  490. .flags = IORESOURCE_IRQ,
  491. },
  492. [2] = {
  493. /* DRCMR for RX */
  494. .start = 15,
  495. .end = 15,
  496. .flags = IORESOURCE_DMA,
  497. },
  498. [3] = {
  499. /* DRCMR for TX */
  500. .start = 16,
  501. .end = 16,
  502. .flags = IORESOURCE_DMA,
  503. },
  504. };
  505. struct platform_device pxa25x_device_nssp = {
  506. .name = "pxa25x-nssp",
  507. .id = 1,
  508. .dev = {
  509. .dma_mask = &pxa25x_nssp_dma_mask,
  510. .coherent_dma_mask = DMA_BIT_MASK(32),
  511. },
  512. .resource = pxa25x_resource_nssp,
  513. .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
  514. };
  515. static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
  516. static struct resource pxa25x_resource_assp[] = {
  517. [0] = {
  518. .start = 0x41500000,
  519. .end = 0x4150002f,
  520. .flags = IORESOURCE_MEM,
  521. },
  522. [1] = {
  523. .start = IRQ_ASSP,
  524. .end = IRQ_ASSP,
  525. .flags = IORESOURCE_IRQ,
  526. },
  527. [2] = {
  528. /* DRCMR for RX */
  529. .start = 23,
  530. .end = 23,
  531. .flags = IORESOURCE_DMA,
  532. },
  533. [3] = {
  534. /* DRCMR for TX */
  535. .start = 24,
  536. .end = 24,
  537. .flags = IORESOURCE_DMA,
  538. },
  539. };
  540. struct platform_device pxa25x_device_assp = {
  541. /* ASSP is basically equivalent to NSSP */
  542. .name = "pxa25x-nssp",
  543. .id = 2,
  544. .dev = {
  545. .dma_mask = &pxa25x_assp_dma_mask,
  546. .coherent_dma_mask = DMA_BIT_MASK(32),
  547. },
  548. .resource = pxa25x_resource_assp,
  549. .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
  550. };
  551. #endif /* CONFIG_PXA25x */
  552. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  553. static struct resource pxa27x_resource_camera[] = {
  554. [0] = {
  555. .start = 0x50000000,
  556. .end = 0x50000fff,
  557. .flags = IORESOURCE_MEM,
  558. },
  559. [1] = {
  560. .start = IRQ_CAMERA,
  561. .end = IRQ_CAMERA,
  562. .flags = IORESOURCE_IRQ,
  563. },
  564. };
  565. static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
  566. static struct platform_device pxa27x_device_camera = {
  567. .name = "pxa27x-camera",
  568. .id = 0, /* This is used to put cameras on this interface */
  569. .dev = {
  570. .dma_mask = &pxa27x_dma_mask_camera,
  571. .coherent_dma_mask = 0xffffffff,
  572. },
  573. .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
  574. .resource = pxa27x_resource_camera,
  575. };
  576. void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
  577. {
  578. pxa_register_device(&pxa27x_device_camera, info);
  579. }
  580. static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
  581. static struct resource pxa27x_resource_ohci[] = {
  582. [0] = {
  583. .start = 0x4C000000,
  584. .end = 0x4C00ff6f,
  585. .flags = IORESOURCE_MEM,
  586. },
  587. [1] = {
  588. .start = IRQ_USBH1,
  589. .end = IRQ_USBH1,
  590. .flags = IORESOURCE_IRQ,
  591. },
  592. };
  593. struct platform_device pxa27x_device_ohci = {
  594. .name = "pxa27x-ohci",
  595. .id = -1,
  596. .dev = {
  597. .dma_mask = &pxa27x_ohci_dma_mask,
  598. .coherent_dma_mask = DMA_BIT_MASK(32),
  599. },
  600. .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
  601. .resource = pxa27x_resource_ohci,
  602. };
  603. void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
  604. {
  605. pxa_register_device(&pxa27x_device_ohci, info);
  606. }
  607. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  608. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
  609. static struct resource pxa27x_resource_keypad[] = {
  610. [0] = {
  611. .start = 0x41500000,
  612. .end = 0x4150004c,
  613. .flags = IORESOURCE_MEM,
  614. },
  615. [1] = {
  616. .start = IRQ_KEYPAD,
  617. .end = IRQ_KEYPAD,
  618. .flags = IORESOURCE_IRQ,
  619. },
  620. };
  621. struct platform_device pxa27x_device_keypad = {
  622. .name = "pxa27x-keypad",
  623. .id = -1,
  624. .resource = pxa27x_resource_keypad,
  625. .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
  626. };
  627. void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
  628. {
  629. pxa_register_device(&pxa27x_device_keypad, info);
  630. }
  631. static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
  632. static struct resource pxa27x_resource_ssp1[] = {
  633. [0] = {
  634. .start = 0x41000000,
  635. .end = 0x4100003f,
  636. .flags = IORESOURCE_MEM,
  637. },
  638. [1] = {
  639. .start = IRQ_SSP,
  640. .end = IRQ_SSP,
  641. .flags = IORESOURCE_IRQ,
  642. },
  643. [2] = {
  644. /* DRCMR for RX */
  645. .start = 13,
  646. .end = 13,
  647. .flags = IORESOURCE_DMA,
  648. },
  649. [3] = {
  650. /* DRCMR for TX */
  651. .start = 14,
  652. .end = 14,
  653. .flags = IORESOURCE_DMA,
  654. },
  655. };
  656. struct platform_device pxa27x_device_ssp1 = {
  657. .name = "pxa27x-ssp",
  658. .id = 0,
  659. .dev = {
  660. .dma_mask = &pxa27x_ssp1_dma_mask,
  661. .coherent_dma_mask = DMA_BIT_MASK(32),
  662. },
  663. .resource = pxa27x_resource_ssp1,
  664. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  665. };
  666. static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
  667. static struct resource pxa27x_resource_ssp2[] = {
  668. [0] = {
  669. .start = 0x41700000,
  670. .end = 0x4170003f,
  671. .flags = IORESOURCE_MEM,
  672. },
  673. [1] = {
  674. .start = IRQ_SSP2,
  675. .end = IRQ_SSP2,
  676. .flags = IORESOURCE_IRQ,
  677. },
  678. [2] = {
  679. /* DRCMR for RX */
  680. .start = 15,
  681. .end = 15,
  682. .flags = IORESOURCE_DMA,
  683. },
  684. [3] = {
  685. /* DRCMR for TX */
  686. .start = 16,
  687. .end = 16,
  688. .flags = IORESOURCE_DMA,
  689. },
  690. };
  691. struct platform_device pxa27x_device_ssp2 = {
  692. .name = "pxa27x-ssp",
  693. .id = 1,
  694. .dev = {
  695. .dma_mask = &pxa27x_ssp2_dma_mask,
  696. .coherent_dma_mask = DMA_BIT_MASK(32),
  697. },
  698. .resource = pxa27x_resource_ssp2,
  699. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  700. };
  701. static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
  702. static struct resource pxa27x_resource_ssp3[] = {
  703. [0] = {
  704. .start = 0x41900000,
  705. .end = 0x4190003f,
  706. .flags = IORESOURCE_MEM,
  707. },
  708. [1] = {
  709. .start = IRQ_SSP3,
  710. .end = IRQ_SSP3,
  711. .flags = IORESOURCE_IRQ,
  712. },
  713. [2] = {
  714. /* DRCMR for RX */
  715. .start = 66,
  716. .end = 66,
  717. .flags = IORESOURCE_DMA,
  718. },
  719. [3] = {
  720. /* DRCMR for TX */
  721. .start = 67,
  722. .end = 67,
  723. .flags = IORESOURCE_DMA,
  724. },
  725. };
  726. struct platform_device pxa27x_device_ssp3 = {
  727. .name = "pxa27x-ssp",
  728. .id = 2,
  729. .dev = {
  730. .dma_mask = &pxa27x_ssp3_dma_mask,
  731. .coherent_dma_mask = DMA_BIT_MASK(32),
  732. },
  733. .resource = pxa27x_resource_ssp3,
  734. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  735. };
  736. static struct resource pxa27x_resource_pwm0[] = {
  737. [0] = {
  738. .start = 0x40b00000,
  739. .end = 0x40b0001f,
  740. .flags = IORESOURCE_MEM,
  741. },
  742. };
  743. struct platform_device pxa27x_device_pwm0 = {
  744. .name = "pxa27x-pwm",
  745. .id = 0,
  746. .resource = pxa27x_resource_pwm0,
  747. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
  748. };
  749. static struct resource pxa27x_resource_pwm1[] = {
  750. [0] = {
  751. .start = 0x40c00000,
  752. .end = 0x40c0001f,
  753. .flags = IORESOURCE_MEM,
  754. },
  755. };
  756. struct platform_device pxa27x_device_pwm1 = {
  757. .name = "pxa27x-pwm",
  758. .id = 1,
  759. .resource = pxa27x_resource_pwm1,
  760. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
  761. };
  762. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx || CONFIG_PXA95x*/
  763. #ifdef CONFIG_PXA3xx
  764. static struct resource pxa3xx_resources_mci2[] = {
  765. [0] = {
  766. .start = 0x42000000,
  767. .end = 0x42000fff,
  768. .flags = IORESOURCE_MEM,
  769. },
  770. [1] = {
  771. .start = IRQ_MMC2,
  772. .end = IRQ_MMC2,
  773. .flags = IORESOURCE_IRQ,
  774. },
  775. [2] = {
  776. .start = 93,
  777. .end = 93,
  778. .flags = IORESOURCE_DMA,
  779. },
  780. [3] = {
  781. .start = 94,
  782. .end = 94,
  783. .flags = IORESOURCE_DMA,
  784. },
  785. };
  786. struct platform_device pxa3xx_device_mci2 = {
  787. .name = "pxa2xx-mci",
  788. .id = 1,
  789. .dev = {
  790. .dma_mask = &pxamci_dmamask,
  791. .coherent_dma_mask = 0xffffffff,
  792. },
  793. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
  794. .resource = pxa3xx_resources_mci2,
  795. };
  796. void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
  797. {
  798. pxa_register_device(&pxa3xx_device_mci2, info);
  799. }
  800. static struct resource pxa3xx_resources_mci3[] = {
  801. [0] = {
  802. .start = 0x42500000,
  803. .end = 0x42500fff,
  804. .flags = IORESOURCE_MEM,
  805. },
  806. [1] = {
  807. .start = IRQ_MMC3,
  808. .end = IRQ_MMC3,
  809. .flags = IORESOURCE_IRQ,
  810. },
  811. [2] = {
  812. .start = 100,
  813. .end = 100,
  814. .flags = IORESOURCE_DMA,
  815. },
  816. [3] = {
  817. .start = 101,
  818. .end = 101,
  819. .flags = IORESOURCE_DMA,
  820. },
  821. };
  822. struct platform_device pxa3xx_device_mci3 = {
  823. .name = "pxa2xx-mci",
  824. .id = 2,
  825. .dev = {
  826. .dma_mask = &pxamci_dmamask,
  827. .coherent_dma_mask = 0xffffffff,
  828. },
  829. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
  830. .resource = pxa3xx_resources_mci3,
  831. };
  832. void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
  833. {
  834. pxa_register_device(&pxa3xx_device_mci3, info);
  835. }
  836. static struct resource pxa3xx_resources_gcu[] = {
  837. {
  838. .start = 0x54000000,
  839. .end = 0x54000fff,
  840. .flags = IORESOURCE_MEM,
  841. },
  842. {
  843. .start = IRQ_GCU,
  844. .end = IRQ_GCU,
  845. .flags = IORESOURCE_IRQ,
  846. },
  847. };
  848. static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
  849. struct platform_device pxa3xx_device_gcu = {
  850. .name = "pxa3xx-gcu",
  851. .id = -1,
  852. .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
  853. .resource = pxa3xx_resources_gcu,
  854. .dev = {
  855. .dma_mask = &pxa3xx_gcu_dmamask,
  856. .coherent_dma_mask = 0xffffffff,
  857. },
  858. };
  859. #endif /* CONFIG_PXA3xx */
  860. #if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
  861. static struct resource pxa3xx_resources_i2c_power[] = {
  862. {
  863. .start = 0x40f500c0,
  864. .end = 0x40f500d3,
  865. .flags = IORESOURCE_MEM,
  866. }, {
  867. .start = IRQ_PWRI2C,
  868. .end = IRQ_PWRI2C,
  869. .flags = IORESOURCE_IRQ,
  870. },
  871. };
  872. struct platform_device pxa3xx_device_i2c_power = {
  873. .name = "pxa3xx-pwri2c",
  874. .id = 1,
  875. .resource = pxa3xx_resources_i2c_power,
  876. .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
  877. };
  878. static struct resource pxa3xx_resources_nand[] = {
  879. [0] = {
  880. .start = 0x43100000,
  881. .end = 0x43100053,
  882. .flags = IORESOURCE_MEM,
  883. },
  884. [1] = {
  885. .start = IRQ_NAND,
  886. .end = IRQ_NAND,
  887. .flags = IORESOURCE_IRQ,
  888. },
  889. [2] = {
  890. /* DRCMR for Data DMA */
  891. .start = 97,
  892. .end = 97,
  893. .flags = IORESOURCE_DMA,
  894. },
  895. [3] = {
  896. /* DRCMR for Command DMA */
  897. .start = 99,
  898. .end = 99,
  899. .flags = IORESOURCE_DMA,
  900. },
  901. };
  902. static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
  903. struct platform_device pxa3xx_device_nand = {
  904. .name = "pxa3xx-nand",
  905. .id = -1,
  906. .dev = {
  907. .dma_mask = &pxa3xx_nand_dma_mask,
  908. .coherent_dma_mask = DMA_BIT_MASK(32),
  909. },
  910. .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
  911. .resource = pxa3xx_resources_nand,
  912. };
  913. void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
  914. {
  915. pxa_register_device(&pxa3xx_device_nand, info);
  916. }
  917. static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
  918. static struct resource pxa3xx_resource_ssp4[] = {
  919. [0] = {
  920. .start = 0x41a00000,
  921. .end = 0x41a0003f,
  922. .flags = IORESOURCE_MEM,
  923. },
  924. [1] = {
  925. .start = IRQ_SSP4,
  926. .end = IRQ_SSP4,
  927. .flags = IORESOURCE_IRQ,
  928. },
  929. [2] = {
  930. /* DRCMR for RX */
  931. .start = 2,
  932. .end = 2,
  933. .flags = IORESOURCE_DMA,
  934. },
  935. [3] = {
  936. /* DRCMR for TX */
  937. .start = 3,
  938. .end = 3,
  939. .flags = IORESOURCE_DMA,
  940. },
  941. };
  942. struct platform_device pxa3xx_device_ssp4 = {
  943. /* PXA3xx SSP is basically equivalent to PXA27x */
  944. .name = "pxa27x-ssp",
  945. .id = 3,
  946. .dev = {
  947. .dma_mask = &pxa3xx_ssp4_dma_mask,
  948. .coherent_dma_mask = DMA_BIT_MASK(32),
  949. },
  950. .resource = pxa3xx_resource_ssp4,
  951. .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
  952. };
  953. #endif /* CONFIG_PXA3xx || CONFIG_PXA95x */
  954. struct resource pxa_resource_gpio[] = {
  955. {
  956. .start = 0x40e00000,
  957. .end = 0x40e0ffff,
  958. .flags = IORESOURCE_MEM,
  959. }, {
  960. .start = IRQ_GPIO0,
  961. .end = IRQ_GPIO0,
  962. .name = "gpio0",
  963. .flags = IORESOURCE_IRQ,
  964. }, {
  965. .start = IRQ_GPIO1,
  966. .end = IRQ_GPIO1,
  967. .name = "gpio1",
  968. .flags = IORESOURCE_IRQ,
  969. }, {
  970. .start = IRQ_GPIO_2_x,
  971. .end = IRQ_GPIO_2_x,
  972. .name = "gpio_mux",
  973. .flags = IORESOURCE_IRQ,
  974. },
  975. };
  976. struct platform_device pxa_device_gpio = {
  977. .name = "pxa-gpio",
  978. .id = -1,
  979. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  980. .resource = pxa_resource_gpio,
  981. };
  982. /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  983. * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
  984. void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
  985. {
  986. struct platform_device *pd;
  987. pd = platform_device_alloc("pxa2xx-spi", id);
  988. if (pd == NULL) {
  989. printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
  990. id);
  991. return;
  992. }
  993. pd->dev.platform_data = info;
  994. platform_device_add(pd);
  995. }