sun4d_irq.c 14 KB

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  1. /*
  2. * SS1000/SC2000 interrupt handling.
  3. *
  4. * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  5. * Heavily based on arch/sparc/kernel/irq.c.
  6. */
  7. #include <linux/kernel_stat.h>
  8. #include <linux/seq_file.h>
  9. #include <asm/timer.h>
  10. #include <asm/traps.h>
  11. #include <asm/irq.h>
  12. #include <asm/io.h>
  13. #include <asm/sbi.h>
  14. #include <asm/cacheflush.h>
  15. #include "kernel.h"
  16. #include "irq.h"
  17. /* Sun4d interrupts fall roughly into two categories. SBUS and
  18. * cpu local. CPU local interrupts cover the timer interrupts
  19. * and whatnot, and we encode those as normal PILs between
  20. * 0 and 15.
  21. *
  22. * SBUS interrupts are encoded integers including the board number
  23. * (plus one), the SBUS level, and the SBUS slot number. Sun4D
  24. * IRQ dispatch is done by:
  25. *
  26. * 1) Reading the BW local interrupt table in order to get the bus
  27. * interrupt mask.
  28. *
  29. * This table is indexed by SBUS interrupt level which can be
  30. * derived from the PIL we got interrupted on.
  31. *
  32. * 2) For each bus showing interrupt pending from #1, read the
  33. * SBI interrupt state register. This will indicate which slots
  34. * have interrupts pending for that SBUS interrupt level.
  35. */
  36. /*
  37. * If you trust current SCSI layer to handle different
  38. * SCSI IRQs, enable this.
  39. * I don't trust it... -jj
  40. */
  41. /* #define DISTRIBUTE_IRQS */
  42. struct sun4d_timer_regs {
  43. u32 l10_timer_limit;
  44. u32 l10_cur_countx;
  45. u32 l10_limit_noclear;
  46. u32 ctrl;
  47. u32 l10_cur_count;
  48. };
  49. static struct sun4d_timer_regs __iomem *sun4d_timers;
  50. #define TIMER_IRQ 10
  51. #define MAX_STATIC_ALLOC 4
  52. static unsigned char sbus_tid[32];
  53. static struct irqaction *irq_action[NR_IRQS];
  54. static struct sbus_action {
  55. struct irqaction *action;
  56. /* For SMP this needs to be extended */
  57. } *sbus_actions;
  58. static int pil_to_sbus[] = {
  59. 0,
  60. 0,
  61. 1,
  62. 2,
  63. 0,
  64. 3,
  65. 0,
  66. 4,
  67. 0,
  68. 5,
  69. 0,
  70. 6,
  71. 0,
  72. 7,
  73. 0,
  74. 0,
  75. };
  76. static int sbus_to_pil[] = {
  77. 0,
  78. 2,
  79. 3,
  80. 5,
  81. 7,
  82. 9,
  83. 11,
  84. 13,
  85. };
  86. static int nsbi;
  87. /* Exported for sun4d_smp.c */
  88. DEFINE_SPINLOCK(sun4d_imsk_lock);
  89. int show_sun4d_interrupts(struct seq_file *p, void *v)
  90. {
  91. int i = *(loff_t *) v, j = 0, k = 0, sbusl;
  92. struct irqaction *action;
  93. unsigned long flags;
  94. #ifdef CONFIG_SMP
  95. int x;
  96. #endif
  97. spin_lock_irqsave(&irq_action_lock, flags);
  98. if (i < NR_IRQS) {
  99. sbusl = pil_to_sbus[i];
  100. if (!sbusl) {
  101. action = *(i + irq_action);
  102. if (!action)
  103. goto out_unlock;
  104. } else {
  105. for (j = 0; j < nsbi; j++) {
  106. for (k = 0; k < 4; k++)
  107. action = sbus_actions[(j << 5) + (sbusl << 2) + k].action;
  108. if (action)
  109. goto found_it;
  110. }
  111. goto out_unlock;
  112. }
  113. found_it: seq_printf(p, "%3d: ", i);
  114. #ifndef CONFIG_SMP
  115. seq_printf(p, "%10u ", kstat_irqs(i));
  116. #else
  117. for_each_online_cpu(x)
  118. seq_printf(p, "%10u ",
  119. kstat_cpu(cpu_logical_map(x)).irqs[i]);
  120. #endif
  121. seq_printf(p, "%c %s",
  122. (action->flags & IRQF_DISABLED) ? '+' : ' ',
  123. action->name);
  124. action = action->next;
  125. for (;;) {
  126. for (; action; action = action->next) {
  127. seq_printf(p, ",%s %s",
  128. (action->flags & IRQF_DISABLED) ? " +" : "",
  129. action->name);
  130. }
  131. if (!sbusl)
  132. break;
  133. k++;
  134. if (k < 4) {
  135. action = sbus_actions[(j << 5) + (sbusl << 2) + k].action;
  136. } else {
  137. j++;
  138. if (j == nsbi)
  139. break;
  140. k = 0;
  141. action = sbus_actions[(j << 5) + (sbusl << 2)].action;
  142. }
  143. }
  144. seq_putc(p, '\n');
  145. }
  146. out_unlock:
  147. spin_unlock_irqrestore(&irq_action_lock, flags);
  148. return 0;
  149. }
  150. void sun4d_free_irq(unsigned int irq, void *dev_id)
  151. {
  152. struct irqaction *action, **actionp;
  153. struct irqaction *tmp = NULL;
  154. unsigned long flags;
  155. spin_lock_irqsave(&irq_action_lock, flags);
  156. if (irq < 15)
  157. actionp = irq + irq_action;
  158. else
  159. actionp = &(sbus_actions[irq - (1 << 5)].action);
  160. action = *actionp;
  161. if (!action) {
  162. printk(KERN_ERR "Trying to free free IRQ%d\n", irq);
  163. goto out_unlock;
  164. }
  165. if (dev_id) {
  166. for (; action; action = action->next) {
  167. if (action->dev_id == dev_id)
  168. break;
  169. tmp = action;
  170. }
  171. if (!action) {
  172. printk(KERN_ERR "Trying to free free shared IRQ%d\n",
  173. irq);
  174. goto out_unlock;
  175. }
  176. } else if (action->flags & IRQF_SHARED) {
  177. printk(KERN_ERR "Trying to free shared IRQ%d with NULL device ID\n",
  178. irq);
  179. goto out_unlock;
  180. }
  181. if (action->flags & SA_STATIC_ALLOC) {
  182. /*
  183. * This interrupt is marked as specially allocated
  184. * so it is a bad idea to free it.
  185. */
  186. printk(KERN_ERR "Attempt to free statically allocated IRQ%d (%s)\n",
  187. irq, action->name);
  188. goto out_unlock;
  189. }
  190. if (tmp)
  191. tmp->next = action->next;
  192. else
  193. *actionp = action->next;
  194. spin_unlock_irqrestore(&irq_action_lock, flags);
  195. synchronize_irq(irq);
  196. spin_lock_irqsave(&irq_action_lock, flags);
  197. kfree(action);
  198. if (!(*actionp))
  199. __disable_irq(irq);
  200. out_unlock:
  201. spin_unlock_irqrestore(&irq_action_lock, flags);
  202. }
  203. void sun4d_handler_irq(int pil, struct pt_regs *regs)
  204. {
  205. struct pt_regs *old_regs;
  206. struct irqaction *action;
  207. int cpu = smp_processor_id();
  208. /* SBUS IRQ level (1 - 7) */
  209. int sbusl = pil_to_sbus[pil];
  210. /* FIXME: Is this necessary?? */
  211. cc_get_ipen();
  212. cc_set_iclr(1 << pil);
  213. old_regs = set_irq_regs(regs);
  214. irq_enter();
  215. kstat_cpu(cpu).irqs[pil]++;
  216. if (!sbusl) {
  217. action = *(pil + irq_action);
  218. if (!action)
  219. unexpected_irq(pil, NULL, regs);
  220. do {
  221. action->handler(pil, action->dev_id);
  222. action = action->next;
  223. } while (action);
  224. } else {
  225. int bus_mask = bw_get_intr_mask(sbusl) & 0x3ffff;
  226. int sbino;
  227. struct sbus_action *actionp;
  228. unsigned mask, slot;
  229. int sbil = (sbusl << 2);
  230. bw_clear_intr_mask(sbusl, bus_mask);
  231. /* Loop for each pending SBI */
  232. for (sbino = 0; bus_mask; sbino++, bus_mask >>= 1)
  233. if (bus_mask & 1) {
  234. mask = acquire_sbi(SBI2DEVID(sbino), 0xf << sbil);
  235. mask &= (0xf << sbil);
  236. actionp = sbus_actions + (sbino << 5) + (sbil);
  237. /* Loop for each pending SBI slot */
  238. for (slot = (1 << sbil); mask; slot <<= 1, actionp++)
  239. if (mask & slot) {
  240. mask &= ~slot;
  241. action = actionp->action;
  242. if (!action)
  243. unexpected_irq(pil, NULL, regs);
  244. do {
  245. action->handler(pil, action->dev_id);
  246. action = action->next;
  247. } while (action);
  248. release_sbi(SBI2DEVID(sbino), slot);
  249. }
  250. }
  251. }
  252. irq_exit();
  253. set_irq_regs(old_regs);
  254. }
  255. int sun4d_request_irq(unsigned int irq,
  256. irq_handler_t handler,
  257. unsigned long irqflags, const char *devname, void *dev_id)
  258. {
  259. struct irqaction *action, *tmp = NULL, **actionp;
  260. unsigned long flags;
  261. int ret;
  262. if (irq > 14 && irq < (1 << 5)) {
  263. ret = -EINVAL;
  264. goto out;
  265. }
  266. if (!handler) {
  267. ret = -EINVAL;
  268. goto out;
  269. }
  270. spin_lock_irqsave(&irq_action_lock, flags);
  271. if (irq >= (1 << 5))
  272. actionp = &(sbus_actions[irq - (1 << 5)].action);
  273. else
  274. actionp = irq + irq_action;
  275. action = *actionp;
  276. if (action) {
  277. if ((action->flags & IRQF_SHARED) && (irqflags & IRQF_SHARED)) {
  278. for (tmp = action; tmp->next; tmp = tmp->next);
  279. } else {
  280. ret = -EBUSY;
  281. goto out_unlock;
  282. }
  283. if ((action->flags & IRQF_DISABLED) ^ (irqflags & IRQF_DISABLED)) {
  284. printk(KERN_ERR "Attempt to mix fast and slow interrupts on IRQ%d denied\n",
  285. irq);
  286. ret = -EBUSY;
  287. goto out_unlock;
  288. }
  289. action = NULL; /* Or else! */
  290. }
  291. /* If this is flagged as statically allocated then we use our
  292. * private struct which is never freed.
  293. */
  294. if (irqflags & SA_STATIC_ALLOC) {
  295. if (static_irq_count < MAX_STATIC_ALLOC)
  296. action = &static_irqaction[static_irq_count++];
  297. else
  298. printk(KERN_ERR "Request for IRQ%d (%s) SA_STATIC_ALLOC failed using kmalloc\n",
  299. irq, devname);
  300. }
  301. if (action == NULL)
  302. action = kmalloc(sizeof(struct irqaction), GFP_ATOMIC);
  303. if (!action) {
  304. ret = -ENOMEM;
  305. goto out_unlock;
  306. }
  307. action->handler = handler;
  308. action->flags = irqflags;
  309. action->name = devname;
  310. action->next = NULL;
  311. action->dev_id = dev_id;
  312. if (tmp)
  313. tmp->next = action;
  314. else
  315. *actionp = action;
  316. __enable_irq(irq);
  317. ret = 0;
  318. out_unlock:
  319. spin_unlock_irqrestore(&irq_action_lock, flags);
  320. out:
  321. return ret;
  322. }
  323. static void sun4d_disable_irq(unsigned int irq)
  324. {
  325. int tid = sbus_tid[(irq >> 5) - 1];
  326. unsigned long flags;
  327. if (irq < NR_IRQS)
  328. return;
  329. spin_lock_irqsave(&sun4d_imsk_lock, flags);
  330. cc_set_imsk_other(tid, cc_get_imsk_other(tid) | (1 << sbus_to_pil[(irq >> 2) & 7]));
  331. spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
  332. }
  333. static void sun4d_enable_irq(unsigned int irq)
  334. {
  335. int tid = sbus_tid[(irq >> 5) - 1];
  336. unsigned long flags;
  337. if (irq < NR_IRQS)
  338. return;
  339. spin_lock_irqsave(&sun4d_imsk_lock, flags);
  340. cc_set_imsk_other(tid, cc_get_imsk_other(tid) & ~(1 << sbus_to_pil[(irq >> 2) & 7]));
  341. spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
  342. }
  343. #ifdef CONFIG_SMP
  344. static void sun4d_set_cpu_int(int cpu, int level)
  345. {
  346. sun4d_send_ipi(cpu, level);
  347. }
  348. static void sun4d_clear_ipi(int cpu, int level)
  349. {
  350. }
  351. static void sun4d_set_udt(int cpu)
  352. {
  353. }
  354. /* Setup IRQ distribution scheme. */
  355. void __init sun4d_distribute_irqs(void)
  356. {
  357. struct device_node *dp;
  358. #ifdef DISTRIBUTE_IRQS
  359. cpumask_t sbus_serving_map;
  360. sbus_serving_map = cpu_present_map;
  361. for_each_node_by_name(dp, "sbi") {
  362. int board = of_getintprop_default(dp, "board#", 0);
  363. if ((board * 2) == boot_cpu_id && cpu_isset(board * 2 + 1, cpu_present_map))
  364. sbus_tid[board] = (board * 2 + 1);
  365. else if (cpu_isset(board * 2, cpu_present_map))
  366. sbus_tid[board] = (board * 2);
  367. else if (cpu_isset(board * 2 + 1, cpu_present_map))
  368. sbus_tid[board] = (board * 2 + 1);
  369. else
  370. sbus_tid[board] = 0xff;
  371. if (sbus_tid[board] != 0xff)
  372. cpu_clear(sbus_tid[board], sbus_serving_map);
  373. }
  374. for_each_node_by_name(dp, "sbi") {
  375. int board = of_getintprop_default(dp, "board#", 0);
  376. if (sbus_tid[board] == 0xff) {
  377. int i = 31;
  378. if (cpus_empty(sbus_serving_map))
  379. sbus_serving_map = cpu_present_map;
  380. while (cpu_isset(i, sbus_serving_map))
  381. i--;
  382. sbus_tid[board] = i;
  383. cpu_clear(i, sbus_serving_map);
  384. }
  385. }
  386. for_each_node_by_name(dp, "sbi") {
  387. int devid = of_getintprop_default(dp, "device-id", 0);
  388. int board = of_getintprop_default(dp, "board#", 0);
  389. printk(KERN_ERR "sbus%d IRQs directed to CPU%d\n",
  390. board, sbus_tid[board]);
  391. set_sbi_tid(devid, sbus_tid[board] << 3);
  392. }
  393. #else
  394. int cpuid = cpu_logical_map(1);
  395. if (cpuid == -1)
  396. cpuid = cpu_logical_map(0);
  397. for_each_node_by_name(dp, "sbi") {
  398. int devid = of_getintprop_default(dp, "device-id", 0);
  399. int board = of_getintprop_default(dp, "board#", 0);
  400. sbus_tid[board] = cpuid;
  401. set_sbi_tid(devid, cpuid << 3);
  402. }
  403. printk(KERN_ERR "All sbus IRQs directed to CPU%d\n", cpuid);
  404. #endif
  405. }
  406. #endif
  407. static void sun4d_clear_clock_irq(void)
  408. {
  409. sbus_readl(&sun4d_timers->l10_timer_limit);
  410. }
  411. static void sun4d_load_profile_irq(int cpu, unsigned int limit)
  412. {
  413. bw_set_prof_limit(cpu, limit);
  414. }
  415. static void __init sun4d_load_profile_irqs(void)
  416. {
  417. int cpu = 0, mid;
  418. while (!cpu_find_by_instance(cpu, NULL, &mid)) {
  419. sun4d_load_profile_irq(mid >> 3, 0);
  420. cpu++;
  421. }
  422. }
  423. static void __init sun4d_fixup_trap_table(void)
  424. {
  425. #ifdef CONFIG_SMP
  426. unsigned long flags;
  427. struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
  428. /* Adjust so that we jump directly to smp4d_ticker */
  429. lvl14_save[2] += smp4d_ticker - real_irq_entry;
  430. /* For SMP we use the level 14 ticker, however the bootup code
  431. * has copied the firmware's level 14 vector into the boot cpu's
  432. * trap table, we must fix this now or we get squashed.
  433. */
  434. local_irq_save(flags);
  435. patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */
  436. trap_table->inst_one = lvl14_save[0];
  437. trap_table->inst_two = lvl14_save[1];
  438. trap_table->inst_three = lvl14_save[2];
  439. trap_table->inst_four = lvl14_save[3];
  440. local_flush_cache_all();
  441. local_irq_restore(flags);
  442. #endif
  443. }
  444. static void __init sun4d_init_timers(irq_handler_t counter_fn)
  445. {
  446. struct device_node *dp;
  447. struct resource res;
  448. const u32 *reg;
  449. int err;
  450. dp = of_find_node_by_name(NULL, "cpu-unit");
  451. if (!dp) {
  452. prom_printf("sun4d_init_timers: Unable to find cpu-unit\n");
  453. prom_halt();
  454. }
  455. /* Which cpu-unit we use is arbitrary, we can view the bootbus timer
  456. * registers via any cpu's mapping. The first 'reg' property is the
  457. * bootbus.
  458. */
  459. reg = of_get_property(dp, "reg", NULL);
  460. of_node_put(dp);
  461. if (!reg) {
  462. prom_printf("sun4d_init_timers: No reg property\n");
  463. prom_halt();
  464. }
  465. res.start = reg[1];
  466. res.end = reg[2] - 1;
  467. res.flags = reg[0] & 0xff;
  468. sun4d_timers = of_ioremap(&res, BW_TIMER_LIMIT,
  469. sizeof(struct sun4d_timer_regs), "user timer");
  470. if (!sun4d_timers) {
  471. prom_printf("sun4d_init_timers: Can't map timer regs\n");
  472. prom_halt();
  473. }
  474. sbus_writel((((1000000/HZ) + 1) << 10), &sun4d_timers->l10_timer_limit);
  475. master_l10_counter = &sun4d_timers->l10_cur_count;
  476. err = request_irq(TIMER_IRQ, counter_fn,
  477. (IRQF_DISABLED | SA_STATIC_ALLOC),
  478. "timer", NULL);
  479. if (err) {
  480. prom_printf("sun4d_init_timers: request_irq() failed with %d\n",
  481. err);
  482. prom_halt();
  483. }
  484. sun4d_load_profile_irqs();
  485. sun4d_fixup_trap_table();
  486. }
  487. void __init sun4d_init_sbi_irq(void)
  488. {
  489. struct device_node *dp;
  490. int target_cpu = 0;
  491. #ifdef CONFIG_SMP
  492. target_cpu = boot_cpu_id;
  493. #endif
  494. nsbi = 0;
  495. for_each_node_by_name(dp, "sbi")
  496. nsbi++;
  497. sbus_actions = kzalloc(nsbi * 8 * 4 * sizeof(struct sbus_action), GFP_ATOMIC);
  498. if (!sbus_actions) {
  499. prom_printf("SUN4D: Cannot allocate sbus_actions, halting.\n");
  500. prom_halt();
  501. }
  502. for_each_node_by_name(dp, "sbi") {
  503. int devid = of_getintprop_default(dp, "device-id", 0);
  504. int board = of_getintprop_default(dp, "board#", 0);
  505. unsigned int mask;
  506. set_sbi_tid(devid, target_cpu << 3);
  507. sbus_tid[board] = target_cpu;
  508. /* Get rid of pending irqs from PROM */
  509. mask = acquire_sbi(devid, 0xffffffff);
  510. if (mask) {
  511. printk(KERN_ERR "Clearing pending IRQs %08x on SBI %d\n",
  512. mask, board);
  513. release_sbi(devid, mask);
  514. }
  515. }
  516. }
  517. void __init sun4d_init_IRQ(void)
  518. {
  519. local_irq_disable();
  520. BTFIXUPSET_CALL(enable_irq, sun4d_enable_irq, BTFIXUPCALL_NORM);
  521. BTFIXUPSET_CALL(disable_irq, sun4d_disable_irq, BTFIXUPCALL_NORM);
  522. BTFIXUPSET_CALL(clear_clock_irq, sun4d_clear_clock_irq, BTFIXUPCALL_NORM);
  523. BTFIXUPSET_CALL(load_profile_irq, sun4d_load_profile_irq, BTFIXUPCALL_NORM);
  524. sparc_init_timers = sun4d_init_timers;
  525. #ifdef CONFIG_SMP
  526. BTFIXUPSET_CALL(set_cpu_int, sun4d_set_cpu_int, BTFIXUPCALL_NORM);
  527. BTFIXUPSET_CALL(clear_cpu_int, sun4d_clear_ipi, BTFIXUPCALL_NOP);
  528. BTFIXUPSET_CALL(set_irq_udt, sun4d_set_udt, BTFIXUPCALL_NOP);
  529. #endif
  530. /* Cannot enable interrupts until OBP ticker is disabled. */
  531. }