main.c 52 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include "ath9k.h"
  18. #include "btcoex.h"
  19. static void ath_cache_conf_rate(struct ath_softc *sc,
  20. struct ieee80211_conf *conf)
  21. {
  22. switch (conf->channel->band) {
  23. case IEEE80211_BAND_2GHZ:
  24. if (conf_is_ht20(conf))
  25. sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
  26. else if (conf_is_ht40_minus(conf))
  27. sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
  28. else if (conf_is_ht40_plus(conf))
  29. sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
  30. else
  31. sc->cur_rate_mode = ATH9K_MODE_11G;
  32. break;
  33. case IEEE80211_BAND_5GHZ:
  34. if (conf_is_ht20(conf))
  35. sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
  36. else if (conf_is_ht40_minus(conf))
  37. sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
  38. else if (conf_is_ht40_plus(conf))
  39. sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
  40. else
  41. sc->cur_rate_mode = ATH9K_MODE_11A;
  42. break;
  43. default:
  44. BUG_ON(1);
  45. break;
  46. }
  47. }
  48. static void ath_update_txpow(struct ath_softc *sc)
  49. {
  50. struct ath_hw *ah = sc->sc_ah;
  51. u32 txpow;
  52. if (sc->curtxpow != sc->config.txpowlimit) {
  53. ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
  54. /* read back in case value is clamped */
  55. ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
  56. sc->curtxpow = txpow;
  57. }
  58. }
  59. static u8 parse_mpdudensity(u8 mpdudensity)
  60. {
  61. /*
  62. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  63. * 0 for no restriction
  64. * 1 for 1/4 us
  65. * 2 for 1/2 us
  66. * 3 for 1 us
  67. * 4 for 2 us
  68. * 5 for 4 us
  69. * 6 for 8 us
  70. * 7 for 16 us
  71. */
  72. switch (mpdudensity) {
  73. case 0:
  74. return 0;
  75. case 1:
  76. case 2:
  77. case 3:
  78. /* Our lower layer calculations limit our precision to
  79. 1 microsecond */
  80. return 1;
  81. case 4:
  82. return 2;
  83. case 5:
  84. return 4;
  85. case 6:
  86. return 8;
  87. case 7:
  88. return 16;
  89. default:
  90. return 0;
  91. }
  92. }
  93. static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
  94. struct ieee80211_hw *hw)
  95. {
  96. struct ieee80211_channel *curchan = hw->conf.channel;
  97. struct ath9k_channel *channel;
  98. u8 chan_idx;
  99. chan_idx = curchan->hw_value;
  100. channel = &sc->sc_ah->channels[chan_idx];
  101. ath9k_update_ichannel(sc, hw, channel);
  102. return channel;
  103. }
  104. bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  105. {
  106. unsigned long flags;
  107. bool ret;
  108. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  109. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  110. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  111. return ret;
  112. }
  113. void ath9k_ps_wakeup(struct ath_softc *sc)
  114. {
  115. unsigned long flags;
  116. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  117. if (++sc->ps_usecount != 1)
  118. goto unlock;
  119. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  120. unlock:
  121. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  122. }
  123. void ath9k_ps_restore(struct ath_softc *sc)
  124. {
  125. unsigned long flags;
  126. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  127. if (--sc->ps_usecount != 0)
  128. goto unlock;
  129. if (sc->ps_idle)
  130. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
  131. else if (sc->ps_enabled &&
  132. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  133. PS_WAIT_FOR_CAB |
  134. PS_WAIT_FOR_PSPOLL_DATA |
  135. PS_WAIT_FOR_TX_ACK)))
  136. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
  137. unlock:
  138. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  139. }
  140. /*
  141. * Set/change channels. If the channel is really being changed, it's done
  142. * by reseting the chip. To accomplish this we must first cleanup any pending
  143. * DMA, then restart stuff.
  144. */
  145. int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  146. struct ath9k_channel *hchan)
  147. {
  148. struct ath_hw *ah = sc->sc_ah;
  149. struct ath_common *common = ath9k_hw_common(ah);
  150. struct ieee80211_conf *conf = &common->hw->conf;
  151. bool fastcc = true, stopped;
  152. struct ieee80211_channel *channel = hw->conf.channel;
  153. int r;
  154. if (sc->sc_flags & SC_OP_INVALID)
  155. return -EIO;
  156. ath9k_ps_wakeup(sc);
  157. /*
  158. * This is only performed if the channel settings have
  159. * actually changed.
  160. *
  161. * To switch channels clear any pending DMA operations;
  162. * wait long enough for the RX fifo to drain, reset the
  163. * hardware at the new frequency, and then re-enable
  164. * the relevant bits of the h/w.
  165. */
  166. ath9k_hw_set_interrupts(ah, 0);
  167. ath_drain_all_txq(sc, false);
  168. stopped = ath_stoprecv(sc);
  169. /* XXX: do not flush receive queue here. We don't want
  170. * to flush data frames already in queue because of
  171. * changing channel. */
  172. if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
  173. fastcc = false;
  174. ath_print(common, ATH_DBG_CONFIG,
  175. "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
  176. sc->sc_ah->curchan->channel,
  177. channel->center_freq, conf_is_ht40(conf));
  178. spin_lock_bh(&sc->sc_resetlock);
  179. r = ath9k_hw_reset(ah, hchan, fastcc);
  180. if (r) {
  181. ath_print(common, ATH_DBG_FATAL,
  182. "Unable to reset channel (%u MHz), "
  183. "reset status %d\n",
  184. channel->center_freq, r);
  185. spin_unlock_bh(&sc->sc_resetlock);
  186. goto ps_restore;
  187. }
  188. spin_unlock_bh(&sc->sc_resetlock);
  189. sc->sc_flags &= ~SC_OP_FULL_RESET;
  190. if (ath_startrecv(sc) != 0) {
  191. ath_print(common, ATH_DBG_FATAL,
  192. "Unable to restart recv logic\n");
  193. r = -EIO;
  194. goto ps_restore;
  195. }
  196. ath_cache_conf_rate(sc, &hw->conf);
  197. ath_update_txpow(sc);
  198. ath9k_hw_set_interrupts(ah, sc->imask);
  199. ps_restore:
  200. ath9k_ps_restore(sc);
  201. return r;
  202. }
  203. /*
  204. * This routine performs the periodic noise floor calibration function
  205. * that is used to adjust and optimize the chip performance. This
  206. * takes environmental changes (location, temperature) into account.
  207. * When the task is complete, it reschedules itself depending on the
  208. * appropriate interval that was calculated.
  209. */
  210. void ath_ani_calibrate(unsigned long data)
  211. {
  212. struct ath_softc *sc = (struct ath_softc *)data;
  213. struct ath_hw *ah = sc->sc_ah;
  214. struct ath_common *common = ath9k_hw_common(ah);
  215. bool longcal = false;
  216. bool shortcal = false;
  217. bool aniflag = false;
  218. unsigned int timestamp = jiffies_to_msecs(jiffies);
  219. u32 cal_interval, short_cal_interval;
  220. short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
  221. ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
  222. /* Only calibrate if awake */
  223. if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
  224. goto set_timer;
  225. ath9k_ps_wakeup(sc);
  226. /* Long calibration runs independently of short calibration. */
  227. if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
  228. longcal = true;
  229. ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
  230. common->ani.longcal_timer = timestamp;
  231. }
  232. /* Short calibration applies only while caldone is false */
  233. if (!common->ani.caldone) {
  234. if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
  235. shortcal = true;
  236. ath_print(common, ATH_DBG_ANI,
  237. "shortcal @%lu\n", jiffies);
  238. common->ani.shortcal_timer = timestamp;
  239. common->ani.resetcal_timer = timestamp;
  240. }
  241. } else {
  242. if ((timestamp - common->ani.resetcal_timer) >=
  243. ATH_RESTART_CALINTERVAL) {
  244. common->ani.caldone = ath9k_hw_reset_calvalid(ah);
  245. if (common->ani.caldone)
  246. common->ani.resetcal_timer = timestamp;
  247. }
  248. }
  249. /* Verify whether we must check ANI */
  250. if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
  251. aniflag = true;
  252. common->ani.checkani_timer = timestamp;
  253. }
  254. /* Skip all processing if there's nothing to do. */
  255. if (longcal || shortcal || aniflag) {
  256. /* Call ANI routine if necessary */
  257. if (aniflag)
  258. ath9k_hw_ani_monitor(ah, ah->curchan);
  259. /* Perform calibration if necessary */
  260. if (longcal || shortcal) {
  261. common->ani.caldone =
  262. ath9k_hw_calibrate(ah,
  263. ah->curchan,
  264. common->rx_chainmask,
  265. longcal);
  266. if (longcal)
  267. common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
  268. ah->curchan);
  269. ath_print(common, ATH_DBG_ANI,
  270. " calibrate chan %u/%x nf: %d\n",
  271. ah->curchan->channel,
  272. ah->curchan->channelFlags,
  273. common->ani.noise_floor);
  274. }
  275. }
  276. ath9k_ps_restore(sc);
  277. set_timer:
  278. /*
  279. * Set timer interval based on previous results.
  280. * The interval must be the shortest necessary to satisfy ANI,
  281. * short calibration and long calibration.
  282. */
  283. cal_interval = ATH_LONG_CALINTERVAL;
  284. if (sc->sc_ah->config.enable_ani)
  285. cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
  286. if (!common->ani.caldone)
  287. cal_interval = min(cal_interval, (u32)short_cal_interval);
  288. mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
  289. }
  290. static void ath_start_ani(struct ath_common *common)
  291. {
  292. unsigned long timestamp = jiffies_to_msecs(jiffies);
  293. common->ani.longcal_timer = timestamp;
  294. common->ani.shortcal_timer = timestamp;
  295. common->ani.checkani_timer = timestamp;
  296. mod_timer(&common->ani.timer,
  297. jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
  298. }
  299. /*
  300. * Update tx/rx chainmask. For legacy association,
  301. * hard code chainmask to 1x1, for 11n association, use
  302. * the chainmask configuration, for bt coexistence, use
  303. * the chainmask configuration even in legacy mode.
  304. */
  305. void ath_update_chainmask(struct ath_softc *sc, int is_ht)
  306. {
  307. struct ath_hw *ah = sc->sc_ah;
  308. struct ath_common *common = ath9k_hw_common(ah);
  309. if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
  310. (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
  311. common->tx_chainmask = ah->caps.tx_chainmask;
  312. common->rx_chainmask = ah->caps.rx_chainmask;
  313. } else {
  314. common->tx_chainmask = 1;
  315. common->rx_chainmask = 1;
  316. }
  317. ath_print(common, ATH_DBG_CONFIG,
  318. "tx chmask: %d, rx chmask: %d\n",
  319. common->tx_chainmask,
  320. common->rx_chainmask);
  321. }
  322. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
  323. {
  324. struct ath_node *an;
  325. an = (struct ath_node *)sta->drv_priv;
  326. if (sc->sc_flags & SC_OP_TXAGGR) {
  327. ath_tx_node_init(sc, an);
  328. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  329. sta->ht_cap.ampdu_factor);
  330. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  331. an->last_rssi = ATH_RSSI_DUMMY_MARKER;
  332. }
  333. }
  334. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  335. {
  336. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  337. if (sc->sc_flags & SC_OP_TXAGGR)
  338. ath_tx_node_cleanup(sc, an);
  339. }
  340. void ath9k_tasklet(unsigned long data)
  341. {
  342. struct ath_softc *sc = (struct ath_softc *)data;
  343. struct ath_hw *ah = sc->sc_ah;
  344. struct ath_common *common = ath9k_hw_common(ah);
  345. u32 status = sc->intrstatus;
  346. ath9k_ps_wakeup(sc);
  347. if (status & ATH9K_INT_FATAL) {
  348. ath_reset(sc, false);
  349. ath9k_ps_restore(sc);
  350. return;
  351. }
  352. if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
  353. spin_lock_bh(&sc->rx.rxflushlock);
  354. ath_rx_tasklet(sc, 0);
  355. spin_unlock_bh(&sc->rx.rxflushlock);
  356. }
  357. if (status & ATH9K_INT_TX)
  358. ath_tx_tasklet(sc);
  359. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  360. /*
  361. * TSF sync does not look correct; remain awake to sync with
  362. * the next Beacon.
  363. */
  364. ath_print(common, ATH_DBG_PS,
  365. "TSFOOR - Sync with next Beacon\n");
  366. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  367. }
  368. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  369. if (status & ATH9K_INT_GENTIMER)
  370. ath_gen_timer_isr(sc->sc_ah);
  371. /* re-enable hardware interrupt */
  372. ath9k_hw_set_interrupts(ah, sc->imask);
  373. ath9k_ps_restore(sc);
  374. }
  375. irqreturn_t ath_isr(int irq, void *dev)
  376. {
  377. #define SCHED_INTR ( \
  378. ATH9K_INT_FATAL | \
  379. ATH9K_INT_RXORN | \
  380. ATH9K_INT_RXEOL | \
  381. ATH9K_INT_RX | \
  382. ATH9K_INT_TX | \
  383. ATH9K_INT_BMISS | \
  384. ATH9K_INT_CST | \
  385. ATH9K_INT_TSFOOR | \
  386. ATH9K_INT_GENTIMER)
  387. struct ath_softc *sc = dev;
  388. struct ath_hw *ah = sc->sc_ah;
  389. enum ath9k_int status;
  390. bool sched = false;
  391. /*
  392. * The hardware is not ready/present, don't
  393. * touch anything. Note this can happen early
  394. * on if the IRQ is shared.
  395. */
  396. if (sc->sc_flags & SC_OP_INVALID)
  397. return IRQ_NONE;
  398. /* shared irq, not for us */
  399. if (!ath9k_hw_intrpend(ah))
  400. return IRQ_NONE;
  401. /*
  402. * Figure out the reason(s) for the interrupt. Note
  403. * that the hal returns a pseudo-ISR that may include
  404. * bits we haven't explicitly enabled so we mask the
  405. * value to insure we only process bits we requested.
  406. */
  407. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  408. status &= sc->imask; /* discard unasked-for bits */
  409. /*
  410. * If there are no status bits set, then this interrupt was not
  411. * for me (should have been caught above).
  412. */
  413. if (!status)
  414. return IRQ_NONE;
  415. /* Cache the status */
  416. sc->intrstatus = status;
  417. if (status & SCHED_INTR)
  418. sched = true;
  419. /*
  420. * If a FATAL or RXORN interrupt is received, we have to reset the
  421. * chip immediately.
  422. */
  423. if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
  424. goto chip_reset;
  425. if (status & ATH9K_INT_SWBA)
  426. tasklet_schedule(&sc->bcon_tasklet);
  427. if (status & ATH9K_INT_TXURN)
  428. ath9k_hw_updatetxtriglevel(ah, true);
  429. if (status & ATH9K_INT_MIB) {
  430. /*
  431. * Disable interrupts until we service the MIB
  432. * interrupt; otherwise it will continue to
  433. * fire.
  434. */
  435. ath9k_hw_set_interrupts(ah, 0);
  436. /*
  437. * Let the hal handle the event. We assume
  438. * it will clear whatever condition caused
  439. * the interrupt.
  440. */
  441. ath9k_hw_procmibevent(ah);
  442. ath9k_hw_set_interrupts(ah, sc->imask);
  443. }
  444. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  445. if (status & ATH9K_INT_TIM_TIMER) {
  446. /* Clear RxAbort bit so that we can
  447. * receive frames */
  448. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  449. ath9k_hw_setrxabort(sc->sc_ah, 0);
  450. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  451. }
  452. chip_reset:
  453. ath_debug_stat_interrupt(sc, status);
  454. if (sched) {
  455. /* turn off every interrupt except SWBA */
  456. ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
  457. tasklet_schedule(&sc->intr_tq);
  458. }
  459. return IRQ_HANDLED;
  460. #undef SCHED_INTR
  461. }
  462. static u32 ath_get_extchanmode(struct ath_softc *sc,
  463. struct ieee80211_channel *chan,
  464. enum nl80211_channel_type channel_type)
  465. {
  466. u32 chanmode = 0;
  467. switch (chan->band) {
  468. case IEEE80211_BAND_2GHZ:
  469. switch(channel_type) {
  470. case NL80211_CHAN_NO_HT:
  471. case NL80211_CHAN_HT20:
  472. chanmode = CHANNEL_G_HT20;
  473. break;
  474. case NL80211_CHAN_HT40PLUS:
  475. chanmode = CHANNEL_G_HT40PLUS;
  476. break;
  477. case NL80211_CHAN_HT40MINUS:
  478. chanmode = CHANNEL_G_HT40MINUS;
  479. break;
  480. }
  481. break;
  482. case IEEE80211_BAND_5GHZ:
  483. switch(channel_type) {
  484. case NL80211_CHAN_NO_HT:
  485. case NL80211_CHAN_HT20:
  486. chanmode = CHANNEL_A_HT20;
  487. break;
  488. case NL80211_CHAN_HT40PLUS:
  489. chanmode = CHANNEL_A_HT40PLUS;
  490. break;
  491. case NL80211_CHAN_HT40MINUS:
  492. chanmode = CHANNEL_A_HT40MINUS;
  493. break;
  494. }
  495. break;
  496. default:
  497. break;
  498. }
  499. return chanmode;
  500. }
  501. static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key,
  502. struct ath9k_keyval *hk, const u8 *addr,
  503. bool authenticator)
  504. {
  505. struct ath_hw *ah = common->ah;
  506. const u8 *key_rxmic;
  507. const u8 *key_txmic;
  508. key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
  509. key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
  510. if (addr == NULL) {
  511. /*
  512. * Group key installation - only two key cache entries are used
  513. * regardless of splitmic capability since group key is only
  514. * used either for TX or RX.
  515. */
  516. if (authenticator) {
  517. memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
  518. memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
  519. } else {
  520. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  521. memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
  522. }
  523. return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
  524. }
  525. if (!common->splitmic) {
  526. /* TX and RX keys share the same key cache entry. */
  527. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  528. memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
  529. return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
  530. }
  531. /* Separate key cache entries for TX and RX */
  532. /* TX key goes at first index, RX key at +32. */
  533. memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
  534. if (!ath9k_hw_set_keycache_entry(ah, keyix, hk, NULL)) {
  535. /* TX MIC entry failed. No need to proceed further */
  536. ath_print(common, ATH_DBG_FATAL,
  537. "Setting TX MIC Key Failed\n");
  538. return 0;
  539. }
  540. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  541. /* XXX delete tx key on failure? */
  542. return ath9k_hw_set_keycache_entry(ah, keyix + 32, hk, addr);
  543. }
  544. static int ath_reserve_key_cache_slot_tkip(struct ath_common *common)
  545. {
  546. int i;
  547. for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
  548. if (test_bit(i, common->keymap) ||
  549. test_bit(i + 64, common->keymap))
  550. continue; /* At least one part of TKIP key allocated */
  551. if (common->splitmic &&
  552. (test_bit(i + 32, common->keymap) ||
  553. test_bit(i + 64 + 32, common->keymap)))
  554. continue; /* At least one part of TKIP key allocated */
  555. /* Found a free slot for a TKIP key */
  556. return i;
  557. }
  558. return -1;
  559. }
  560. static int ath_reserve_key_cache_slot(struct ath_common *common)
  561. {
  562. int i;
  563. /* First, try to find slots that would not be available for TKIP. */
  564. if (common->splitmic) {
  565. for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) {
  566. if (!test_bit(i, common->keymap) &&
  567. (test_bit(i + 32, common->keymap) ||
  568. test_bit(i + 64, common->keymap) ||
  569. test_bit(i + 64 + 32, common->keymap)))
  570. return i;
  571. if (!test_bit(i + 32, common->keymap) &&
  572. (test_bit(i, common->keymap) ||
  573. test_bit(i + 64, common->keymap) ||
  574. test_bit(i + 64 + 32, common->keymap)))
  575. return i + 32;
  576. if (!test_bit(i + 64, common->keymap) &&
  577. (test_bit(i , common->keymap) ||
  578. test_bit(i + 32, common->keymap) ||
  579. test_bit(i + 64 + 32, common->keymap)))
  580. return i + 64;
  581. if (!test_bit(i + 64 + 32, common->keymap) &&
  582. (test_bit(i, common->keymap) ||
  583. test_bit(i + 32, common->keymap) ||
  584. test_bit(i + 64, common->keymap)))
  585. return i + 64 + 32;
  586. }
  587. } else {
  588. for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
  589. if (!test_bit(i, common->keymap) &&
  590. test_bit(i + 64, common->keymap))
  591. return i;
  592. if (test_bit(i, common->keymap) &&
  593. !test_bit(i + 64, common->keymap))
  594. return i + 64;
  595. }
  596. }
  597. /* No partially used TKIP slots, pick any available slot */
  598. for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) {
  599. /* Do not allow slots that could be needed for TKIP group keys
  600. * to be used. This limitation could be removed if we know that
  601. * TKIP will not be used. */
  602. if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
  603. continue;
  604. if (common->splitmic) {
  605. if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
  606. continue;
  607. if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
  608. continue;
  609. }
  610. if (!test_bit(i, common->keymap))
  611. return i; /* Found a free slot for a key */
  612. }
  613. /* No free slot found */
  614. return -1;
  615. }
  616. static int ath_key_config(struct ath_common *common,
  617. struct ieee80211_vif *vif,
  618. struct ieee80211_sta *sta,
  619. struct ieee80211_key_conf *key)
  620. {
  621. struct ath_hw *ah = common->ah;
  622. struct ath9k_keyval hk;
  623. const u8 *mac = NULL;
  624. int ret = 0;
  625. int idx;
  626. memset(&hk, 0, sizeof(hk));
  627. switch (key->alg) {
  628. case ALG_WEP:
  629. hk.kv_type = ATH9K_CIPHER_WEP;
  630. break;
  631. case ALG_TKIP:
  632. hk.kv_type = ATH9K_CIPHER_TKIP;
  633. break;
  634. case ALG_CCMP:
  635. hk.kv_type = ATH9K_CIPHER_AES_CCM;
  636. break;
  637. default:
  638. return -EOPNOTSUPP;
  639. }
  640. hk.kv_len = key->keylen;
  641. memcpy(hk.kv_val, key->key, key->keylen);
  642. if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  643. /* For now, use the default keys for broadcast keys. This may
  644. * need to change with virtual interfaces. */
  645. idx = key->keyidx;
  646. } else if (key->keyidx) {
  647. if (WARN_ON(!sta))
  648. return -EOPNOTSUPP;
  649. mac = sta->addr;
  650. if (vif->type != NL80211_IFTYPE_AP) {
  651. /* Only keyidx 0 should be used with unicast key, but
  652. * allow this for client mode for now. */
  653. idx = key->keyidx;
  654. } else
  655. return -EIO;
  656. } else {
  657. if (WARN_ON(!sta))
  658. return -EOPNOTSUPP;
  659. mac = sta->addr;
  660. if (key->alg == ALG_TKIP)
  661. idx = ath_reserve_key_cache_slot_tkip(common);
  662. else
  663. idx = ath_reserve_key_cache_slot(common);
  664. if (idx < 0)
  665. return -ENOSPC; /* no free key cache entries */
  666. }
  667. if (key->alg == ALG_TKIP)
  668. ret = ath_setkey_tkip(common, idx, key->key, &hk, mac,
  669. vif->type == NL80211_IFTYPE_AP);
  670. else
  671. ret = ath9k_hw_set_keycache_entry(ah, idx, &hk, mac);
  672. if (!ret)
  673. return -EIO;
  674. set_bit(idx, common->keymap);
  675. if (key->alg == ALG_TKIP) {
  676. set_bit(idx + 64, common->keymap);
  677. if (common->splitmic) {
  678. set_bit(idx + 32, common->keymap);
  679. set_bit(idx + 64 + 32, common->keymap);
  680. }
  681. }
  682. return idx;
  683. }
  684. static void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key)
  685. {
  686. struct ath_hw *ah = common->ah;
  687. ath9k_hw_keyreset(ah, key->hw_key_idx);
  688. if (key->hw_key_idx < IEEE80211_WEP_NKID)
  689. return;
  690. clear_bit(key->hw_key_idx, common->keymap);
  691. if (key->alg != ALG_TKIP)
  692. return;
  693. clear_bit(key->hw_key_idx + 64, common->keymap);
  694. if (common->splitmic) {
  695. ath9k_hw_keyreset(ah, key->hw_key_idx + 32);
  696. clear_bit(key->hw_key_idx + 32, common->keymap);
  697. clear_bit(key->hw_key_idx + 64 + 32, common->keymap);
  698. }
  699. }
  700. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  701. struct ieee80211_vif *vif,
  702. struct ieee80211_bss_conf *bss_conf)
  703. {
  704. struct ath_hw *ah = sc->sc_ah;
  705. struct ath_common *common = ath9k_hw_common(ah);
  706. if (bss_conf->assoc) {
  707. ath_print(common, ATH_DBG_CONFIG,
  708. "Bss Info ASSOC %d, bssid: %pM\n",
  709. bss_conf->aid, common->curbssid);
  710. /* New association, store aid */
  711. common->curaid = bss_conf->aid;
  712. ath9k_hw_write_associd(ah);
  713. /*
  714. * Request a re-configuration of Beacon related timers
  715. * on the receipt of the first Beacon frame (i.e.,
  716. * after time sync with the AP).
  717. */
  718. sc->ps_flags |= PS_BEACON_SYNC;
  719. /* Configure the beacon */
  720. ath_beacon_config(sc, vif);
  721. /* Reset rssi stats */
  722. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  723. ath_start_ani(common);
  724. } else {
  725. ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
  726. common->curaid = 0;
  727. /* Stop ANI */
  728. del_timer_sync(&common->ani.timer);
  729. }
  730. }
  731. void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
  732. {
  733. struct ath_hw *ah = sc->sc_ah;
  734. struct ath_common *common = ath9k_hw_common(ah);
  735. struct ieee80211_channel *channel = hw->conf.channel;
  736. int r;
  737. ath9k_ps_wakeup(sc);
  738. ath9k_hw_configpcipowersave(ah, 0, 0);
  739. if (!ah->curchan)
  740. ah->curchan = ath_get_curchannel(sc, sc->hw);
  741. spin_lock_bh(&sc->sc_resetlock);
  742. r = ath9k_hw_reset(ah, ah->curchan, false);
  743. if (r) {
  744. ath_print(common, ATH_DBG_FATAL,
  745. "Unable to reset channel (%u MHz), "
  746. "reset status %d\n",
  747. channel->center_freq, r);
  748. }
  749. spin_unlock_bh(&sc->sc_resetlock);
  750. ath_update_txpow(sc);
  751. if (ath_startrecv(sc) != 0) {
  752. ath_print(common, ATH_DBG_FATAL,
  753. "Unable to restart recv logic\n");
  754. return;
  755. }
  756. if (sc->sc_flags & SC_OP_BEACONS)
  757. ath_beacon_config(sc, NULL); /* restart beacons */
  758. /* Re-Enable interrupts */
  759. ath9k_hw_set_interrupts(ah, sc->imask);
  760. /* Enable LED */
  761. ath9k_hw_cfg_output(ah, ah->led_pin,
  762. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  763. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  764. ieee80211_wake_queues(hw);
  765. ath9k_ps_restore(sc);
  766. }
  767. void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
  768. {
  769. struct ath_hw *ah = sc->sc_ah;
  770. struct ieee80211_channel *channel = hw->conf.channel;
  771. int r;
  772. ath9k_ps_wakeup(sc);
  773. ieee80211_stop_queues(hw);
  774. /* Disable LED */
  775. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  776. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  777. /* Disable interrupts */
  778. ath9k_hw_set_interrupts(ah, 0);
  779. ath_drain_all_txq(sc, false); /* clear pending tx frames */
  780. ath_stoprecv(sc); /* turn off frame recv */
  781. ath_flushrecv(sc); /* flush recv queue */
  782. if (!ah->curchan)
  783. ah->curchan = ath_get_curchannel(sc, hw);
  784. spin_lock_bh(&sc->sc_resetlock);
  785. r = ath9k_hw_reset(ah, ah->curchan, false);
  786. if (r) {
  787. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
  788. "Unable to reset channel (%u MHz), "
  789. "reset status %d\n",
  790. channel->center_freq, r);
  791. }
  792. spin_unlock_bh(&sc->sc_resetlock);
  793. ath9k_hw_phy_disable(ah);
  794. ath9k_hw_configpcipowersave(ah, 1, 1);
  795. ath9k_ps_restore(sc);
  796. ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  797. }
  798. int ath_reset(struct ath_softc *sc, bool retry_tx)
  799. {
  800. struct ath_hw *ah = sc->sc_ah;
  801. struct ath_common *common = ath9k_hw_common(ah);
  802. struct ieee80211_hw *hw = sc->hw;
  803. int r;
  804. /* Stop ANI */
  805. del_timer_sync(&common->ani.timer);
  806. ieee80211_stop_queues(hw);
  807. ath9k_hw_set_interrupts(ah, 0);
  808. ath_drain_all_txq(sc, retry_tx);
  809. ath_stoprecv(sc);
  810. ath_flushrecv(sc);
  811. spin_lock_bh(&sc->sc_resetlock);
  812. r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
  813. if (r)
  814. ath_print(common, ATH_DBG_FATAL,
  815. "Unable to reset hardware; reset status %d\n", r);
  816. spin_unlock_bh(&sc->sc_resetlock);
  817. if (ath_startrecv(sc) != 0)
  818. ath_print(common, ATH_DBG_FATAL,
  819. "Unable to start recv logic\n");
  820. /*
  821. * We may be doing a reset in response to a request
  822. * that changes the channel so update any state that
  823. * might change as a result.
  824. */
  825. ath_cache_conf_rate(sc, &hw->conf);
  826. ath_update_txpow(sc);
  827. if (sc->sc_flags & SC_OP_BEACONS)
  828. ath_beacon_config(sc, NULL); /* restart beacons */
  829. ath9k_hw_set_interrupts(ah, sc->imask);
  830. if (retry_tx) {
  831. int i;
  832. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  833. if (ATH_TXQ_SETUP(sc, i)) {
  834. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  835. ath_txq_schedule(sc, &sc->tx.txq[i]);
  836. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  837. }
  838. }
  839. }
  840. ieee80211_wake_queues(hw);
  841. /* Start ANI */
  842. ath_start_ani(common);
  843. return r;
  844. }
  845. int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
  846. {
  847. int qnum;
  848. switch (queue) {
  849. case 0:
  850. qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
  851. break;
  852. case 1:
  853. qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
  854. break;
  855. case 2:
  856. qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
  857. break;
  858. case 3:
  859. qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
  860. break;
  861. default:
  862. qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
  863. break;
  864. }
  865. return qnum;
  866. }
  867. int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
  868. {
  869. int qnum;
  870. switch (queue) {
  871. case ATH9K_WME_AC_VO:
  872. qnum = 0;
  873. break;
  874. case ATH9K_WME_AC_VI:
  875. qnum = 1;
  876. break;
  877. case ATH9K_WME_AC_BE:
  878. qnum = 2;
  879. break;
  880. case ATH9K_WME_AC_BK:
  881. qnum = 3;
  882. break;
  883. default:
  884. qnum = -1;
  885. break;
  886. }
  887. return qnum;
  888. }
  889. /* XXX: Remove me once we don't depend on ath9k_channel for all
  890. * this redundant data */
  891. void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
  892. struct ath9k_channel *ichan)
  893. {
  894. struct ieee80211_channel *chan = hw->conf.channel;
  895. struct ieee80211_conf *conf = &hw->conf;
  896. ichan->channel = chan->center_freq;
  897. ichan->chan = chan;
  898. if (chan->band == IEEE80211_BAND_2GHZ) {
  899. ichan->chanmode = CHANNEL_G;
  900. ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
  901. } else {
  902. ichan->chanmode = CHANNEL_A;
  903. ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
  904. }
  905. if (conf_is_ht(conf))
  906. ichan->chanmode = ath_get_extchanmode(sc, chan,
  907. conf->channel_type);
  908. }
  909. /**********************/
  910. /* mac80211 callbacks */
  911. /**********************/
  912. static int ath9k_start(struct ieee80211_hw *hw)
  913. {
  914. struct ath_wiphy *aphy = hw->priv;
  915. struct ath_softc *sc = aphy->sc;
  916. struct ath_hw *ah = sc->sc_ah;
  917. struct ath_common *common = ath9k_hw_common(ah);
  918. struct ieee80211_channel *curchan = hw->conf.channel;
  919. struct ath9k_channel *init_channel;
  920. int r;
  921. ath_print(common, ATH_DBG_CONFIG,
  922. "Starting driver with initial channel: %d MHz\n",
  923. curchan->center_freq);
  924. mutex_lock(&sc->mutex);
  925. if (ath9k_wiphy_started(sc)) {
  926. if (sc->chan_idx == curchan->hw_value) {
  927. /*
  928. * Already on the operational channel, the new wiphy
  929. * can be marked active.
  930. */
  931. aphy->state = ATH_WIPHY_ACTIVE;
  932. ieee80211_wake_queues(hw);
  933. } else {
  934. /*
  935. * Another wiphy is on another channel, start the new
  936. * wiphy in paused state.
  937. */
  938. aphy->state = ATH_WIPHY_PAUSED;
  939. ieee80211_stop_queues(hw);
  940. }
  941. mutex_unlock(&sc->mutex);
  942. return 0;
  943. }
  944. aphy->state = ATH_WIPHY_ACTIVE;
  945. /* setup initial channel */
  946. sc->chan_idx = curchan->hw_value;
  947. init_channel = ath_get_curchannel(sc, hw);
  948. /* Reset SERDES registers */
  949. ath9k_hw_configpcipowersave(ah, 0, 0);
  950. /*
  951. * The basic interface to setting the hardware in a good
  952. * state is ``reset''. On return the hardware is known to
  953. * be powered up and with interrupts disabled. This must
  954. * be followed by initialization of the appropriate bits
  955. * and then setup of the interrupt mask.
  956. */
  957. spin_lock_bh(&sc->sc_resetlock);
  958. r = ath9k_hw_reset(ah, init_channel, false);
  959. if (r) {
  960. ath_print(common, ATH_DBG_FATAL,
  961. "Unable to reset hardware; reset status %d "
  962. "(freq %u MHz)\n", r,
  963. curchan->center_freq);
  964. spin_unlock_bh(&sc->sc_resetlock);
  965. goto mutex_unlock;
  966. }
  967. spin_unlock_bh(&sc->sc_resetlock);
  968. /*
  969. * This is needed only to setup initial state
  970. * but it's best done after a reset.
  971. */
  972. ath_update_txpow(sc);
  973. /*
  974. * Setup the hardware after reset:
  975. * The receive engine is set going.
  976. * Frame transmit is handled entirely
  977. * in the frame output path; there's nothing to do
  978. * here except setup the interrupt mask.
  979. */
  980. if (ath_startrecv(sc) != 0) {
  981. ath_print(common, ATH_DBG_FATAL,
  982. "Unable to start recv logic\n");
  983. r = -EIO;
  984. goto mutex_unlock;
  985. }
  986. /* Setup our intr mask. */
  987. sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
  988. | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
  989. | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
  990. if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
  991. sc->imask |= ATH9K_INT_GTT;
  992. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  993. sc->imask |= ATH9K_INT_CST;
  994. ath_cache_conf_rate(sc, &hw->conf);
  995. sc->sc_flags &= ~SC_OP_INVALID;
  996. /* Disable BMISS interrupt when we're not associated */
  997. sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  998. ath9k_hw_set_interrupts(ah, sc->imask);
  999. ieee80211_wake_queues(hw);
  1000. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  1001. if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
  1002. !ah->btcoex_hw.enabled) {
  1003. ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
  1004. AR_STOMP_LOW_WLAN_WGHT);
  1005. ath9k_hw_btcoex_enable(ah);
  1006. if (common->bus_ops->bt_coex_prep)
  1007. common->bus_ops->bt_coex_prep(common);
  1008. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  1009. ath9k_btcoex_timer_resume(sc);
  1010. }
  1011. mutex_unlock:
  1012. mutex_unlock(&sc->mutex);
  1013. return r;
  1014. }
  1015. static int ath9k_tx(struct ieee80211_hw *hw,
  1016. struct sk_buff *skb)
  1017. {
  1018. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1019. struct ath_wiphy *aphy = hw->priv;
  1020. struct ath_softc *sc = aphy->sc;
  1021. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1022. struct ath_tx_control txctl;
  1023. int padpos, padsize;
  1024. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  1025. if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
  1026. ath_print(common, ATH_DBG_XMIT,
  1027. "ath9k: %s: TX in unexpected wiphy state "
  1028. "%d\n", wiphy_name(hw->wiphy), aphy->state);
  1029. goto exit;
  1030. }
  1031. if (sc->ps_enabled) {
  1032. /*
  1033. * mac80211 does not set PM field for normal data frames, so we
  1034. * need to update that based on the current PS mode.
  1035. */
  1036. if (ieee80211_is_data(hdr->frame_control) &&
  1037. !ieee80211_is_nullfunc(hdr->frame_control) &&
  1038. !ieee80211_has_pm(hdr->frame_control)) {
  1039. ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
  1040. "while in PS mode\n");
  1041. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  1042. }
  1043. }
  1044. if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
  1045. /*
  1046. * We are using PS-Poll and mac80211 can request TX while in
  1047. * power save mode. Need to wake up hardware for the TX to be
  1048. * completed and if needed, also for RX of buffered frames.
  1049. */
  1050. ath9k_ps_wakeup(sc);
  1051. ath9k_hw_setrxabort(sc->sc_ah, 0);
  1052. if (ieee80211_is_pspoll(hdr->frame_control)) {
  1053. ath_print(common, ATH_DBG_PS,
  1054. "Sending PS-Poll to pick a buffered frame\n");
  1055. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  1056. } else {
  1057. ath_print(common, ATH_DBG_PS,
  1058. "Wake up to complete TX\n");
  1059. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  1060. }
  1061. /*
  1062. * The actual restore operation will happen only after
  1063. * the sc_flags bit is cleared. We are just dropping
  1064. * the ps_usecount here.
  1065. */
  1066. ath9k_ps_restore(sc);
  1067. }
  1068. memset(&txctl, 0, sizeof(struct ath_tx_control));
  1069. /*
  1070. * As a temporary workaround, assign seq# here; this will likely need
  1071. * to be cleaned up to work better with Beacon transmission and virtual
  1072. * BSSes.
  1073. */
  1074. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  1075. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  1076. sc->tx.seq_no += 0x10;
  1077. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  1078. hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
  1079. }
  1080. /* Add the padding after the header if this is not already done */
  1081. padpos = ath9k_cmn_padpos(hdr->frame_control);
  1082. padsize = padpos & 3;
  1083. if (padsize && skb->len>padpos) {
  1084. if (skb_headroom(skb) < padsize)
  1085. return -1;
  1086. skb_push(skb, padsize);
  1087. memmove(skb->data, skb->data + padsize, padpos);
  1088. }
  1089. /* Check if a tx queue is available */
  1090. txctl.txq = ath_test_get_txq(sc, skb);
  1091. if (!txctl.txq)
  1092. goto exit;
  1093. ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
  1094. if (ath_tx_start(hw, skb, &txctl) != 0) {
  1095. ath_print(common, ATH_DBG_XMIT, "TX failed\n");
  1096. goto exit;
  1097. }
  1098. return 0;
  1099. exit:
  1100. dev_kfree_skb_any(skb);
  1101. return 0;
  1102. }
  1103. static void ath9k_stop(struct ieee80211_hw *hw)
  1104. {
  1105. struct ath_wiphy *aphy = hw->priv;
  1106. struct ath_softc *sc = aphy->sc;
  1107. struct ath_hw *ah = sc->sc_ah;
  1108. struct ath_common *common = ath9k_hw_common(ah);
  1109. mutex_lock(&sc->mutex);
  1110. aphy->state = ATH_WIPHY_INACTIVE;
  1111. cancel_delayed_work_sync(&sc->ath_led_blink_work);
  1112. cancel_delayed_work_sync(&sc->tx_complete_work);
  1113. if (!sc->num_sec_wiphy) {
  1114. cancel_delayed_work_sync(&sc->wiphy_work);
  1115. cancel_work_sync(&sc->chan_work);
  1116. }
  1117. if (sc->sc_flags & SC_OP_INVALID) {
  1118. ath_print(common, ATH_DBG_ANY, "Device not present\n");
  1119. mutex_unlock(&sc->mutex);
  1120. return;
  1121. }
  1122. if (ath9k_wiphy_started(sc)) {
  1123. mutex_unlock(&sc->mutex);
  1124. return; /* another wiphy still in use */
  1125. }
  1126. /* Ensure HW is awake when we try to shut it down. */
  1127. ath9k_ps_wakeup(sc);
  1128. if (ah->btcoex_hw.enabled) {
  1129. ath9k_hw_btcoex_disable(ah);
  1130. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  1131. ath9k_btcoex_timer_pause(sc);
  1132. }
  1133. /* make sure h/w will not generate any interrupt
  1134. * before setting the invalid flag. */
  1135. ath9k_hw_set_interrupts(ah, 0);
  1136. if (!(sc->sc_flags & SC_OP_INVALID)) {
  1137. ath_drain_all_txq(sc, false);
  1138. ath_stoprecv(sc);
  1139. ath9k_hw_phy_disable(ah);
  1140. } else
  1141. sc->rx.rxlink = NULL;
  1142. /* disable HAL and put h/w to sleep */
  1143. ath9k_hw_disable(ah);
  1144. ath9k_hw_configpcipowersave(ah, 1, 1);
  1145. ath9k_ps_restore(sc);
  1146. /* Finally, put the chip in FULL SLEEP mode */
  1147. ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  1148. sc->sc_flags |= SC_OP_INVALID;
  1149. mutex_unlock(&sc->mutex);
  1150. ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
  1151. }
  1152. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1153. struct ieee80211_vif *vif)
  1154. {
  1155. struct ath_wiphy *aphy = hw->priv;
  1156. struct ath_softc *sc = aphy->sc;
  1157. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1158. struct ath_vif *avp = (void *)vif->drv_priv;
  1159. enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
  1160. int ret = 0;
  1161. mutex_lock(&sc->mutex);
  1162. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
  1163. sc->nvifs > 0) {
  1164. ret = -ENOBUFS;
  1165. goto out;
  1166. }
  1167. switch (vif->type) {
  1168. case NL80211_IFTYPE_STATION:
  1169. ic_opmode = NL80211_IFTYPE_STATION;
  1170. break;
  1171. case NL80211_IFTYPE_ADHOC:
  1172. case NL80211_IFTYPE_AP:
  1173. case NL80211_IFTYPE_MESH_POINT:
  1174. if (sc->nbcnvifs >= ATH_BCBUF) {
  1175. ret = -ENOBUFS;
  1176. goto out;
  1177. }
  1178. ic_opmode = vif->type;
  1179. break;
  1180. default:
  1181. ath_print(common, ATH_DBG_FATAL,
  1182. "Interface type %d not yet supported\n", vif->type);
  1183. ret = -EOPNOTSUPP;
  1184. goto out;
  1185. }
  1186. ath_print(common, ATH_DBG_CONFIG,
  1187. "Attach a VIF of type: %d\n", ic_opmode);
  1188. /* Set the VIF opmode */
  1189. avp->av_opmode = ic_opmode;
  1190. avp->av_bslot = -1;
  1191. sc->nvifs++;
  1192. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
  1193. ath9k_set_bssid_mask(hw);
  1194. if (sc->nvifs > 1)
  1195. goto out; /* skip global settings for secondary vif */
  1196. if (ic_opmode == NL80211_IFTYPE_AP) {
  1197. ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
  1198. sc->sc_flags |= SC_OP_TSF_RESET;
  1199. }
  1200. /* Set the device opmode */
  1201. sc->sc_ah->opmode = ic_opmode;
  1202. /*
  1203. * Enable MIB interrupts when there are hardware phy counters.
  1204. * Note we only do this (at the moment) for station mode.
  1205. */
  1206. if ((vif->type == NL80211_IFTYPE_STATION) ||
  1207. (vif->type == NL80211_IFTYPE_ADHOC) ||
  1208. (vif->type == NL80211_IFTYPE_MESH_POINT)) {
  1209. sc->imask |= ATH9K_INT_MIB;
  1210. sc->imask |= ATH9K_INT_TSFOOR;
  1211. }
  1212. ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
  1213. if (vif->type == NL80211_IFTYPE_AP ||
  1214. vif->type == NL80211_IFTYPE_ADHOC ||
  1215. vif->type == NL80211_IFTYPE_MONITOR)
  1216. ath_start_ani(common);
  1217. out:
  1218. mutex_unlock(&sc->mutex);
  1219. return ret;
  1220. }
  1221. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1222. struct ieee80211_vif *vif)
  1223. {
  1224. struct ath_wiphy *aphy = hw->priv;
  1225. struct ath_softc *sc = aphy->sc;
  1226. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1227. struct ath_vif *avp = (void *)vif->drv_priv;
  1228. int i;
  1229. ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
  1230. mutex_lock(&sc->mutex);
  1231. /* Stop ANI */
  1232. del_timer_sync(&common->ani.timer);
  1233. /* Reclaim beacon resources */
  1234. if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
  1235. (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
  1236. (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
  1237. ath9k_ps_wakeup(sc);
  1238. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1239. ath9k_ps_restore(sc);
  1240. }
  1241. ath_beacon_return(sc, avp);
  1242. sc->sc_flags &= ~SC_OP_BEACONS;
  1243. for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
  1244. if (sc->beacon.bslot[i] == vif) {
  1245. printk(KERN_DEBUG "%s: vif had allocated beacon "
  1246. "slot\n", __func__);
  1247. sc->beacon.bslot[i] = NULL;
  1248. sc->beacon.bslot_aphy[i] = NULL;
  1249. }
  1250. }
  1251. sc->nvifs--;
  1252. mutex_unlock(&sc->mutex);
  1253. }
  1254. void ath9k_enable_ps(struct ath_softc *sc)
  1255. {
  1256. sc->ps_enabled = true;
  1257. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1258. if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1259. sc->imask |= ATH9K_INT_TIM_TIMER;
  1260. ath9k_hw_set_interrupts(sc->sc_ah,
  1261. sc->imask);
  1262. }
  1263. }
  1264. ath9k_hw_setrxabort(sc->sc_ah, 1);
  1265. }
  1266. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1267. {
  1268. struct ath_wiphy *aphy = hw->priv;
  1269. struct ath_softc *sc = aphy->sc;
  1270. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1271. struct ieee80211_conf *conf = &hw->conf;
  1272. struct ath_hw *ah = sc->sc_ah;
  1273. bool disable_radio;
  1274. mutex_lock(&sc->mutex);
  1275. /*
  1276. * Leave this as the first check because we need to turn on the
  1277. * radio if it was disabled before prior to processing the rest
  1278. * of the changes. Likewise we must only disable the radio towards
  1279. * the end.
  1280. */
  1281. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1282. bool enable_radio;
  1283. bool all_wiphys_idle;
  1284. bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1285. spin_lock_bh(&sc->wiphy_lock);
  1286. all_wiphys_idle = ath9k_all_wiphys_idle(sc);
  1287. ath9k_set_wiphy_idle(aphy, idle);
  1288. if (!idle && all_wiphys_idle)
  1289. enable_radio = true;
  1290. /*
  1291. * After we unlock here its possible another wiphy
  1292. * can be re-renabled so to account for that we will
  1293. * only disable the radio toward the end of this routine
  1294. * if by then all wiphys are still idle.
  1295. */
  1296. spin_unlock_bh(&sc->wiphy_lock);
  1297. if (enable_radio) {
  1298. sc->ps_idle = false;
  1299. ath_radio_enable(sc, hw);
  1300. ath_print(common, ATH_DBG_CONFIG,
  1301. "not-idle: enabling radio\n");
  1302. }
  1303. }
  1304. /*
  1305. * We just prepare to enable PS. We have to wait until our AP has
  1306. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1307. * those ACKs and end up retransmitting the same null data frames.
  1308. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1309. */
  1310. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1311. if (conf->flags & IEEE80211_CONF_PS) {
  1312. sc->ps_flags |= PS_ENABLED;
  1313. /*
  1314. * At this point we know hardware has received an ACK
  1315. * of a previously sent null data frame.
  1316. */
  1317. if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) {
  1318. sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
  1319. ath9k_enable_ps(sc);
  1320. }
  1321. } else {
  1322. sc->ps_enabled = false;
  1323. sc->ps_flags &= ~(PS_ENABLED |
  1324. PS_NULLFUNC_COMPLETED);
  1325. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  1326. if (!(ah->caps.hw_caps &
  1327. ATH9K_HW_CAP_AUTOSLEEP)) {
  1328. ath9k_hw_setrxabort(sc->sc_ah, 0);
  1329. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1330. PS_WAIT_FOR_CAB |
  1331. PS_WAIT_FOR_PSPOLL_DATA |
  1332. PS_WAIT_FOR_TX_ACK);
  1333. if (sc->imask & ATH9K_INT_TIM_TIMER) {
  1334. sc->imask &= ~ATH9K_INT_TIM_TIMER;
  1335. ath9k_hw_set_interrupts(sc->sc_ah,
  1336. sc->imask);
  1337. }
  1338. }
  1339. }
  1340. }
  1341. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1342. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1343. ath_print(common, ATH_DBG_CONFIG,
  1344. "HW opmode set to Monitor mode\n");
  1345. sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
  1346. }
  1347. }
  1348. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  1349. struct ieee80211_channel *curchan = hw->conf.channel;
  1350. int pos = curchan->hw_value;
  1351. aphy->chan_idx = pos;
  1352. aphy->chan_is_ht = conf_is_ht(conf);
  1353. if (aphy->state == ATH_WIPHY_SCAN ||
  1354. aphy->state == ATH_WIPHY_ACTIVE)
  1355. ath9k_wiphy_pause_all_forced(sc, aphy);
  1356. else {
  1357. /*
  1358. * Do not change operational channel based on a paused
  1359. * wiphy changes.
  1360. */
  1361. goto skip_chan_change;
  1362. }
  1363. ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
  1364. curchan->center_freq);
  1365. /* XXX: remove me eventualy */
  1366. ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
  1367. ath_update_chainmask(sc, conf_is_ht(conf));
  1368. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1369. ath_print(common, ATH_DBG_FATAL,
  1370. "Unable to set channel\n");
  1371. mutex_unlock(&sc->mutex);
  1372. return -EINVAL;
  1373. }
  1374. }
  1375. skip_chan_change:
  1376. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1377. sc->config.txpowlimit = 2 * conf->power_level;
  1378. ath_update_txpow(sc);
  1379. }
  1380. spin_lock_bh(&sc->wiphy_lock);
  1381. disable_radio = ath9k_all_wiphys_idle(sc);
  1382. spin_unlock_bh(&sc->wiphy_lock);
  1383. if (disable_radio) {
  1384. ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
  1385. sc->ps_idle = true;
  1386. ath_radio_disable(sc, hw);
  1387. }
  1388. mutex_unlock(&sc->mutex);
  1389. return 0;
  1390. }
  1391. #define SUPPORTED_FILTERS \
  1392. (FIF_PROMISC_IN_BSS | \
  1393. FIF_ALLMULTI | \
  1394. FIF_CONTROL | \
  1395. FIF_PSPOLL | \
  1396. FIF_OTHER_BSS | \
  1397. FIF_BCN_PRBRESP_PROMISC | \
  1398. FIF_FCSFAIL)
  1399. /* FIXME: sc->sc_full_reset ? */
  1400. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1401. unsigned int changed_flags,
  1402. unsigned int *total_flags,
  1403. u64 multicast)
  1404. {
  1405. struct ath_wiphy *aphy = hw->priv;
  1406. struct ath_softc *sc = aphy->sc;
  1407. u32 rfilt;
  1408. changed_flags &= SUPPORTED_FILTERS;
  1409. *total_flags &= SUPPORTED_FILTERS;
  1410. sc->rx.rxfilter = *total_flags;
  1411. ath9k_ps_wakeup(sc);
  1412. rfilt = ath_calcrxfilter(sc);
  1413. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1414. ath9k_ps_restore(sc);
  1415. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
  1416. "Set HW RX filter: 0x%x\n", rfilt);
  1417. }
  1418. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1419. struct ieee80211_vif *vif,
  1420. struct ieee80211_sta *sta)
  1421. {
  1422. struct ath_wiphy *aphy = hw->priv;
  1423. struct ath_softc *sc = aphy->sc;
  1424. ath_node_attach(sc, sta);
  1425. return 0;
  1426. }
  1427. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1428. struct ieee80211_vif *vif,
  1429. struct ieee80211_sta *sta)
  1430. {
  1431. struct ath_wiphy *aphy = hw->priv;
  1432. struct ath_softc *sc = aphy->sc;
  1433. ath_node_detach(sc, sta);
  1434. return 0;
  1435. }
  1436. static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1437. const struct ieee80211_tx_queue_params *params)
  1438. {
  1439. struct ath_wiphy *aphy = hw->priv;
  1440. struct ath_softc *sc = aphy->sc;
  1441. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1442. struct ath9k_tx_queue_info qi;
  1443. int ret = 0, qnum;
  1444. if (queue >= WME_NUM_AC)
  1445. return 0;
  1446. mutex_lock(&sc->mutex);
  1447. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1448. qi.tqi_aifs = params->aifs;
  1449. qi.tqi_cwmin = params->cw_min;
  1450. qi.tqi_cwmax = params->cw_max;
  1451. qi.tqi_burstTime = params->txop;
  1452. qnum = ath_get_hal_qnum(queue, sc);
  1453. ath_print(common, ATH_DBG_CONFIG,
  1454. "Configure tx [queue/halq] [%d/%d], "
  1455. "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1456. queue, qnum, params->aifs, params->cw_min,
  1457. params->cw_max, params->txop);
  1458. ret = ath_txq_update(sc, qnum, &qi);
  1459. if (ret)
  1460. ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
  1461. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1462. if ((qnum == sc->tx.hwq_map[ATH9K_WME_AC_BE]) && !ret)
  1463. ath_beaconq_config(sc);
  1464. mutex_unlock(&sc->mutex);
  1465. return ret;
  1466. }
  1467. static int ath9k_set_key(struct ieee80211_hw *hw,
  1468. enum set_key_cmd cmd,
  1469. struct ieee80211_vif *vif,
  1470. struct ieee80211_sta *sta,
  1471. struct ieee80211_key_conf *key)
  1472. {
  1473. struct ath_wiphy *aphy = hw->priv;
  1474. struct ath_softc *sc = aphy->sc;
  1475. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1476. int ret = 0;
  1477. if (modparam_nohwcrypt)
  1478. return -ENOSPC;
  1479. mutex_lock(&sc->mutex);
  1480. ath9k_ps_wakeup(sc);
  1481. ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
  1482. switch (cmd) {
  1483. case SET_KEY:
  1484. ret = ath_key_config(common, vif, sta, key);
  1485. if (ret >= 0) {
  1486. key->hw_key_idx = ret;
  1487. /* push IV and Michael MIC generation to stack */
  1488. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1489. if (key->alg == ALG_TKIP)
  1490. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1491. if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
  1492. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1493. ret = 0;
  1494. }
  1495. break;
  1496. case DISABLE_KEY:
  1497. ath_key_delete(common, key);
  1498. break;
  1499. default:
  1500. ret = -EINVAL;
  1501. }
  1502. ath9k_ps_restore(sc);
  1503. mutex_unlock(&sc->mutex);
  1504. return ret;
  1505. }
  1506. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1507. struct ieee80211_vif *vif,
  1508. struct ieee80211_bss_conf *bss_conf,
  1509. u32 changed)
  1510. {
  1511. struct ath_wiphy *aphy = hw->priv;
  1512. struct ath_softc *sc = aphy->sc;
  1513. struct ath_hw *ah = sc->sc_ah;
  1514. struct ath_common *common = ath9k_hw_common(ah);
  1515. struct ath_vif *avp = (void *)vif->drv_priv;
  1516. int slottime;
  1517. int error;
  1518. mutex_lock(&sc->mutex);
  1519. if (changed & BSS_CHANGED_BSSID) {
  1520. /* Set BSSID */
  1521. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1522. memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
  1523. common->curaid = 0;
  1524. ath9k_hw_write_associd(ah);
  1525. /* Set aggregation protection mode parameters */
  1526. sc->config.ath_aggr_prot = 0;
  1527. /* Only legacy IBSS for now */
  1528. if (vif->type == NL80211_IFTYPE_ADHOC)
  1529. ath_update_chainmask(sc, 0);
  1530. ath_print(common, ATH_DBG_CONFIG,
  1531. "BSSID: %pM aid: 0x%x\n",
  1532. common->curbssid, common->curaid);
  1533. /* need to reconfigure the beacon */
  1534. sc->sc_flags &= ~SC_OP_BEACONS ;
  1535. }
  1536. /* Enable transmission of beacons (AP, IBSS, MESH) */
  1537. if ((changed & BSS_CHANGED_BEACON) ||
  1538. ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
  1539. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1540. error = ath_beacon_alloc(aphy, vif);
  1541. if (!error)
  1542. ath_beacon_config(sc, vif);
  1543. }
  1544. if (changed & BSS_CHANGED_ERP_SLOT) {
  1545. if (bss_conf->use_short_slot)
  1546. slottime = 9;
  1547. else
  1548. slottime = 20;
  1549. if (vif->type == NL80211_IFTYPE_AP) {
  1550. /*
  1551. * Defer update, so that connected stations can adjust
  1552. * their settings at the same time.
  1553. * See beacon.c for more details
  1554. */
  1555. sc->beacon.slottime = slottime;
  1556. sc->beacon.updateslot = UPDATE;
  1557. } else {
  1558. ah->slottime = slottime;
  1559. ath9k_hw_init_global_settings(ah);
  1560. }
  1561. }
  1562. /* Disable transmission of beacons */
  1563. if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
  1564. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1565. if (changed & BSS_CHANGED_BEACON_INT) {
  1566. sc->beacon_interval = bss_conf->beacon_int;
  1567. /*
  1568. * In case of AP mode, the HW TSF has to be reset
  1569. * when the beacon interval changes.
  1570. */
  1571. if (vif->type == NL80211_IFTYPE_AP) {
  1572. sc->sc_flags |= SC_OP_TSF_RESET;
  1573. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1574. error = ath_beacon_alloc(aphy, vif);
  1575. if (!error)
  1576. ath_beacon_config(sc, vif);
  1577. } else {
  1578. ath_beacon_config(sc, vif);
  1579. }
  1580. }
  1581. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1582. ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
  1583. bss_conf->use_short_preamble);
  1584. if (bss_conf->use_short_preamble)
  1585. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1586. else
  1587. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1588. }
  1589. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1590. ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
  1591. bss_conf->use_cts_prot);
  1592. if (bss_conf->use_cts_prot &&
  1593. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1594. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1595. else
  1596. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1597. }
  1598. if (changed & BSS_CHANGED_ASSOC) {
  1599. ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
  1600. bss_conf->assoc);
  1601. ath9k_bss_assoc_info(sc, vif, bss_conf);
  1602. }
  1603. mutex_unlock(&sc->mutex);
  1604. }
  1605. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  1606. {
  1607. u64 tsf;
  1608. struct ath_wiphy *aphy = hw->priv;
  1609. struct ath_softc *sc = aphy->sc;
  1610. mutex_lock(&sc->mutex);
  1611. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1612. mutex_unlock(&sc->mutex);
  1613. return tsf;
  1614. }
  1615. static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
  1616. {
  1617. struct ath_wiphy *aphy = hw->priv;
  1618. struct ath_softc *sc = aphy->sc;
  1619. mutex_lock(&sc->mutex);
  1620. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1621. mutex_unlock(&sc->mutex);
  1622. }
  1623. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  1624. {
  1625. struct ath_wiphy *aphy = hw->priv;
  1626. struct ath_softc *sc = aphy->sc;
  1627. mutex_lock(&sc->mutex);
  1628. ath9k_ps_wakeup(sc);
  1629. ath9k_hw_reset_tsf(sc->sc_ah);
  1630. ath9k_ps_restore(sc);
  1631. mutex_unlock(&sc->mutex);
  1632. }
  1633. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1634. struct ieee80211_vif *vif,
  1635. enum ieee80211_ampdu_mlme_action action,
  1636. struct ieee80211_sta *sta,
  1637. u16 tid, u16 *ssn)
  1638. {
  1639. struct ath_wiphy *aphy = hw->priv;
  1640. struct ath_softc *sc = aphy->sc;
  1641. int ret = 0;
  1642. switch (action) {
  1643. case IEEE80211_AMPDU_RX_START:
  1644. if (!(sc->sc_flags & SC_OP_RXAGGR))
  1645. ret = -ENOTSUPP;
  1646. break;
  1647. case IEEE80211_AMPDU_RX_STOP:
  1648. break;
  1649. case IEEE80211_AMPDU_TX_START:
  1650. ath9k_ps_wakeup(sc);
  1651. ath_tx_aggr_start(sc, sta, tid, ssn);
  1652. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1653. ath9k_ps_restore(sc);
  1654. break;
  1655. case IEEE80211_AMPDU_TX_STOP:
  1656. ath9k_ps_wakeup(sc);
  1657. ath_tx_aggr_stop(sc, sta, tid);
  1658. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1659. ath9k_ps_restore(sc);
  1660. break;
  1661. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1662. ath9k_ps_wakeup(sc);
  1663. ath_tx_aggr_resume(sc, sta, tid);
  1664. ath9k_ps_restore(sc);
  1665. break;
  1666. default:
  1667. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
  1668. "Unknown AMPDU action\n");
  1669. }
  1670. return ret;
  1671. }
  1672. static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
  1673. {
  1674. struct ath_wiphy *aphy = hw->priv;
  1675. struct ath_softc *sc = aphy->sc;
  1676. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1677. mutex_lock(&sc->mutex);
  1678. if (ath9k_wiphy_scanning(sc)) {
  1679. printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
  1680. "same time\n");
  1681. /*
  1682. * Do not allow the concurrent scanning state for now. This
  1683. * could be improved with scanning control moved into ath9k.
  1684. */
  1685. mutex_unlock(&sc->mutex);
  1686. return;
  1687. }
  1688. aphy->state = ATH_WIPHY_SCAN;
  1689. ath9k_wiphy_pause_all_forced(sc, aphy);
  1690. sc->sc_flags |= SC_OP_SCANNING;
  1691. del_timer_sync(&common->ani.timer);
  1692. cancel_delayed_work_sync(&sc->tx_complete_work);
  1693. mutex_unlock(&sc->mutex);
  1694. }
  1695. static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
  1696. {
  1697. struct ath_wiphy *aphy = hw->priv;
  1698. struct ath_softc *sc = aphy->sc;
  1699. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1700. mutex_lock(&sc->mutex);
  1701. aphy->state = ATH_WIPHY_ACTIVE;
  1702. sc->sc_flags &= ~SC_OP_SCANNING;
  1703. sc->sc_flags |= SC_OP_FULL_RESET;
  1704. ath_start_ani(common);
  1705. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  1706. ath_beacon_config(sc, NULL);
  1707. mutex_unlock(&sc->mutex);
  1708. }
  1709. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1710. {
  1711. struct ath_wiphy *aphy = hw->priv;
  1712. struct ath_softc *sc = aphy->sc;
  1713. struct ath_hw *ah = sc->sc_ah;
  1714. mutex_lock(&sc->mutex);
  1715. ah->coverage_class = coverage_class;
  1716. ath9k_hw_init_global_settings(ah);
  1717. mutex_unlock(&sc->mutex);
  1718. }
  1719. struct ieee80211_ops ath9k_ops = {
  1720. .tx = ath9k_tx,
  1721. .start = ath9k_start,
  1722. .stop = ath9k_stop,
  1723. .add_interface = ath9k_add_interface,
  1724. .remove_interface = ath9k_remove_interface,
  1725. .config = ath9k_config,
  1726. .configure_filter = ath9k_configure_filter,
  1727. .sta_add = ath9k_sta_add,
  1728. .sta_remove = ath9k_sta_remove,
  1729. .conf_tx = ath9k_conf_tx,
  1730. .bss_info_changed = ath9k_bss_info_changed,
  1731. .set_key = ath9k_set_key,
  1732. .get_tsf = ath9k_get_tsf,
  1733. .set_tsf = ath9k_set_tsf,
  1734. .reset_tsf = ath9k_reset_tsf,
  1735. .ampdu_action = ath9k_ampdu_action,
  1736. .sw_scan_start = ath9k_sw_scan_start,
  1737. .sw_scan_complete = ath9k_sw_scan_complete,
  1738. .rfkill_poll = ath9k_rfkill_poll_state,
  1739. .set_coverage_class = ath9k_set_coverage_class,
  1740. };