3c359.c 59 KB

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  1. /*
  2. * 3c359.c (c) 2000 Mike Phillips (mikep@linuxtr.net) All Rights Reserved
  3. *
  4. * Linux driver for 3Com 3c359 Tokenlink Velocity XL PCI NIC
  5. *
  6. * Base Driver Olympic:
  7. * Written 1999 Peter De Schrijver & Mike Phillips
  8. *
  9. * This software may be used and distributed according to the terms
  10. * of the GNU General Public License, incorporated herein by reference.
  11. *
  12. * 7/17/00 - Clean up, version number 0.9.0. Ready to release to the world.
  13. *
  14. * 2/16/01 - Port up to kernel 2.4.2 ready for submission into the kernel.
  15. * 3/05/01 - Last clean up stuff before submission.
  16. * 2/15/01 - Finally, update to new pci api.
  17. *
  18. * To Do:
  19. */
  20. /*
  21. * Technical Card Details
  22. *
  23. * All access to data is done with 16/8 bit transfers. The transfer
  24. * method really sucks. You can only read or write one location at a time.
  25. *
  26. * Also, the microcode for the card must be uploaded if the card does not have
  27. * the flashrom on board. This is a 28K bloat in the driver when compiled
  28. * as a module.
  29. *
  30. * Rx is very simple, status into a ring of descriptors, dma data transfer,
  31. * interrupts to tell us when a packet is received.
  32. *
  33. * Tx is a little more interesting. Similar scenario, descriptor and dma data
  34. * transfers, but we don't have to interrupt the card to tell it another packet
  35. * is ready for transmission, we are just doing simple memory writes, not io or mmio
  36. * writes. The card can be set up to simply poll on the next
  37. * descriptor pointer and when this value is non-zero will automatically download
  38. * the next packet. The card then interrupts us when the packet is done.
  39. *
  40. */
  41. #define XL_DEBUG 0
  42. #include <linux/jiffies.h>
  43. #include <linux/module.h>
  44. #include <linux/kernel.h>
  45. #include <linux/errno.h>
  46. #include <linux/timer.h>
  47. #include <linux/in.h>
  48. #include <linux/ioport.h>
  49. #include <linux/string.h>
  50. #include <linux/proc_fs.h>
  51. #include <linux/ptrace.h>
  52. #include <linux/skbuff.h>
  53. #include <linux/interrupt.h>
  54. #include <linux/delay.h>
  55. #include <linux/netdevice.h>
  56. #include <linux/trdevice.h>
  57. #include <linux/stddef.h>
  58. #include <linux/init.h>
  59. #include <linux/pci.h>
  60. #include <linux/spinlock.h>
  61. #include <linux/bitops.h>
  62. #include <linux/firmware.h>
  63. #include <net/checksum.h>
  64. #include <asm/io.h>
  65. #include <asm/system.h>
  66. #include "3c359.h"
  67. static char version[] __devinitdata =
  68. "3c359.c v1.2.0 2/17/01 - Mike Phillips (mikep@linuxtr.net)" ;
  69. #define FW_NAME "3com/3C359.bin"
  70. MODULE_AUTHOR("Mike Phillips <mikep@linuxtr.net>") ;
  71. MODULE_DESCRIPTION("3Com 3C359 Velocity XL Token Ring Adapter Driver \n") ;
  72. MODULE_FIRMWARE(FW_NAME);
  73. /* Module parameters */
  74. /* Ring Speed 0,4,16
  75. * 0 = Autosense
  76. * 4,16 = Selected speed only, no autosense
  77. * This allows the card to be the first on the ring
  78. * and become the active monitor.
  79. *
  80. * WARNING: Some hubs will allow you to insert
  81. * at the wrong speed.
  82. *
  83. * The adapter will _not_ fail to open if there are no
  84. * active monitors on the ring, it will simply open up in
  85. * its last known ringspeed if no ringspeed is specified.
  86. */
  87. static int ringspeed[XL_MAX_ADAPTERS] = {0,} ;
  88. module_param_array(ringspeed, int, NULL, 0);
  89. MODULE_PARM_DESC(ringspeed,"3c359: Ringspeed selection - 4,16 or 0") ;
  90. /* Packet buffer size */
  91. static int pkt_buf_sz[XL_MAX_ADAPTERS] = {0,} ;
  92. module_param_array(pkt_buf_sz, int, NULL, 0) ;
  93. MODULE_PARM_DESC(pkt_buf_sz,"3c359: Initial buffer size") ;
  94. /* Message Level */
  95. static int message_level[XL_MAX_ADAPTERS] = {0,} ;
  96. module_param_array(message_level, int, NULL, 0) ;
  97. MODULE_PARM_DESC(message_level, "3c359: Level of reported messages") ;
  98. /*
  99. * This is a real nasty way of doing this, but otherwise you
  100. * will be stuck with 1555 lines of hex #'s in the code.
  101. */
  102. static DEFINE_PCI_DEVICE_TABLE(xl_pci_tbl) =
  103. {
  104. {PCI_VENDOR_ID_3COM,PCI_DEVICE_ID_3COM_3C359, PCI_ANY_ID, PCI_ANY_ID, },
  105. { } /* terminate list */
  106. };
  107. MODULE_DEVICE_TABLE(pci,xl_pci_tbl) ;
  108. static int xl_init(struct net_device *dev);
  109. static int xl_open(struct net_device *dev);
  110. static int xl_open_hw(struct net_device *dev) ;
  111. static int xl_hw_reset(struct net_device *dev);
  112. static netdev_tx_t xl_xmit(struct sk_buff *skb, struct net_device *dev);
  113. static void xl_dn_comp(struct net_device *dev);
  114. static int xl_close(struct net_device *dev);
  115. static void xl_set_rx_mode(struct net_device *dev);
  116. static irqreturn_t xl_interrupt(int irq, void *dev_id);
  117. static int xl_set_mac_address(struct net_device *dev, void *addr) ;
  118. static void xl_arb_cmd(struct net_device *dev);
  119. static void xl_asb_cmd(struct net_device *dev) ;
  120. static void xl_srb_cmd(struct net_device *dev, int srb_cmd) ;
  121. static void xl_wait_misr_flags(struct net_device *dev) ;
  122. static int xl_change_mtu(struct net_device *dev, int mtu);
  123. static void xl_srb_bh(struct net_device *dev) ;
  124. static void xl_asb_bh(struct net_device *dev) ;
  125. static void xl_reset(struct net_device *dev) ;
  126. static void xl_freemem(struct net_device *dev) ;
  127. /* EEProm Access Functions */
  128. static u16 xl_ee_read(struct net_device *dev, int ee_addr) ;
  129. static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value) ;
  130. /* Debugging functions */
  131. #if XL_DEBUG
  132. static void print_tx_state(struct net_device *dev) ;
  133. static void print_rx_state(struct net_device *dev) ;
  134. static void print_tx_state(struct net_device *dev)
  135. {
  136. struct xl_private *xl_priv = netdev_priv(dev);
  137. struct xl_tx_desc *txd ;
  138. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  139. int i ;
  140. printk("tx_ring_head: %d, tx_ring_tail: %d, free_ent: %d \n",xl_priv->tx_ring_head,
  141. xl_priv->tx_ring_tail, xl_priv->free_ring_entries) ;
  142. printk("Ring , Address , FSH , DnNextPtr, Buffer, Buffer_Len \n");
  143. for (i = 0; i < 16; i++) {
  144. txd = &(xl_priv->xl_tx_ring[i]) ;
  145. printk("%d, %08lx, %08x, %08x, %08x, %08x \n", i, virt_to_bus(txd),
  146. txd->framestartheader, txd->dnnextptr, txd->buffer, txd->buffer_length ) ;
  147. }
  148. printk("DNLISTPTR = %04x \n", readl(xl_mmio + MMIO_DNLISTPTR) );
  149. printk("DmaCtl = %04x \n", readl(xl_mmio + MMIO_DMA_CTRL) );
  150. printk("Queue status = %0x \n",netif_running(dev) ) ;
  151. }
  152. static void print_rx_state(struct net_device *dev)
  153. {
  154. struct xl_private *xl_priv = netdev_priv(dev);
  155. struct xl_rx_desc *rxd ;
  156. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  157. int i ;
  158. printk("rx_ring_tail: %d \n", xl_priv->rx_ring_tail) ;
  159. printk("Ring , Address , FrameState , UPNextPtr, FragAddr, Frag_Len \n");
  160. for (i = 0; i < 16; i++) {
  161. /* rxd = (struct xl_rx_desc *)xl_priv->rx_ring_dma_addr + (i * sizeof(struct xl_rx_desc)) ; */
  162. rxd = &(xl_priv->xl_rx_ring[i]) ;
  163. printk("%d, %08lx, %08x, %08x, %08x, %08x \n", i, virt_to_bus(rxd),
  164. rxd->framestatus, rxd->upnextptr, rxd->upfragaddr, rxd->upfraglen ) ;
  165. }
  166. printk("UPLISTPTR = %04x \n", readl(xl_mmio + MMIO_UPLISTPTR) );
  167. printk("DmaCtl = %04x \n", readl(xl_mmio + MMIO_DMA_CTRL) );
  168. printk("Queue status = %0x \n",netif_running(dev) ) ;
  169. }
  170. #endif
  171. /*
  172. * Read values from the on-board EEProm. This looks very strange
  173. * but you have to wait for the EEProm to get/set the value before
  174. * passing/getting the next value from the nic. As with all requests
  175. * on this nic it has to be done in two stages, a) tell the nic which
  176. * memory address you want to access and b) pass/get the value from the nic.
  177. * With the EEProm, you have to wait before and inbetween access a) and b).
  178. * As this is only read at initialization time and the wait period is very
  179. * small we shouldn't have to worry about scheduling issues.
  180. */
  181. static u16 xl_ee_read(struct net_device *dev, int ee_addr)
  182. {
  183. struct xl_private *xl_priv = netdev_priv(dev);
  184. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  185. /* Wait for EEProm to not be busy */
  186. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  187. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  188. /* Tell EEProm what we want to do and where */
  189. writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  190. writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
  191. /* Wait for EEProm to not be busy */
  192. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  193. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  194. /* Tell EEProm what we want to do and where */
  195. writel(IO_WORD_WRITE | EECONTROL , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  196. writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
  197. /* Finally read the value from the EEProm */
  198. writel(IO_WORD_READ | EEDATA , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  199. return readw(xl_mmio + MMIO_MACDATA) ;
  200. }
  201. /*
  202. * Write values to the onboard eeprom. As with eeprom read you need to
  203. * set which location to write, wait, value to write, wait, with the
  204. * added twist of having to enable eeprom writes as well.
  205. */
  206. static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value)
  207. {
  208. struct xl_private *xl_priv = netdev_priv(dev);
  209. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  210. /* Wait for EEProm to not be busy */
  211. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  212. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  213. /* Enable write/erase */
  214. writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  215. writew(EE_ENABLE_WRITE, xl_mmio + MMIO_MACDATA) ;
  216. /* Wait for EEProm to not be busy */
  217. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  218. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  219. /* Put the value we want to write into EEDATA */
  220. writel(IO_WORD_WRITE | EEDATA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  221. writew(ee_value, xl_mmio + MMIO_MACDATA) ;
  222. /* Tell EEProm to write eevalue into ee_addr */
  223. writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  224. writew(EEWRITE + ee_addr, xl_mmio + MMIO_MACDATA) ;
  225. /* Wait for EEProm to not be busy, to ensure write gets done */
  226. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  227. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  228. return ;
  229. }
  230. static const struct net_device_ops xl_netdev_ops = {
  231. .ndo_open = xl_open,
  232. .ndo_stop = xl_close,
  233. .ndo_start_xmit = xl_xmit,
  234. .ndo_change_mtu = xl_change_mtu,
  235. .ndo_set_multicast_list = xl_set_rx_mode,
  236. .ndo_set_mac_address = xl_set_mac_address,
  237. };
  238. static int __devinit xl_probe(struct pci_dev *pdev,
  239. const struct pci_device_id *ent)
  240. {
  241. struct net_device *dev ;
  242. struct xl_private *xl_priv ;
  243. static int card_no = -1 ;
  244. int i ;
  245. card_no++ ;
  246. if (pci_enable_device(pdev)) {
  247. return -ENODEV ;
  248. }
  249. pci_set_master(pdev);
  250. if ((i = pci_request_regions(pdev,"3c359"))) {
  251. return i ;
  252. } ;
  253. /*
  254. * Allowing init_trdev to allocate the private data will align
  255. * xl_private on a 32 bytes boundary which we need for the rx/tx
  256. * descriptors
  257. */
  258. dev = alloc_trdev(sizeof(struct xl_private)) ;
  259. if (!dev) {
  260. pci_release_regions(pdev) ;
  261. return -ENOMEM ;
  262. }
  263. xl_priv = netdev_priv(dev);
  264. #if XL_DEBUG
  265. printk("pci_device: %p, dev:%p, dev->priv: %p, ba[0]: %10x, ba[1]:%10x\n",
  266. pdev, dev, netdev_priv(dev), (unsigned int)pdev->resource[0].start, (unsigned int)pdev->resource[1].start);
  267. #endif
  268. dev->irq=pdev->irq;
  269. dev->base_addr=pci_resource_start(pdev,0) ;
  270. xl_priv->xl_card_name = pci_name(pdev);
  271. xl_priv->xl_mmio=ioremap(pci_resource_start(pdev,1), XL_IO_SPACE);
  272. xl_priv->pdev = pdev ;
  273. if ((pkt_buf_sz[card_no] < 100) || (pkt_buf_sz[card_no] > 18000) )
  274. xl_priv->pkt_buf_sz = PKT_BUF_SZ ;
  275. else
  276. xl_priv->pkt_buf_sz = pkt_buf_sz[card_no] ;
  277. dev->mtu = xl_priv->pkt_buf_sz - TR_HLEN ;
  278. xl_priv->xl_ring_speed = ringspeed[card_no] ;
  279. xl_priv->xl_message_level = message_level[card_no] ;
  280. xl_priv->xl_functional_addr[0] = xl_priv->xl_functional_addr[1] = xl_priv->xl_functional_addr[2] = xl_priv->xl_functional_addr[3] = 0 ;
  281. xl_priv->xl_copy_all_options = 0 ;
  282. if((i = xl_init(dev))) {
  283. iounmap(xl_priv->xl_mmio) ;
  284. free_netdev(dev) ;
  285. pci_release_regions(pdev) ;
  286. return i ;
  287. }
  288. dev->netdev_ops = &xl_netdev_ops;
  289. SET_NETDEV_DEV(dev, &pdev->dev);
  290. pci_set_drvdata(pdev,dev) ;
  291. if ((i = register_netdev(dev))) {
  292. printk(KERN_ERR "3C359, register netdev failed\n") ;
  293. pci_set_drvdata(pdev,NULL) ;
  294. iounmap(xl_priv->xl_mmio) ;
  295. free_netdev(dev) ;
  296. pci_release_regions(pdev) ;
  297. return i ;
  298. }
  299. printk(KERN_INFO "3C359: %s registered as: %s\n",xl_priv->xl_card_name,dev->name) ;
  300. return 0;
  301. }
  302. static int xl_init_firmware(struct xl_private *xl_priv)
  303. {
  304. int err;
  305. err = request_firmware(&xl_priv->fw, FW_NAME, &xl_priv->pdev->dev);
  306. if (err) {
  307. printk(KERN_ERR "Failed to load firmware \"%s\"\n", FW_NAME);
  308. return err;
  309. }
  310. if (xl_priv->fw->size < 16) {
  311. printk(KERN_ERR "Bogus length %zu in \"%s\"\n",
  312. xl_priv->fw->size, FW_NAME);
  313. release_firmware(xl_priv->fw);
  314. err = -EINVAL;
  315. }
  316. return err;
  317. }
  318. static int __devinit xl_init(struct net_device *dev)
  319. {
  320. struct xl_private *xl_priv = netdev_priv(dev);
  321. int err;
  322. printk(KERN_INFO "%s \n", version);
  323. printk(KERN_INFO "%s: I/O at %hx, MMIO at %p, using irq %d\n",
  324. xl_priv->xl_card_name, (unsigned int)dev->base_addr ,xl_priv->xl_mmio, dev->irq);
  325. spin_lock_init(&xl_priv->xl_lock) ;
  326. err = xl_init_firmware(xl_priv);
  327. if (err == 0)
  328. err = xl_hw_reset(dev);
  329. return err;
  330. }
  331. /*
  332. * Hardware reset. This needs to be a separate entity as we need to reset the card
  333. * when we change the EEProm settings.
  334. */
  335. static int xl_hw_reset(struct net_device *dev)
  336. {
  337. struct xl_private *xl_priv = netdev_priv(dev);
  338. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  339. unsigned long t ;
  340. u16 i ;
  341. u16 result_16 ;
  342. u8 result_8 ;
  343. u16 start ;
  344. int j ;
  345. if (xl_priv->fw == NULL)
  346. return -EINVAL;
  347. /*
  348. * Reset the card. If the card has got the microcode on board, we have
  349. * missed the initialization interrupt, so we must always do this.
  350. */
  351. writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
  352. /*
  353. * Must wait for cmdInProgress bit (12) to clear before continuing with
  354. * card configuration.
  355. */
  356. t=jiffies;
  357. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  358. schedule();
  359. if (time_after(jiffies, t + 40 * HZ)) {
  360. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL card not responding to global reset.\n", dev->name);
  361. return -ENODEV;
  362. }
  363. }
  364. /*
  365. * Enable pmbar by setting bit in CPAttention
  366. */
  367. writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  368. result_8 = readb(xl_mmio + MMIO_MACDATA) ;
  369. result_8 = result_8 | CPA_PMBARVIS ;
  370. writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  371. writeb(result_8, xl_mmio + MMIO_MACDATA) ;
  372. /*
  373. * Read cpHold bit in pmbar, if cleared we have got Flashrom on board.
  374. * If not, we need to upload the microcode to the card
  375. */
  376. writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
  377. #if XL_DEBUG
  378. printk(KERN_INFO "Read from PMBAR = %04x \n", readw(xl_mmio + MMIO_MACDATA)) ;
  379. #endif
  380. if ( readw( (xl_mmio + MMIO_MACDATA)) & PMB_CPHOLD ) {
  381. /* Set PmBar, privateMemoryBase bits (8:2) to 0 */
  382. writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
  383. result_16 = readw(xl_mmio + MMIO_MACDATA) ;
  384. result_16 = result_16 & ~((0x7F) << 2) ;
  385. writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  386. writew(result_16,xl_mmio + MMIO_MACDATA) ;
  387. /* Set CPAttention, memWrEn bit */
  388. writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  389. result_8 = readb(xl_mmio + MMIO_MACDATA) ;
  390. result_8 = result_8 | CPA_MEMWREN ;
  391. writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  392. writeb(result_8, xl_mmio + MMIO_MACDATA) ;
  393. /*
  394. * Now to write the microcode into the shared ram
  395. * The microcode must finish at position 0xFFFF,
  396. * so we must subtract to get the start position for the code
  397. *
  398. * Looks strange but ensures compiler only uses
  399. * 16 bit unsigned int
  400. */
  401. start = (0xFFFF - (xl_priv->fw->size) + 1) ;
  402. printk(KERN_INFO "3C359: Uploading Microcode: ");
  403. for (i = start, j = 0; j < xl_priv->fw->size; i++, j++) {
  404. writel(MEM_BYTE_WRITE | 0XD0000 | i,
  405. xl_mmio + MMIO_MAC_ACCESS_CMD);
  406. writeb(xl_priv->fw->data[j], xl_mmio + MMIO_MACDATA);
  407. if (j % 1024 == 0)
  408. printk(".");
  409. }
  410. printk("\n") ;
  411. for (i = 0; i < 16; i++) {
  412. writel((MEM_BYTE_WRITE | 0xDFFF0) + i,
  413. xl_mmio + MMIO_MAC_ACCESS_CMD);
  414. writeb(xl_priv->fw->data[xl_priv->fw->size - 16 + i],
  415. xl_mmio + MMIO_MACDATA);
  416. }
  417. /*
  418. * Have to write the start address of the upload to FFF4, but
  419. * the address must be >> 4. You do not want to know how long
  420. * it took me to discover this.
  421. */
  422. writel(MEM_WORD_WRITE | 0xDFFF4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  423. writew(start >> 4, xl_mmio + MMIO_MACDATA);
  424. /* Clear the CPAttention, memWrEn Bit */
  425. writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  426. result_8 = readb(xl_mmio + MMIO_MACDATA) ;
  427. result_8 = result_8 & ~CPA_MEMWREN ;
  428. writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  429. writeb(result_8, xl_mmio + MMIO_MACDATA) ;
  430. /* Clear the cpHold bit in pmbar */
  431. writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
  432. result_16 = readw(xl_mmio + MMIO_MACDATA) ;
  433. result_16 = result_16 & ~PMB_CPHOLD ;
  434. writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  435. writew(result_16,xl_mmio + MMIO_MACDATA) ;
  436. } /* If microcode upload required */
  437. /*
  438. * The card should now go though a self test procedure and get itself ready
  439. * to be opened, we must wait for an srb response with the initialization
  440. * information.
  441. */
  442. #if XL_DEBUG
  443. printk(KERN_INFO "%s: Microcode uploaded, must wait for the self test to complete\n", dev->name);
  444. #endif
  445. writew(SETINDENABLE | 0xFFF, xl_mmio + MMIO_COMMAND) ;
  446. t=jiffies;
  447. while ( !(readw(xl_mmio + MMIO_INTSTATUS_AUTO) & INTSTAT_SRB) ) {
  448. schedule();
  449. if (time_after(jiffies, t + 15 * HZ)) {
  450. printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
  451. return -ENODEV;
  452. }
  453. }
  454. /*
  455. * Write the RxBufArea with D000, RxEarlyThresh, TxStartThresh,
  456. * DnPriReqThresh, read the tech docs if you want to know what
  457. * values they need to be.
  458. */
  459. writel(MMIO_WORD_WRITE | RXBUFAREA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  460. writew(0xD000, xl_mmio + MMIO_MACDATA) ;
  461. writel(MMIO_WORD_WRITE | RXEARLYTHRESH, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  462. writew(0X0020, xl_mmio + MMIO_MACDATA) ;
  463. writew( SETTXSTARTTHRESH | 0x40 , xl_mmio + MMIO_COMMAND) ;
  464. writeb(0x04, xl_mmio + MMIO_DNBURSTTHRESH) ;
  465. writeb(0x04, xl_mmio + DNPRIREQTHRESH) ;
  466. /*
  467. * Read WRBR to provide the location of the srb block, have to use byte reads not word reads.
  468. * Tech docs have this wrong !!!!
  469. */
  470. writel(MMIO_BYTE_READ | WRBR, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  471. xl_priv->srb = readb(xl_mmio + MMIO_MACDATA) << 8 ;
  472. writel( (MMIO_BYTE_READ | WRBR) + 1, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  473. xl_priv->srb = xl_priv->srb | readb(xl_mmio + MMIO_MACDATA) ;
  474. #if XL_DEBUG
  475. writel(IO_WORD_READ | SWITCHSETTINGS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  476. if ( readw(xl_mmio + MMIO_MACDATA) & 2) {
  477. printk(KERN_INFO "Default ring speed 4 mbps \n") ;
  478. } else {
  479. printk(KERN_INFO "Default ring speed 16 mbps \n") ;
  480. }
  481. printk(KERN_INFO "%s: xl_priv->srb = %04x\n",xl_priv->xl_card_name, xl_priv->srb);
  482. #endif
  483. return 0;
  484. }
  485. static int xl_open(struct net_device *dev)
  486. {
  487. struct xl_private *xl_priv=netdev_priv(dev);
  488. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  489. u8 i ;
  490. __le16 hwaddr[3] ; /* Should be u8[6] but we get word return values */
  491. int open_err ;
  492. u16 switchsettings, switchsettings_eeprom ;
  493. if (request_irq(dev->irq, xl_interrupt, IRQF_SHARED , "3c359", dev))
  494. return -EAGAIN;
  495. /*
  496. * Read the information from the EEPROM that we need.
  497. */
  498. hwaddr[0] = cpu_to_le16(xl_ee_read(dev,0x10));
  499. hwaddr[1] = cpu_to_le16(xl_ee_read(dev,0x11));
  500. hwaddr[2] = cpu_to_le16(xl_ee_read(dev,0x12));
  501. /* Ring speed */
  502. switchsettings_eeprom = xl_ee_read(dev,0x08) ;
  503. switchsettings = switchsettings_eeprom ;
  504. if (xl_priv->xl_ring_speed != 0) {
  505. if (xl_priv->xl_ring_speed == 4)
  506. switchsettings = switchsettings | 0x02 ;
  507. else
  508. switchsettings = switchsettings & ~0x02 ;
  509. }
  510. /* Only write EEProm if there has been a change */
  511. if (switchsettings != switchsettings_eeprom) {
  512. xl_ee_write(dev,0x08,switchsettings) ;
  513. /* Hardware reset after changing EEProm */
  514. xl_hw_reset(dev) ;
  515. }
  516. memcpy(dev->dev_addr,hwaddr,dev->addr_len) ;
  517. open_err = xl_open_hw(dev) ;
  518. /*
  519. * This really needs to be cleaned up with better error reporting.
  520. */
  521. if (open_err != 0) { /* Something went wrong with the open command */
  522. if (open_err & 0x07) { /* Wrong speed, retry at different speed */
  523. printk(KERN_WARNING "%s: Open Error, retrying at different ringspeed \n", dev->name) ;
  524. switchsettings = switchsettings ^ 2 ;
  525. xl_ee_write(dev,0x08,switchsettings) ;
  526. xl_hw_reset(dev) ;
  527. open_err = xl_open_hw(dev) ;
  528. if (open_err != 0) {
  529. printk(KERN_WARNING "%s: Open error returned a second time, we're bombing out now\n", dev->name);
  530. free_irq(dev->irq,dev) ;
  531. return -ENODEV ;
  532. }
  533. } else {
  534. printk(KERN_WARNING "%s: Open Error = %04x\n", dev->name, open_err) ;
  535. free_irq(dev->irq,dev) ;
  536. return -ENODEV ;
  537. }
  538. }
  539. /*
  540. * Now to set up the Rx and Tx buffer structures
  541. */
  542. /* These MUST be on 8 byte boundaries */
  543. xl_priv->xl_tx_ring = kzalloc((sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE) + 7, GFP_DMA | GFP_KERNEL);
  544. if (xl_priv->xl_tx_ring == NULL) {
  545. printk(KERN_WARNING "%s: Not enough memory to allocate tx buffers.\n",
  546. dev->name);
  547. free_irq(dev->irq,dev);
  548. return -ENOMEM;
  549. }
  550. xl_priv->xl_rx_ring = kzalloc((sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE) +7, GFP_DMA | GFP_KERNEL);
  551. if (xl_priv->xl_rx_ring == NULL) {
  552. printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers.\n",
  553. dev->name);
  554. free_irq(dev->irq,dev);
  555. kfree(xl_priv->xl_tx_ring);
  556. return -ENOMEM;
  557. }
  558. /* Setup Rx Ring */
  559. for (i=0 ; i < XL_RX_RING_SIZE ; i++) {
  560. struct sk_buff *skb ;
  561. skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ;
  562. if (skb==NULL)
  563. break ;
  564. skb->dev = dev ;
  565. xl_priv->xl_rx_ring[i].upfragaddr = cpu_to_le32(pci_map_single(xl_priv->pdev, skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE));
  566. xl_priv->xl_rx_ring[i].upfraglen = cpu_to_le32(xl_priv->pkt_buf_sz) | RXUPLASTFRAG;
  567. xl_priv->rx_ring_skb[i] = skb ;
  568. }
  569. if (i==0) {
  570. printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers. Adapter disabled \n",dev->name) ;
  571. free_irq(dev->irq,dev) ;
  572. kfree(xl_priv->xl_tx_ring);
  573. kfree(xl_priv->xl_rx_ring);
  574. return -EIO ;
  575. }
  576. xl_priv->rx_ring_no = i ;
  577. xl_priv->rx_ring_tail = 0 ;
  578. xl_priv->rx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_rx_ring, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_TODEVICE) ;
  579. for (i=0;i<(xl_priv->rx_ring_no-1);i++) {
  580. xl_priv->xl_rx_ring[i].upnextptr = cpu_to_le32(xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * (i+1)));
  581. }
  582. xl_priv->xl_rx_ring[i].upnextptr = 0 ;
  583. writel(xl_priv->rx_ring_dma_addr, xl_mmio + MMIO_UPLISTPTR) ;
  584. /* Setup Tx Ring */
  585. xl_priv->tx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_tx_ring, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE,PCI_DMA_TODEVICE) ;
  586. xl_priv->tx_ring_head = 1 ;
  587. xl_priv->tx_ring_tail = 255 ; /* Special marker for first packet */
  588. xl_priv->free_ring_entries = XL_TX_RING_SIZE ;
  589. /*
  590. * Setup the first dummy DPD entry for polling to start working.
  591. */
  592. xl_priv->xl_tx_ring[0].framestartheader = TXDPDEMPTY;
  593. xl_priv->xl_tx_ring[0].buffer = 0 ;
  594. xl_priv->xl_tx_ring[0].buffer_length = 0 ;
  595. xl_priv->xl_tx_ring[0].dnnextptr = 0 ;
  596. writel(xl_priv->tx_ring_dma_addr, xl_mmio + MMIO_DNLISTPTR) ;
  597. writel(DNUNSTALL, xl_mmio + MMIO_COMMAND) ;
  598. writel(UPUNSTALL, xl_mmio + MMIO_COMMAND) ;
  599. writel(DNENABLE, xl_mmio + MMIO_COMMAND) ;
  600. writeb(0x40, xl_mmio + MMIO_DNPOLL) ;
  601. /*
  602. * Enable interrupts on the card
  603. */
  604. writel(SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
  605. writel(SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
  606. netif_start_queue(dev) ;
  607. return 0;
  608. }
  609. static int xl_open_hw(struct net_device *dev)
  610. {
  611. struct xl_private *xl_priv=netdev_priv(dev);
  612. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  613. u16 vsoff ;
  614. char ver_str[33];
  615. int open_err ;
  616. int i ;
  617. unsigned long t ;
  618. /*
  619. * Okay, let's build up the Open.NIC srb command
  620. *
  621. */
  622. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  623. writeb(OPEN_NIC, xl_mmio + MMIO_MACDATA) ;
  624. /*
  625. * Use this as a test byte, if it comes back with the same value, the command didn't work
  626. */
  627. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb)+ 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  628. writeb(0xff,xl_mmio + MMIO_MACDATA) ;
  629. /* Open options */
  630. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  631. writeb(0x00, xl_mmio + MMIO_MACDATA) ;
  632. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 9, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  633. writeb(0x00, xl_mmio + MMIO_MACDATA) ;
  634. /*
  635. * Node address, be careful here, the docs say you can just put zeros here and it will use
  636. * the hardware address, it doesn't, you must include the node address in the open command.
  637. */
  638. if (xl_priv->xl_laa[0]) { /* If using a LAA address */
  639. for (i=10;i<16;i++) {
  640. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  641. writeb(xl_priv->xl_laa[i-10],xl_mmio + MMIO_MACDATA) ;
  642. }
  643. memcpy(dev->dev_addr,xl_priv->xl_laa,dev->addr_len) ;
  644. } else { /* Regular hardware address */
  645. for (i=10;i<16;i++) {
  646. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  647. writeb(dev->dev_addr[i-10], xl_mmio + MMIO_MACDATA) ;
  648. }
  649. }
  650. /* Default everything else to 0 */
  651. for (i = 16; i < 34; i++) {
  652. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  653. writeb(0x00,xl_mmio + MMIO_MACDATA) ;
  654. }
  655. /*
  656. * Set the csrb bit in the MISR register
  657. */
  658. xl_wait_misr_flags(dev) ;
  659. writel(MEM_BYTE_WRITE | MF_CSRB, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  660. writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
  661. writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  662. writeb(MISR_CSRB , xl_mmio + MMIO_MACDATA) ;
  663. /*
  664. * Now wait for the command to run
  665. */
  666. t=jiffies;
  667. while (! (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
  668. schedule();
  669. if (time_after(jiffies, t + 40 * HZ)) {
  670. printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
  671. break ;
  672. }
  673. }
  674. /*
  675. * Let's interpret the open response
  676. */
  677. writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb)+2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  678. if (readb(xl_mmio + MMIO_MACDATA)!=0) {
  679. open_err = readb(xl_mmio + MMIO_MACDATA) << 8 ;
  680. writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb) + 7, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  681. open_err |= readb(xl_mmio + MMIO_MACDATA) ;
  682. return open_err ;
  683. } else {
  684. writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  685. xl_priv->asb = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
  686. printk(KERN_INFO "%s: Adapter Opened Details: ",dev->name) ;
  687. printk("ASB: %04x",xl_priv->asb ) ;
  688. writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 10, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  689. printk(", SRB: %04x",swab16(readw(xl_mmio + MMIO_MACDATA)) ) ;
  690. writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 12, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  691. xl_priv->arb = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
  692. printk(", ARB: %04x \n",xl_priv->arb ) ;
  693. writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 14, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  694. vsoff = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
  695. /*
  696. * Interesting, sending the individual characters directly to printk was causing klogd to use
  697. * use 100% of processor time, so we build up the string and print that instead.
  698. */
  699. for (i=0;i<0x20;i++) {
  700. writel( (MEM_BYTE_READ | 0xD0000 | vsoff) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  701. ver_str[i] = readb(xl_mmio + MMIO_MACDATA) ;
  702. }
  703. ver_str[i] = '\0' ;
  704. printk(KERN_INFO "%s: Microcode version String: %s \n",dev->name,ver_str);
  705. }
  706. /*
  707. * Issue the AckInterrupt
  708. */
  709. writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  710. return 0 ;
  711. }
  712. /*
  713. * There are two ways of implementing rx on the 359 NIC, either
  714. * interrupt driven or polling. We are going to uses interrupts,
  715. * it is the easier way of doing things.
  716. *
  717. * The Rx works with a ring of Rx descriptors. At initialise time the ring
  718. * entries point to the next entry except for the last entry in the ring
  719. * which points to 0. The card is programmed with the location of the first
  720. * available descriptor and keeps reading the next_ptr until next_ptr is set
  721. * to 0. Hopefully with a ring size of 16 the card will never get to read a next_ptr
  722. * of 0. As the Rx interrupt is received we copy the frame up to the protocol layers
  723. * and then point the end of the ring to our current position and point our current
  724. * position to 0, therefore making the current position the last position on the ring.
  725. * The last position on the ring therefore loops continually loops around the rx ring.
  726. *
  727. * rx_ring_tail is the position on the ring to process next. (Think of a snake, the head
  728. * expands as the card adds new packets and we go around eating the tail processing the
  729. * packets.)
  730. *
  731. * Undoubtably it could be streamlined and improved upon, but at the moment it works
  732. * and the fast path through the routine is fine.
  733. *
  734. * adv_rx_ring could be inlined to increase performance, but its called a *lot* of times
  735. * in xl_rx so would increase the size of the function significantly.
  736. */
  737. static void adv_rx_ring(struct net_device *dev) /* Advance rx_ring, cut down on bloat in xl_rx */
  738. {
  739. struct xl_private *xl_priv=netdev_priv(dev);
  740. int n = xl_priv->rx_ring_tail;
  741. int prev_ring_loc;
  742. prev_ring_loc = (n + XL_RX_RING_SIZE - 1) & (XL_RX_RING_SIZE - 1);
  743. xl_priv->xl_rx_ring[prev_ring_loc].upnextptr = cpu_to_le32(xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * n));
  744. xl_priv->xl_rx_ring[n].framestatus = 0;
  745. xl_priv->xl_rx_ring[n].upnextptr = 0;
  746. xl_priv->rx_ring_tail++;
  747. xl_priv->rx_ring_tail &= (XL_RX_RING_SIZE-1);
  748. }
  749. static void xl_rx(struct net_device *dev)
  750. {
  751. struct xl_private *xl_priv=netdev_priv(dev);
  752. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  753. struct sk_buff *skb, *skb2 ;
  754. int frame_length = 0, copy_len = 0 ;
  755. int temp_ring_loc ;
  756. /*
  757. * Receive the next frame, loop around the ring until all frames
  758. * have been received.
  759. */
  760. while (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & (RXUPDCOMPLETE | RXUPDFULL) ) { /* Descriptor to process */
  761. if (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & RXUPDFULL ) { /* UpdFull, Multiple Descriptors used for the frame */
  762. /*
  763. * This is a pain, you need to go through all the descriptors until the last one
  764. * for this frame to find the framelength
  765. */
  766. temp_ring_loc = xl_priv->rx_ring_tail ;
  767. while (xl_priv->xl_rx_ring[temp_ring_loc].framestatus & RXUPDFULL ) {
  768. temp_ring_loc++ ;
  769. temp_ring_loc &= (XL_RX_RING_SIZE-1) ;
  770. }
  771. frame_length = le32_to_cpu(xl_priv->xl_rx_ring[temp_ring_loc].framestatus) & 0x7FFF;
  772. skb = dev_alloc_skb(frame_length) ;
  773. if (skb==NULL) { /* No memory for frame, still need to roll forward the rx ring */
  774. printk(KERN_WARNING "%s: dev_alloc_skb failed - multi buffer !\n", dev->name) ;
  775. while (xl_priv->rx_ring_tail != temp_ring_loc)
  776. adv_rx_ring(dev) ;
  777. adv_rx_ring(dev) ; /* One more time just for luck :) */
  778. dev->stats.rx_dropped++ ;
  779. writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  780. return ;
  781. }
  782. while (xl_priv->rx_ring_tail != temp_ring_loc) {
  783. copy_len = le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen) & 0x7FFF;
  784. frame_length -= copy_len ;
  785. pci_dma_sync_single_for_cpu(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
  786. skb_copy_from_linear_data(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail],
  787. skb_put(skb, copy_len),
  788. copy_len);
  789. pci_dma_sync_single_for_device(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
  790. adv_rx_ring(dev) ;
  791. }
  792. /* Now we have found the last fragment */
  793. pci_dma_sync_single_for_cpu(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
  794. skb_copy_from_linear_data(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail],
  795. skb_put(skb,copy_len), frame_length);
  796. /* memcpy(skb_put(skb,frame_length), bus_to_virt(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), frame_length) ; */
  797. pci_dma_sync_single_for_device(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
  798. adv_rx_ring(dev) ;
  799. skb->protocol = tr_type_trans(skb,dev) ;
  800. netif_rx(skb) ;
  801. } else { /* Single Descriptor Used, simply swap buffers over, fast path */
  802. frame_length = le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus) & 0x7FFF;
  803. skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ;
  804. if (skb==NULL) { /* Still need to fix the rx ring */
  805. printk(KERN_WARNING "%s: dev_alloc_skb failed in rx, single buffer \n",dev->name) ;
  806. adv_rx_ring(dev) ;
  807. dev->stats.rx_dropped++ ;
  808. writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  809. return ;
  810. }
  811. skb2 = xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] ;
  812. pci_unmap_single(xl_priv->pdev, le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
  813. skb_put(skb2, frame_length) ;
  814. skb2->protocol = tr_type_trans(skb2,dev) ;
  815. xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] = skb ;
  816. xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr = cpu_to_le32(pci_map_single(xl_priv->pdev,skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE));
  817. xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen = cpu_to_le32(xl_priv->pkt_buf_sz) | RXUPLASTFRAG;
  818. adv_rx_ring(dev) ;
  819. dev->stats.rx_packets++ ;
  820. dev->stats.rx_bytes += frame_length ;
  821. netif_rx(skb2) ;
  822. } /* if multiple buffers */
  823. } /* while packet to do */
  824. /* Clear the updComplete interrupt */
  825. writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  826. return ;
  827. }
  828. /*
  829. * This is ruthless, it doesn't care what state the card is in it will
  830. * completely reset the adapter.
  831. */
  832. static void xl_reset(struct net_device *dev)
  833. {
  834. struct xl_private *xl_priv=netdev_priv(dev);
  835. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  836. unsigned long t;
  837. writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
  838. /*
  839. * Must wait for cmdInProgress bit (12) to clear before continuing with
  840. * card configuration.
  841. */
  842. t=jiffies;
  843. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  844. if (time_after(jiffies, t + 40 * HZ)) {
  845. printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
  846. break ;
  847. }
  848. }
  849. }
  850. static void xl_freemem(struct net_device *dev)
  851. {
  852. struct xl_private *xl_priv=netdev_priv(dev);
  853. int i ;
  854. for (i=0;i<XL_RX_RING_SIZE;i++) {
  855. dev_kfree_skb_irq(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail]) ;
  856. pci_unmap_single(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE);
  857. xl_priv->rx_ring_tail++ ;
  858. xl_priv->rx_ring_tail &= XL_RX_RING_SIZE-1;
  859. }
  860. /* unmap ring */
  861. pci_unmap_single(xl_priv->pdev,xl_priv->rx_ring_dma_addr, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_FROMDEVICE) ;
  862. pci_unmap_single(xl_priv->pdev,xl_priv->tx_ring_dma_addr, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE, PCI_DMA_TODEVICE) ;
  863. kfree(xl_priv->xl_rx_ring) ;
  864. kfree(xl_priv->xl_tx_ring) ;
  865. return ;
  866. }
  867. static irqreturn_t xl_interrupt(int irq, void *dev_id)
  868. {
  869. struct net_device *dev = (struct net_device *)dev_id;
  870. struct xl_private *xl_priv =netdev_priv(dev);
  871. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  872. u16 intstatus, macstatus ;
  873. intstatus = readw(xl_mmio + MMIO_INTSTATUS) ;
  874. if (!(intstatus & 1)) /* We didn't generate the interrupt */
  875. return IRQ_NONE;
  876. spin_lock(&xl_priv->xl_lock) ;
  877. /*
  878. * Process the interrupt
  879. */
  880. /*
  881. * Something fishy going on here, we shouldn't get 0001 ints, not fatal though.
  882. */
  883. if (intstatus == 0x0001) {
  884. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  885. printk(KERN_INFO "%s: 00001 int received \n",dev->name) ;
  886. } else {
  887. if (intstatus & (HOSTERRINT | SRBRINT | ARBCINT | UPCOMPINT | DNCOMPINT | HARDERRINT | (1<<8) | TXUNDERRUN | ASBFINT)) {
  888. /*
  889. * Host Error.
  890. * It may be possible to recover from this, but usually it means something
  891. * is seriously fubar, so we just close the adapter.
  892. */
  893. if (intstatus & HOSTERRINT) {
  894. printk(KERN_WARNING "%s: Host Error, performing global reset, intstatus = %04x \n",dev->name,intstatus) ;
  895. writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
  896. printk(KERN_WARNING "%s: Resetting hardware: \n", dev->name);
  897. netif_stop_queue(dev) ;
  898. xl_freemem(dev) ;
  899. free_irq(dev->irq,dev);
  900. xl_reset(dev) ;
  901. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  902. spin_unlock(&xl_priv->xl_lock) ;
  903. return IRQ_HANDLED;
  904. } /* Host Error */
  905. if (intstatus & SRBRINT ) { /* Srbc interrupt */
  906. writel(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  907. if (xl_priv->srb_queued)
  908. xl_srb_bh(dev) ;
  909. } /* SRBR Interrupt */
  910. if (intstatus & TXUNDERRUN) { /* Issue DnReset command */
  911. writel(DNRESET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  912. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { /* Wait for command to run */
  913. /* !!! FIX-ME !!!!
  914. Must put a timeout check here ! */
  915. /* Empty Loop */
  916. }
  917. printk(KERN_WARNING "%s: TX Underrun received \n",dev->name) ;
  918. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  919. } /* TxUnderRun */
  920. if (intstatus & ARBCINT ) { /* Arbc interrupt */
  921. xl_arb_cmd(dev) ;
  922. } /* Arbc */
  923. if (intstatus & ASBFINT) {
  924. if (xl_priv->asb_queued == 1) {
  925. xl_asb_cmd(dev) ;
  926. } else if (xl_priv->asb_queued == 2) {
  927. xl_asb_bh(dev) ;
  928. } else {
  929. writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
  930. }
  931. } /* Asbf */
  932. if (intstatus & UPCOMPINT ) /* UpComplete */
  933. xl_rx(dev) ;
  934. if (intstatus & DNCOMPINT ) /* DnComplete */
  935. xl_dn_comp(dev) ;
  936. if (intstatus & HARDERRINT ) { /* Hardware error */
  937. writel(MMIO_WORD_READ | MACSTATUS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  938. macstatus = readw(xl_mmio + MMIO_MACDATA) ;
  939. printk(KERN_WARNING "%s: MacStatusError, details: ", dev->name);
  940. if (macstatus & (1<<14))
  941. printk(KERN_WARNING "tchk error: Unrecoverable error \n") ;
  942. if (macstatus & (1<<3))
  943. printk(KERN_WARNING "eint error: Internal watchdog timer expired \n") ;
  944. if (macstatus & (1<<2))
  945. printk(KERN_WARNING "aint error: Host tried to perform invalid operation \n") ;
  946. printk(KERN_WARNING "Instatus = %02x, macstatus = %02x\n",intstatus,macstatus) ;
  947. printk(KERN_WARNING "%s: Resetting hardware: \n", dev->name);
  948. netif_stop_queue(dev) ;
  949. xl_freemem(dev) ;
  950. free_irq(dev->irq,dev);
  951. unregister_netdev(dev) ;
  952. free_netdev(dev) ;
  953. xl_reset(dev) ;
  954. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  955. spin_unlock(&xl_priv->xl_lock) ;
  956. return IRQ_HANDLED;
  957. }
  958. } else {
  959. printk(KERN_WARNING "%s: Received Unknown interrupt : %04x \n", dev->name, intstatus) ;
  960. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  961. }
  962. }
  963. /* Turn interrupts back on */
  964. writel( SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
  965. writel( SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
  966. spin_unlock(&xl_priv->xl_lock) ;
  967. return IRQ_HANDLED;
  968. }
  969. /*
  970. * Tx - Polling configuration
  971. */
  972. static netdev_tx_t xl_xmit(struct sk_buff *skb, struct net_device *dev)
  973. {
  974. struct xl_private *xl_priv=netdev_priv(dev);
  975. struct xl_tx_desc *txd ;
  976. int tx_head, tx_tail, tx_prev ;
  977. unsigned long flags ;
  978. spin_lock_irqsave(&xl_priv->xl_lock,flags) ;
  979. netif_stop_queue(dev) ;
  980. if (xl_priv->free_ring_entries > 1 ) {
  981. /*
  982. * Set up the descriptor for the packet
  983. */
  984. tx_head = xl_priv->tx_ring_head ;
  985. tx_tail = xl_priv->tx_ring_tail ;
  986. txd = &(xl_priv->xl_tx_ring[tx_head]) ;
  987. txd->dnnextptr = 0 ;
  988. txd->framestartheader = cpu_to_le32(skb->len) | TXDNINDICATE;
  989. txd->buffer = cpu_to_le32(pci_map_single(xl_priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE));
  990. txd->buffer_length = cpu_to_le32(skb->len) | TXDNFRAGLAST;
  991. xl_priv->tx_ring_skb[tx_head] = skb ;
  992. dev->stats.tx_packets++ ;
  993. dev->stats.tx_bytes += skb->len ;
  994. /*
  995. * Set the nextptr of the previous descriptor equal to this descriptor, add XL_TX_RING_SIZE -1
  996. * to ensure no negative numbers in unsigned locations.
  997. */
  998. tx_prev = (xl_priv->tx_ring_head + XL_TX_RING_SIZE - 1) & (XL_TX_RING_SIZE - 1) ;
  999. xl_priv->tx_ring_head++ ;
  1000. xl_priv->tx_ring_head &= (XL_TX_RING_SIZE - 1) ;
  1001. xl_priv->free_ring_entries-- ;
  1002. xl_priv->xl_tx_ring[tx_prev].dnnextptr = cpu_to_le32(xl_priv->tx_ring_dma_addr + (sizeof (struct xl_tx_desc) * tx_head));
  1003. /* Sneaky, by doing a read on DnListPtr we can force the card to poll on the DnNextPtr */
  1004. /* readl(xl_mmio + MMIO_DNLISTPTR) ; */
  1005. netif_wake_queue(dev) ;
  1006. spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ;
  1007. return NETDEV_TX_OK;
  1008. } else {
  1009. spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ;
  1010. return NETDEV_TX_BUSY;
  1011. }
  1012. }
  1013. /*
  1014. * The NIC has told us that a packet has been downloaded onto the card, we must
  1015. * find out which packet it has done, clear the skb and information for the packet
  1016. * then advance around the ring for all tranmitted packets
  1017. */
  1018. static void xl_dn_comp(struct net_device *dev)
  1019. {
  1020. struct xl_private *xl_priv=netdev_priv(dev);
  1021. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1022. struct xl_tx_desc *txd ;
  1023. if (xl_priv->tx_ring_tail == 255) {/* First time */
  1024. xl_priv->xl_tx_ring[0].framestartheader = 0 ;
  1025. xl_priv->xl_tx_ring[0].dnnextptr = 0 ;
  1026. xl_priv->tx_ring_tail = 1 ;
  1027. }
  1028. while (xl_priv->xl_tx_ring[xl_priv->tx_ring_tail].framestartheader & TXDNCOMPLETE ) {
  1029. txd = &(xl_priv->xl_tx_ring[xl_priv->tx_ring_tail]) ;
  1030. pci_unmap_single(xl_priv->pdev, le32_to_cpu(txd->buffer), xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]->len, PCI_DMA_TODEVICE);
  1031. txd->framestartheader = 0 ;
  1032. txd->buffer = cpu_to_le32(0xdeadbeef);
  1033. txd->buffer_length = 0 ;
  1034. dev_kfree_skb_irq(xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]) ;
  1035. xl_priv->tx_ring_tail++ ;
  1036. xl_priv->tx_ring_tail &= (XL_TX_RING_SIZE - 1) ;
  1037. xl_priv->free_ring_entries++ ;
  1038. }
  1039. netif_wake_queue(dev) ;
  1040. writel(ACK_INTERRUPT | DNCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  1041. }
  1042. /*
  1043. * Close the adapter properly.
  1044. * This srb reply cannot be handled from interrupt context as we have
  1045. * to free the interrupt from the driver.
  1046. */
  1047. static int xl_close(struct net_device *dev)
  1048. {
  1049. struct xl_private *xl_priv = netdev_priv(dev);
  1050. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1051. unsigned long t ;
  1052. netif_stop_queue(dev) ;
  1053. /*
  1054. * Close the adapter, need to stall the rx and tx queues.
  1055. */
  1056. writew(DNSTALL, xl_mmio + MMIO_COMMAND) ;
  1057. t=jiffies;
  1058. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1059. schedule();
  1060. if (time_after(jiffies, t + 10 * HZ)) {
  1061. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNSTALL not responding.\n", dev->name);
  1062. break ;
  1063. }
  1064. }
  1065. writew(DNDISABLE, xl_mmio + MMIO_COMMAND) ;
  1066. t=jiffies;
  1067. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1068. schedule();
  1069. if (time_after(jiffies, t + 10 * HZ)) {
  1070. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNDISABLE not responding.\n", dev->name);
  1071. break ;
  1072. }
  1073. }
  1074. writew(UPSTALL, xl_mmio + MMIO_COMMAND) ;
  1075. t=jiffies;
  1076. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1077. schedule();
  1078. if (time_after(jiffies, t + 10 * HZ)) {
  1079. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPSTALL not responding.\n", dev->name);
  1080. break ;
  1081. }
  1082. }
  1083. /* Turn off interrupts, we will still get the indication though
  1084. * so we can trap it
  1085. */
  1086. writel(SETINTENABLE, xl_mmio + MMIO_COMMAND) ;
  1087. xl_srb_cmd(dev,CLOSE_NIC) ;
  1088. t=jiffies;
  1089. while (!(readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
  1090. schedule();
  1091. if (time_after(jiffies, t + 10 * HZ)) {
  1092. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-CLOSENIC not responding.\n", dev->name);
  1093. break ;
  1094. }
  1095. }
  1096. /* Read the srb response from the adapter */
  1097. writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD);
  1098. if (readb(xl_mmio + MMIO_MACDATA) != CLOSE_NIC) {
  1099. printk(KERN_INFO "%s: CLOSE_NIC did not get a CLOSE_NIC response \n",dev->name) ;
  1100. } else {
  1101. writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1102. if (readb(xl_mmio + MMIO_MACDATA)==0) {
  1103. printk(KERN_INFO "%s: Adapter has been closed \n",dev->name) ;
  1104. writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  1105. xl_freemem(dev) ;
  1106. free_irq(dev->irq,dev) ;
  1107. } else {
  1108. printk(KERN_INFO "%s: Close nic command returned error code %02x\n",dev->name, readb(xl_mmio + MMIO_MACDATA)) ;
  1109. }
  1110. }
  1111. /* Reset the upload and download logic */
  1112. writew(UPRESET, xl_mmio + MMIO_COMMAND) ;
  1113. t=jiffies;
  1114. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1115. schedule();
  1116. if (time_after(jiffies, t + 10 * HZ)) {
  1117. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPRESET not responding.\n", dev->name);
  1118. break ;
  1119. }
  1120. }
  1121. writew(DNRESET, xl_mmio + MMIO_COMMAND) ;
  1122. t=jiffies;
  1123. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1124. schedule();
  1125. if (time_after(jiffies, t + 10 * HZ)) {
  1126. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNRESET not responding.\n", dev->name);
  1127. break ;
  1128. }
  1129. }
  1130. xl_hw_reset(dev) ;
  1131. return 0 ;
  1132. }
  1133. static void xl_set_rx_mode(struct net_device *dev)
  1134. {
  1135. struct xl_private *xl_priv = netdev_priv(dev);
  1136. struct dev_mc_list *dmi;
  1137. unsigned char dev_mc_address[4] ;
  1138. u16 options ;
  1139. if (dev->flags & IFF_PROMISC)
  1140. options = 0x0004 ;
  1141. else
  1142. options = 0x0000 ;
  1143. if (options ^ xl_priv->xl_copy_all_options) { /* Changed, must send command */
  1144. xl_priv->xl_copy_all_options = options ;
  1145. xl_srb_cmd(dev, SET_RECEIVE_MODE) ;
  1146. return ;
  1147. }
  1148. dev_mc_address[0] = dev_mc_address[1] = dev_mc_address[2] = dev_mc_address[3] = 0 ;
  1149. netdev_for_each_mc_addr(dmi, dev) {
  1150. dev_mc_address[0] |= dmi->dmi_addr[2] ;
  1151. dev_mc_address[1] |= dmi->dmi_addr[3] ;
  1152. dev_mc_address[2] |= dmi->dmi_addr[4] ;
  1153. dev_mc_address[3] |= dmi->dmi_addr[5] ;
  1154. }
  1155. if (memcmp(xl_priv->xl_functional_addr,dev_mc_address,4) != 0) { /* Options have changed, run the command */
  1156. memcpy(xl_priv->xl_functional_addr, dev_mc_address,4) ;
  1157. xl_srb_cmd(dev, SET_FUNC_ADDRESS) ;
  1158. }
  1159. return ;
  1160. }
  1161. /*
  1162. * We issued an srb command and now we must read
  1163. * the response from the completed command.
  1164. */
  1165. static void xl_srb_bh(struct net_device *dev)
  1166. {
  1167. struct xl_private *xl_priv = netdev_priv(dev);
  1168. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1169. u8 srb_cmd, ret_code ;
  1170. int i ;
  1171. writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1172. srb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
  1173. writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1174. ret_code = readb(xl_mmio + MMIO_MACDATA) ;
  1175. /* Ret_code is standard across all commands */
  1176. switch (ret_code) {
  1177. case 1:
  1178. printk(KERN_INFO "%s: Command: %d - Invalid Command code\n",dev->name,srb_cmd) ;
  1179. break ;
  1180. case 4:
  1181. printk(KERN_INFO "%s: Command: %d - Adapter is closed, must be open for this command \n",dev->name,srb_cmd) ;
  1182. break ;
  1183. case 6:
  1184. printk(KERN_INFO "%s: Command: %d - Options Invalid for command \n",dev->name,srb_cmd) ;
  1185. break ;
  1186. case 0: /* Successful command execution */
  1187. switch (srb_cmd) {
  1188. case READ_LOG: /* Returns 14 bytes of data from the NIC */
  1189. if(xl_priv->xl_message_level)
  1190. printk(KERN_INFO "%s: READ.LOG 14 bytes of data ",dev->name) ;
  1191. /*
  1192. * We still have to read the log even if message_level = 0 and we don't want
  1193. * to see it
  1194. */
  1195. for (i=0;i<14;i++) {
  1196. writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1197. if(xl_priv->xl_message_level)
  1198. printk("%02x:",readb(xl_mmio + MMIO_MACDATA)) ;
  1199. }
  1200. printk("\n") ;
  1201. break ;
  1202. case SET_FUNC_ADDRESS:
  1203. if(xl_priv->xl_message_level)
  1204. printk(KERN_INFO "%s: Functional Address Set \n",dev->name) ;
  1205. break ;
  1206. case CLOSE_NIC:
  1207. if(xl_priv->xl_message_level)
  1208. printk(KERN_INFO "%s: Received CLOSE_NIC interrupt in interrupt handler \n",dev->name) ;
  1209. break ;
  1210. case SET_MULTICAST_MODE:
  1211. if(xl_priv->xl_message_level)
  1212. printk(KERN_INFO "%s: Multicast options successfully changed\n",dev->name) ;
  1213. break ;
  1214. case SET_RECEIVE_MODE:
  1215. if(xl_priv->xl_message_level) {
  1216. if (xl_priv->xl_copy_all_options == 0x0004)
  1217. printk(KERN_INFO "%s: Entering promiscuous mode \n", dev->name) ;
  1218. else
  1219. printk(KERN_INFO "%s: Entering normal receive mode \n",dev->name) ;
  1220. }
  1221. break ;
  1222. } /* switch */
  1223. break ;
  1224. } /* switch */
  1225. return ;
  1226. }
  1227. static int xl_set_mac_address (struct net_device *dev, void *addr)
  1228. {
  1229. struct sockaddr *saddr = addr ;
  1230. struct xl_private *xl_priv = netdev_priv(dev);
  1231. if (netif_running(dev)) {
  1232. printk(KERN_WARNING "%s: Cannot set mac/laa address while card is open\n", dev->name) ;
  1233. return -EIO ;
  1234. }
  1235. memcpy(xl_priv->xl_laa, saddr->sa_data,dev->addr_len) ;
  1236. if (xl_priv->xl_message_level) {
  1237. printk(KERN_INFO "%s: MAC/LAA Set to = %x.%x.%x.%x.%x.%x\n",dev->name, xl_priv->xl_laa[0],
  1238. xl_priv->xl_laa[1], xl_priv->xl_laa[2],
  1239. xl_priv->xl_laa[3], xl_priv->xl_laa[4],
  1240. xl_priv->xl_laa[5]);
  1241. }
  1242. return 0 ;
  1243. }
  1244. static void xl_arb_cmd(struct net_device *dev)
  1245. {
  1246. struct xl_private *xl_priv = netdev_priv(dev);
  1247. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1248. u8 arb_cmd ;
  1249. u16 lan_status, lan_status_diff ;
  1250. writel( ( MEM_BYTE_READ | 0xD0000 | xl_priv->arb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1251. arb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
  1252. if (arb_cmd == RING_STATUS_CHANGE) { /* Ring.Status.Change */
  1253. writel( ( (MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1254. printk(KERN_INFO "%s: Ring Status Change: New Status = %04x\n", dev->name, swab16(readw(xl_mmio + MMIO_MACDATA) )) ;
  1255. lan_status = swab16(readw(xl_mmio + MMIO_MACDATA));
  1256. /* Acknowledge interrupt, this tells nic we are done with the arb */
  1257. writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  1258. lan_status_diff = xl_priv->xl_lan_status ^ lan_status ;
  1259. if (lan_status_diff & (LSC_LWF | LSC_ARW | LSC_FPE | LSC_RR) ) {
  1260. if (lan_status_diff & LSC_LWF)
  1261. printk(KERN_WARNING "%s: Short circuit detected on the lobe\n",dev->name);
  1262. if (lan_status_diff & LSC_ARW)
  1263. printk(KERN_WARNING "%s: Auto removal error\n",dev->name);
  1264. if (lan_status_diff & LSC_FPE)
  1265. printk(KERN_WARNING "%s: FDX Protocol Error\n",dev->name);
  1266. if (lan_status_diff & LSC_RR)
  1267. printk(KERN_WARNING "%s: Force remove MAC frame received\n",dev->name);
  1268. /* Adapter has been closed by the hardware */
  1269. netif_stop_queue(dev);
  1270. xl_freemem(dev) ;
  1271. free_irq(dev->irq,dev);
  1272. printk(KERN_WARNING "%s: Adapter has been closed \n", dev->name) ;
  1273. } /* If serious error */
  1274. if (xl_priv->xl_message_level) {
  1275. if (lan_status_diff & LSC_SIG_LOSS)
  1276. printk(KERN_WARNING "%s: No receive signal detected \n", dev->name) ;
  1277. if (lan_status_diff & LSC_HARD_ERR)
  1278. printk(KERN_INFO "%s: Beaconing \n",dev->name);
  1279. if (lan_status_diff & LSC_SOFT_ERR)
  1280. printk(KERN_WARNING "%s: Adapter transmitted Soft Error Report Mac Frame \n",dev->name);
  1281. if (lan_status_diff & LSC_TRAN_BCN)
  1282. printk(KERN_INFO "%s: We are tranmitting the beacon, aaah\n",dev->name);
  1283. if (lan_status_diff & LSC_SS)
  1284. printk(KERN_INFO "%s: Single Station on the ring \n", dev->name);
  1285. if (lan_status_diff & LSC_RING_REC)
  1286. printk(KERN_INFO "%s: Ring recovery ongoing\n",dev->name);
  1287. if (lan_status_diff & LSC_FDX_MODE)
  1288. printk(KERN_INFO "%s: Operating in FDX mode\n",dev->name);
  1289. }
  1290. if (lan_status_diff & LSC_CO) {
  1291. if (xl_priv->xl_message_level)
  1292. printk(KERN_INFO "%s: Counter Overflow \n", dev->name);
  1293. /* Issue READ.LOG command */
  1294. xl_srb_cmd(dev, READ_LOG) ;
  1295. }
  1296. /* There is no command in the tech docs to issue the read_sr_counters */
  1297. if (lan_status_diff & LSC_SR_CO) {
  1298. if (xl_priv->xl_message_level)
  1299. printk(KERN_INFO "%s: Source routing counters overflow\n", dev->name);
  1300. }
  1301. xl_priv->xl_lan_status = lan_status ;
  1302. } /* Lan.change.status */
  1303. else if ( arb_cmd == RECEIVE_DATA) { /* Received.Data */
  1304. #if XL_DEBUG
  1305. printk(KERN_INFO "Received.Data \n") ;
  1306. #endif
  1307. writel( ((MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1308. xl_priv->mac_buffer = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
  1309. /* Now we are going to be really basic here and not do anything
  1310. * with the data at all. The tech docs do not give me enough
  1311. * information to calculate the buffers properly so we're
  1312. * just going to tell the nic that we've dealt with the frame
  1313. * anyway.
  1314. */
  1315. /* Acknowledge interrupt, this tells nic we are done with the arb */
  1316. writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  1317. /* Is the ASB free ? */
  1318. xl_priv->asb_queued = 0 ;
  1319. writel( ((MEM_BYTE_READ | 0xD0000 | xl_priv->asb) + 2), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1320. if (readb(xl_mmio + MMIO_MACDATA) != 0xff) {
  1321. xl_priv->asb_queued = 1 ;
  1322. xl_wait_misr_flags(dev) ;
  1323. writel(MEM_BYTE_WRITE | MF_ASBFR, xl_mmio + MMIO_MAC_ACCESS_CMD);
  1324. writeb(0xff, xl_mmio + MMIO_MACDATA) ;
  1325. writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1326. writeb(MISR_ASBFR, xl_mmio + MMIO_MACDATA) ;
  1327. return ;
  1328. /* Drop out and wait for the bottom half to be run */
  1329. }
  1330. xl_asb_cmd(dev) ;
  1331. } else {
  1332. printk(KERN_WARNING "%s: Received unknown arb (xl_priv) command: %02x \n",dev->name,arb_cmd) ;
  1333. }
  1334. /* Acknowledge the arb interrupt */
  1335. writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  1336. return ;
  1337. }
  1338. /*
  1339. * There is only one asb command, but we can get called from different
  1340. * places.
  1341. */
  1342. static void xl_asb_cmd(struct net_device *dev)
  1343. {
  1344. struct xl_private *xl_priv = netdev_priv(dev);
  1345. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1346. if (xl_priv->asb_queued == 1)
  1347. writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
  1348. writel(MEM_BYTE_WRITE | 0xd0000 | xl_priv->asb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1349. writeb(0x81, xl_mmio + MMIO_MACDATA) ;
  1350. writel(MEM_WORD_WRITE | 0xd0000 | xl_priv->asb | 6, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1351. writew(swab16(xl_priv->mac_buffer), xl_mmio + MMIO_MACDATA) ;
  1352. xl_wait_misr_flags(dev) ;
  1353. writel(MEM_BYTE_WRITE | MF_RASB, xl_mmio + MMIO_MAC_ACCESS_CMD);
  1354. writeb(0xff, xl_mmio + MMIO_MACDATA) ;
  1355. writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1356. writeb(MISR_RASB, xl_mmio + MMIO_MACDATA) ;
  1357. xl_priv->asb_queued = 2 ;
  1358. return ;
  1359. }
  1360. /*
  1361. * This will only get called if there was an error
  1362. * from the asb cmd.
  1363. */
  1364. static void xl_asb_bh(struct net_device *dev)
  1365. {
  1366. struct xl_private *xl_priv = netdev_priv(dev);
  1367. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1368. u8 ret_code ;
  1369. writel(MMIO_BYTE_READ | 0xd0000 | xl_priv->asb | 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1370. ret_code = readb(xl_mmio + MMIO_MACDATA) ;
  1371. switch (ret_code) {
  1372. case 0x01:
  1373. printk(KERN_INFO "%s: ASB Command, unrecognized command code \n",dev->name) ;
  1374. break ;
  1375. case 0x26:
  1376. printk(KERN_INFO "%s: ASB Command, unexpected receive buffer \n", dev->name) ;
  1377. break ;
  1378. case 0x40:
  1379. printk(KERN_INFO "%s: ASB Command, Invalid Station ID \n", dev->name) ;
  1380. break ;
  1381. }
  1382. xl_priv->asb_queued = 0 ;
  1383. writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
  1384. return ;
  1385. }
  1386. /*
  1387. * Issue srb commands to the nic
  1388. */
  1389. static void xl_srb_cmd(struct net_device *dev, int srb_cmd)
  1390. {
  1391. struct xl_private *xl_priv = netdev_priv(dev);
  1392. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1393. switch (srb_cmd) {
  1394. case READ_LOG:
  1395. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1396. writeb(READ_LOG, xl_mmio + MMIO_MACDATA) ;
  1397. break;
  1398. case CLOSE_NIC:
  1399. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1400. writeb(CLOSE_NIC, xl_mmio + MMIO_MACDATA) ;
  1401. break ;
  1402. case SET_RECEIVE_MODE:
  1403. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1404. writeb(SET_RECEIVE_MODE, xl_mmio + MMIO_MACDATA) ;
  1405. writel(MEM_WORD_WRITE | 0xD0000 | xl_priv->srb | 4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1406. writew(xl_priv->xl_copy_all_options, xl_mmio + MMIO_MACDATA) ;
  1407. break ;
  1408. case SET_FUNC_ADDRESS:
  1409. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1410. writeb(SET_FUNC_ADDRESS, xl_mmio + MMIO_MACDATA) ;
  1411. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 6 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1412. writeb(xl_priv->xl_functional_addr[0], xl_mmio + MMIO_MACDATA) ;
  1413. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 7 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1414. writeb(xl_priv->xl_functional_addr[1], xl_mmio + MMIO_MACDATA) ;
  1415. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 8 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1416. writeb(xl_priv->xl_functional_addr[2], xl_mmio + MMIO_MACDATA) ;
  1417. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 9 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1418. writeb(xl_priv->xl_functional_addr[3], xl_mmio + MMIO_MACDATA) ;
  1419. break ;
  1420. } /* switch */
  1421. xl_wait_misr_flags(dev) ;
  1422. /* Write 0xff to the CSRB flag */
  1423. writel(MEM_BYTE_WRITE | MF_CSRB , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1424. writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
  1425. /* Set csrb bit in MISR register to process command */
  1426. writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1427. writeb(MISR_CSRB, xl_mmio + MMIO_MACDATA) ;
  1428. xl_priv->srb_queued = 1 ;
  1429. return ;
  1430. }
  1431. /*
  1432. * This is nasty, to use the MISR command you have to wait for 6 memory locations
  1433. * to be zero. This is the way the driver does on other OS'es so we should be ok with
  1434. * the empty loop.
  1435. */
  1436. static void xl_wait_misr_flags(struct net_device *dev)
  1437. {
  1438. struct xl_private *xl_priv = netdev_priv(dev);
  1439. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1440. int i ;
  1441. writel(MMIO_BYTE_READ | MISR_RW, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1442. if (readb(xl_mmio + MMIO_MACDATA) != 0) { /* Misr not clear */
  1443. for (i=0; i<6; i++) {
  1444. writel(MEM_BYTE_READ | 0xDFFE0 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1445. while (readb(xl_mmio + MMIO_MACDATA) != 0 ) {} ; /* Empty Loop */
  1446. }
  1447. }
  1448. writel(MMIO_BYTE_WRITE | MISR_AND, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1449. writeb(0x80, xl_mmio + MMIO_MACDATA) ;
  1450. return ;
  1451. }
  1452. /*
  1453. * Change mtu size, this should work the same as olympic
  1454. */
  1455. static int xl_change_mtu(struct net_device *dev, int mtu)
  1456. {
  1457. struct xl_private *xl_priv = netdev_priv(dev);
  1458. u16 max_mtu ;
  1459. if (xl_priv->xl_ring_speed == 4)
  1460. max_mtu = 4500 ;
  1461. else
  1462. max_mtu = 18000 ;
  1463. if (mtu > max_mtu)
  1464. return -EINVAL ;
  1465. if (mtu < 100)
  1466. return -EINVAL ;
  1467. dev->mtu = mtu ;
  1468. xl_priv->pkt_buf_sz = mtu + TR_HLEN ;
  1469. return 0 ;
  1470. }
  1471. static void __devexit xl_remove_one (struct pci_dev *pdev)
  1472. {
  1473. struct net_device *dev = pci_get_drvdata(pdev);
  1474. struct xl_private *xl_priv=netdev_priv(dev);
  1475. release_firmware(xl_priv->fw);
  1476. unregister_netdev(dev);
  1477. iounmap(xl_priv->xl_mmio) ;
  1478. pci_release_regions(pdev) ;
  1479. pci_set_drvdata(pdev,NULL) ;
  1480. free_netdev(dev);
  1481. return ;
  1482. }
  1483. static struct pci_driver xl_3c359_driver = {
  1484. .name = "3c359",
  1485. .id_table = xl_pci_tbl,
  1486. .probe = xl_probe,
  1487. .remove = __devexit_p(xl_remove_one),
  1488. };
  1489. static int __init xl_pci_init (void)
  1490. {
  1491. return pci_register_driver(&xl_3c359_driver);
  1492. }
  1493. static void __exit xl_pci_cleanup (void)
  1494. {
  1495. pci_unregister_driver (&xl_3c359_driver);
  1496. }
  1497. module_init(xl_pci_init);
  1498. module_exit(xl_pci_cleanup);
  1499. MODULE_LICENSE("GPL") ;