sge.c 93 KB

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  1. /*
  2. * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/skbuff.h>
  33. #include <linux/netdevice.h>
  34. #include <linux/etherdevice.h>
  35. #include <linux/if_vlan.h>
  36. #include <linux/ip.h>
  37. #include <linux/tcp.h>
  38. #include <linux/dma-mapping.h>
  39. #include <net/arp.h>
  40. #include "common.h"
  41. #include "regs.h"
  42. #include "sge_defs.h"
  43. #include "t3_cpl.h"
  44. #include "firmware_exports.h"
  45. #define USE_GTS 0
  46. #define SGE_RX_SM_BUF_SIZE 1536
  47. #define SGE_RX_COPY_THRES 256
  48. #define SGE_RX_PULL_LEN 128
  49. #define SGE_PG_RSVD SMP_CACHE_BYTES
  50. /*
  51. * Page chunk size for FL0 buffers if FL0 is to be populated with page chunks.
  52. * It must be a divisor of PAGE_SIZE. If set to 0 FL0 will use sk_buffs
  53. * directly.
  54. */
  55. #define FL0_PG_CHUNK_SIZE 2048
  56. #define FL0_PG_ORDER 0
  57. #define FL0_PG_ALLOC_SIZE (PAGE_SIZE << FL0_PG_ORDER)
  58. #define FL1_PG_CHUNK_SIZE (PAGE_SIZE > 8192 ? 16384 : 8192)
  59. #define FL1_PG_ORDER (PAGE_SIZE > 8192 ? 0 : 1)
  60. #define FL1_PG_ALLOC_SIZE (PAGE_SIZE << FL1_PG_ORDER)
  61. #define SGE_RX_DROP_THRES 16
  62. #define RX_RECLAIM_PERIOD (HZ/4)
  63. /*
  64. * Max number of Rx buffers we replenish at a time.
  65. */
  66. #define MAX_RX_REFILL 16U
  67. /*
  68. * Period of the Tx buffer reclaim timer. This timer does not need to run
  69. * frequently as Tx buffers are usually reclaimed by new Tx packets.
  70. */
  71. #define TX_RECLAIM_PERIOD (HZ / 4)
  72. #define TX_RECLAIM_TIMER_CHUNK 64U
  73. #define TX_RECLAIM_CHUNK 16U
  74. /* WR size in bytes */
  75. #define WR_LEN (WR_FLITS * 8)
  76. /*
  77. * Types of Tx queues in each queue set. Order here matters, do not change.
  78. */
  79. enum { TXQ_ETH, TXQ_OFLD, TXQ_CTRL };
  80. /* Values for sge_txq.flags */
  81. enum {
  82. TXQ_RUNNING = 1 << 0, /* fetch engine is running */
  83. TXQ_LAST_PKT_DB = 1 << 1, /* last packet rang the doorbell */
  84. };
  85. struct tx_desc {
  86. __be64 flit[TX_DESC_FLITS];
  87. };
  88. struct rx_desc {
  89. __be32 addr_lo;
  90. __be32 len_gen;
  91. __be32 gen2;
  92. __be32 addr_hi;
  93. };
  94. struct tx_sw_desc { /* SW state per Tx descriptor */
  95. struct sk_buff *skb;
  96. u8 eop; /* set if last descriptor for packet */
  97. u8 addr_idx; /* buffer index of first SGL entry in descriptor */
  98. u8 fragidx; /* first page fragment associated with descriptor */
  99. s8 sflit; /* start flit of first SGL entry in descriptor */
  100. };
  101. struct rx_sw_desc { /* SW state per Rx descriptor */
  102. union {
  103. struct sk_buff *skb;
  104. struct fl_pg_chunk pg_chunk;
  105. };
  106. DECLARE_PCI_UNMAP_ADDR(dma_addr);
  107. };
  108. struct rsp_desc { /* response queue descriptor */
  109. struct rss_header rss_hdr;
  110. __be32 flags;
  111. __be32 len_cq;
  112. u8 imm_data[47];
  113. u8 intr_gen;
  114. };
  115. /*
  116. * Holds unmapping information for Tx packets that need deferred unmapping.
  117. * This structure lives at skb->head and must be allocated by callers.
  118. */
  119. struct deferred_unmap_info {
  120. struct pci_dev *pdev;
  121. dma_addr_t addr[MAX_SKB_FRAGS + 1];
  122. };
  123. /*
  124. * Maps a number of flits to the number of Tx descriptors that can hold them.
  125. * The formula is
  126. *
  127. * desc = 1 + (flits - 2) / (WR_FLITS - 1).
  128. *
  129. * HW allows up to 4 descriptors to be combined into a WR.
  130. */
  131. static u8 flit_desc_map[] = {
  132. 0,
  133. #if SGE_NUM_GENBITS == 1
  134. 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
  135. 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
  136. 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
  137. 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4
  138. #elif SGE_NUM_GENBITS == 2
  139. 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
  140. 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
  141. 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
  142. 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
  143. #else
  144. # error "SGE_NUM_GENBITS must be 1 or 2"
  145. #endif
  146. };
  147. static inline struct sge_qset *fl_to_qset(const struct sge_fl *q, int qidx)
  148. {
  149. return container_of(q, struct sge_qset, fl[qidx]);
  150. }
  151. static inline struct sge_qset *rspq_to_qset(const struct sge_rspq *q)
  152. {
  153. return container_of(q, struct sge_qset, rspq);
  154. }
  155. static inline struct sge_qset *txq_to_qset(const struct sge_txq *q, int qidx)
  156. {
  157. return container_of(q, struct sge_qset, txq[qidx]);
  158. }
  159. /**
  160. * refill_rspq - replenish an SGE response queue
  161. * @adapter: the adapter
  162. * @q: the response queue to replenish
  163. * @credits: how many new responses to make available
  164. *
  165. * Replenishes a response queue by making the supplied number of responses
  166. * available to HW.
  167. */
  168. static inline void refill_rspq(struct adapter *adapter,
  169. const struct sge_rspq *q, unsigned int credits)
  170. {
  171. rmb();
  172. t3_write_reg(adapter, A_SG_RSPQ_CREDIT_RETURN,
  173. V_RSPQ(q->cntxt_id) | V_CREDITS(credits));
  174. }
  175. /**
  176. * need_skb_unmap - does the platform need unmapping of sk_buffs?
  177. *
  178. * Returns true if the platfrom needs sk_buff unmapping. The compiler
  179. * optimizes away unecessary code if this returns true.
  180. */
  181. static inline int need_skb_unmap(void)
  182. {
  183. /*
  184. * This structure is used to tell if the platfrom needs buffer
  185. * unmapping by checking if DECLARE_PCI_UNMAP_ADDR defines anything.
  186. */
  187. struct dummy {
  188. DECLARE_PCI_UNMAP_ADDR(addr);
  189. };
  190. return sizeof(struct dummy) != 0;
  191. }
  192. /**
  193. * unmap_skb - unmap a packet main body and its page fragments
  194. * @skb: the packet
  195. * @q: the Tx queue containing Tx descriptors for the packet
  196. * @cidx: index of Tx descriptor
  197. * @pdev: the PCI device
  198. *
  199. * Unmap the main body of an sk_buff and its page fragments, if any.
  200. * Because of the fairly complicated structure of our SGLs and the desire
  201. * to conserve space for metadata, the information necessary to unmap an
  202. * sk_buff is spread across the sk_buff itself (buffer lengths), the HW Tx
  203. * descriptors (the physical addresses of the various data buffers), and
  204. * the SW descriptor state (assorted indices). The send functions
  205. * initialize the indices for the first packet descriptor so we can unmap
  206. * the buffers held in the first Tx descriptor here, and we have enough
  207. * information at this point to set the state for the next Tx descriptor.
  208. *
  209. * Note that it is possible to clean up the first descriptor of a packet
  210. * before the send routines have written the next descriptors, but this
  211. * race does not cause any problem. We just end up writing the unmapping
  212. * info for the descriptor first.
  213. */
  214. static inline void unmap_skb(struct sk_buff *skb, struct sge_txq *q,
  215. unsigned int cidx, struct pci_dev *pdev)
  216. {
  217. const struct sg_ent *sgp;
  218. struct tx_sw_desc *d = &q->sdesc[cidx];
  219. int nfrags, frag_idx, curflit, j = d->addr_idx;
  220. sgp = (struct sg_ent *)&q->desc[cidx].flit[d->sflit];
  221. frag_idx = d->fragidx;
  222. if (frag_idx == 0 && skb_headlen(skb)) {
  223. pci_unmap_single(pdev, be64_to_cpu(sgp->addr[0]),
  224. skb_headlen(skb), PCI_DMA_TODEVICE);
  225. j = 1;
  226. }
  227. curflit = d->sflit + 1 + j;
  228. nfrags = skb_shinfo(skb)->nr_frags;
  229. while (frag_idx < nfrags && curflit < WR_FLITS) {
  230. pci_unmap_page(pdev, be64_to_cpu(sgp->addr[j]),
  231. skb_shinfo(skb)->frags[frag_idx].size,
  232. PCI_DMA_TODEVICE);
  233. j ^= 1;
  234. if (j == 0) {
  235. sgp++;
  236. curflit++;
  237. }
  238. curflit++;
  239. frag_idx++;
  240. }
  241. if (frag_idx < nfrags) { /* SGL continues into next Tx descriptor */
  242. d = cidx + 1 == q->size ? q->sdesc : d + 1;
  243. d->fragidx = frag_idx;
  244. d->addr_idx = j;
  245. d->sflit = curflit - WR_FLITS - j; /* sflit can be -1 */
  246. }
  247. }
  248. /**
  249. * free_tx_desc - reclaims Tx descriptors and their buffers
  250. * @adapter: the adapter
  251. * @q: the Tx queue to reclaim descriptors from
  252. * @n: the number of descriptors to reclaim
  253. *
  254. * Reclaims Tx descriptors from an SGE Tx queue and frees the associated
  255. * Tx buffers. Called with the Tx queue lock held.
  256. */
  257. static void free_tx_desc(struct adapter *adapter, struct sge_txq *q,
  258. unsigned int n)
  259. {
  260. struct tx_sw_desc *d;
  261. struct pci_dev *pdev = adapter->pdev;
  262. unsigned int cidx = q->cidx;
  263. const int need_unmap = need_skb_unmap() &&
  264. q->cntxt_id >= FW_TUNNEL_SGEEC_START;
  265. d = &q->sdesc[cidx];
  266. while (n--) {
  267. if (d->skb) { /* an SGL is present */
  268. if (need_unmap)
  269. unmap_skb(d->skb, q, cidx, pdev);
  270. if (d->eop)
  271. kfree_skb(d->skb);
  272. }
  273. ++d;
  274. if (++cidx == q->size) {
  275. cidx = 0;
  276. d = q->sdesc;
  277. }
  278. }
  279. q->cidx = cidx;
  280. }
  281. /**
  282. * reclaim_completed_tx - reclaims completed Tx descriptors
  283. * @adapter: the adapter
  284. * @q: the Tx queue to reclaim completed descriptors from
  285. * @chunk: maximum number of descriptors to reclaim
  286. *
  287. * Reclaims Tx descriptors that the SGE has indicated it has processed,
  288. * and frees the associated buffers if possible. Called with the Tx
  289. * queue's lock held.
  290. */
  291. static inline unsigned int reclaim_completed_tx(struct adapter *adapter,
  292. struct sge_txq *q,
  293. unsigned int chunk)
  294. {
  295. unsigned int reclaim = q->processed - q->cleaned;
  296. reclaim = min(chunk, reclaim);
  297. if (reclaim) {
  298. free_tx_desc(adapter, q, reclaim);
  299. q->cleaned += reclaim;
  300. q->in_use -= reclaim;
  301. }
  302. return q->processed - q->cleaned;
  303. }
  304. /**
  305. * should_restart_tx - are there enough resources to restart a Tx queue?
  306. * @q: the Tx queue
  307. *
  308. * Checks if there are enough descriptors to restart a suspended Tx queue.
  309. */
  310. static inline int should_restart_tx(const struct sge_txq *q)
  311. {
  312. unsigned int r = q->processed - q->cleaned;
  313. return q->in_use - r < (q->size >> 1);
  314. }
  315. static void clear_rx_desc(struct pci_dev *pdev, const struct sge_fl *q,
  316. struct rx_sw_desc *d)
  317. {
  318. if (q->use_pages && d->pg_chunk.page) {
  319. (*d->pg_chunk.p_cnt)--;
  320. if (!*d->pg_chunk.p_cnt)
  321. pci_unmap_page(pdev,
  322. d->pg_chunk.mapping,
  323. q->alloc_size, PCI_DMA_FROMDEVICE);
  324. put_page(d->pg_chunk.page);
  325. d->pg_chunk.page = NULL;
  326. } else {
  327. pci_unmap_single(pdev, pci_unmap_addr(d, dma_addr),
  328. q->buf_size, PCI_DMA_FROMDEVICE);
  329. kfree_skb(d->skb);
  330. d->skb = NULL;
  331. }
  332. }
  333. /**
  334. * free_rx_bufs - free the Rx buffers on an SGE free list
  335. * @pdev: the PCI device associated with the adapter
  336. * @rxq: the SGE free list to clean up
  337. *
  338. * Release the buffers on an SGE free-buffer Rx queue. HW fetching from
  339. * this queue should be stopped before calling this function.
  340. */
  341. static void free_rx_bufs(struct pci_dev *pdev, struct sge_fl *q)
  342. {
  343. unsigned int cidx = q->cidx;
  344. while (q->credits--) {
  345. struct rx_sw_desc *d = &q->sdesc[cidx];
  346. clear_rx_desc(pdev, q, d);
  347. if (++cidx == q->size)
  348. cidx = 0;
  349. }
  350. if (q->pg_chunk.page) {
  351. __free_pages(q->pg_chunk.page, q->order);
  352. q->pg_chunk.page = NULL;
  353. }
  354. }
  355. /**
  356. * add_one_rx_buf - add a packet buffer to a free-buffer list
  357. * @va: buffer start VA
  358. * @len: the buffer length
  359. * @d: the HW Rx descriptor to write
  360. * @sd: the SW Rx descriptor to write
  361. * @gen: the generation bit value
  362. * @pdev: the PCI device associated with the adapter
  363. *
  364. * Add a buffer of the given length to the supplied HW and SW Rx
  365. * descriptors.
  366. */
  367. static inline int add_one_rx_buf(void *va, unsigned int len,
  368. struct rx_desc *d, struct rx_sw_desc *sd,
  369. unsigned int gen, struct pci_dev *pdev)
  370. {
  371. dma_addr_t mapping;
  372. mapping = pci_map_single(pdev, va, len, PCI_DMA_FROMDEVICE);
  373. if (unlikely(pci_dma_mapping_error(pdev, mapping)))
  374. return -ENOMEM;
  375. pci_unmap_addr_set(sd, dma_addr, mapping);
  376. d->addr_lo = cpu_to_be32(mapping);
  377. d->addr_hi = cpu_to_be32((u64) mapping >> 32);
  378. wmb();
  379. d->len_gen = cpu_to_be32(V_FLD_GEN1(gen));
  380. d->gen2 = cpu_to_be32(V_FLD_GEN2(gen));
  381. return 0;
  382. }
  383. static inline int add_one_rx_chunk(dma_addr_t mapping, struct rx_desc *d,
  384. unsigned int gen)
  385. {
  386. d->addr_lo = cpu_to_be32(mapping);
  387. d->addr_hi = cpu_to_be32((u64) mapping >> 32);
  388. wmb();
  389. d->len_gen = cpu_to_be32(V_FLD_GEN1(gen));
  390. d->gen2 = cpu_to_be32(V_FLD_GEN2(gen));
  391. return 0;
  392. }
  393. static int alloc_pg_chunk(struct adapter *adapter, struct sge_fl *q,
  394. struct rx_sw_desc *sd, gfp_t gfp,
  395. unsigned int order)
  396. {
  397. if (!q->pg_chunk.page) {
  398. dma_addr_t mapping;
  399. q->pg_chunk.page = alloc_pages(gfp, order);
  400. if (unlikely(!q->pg_chunk.page))
  401. return -ENOMEM;
  402. q->pg_chunk.va = page_address(q->pg_chunk.page);
  403. q->pg_chunk.p_cnt = q->pg_chunk.va + (PAGE_SIZE << order) -
  404. SGE_PG_RSVD;
  405. q->pg_chunk.offset = 0;
  406. mapping = pci_map_page(adapter->pdev, q->pg_chunk.page,
  407. 0, q->alloc_size, PCI_DMA_FROMDEVICE);
  408. q->pg_chunk.mapping = mapping;
  409. }
  410. sd->pg_chunk = q->pg_chunk;
  411. prefetch(sd->pg_chunk.p_cnt);
  412. q->pg_chunk.offset += q->buf_size;
  413. if (q->pg_chunk.offset == (PAGE_SIZE << order))
  414. q->pg_chunk.page = NULL;
  415. else {
  416. q->pg_chunk.va += q->buf_size;
  417. get_page(q->pg_chunk.page);
  418. }
  419. if (sd->pg_chunk.offset == 0)
  420. *sd->pg_chunk.p_cnt = 1;
  421. else
  422. *sd->pg_chunk.p_cnt += 1;
  423. return 0;
  424. }
  425. static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q)
  426. {
  427. if (q->pend_cred >= q->credits / 4) {
  428. q->pend_cred = 0;
  429. wmb();
  430. t3_write_reg(adap, A_SG_KDOORBELL, V_EGRCNTX(q->cntxt_id));
  431. }
  432. }
  433. /**
  434. * refill_fl - refill an SGE free-buffer list
  435. * @adapter: the adapter
  436. * @q: the free-list to refill
  437. * @n: the number of new buffers to allocate
  438. * @gfp: the gfp flags for allocating new buffers
  439. *
  440. * (Re)populate an SGE free-buffer list with up to @n new packet buffers,
  441. * allocated with the supplied gfp flags. The caller must assure that
  442. * @n does not exceed the queue's capacity.
  443. */
  444. static int refill_fl(struct adapter *adap, struct sge_fl *q, int n, gfp_t gfp)
  445. {
  446. struct rx_sw_desc *sd = &q->sdesc[q->pidx];
  447. struct rx_desc *d = &q->desc[q->pidx];
  448. unsigned int count = 0;
  449. while (n--) {
  450. dma_addr_t mapping;
  451. int err;
  452. if (q->use_pages) {
  453. if (unlikely(alloc_pg_chunk(adap, q, sd, gfp,
  454. q->order))) {
  455. nomem: q->alloc_failed++;
  456. break;
  457. }
  458. mapping = sd->pg_chunk.mapping + sd->pg_chunk.offset;
  459. pci_unmap_addr_set(sd, dma_addr, mapping);
  460. add_one_rx_chunk(mapping, d, q->gen);
  461. pci_dma_sync_single_for_device(adap->pdev, mapping,
  462. q->buf_size - SGE_PG_RSVD,
  463. PCI_DMA_FROMDEVICE);
  464. } else {
  465. void *buf_start;
  466. struct sk_buff *skb = alloc_skb(q->buf_size, gfp);
  467. if (!skb)
  468. goto nomem;
  469. sd->skb = skb;
  470. buf_start = skb->data;
  471. err = add_one_rx_buf(buf_start, q->buf_size, d, sd,
  472. q->gen, adap->pdev);
  473. if (unlikely(err)) {
  474. clear_rx_desc(adap->pdev, q, sd);
  475. break;
  476. }
  477. }
  478. d++;
  479. sd++;
  480. if (++q->pidx == q->size) {
  481. q->pidx = 0;
  482. q->gen ^= 1;
  483. sd = q->sdesc;
  484. d = q->desc;
  485. }
  486. count++;
  487. }
  488. q->credits += count;
  489. q->pend_cred += count;
  490. ring_fl_db(adap, q);
  491. return count;
  492. }
  493. static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl)
  494. {
  495. refill_fl(adap, fl, min(MAX_RX_REFILL, fl->size - fl->credits),
  496. GFP_ATOMIC | __GFP_COMP);
  497. }
  498. /**
  499. * recycle_rx_buf - recycle a receive buffer
  500. * @adapter: the adapter
  501. * @q: the SGE free list
  502. * @idx: index of buffer to recycle
  503. *
  504. * Recycles the specified buffer on the given free list by adding it at
  505. * the next available slot on the list.
  506. */
  507. static void recycle_rx_buf(struct adapter *adap, struct sge_fl *q,
  508. unsigned int idx)
  509. {
  510. struct rx_desc *from = &q->desc[idx];
  511. struct rx_desc *to = &q->desc[q->pidx];
  512. q->sdesc[q->pidx] = q->sdesc[idx];
  513. to->addr_lo = from->addr_lo; /* already big endian */
  514. to->addr_hi = from->addr_hi; /* likewise */
  515. wmb();
  516. to->len_gen = cpu_to_be32(V_FLD_GEN1(q->gen));
  517. to->gen2 = cpu_to_be32(V_FLD_GEN2(q->gen));
  518. if (++q->pidx == q->size) {
  519. q->pidx = 0;
  520. q->gen ^= 1;
  521. }
  522. q->credits++;
  523. q->pend_cred++;
  524. ring_fl_db(adap, q);
  525. }
  526. /**
  527. * alloc_ring - allocate resources for an SGE descriptor ring
  528. * @pdev: the PCI device
  529. * @nelem: the number of descriptors
  530. * @elem_size: the size of each descriptor
  531. * @sw_size: the size of the SW state associated with each ring element
  532. * @phys: the physical address of the allocated ring
  533. * @metadata: address of the array holding the SW state for the ring
  534. *
  535. * Allocates resources for an SGE descriptor ring, such as Tx queues,
  536. * free buffer lists, or response queues. Each SGE ring requires
  537. * space for its HW descriptors plus, optionally, space for the SW state
  538. * associated with each HW entry (the metadata). The function returns
  539. * three values: the virtual address for the HW ring (the return value
  540. * of the function), the physical address of the HW ring, and the address
  541. * of the SW ring.
  542. */
  543. static void *alloc_ring(struct pci_dev *pdev, size_t nelem, size_t elem_size,
  544. size_t sw_size, dma_addr_t * phys, void *metadata)
  545. {
  546. size_t len = nelem * elem_size;
  547. void *s = NULL;
  548. void *p = dma_alloc_coherent(&pdev->dev, len, phys, GFP_KERNEL);
  549. if (!p)
  550. return NULL;
  551. if (sw_size && metadata) {
  552. s = kcalloc(nelem, sw_size, GFP_KERNEL);
  553. if (!s) {
  554. dma_free_coherent(&pdev->dev, len, p, *phys);
  555. return NULL;
  556. }
  557. *(void **)metadata = s;
  558. }
  559. memset(p, 0, len);
  560. return p;
  561. }
  562. /**
  563. * t3_reset_qset - reset a sge qset
  564. * @q: the queue set
  565. *
  566. * Reset the qset structure.
  567. * the NAPI structure is preserved in the event of
  568. * the qset's reincarnation, for example during EEH recovery.
  569. */
  570. static void t3_reset_qset(struct sge_qset *q)
  571. {
  572. if (q->adap &&
  573. !(q->adap->flags & NAPI_INIT)) {
  574. memset(q, 0, sizeof(*q));
  575. return;
  576. }
  577. q->adap = NULL;
  578. memset(&q->rspq, 0, sizeof(q->rspq));
  579. memset(q->fl, 0, sizeof(struct sge_fl) * SGE_RXQ_PER_SET);
  580. memset(q->txq, 0, sizeof(struct sge_txq) * SGE_TXQ_PER_SET);
  581. q->txq_stopped = 0;
  582. q->tx_reclaim_timer.function = NULL; /* for t3_stop_sge_timers() */
  583. q->rx_reclaim_timer.function = NULL;
  584. q->nomem = 0;
  585. napi_free_frags(&q->napi);
  586. }
  587. /**
  588. * free_qset - free the resources of an SGE queue set
  589. * @adapter: the adapter owning the queue set
  590. * @q: the queue set
  591. *
  592. * Release the HW and SW resources associated with an SGE queue set, such
  593. * as HW contexts, packet buffers, and descriptor rings. Traffic to the
  594. * queue set must be quiesced prior to calling this.
  595. */
  596. static void t3_free_qset(struct adapter *adapter, struct sge_qset *q)
  597. {
  598. int i;
  599. struct pci_dev *pdev = adapter->pdev;
  600. for (i = 0; i < SGE_RXQ_PER_SET; ++i)
  601. if (q->fl[i].desc) {
  602. spin_lock_irq(&adapter->sge.reg_lock);
  603. t3_sge_disable_fl(adapter, q->fl[i].cntxt_id);
  604. spin_unlock_irq(&adapter->sge.reg_lock);
  605. free_rx_bufs(pdev, &q->fl[i]);
  606. kfree(q->fl[i].sdesc);
  607. dma_free_coherent(&pdev->dev,
  608. q->fl[i].size *
  609. sizeof(struct rx_desc), q->fl[i].desc,
  610. q->fl[i].phys_addr);
  611. }
  612. for (i = 0; i < SGE_TXQ_PER_SET; ++i)
  613. if (q->txq[i].desc) {
  614. spin_lock_irq(&adapter->sge.reg_lock);
  615. t3_sge_enable_ecntxt(adapter, q->txq[i].cntxt_id, 0);
  616. spin_unlock_irq(&adapter->sge.reg_lock);
  617. if (q->txq[i].sdesc) {
  618. free_tx_desc(adapter, &q->txq[i],
  619. q->txq[i].in_use);
  620. kfree(q->txq[i].sdesc);
  621. }
  622. dma_free_coherent(&pdev->dev,
  623. q->txq[i].size *
  624. sizeof(struct tx_desc),
  625. q->txq[i].desc, q->txq[i].phys_addr);
  626. __skb_queue_purge(&q->txq[i].sendq);
  627. }
  628. if (q->rspq.desc) {
  629. spin_lock_irq(&adapter->sge.reg_lock);
  630. t3_sge_disable_rspcntxt(adapter, q->rspq.cntxt_id);
  631. spin_unlock_irq(&adapter->sge.reg_lock);
  632. dma_free_coherent(&pdev->dev,
  633. q->rspq.size * sizeof(struct rsp_desc),
  634. q->rspq.desc, q->rspq.phys_addr);
  635. }
  636. t3_reset_qset(q);
  637. }
  638. /**
  639. * init_qset_cntxt - initialize an SGE queue set context info
  640. * @qs: the queue set
  641. * @id: the queue set id
  642. *
  643. * Initializes the TIDs and context ids for the queues of a queue set.
  644. */
  645. static void init_qset_cntxt(struct sge_qset *qs, unsigned int id)
  646. {
  647. qs->rspq.cntxt_id = id;
  648. qs->fl[0].cntxt_id = 2 * id;
  649. qs->fl[1].cntxt_id = 2 * id + 1;
  650. qs->txq[TXQ_ETH].cntxt_id = FW_TUNNEL_SGEEC_START + id;
  651. qs->txq[TXQ_ETH].token = FW_TUNNEL_TID_START + id;
  652. qs->txq[TXQ_OFLD].cntxt_id = FW_OFLD_SGEEC_START + id;
  653. qs->txq[TXQ_CTRL].cntxt_id = FW_CTRL_SGEEC_START + id;
  654. qs->txq[TXQ_CTRL].token = FW_CTRL_TID_START + id;
  655. }
  656. /**
  657. * sgl_len - calculates the size of an SGL of the given capacity
  658. * @n: the number of SGL entries
  659. *
  660. * Calculates the number of flits needed for a scatter/gather list that
  661. * can hold the given number of entries.
  662. */
  663. static inline unsigned int sgl_len(unsigned int n)
  664. {
  665. /* alternatively: 3 * (n / 2) + 2 * (n & 1) */
  666. return (3 * n) / 2 + (n & 1);
  667. }
  668. /**
  669. * flits_to_desc - returns the num of Tx descriptors for the given flits
  670. * @n: the number of flits
  671. *
  672. * Calculates the number of Tx descriptors needed for the supplied number
  673. * of flits.
  674. */
  675. static inline unsigned int flits_to_desc(unsigned int n)
  676. {
  677. BUG_ON(n >= ARRAY_SIZE(flit_desc_map));
  678. return flit_desc_map[n];
  679. }
  680. /**
  681. * get_packet - return the next ingress packet buffer from a free list
  682. * @adap: the adapter that received the packet
  683. * @fl: the SGE free list holding the packet
  684. * @len: the packet length including any SGE padding
  685. * @drop_thres: # of remaining buffers before we start dropping packets
  686. *
  687. * Get the next packet from a free list and complete setup of the
  688. * sk_buff. If the packet is small we make a copy and recycle the
  689. * original buffer, otherwise we use the original buffer itself. If a
  690. * positive drop threshold is supplied packets are dropped and their
  691. * buffers recycled if (a) the number of remaining buffers is under the
  692. * threshold and the packet is too big to copy, or (b) the packet should
  693. * be copied but there is no memory for the copy.
  694. */
  695. static struct sk_buff *get_packet(struct adapter *adap, struct sge_fl *fl,
  696. unsigned int len, unsigned int drop_thres)
  697. {
  698. struct sk_buff *skb = NULL;
  699. struct rx_sw_desc *sd = &fl->sdesc[fl->cidx];
  700. prefetch(sd->skb->data);
  701. fl->credits--;
  702. if (len <= SGE_RX_COPY_THRES) {
  703. skb = alloc_skb(len, GFP_ATOMIC);
  704. if (likely(skb != NULL)) {
  705. __skb_put(skb, len);
  706. pci_dma_sync_single_for_cpu(adap->pdev,
  707. pci_unmap_addr(sd, dma_addr), len,
  708. PCI_DMA_FROMDEVICE);
  709. memcpy(skb->data, sd->skb->data, len);
  710. pci_dma_sync_single_for_device(adap->pdev,
  711. pci_unmap_addr(sd, dma_addr), len,
  712. PCI_DMA_FROMDEVICE);
  713. } else if (!drop_thres)
  714. goto use_orig_buf;
  715. recycle:
  716. recycle_rx_buf(adap, fl, fl->cidx);
  717. return skb;
  718. }
  719. if (unlikely(fl->credits < drop_thres) &&
  720. refill_fl(adap, fl, min(MAX_RX_REFILL, fl->size - fl->credits - 1),
  721. GFP_ATOMIC | __GFP_COMP) == 0)
  722. goto recycle;
  723. use_orig_buf:
  724. pci_unmap_single(adap->pdev, pci_unmap_addr(sd, dma_addr),
  725. fl->buf_size, PCI_DMA_FROMDEVICE);
  726. skb = sd->skb;
  727. skb_put(skb, len);
  728. __refill_fl(adap, fl);
  729. return skb;
  730. }
  731. /**
  732. * get_packet_pg - return the next ingress packet buffer from a free list
  733. * @adap: the adapter that received the packet
  734. * @fl: the SGE free list holding the packet
  735. * @len: the packet length including any SGE padding
  736. * @drop_thres: # of remaining buffers before we start dropping packets
  737. *
  738. * Get the next packet from a free list populated with page chunks.
  739. * If the packet is small we make a copy and recycle the original buffer,
  740. * otherwise we attach the original buffer as a page fragment to a fresh
  741. * sk_buff. If a positive drop threshold is supplied packets are dropped
  742. * and their buffers recycled if (a) the number of remaining buffers is
  743. * under the threshold and the packet is too big to copy, or (b) there's
  744. * no system memory.
  745. *
  746. * Note: this function is similar to @get_packet but deals with Rx buffers
  747. * that are page chunks rather than sk_buffs.
  748. */
  749. static struct sk_buff *get_packet_pg(struct adapter *adap, struct sge_fl *fl,
  750. struct sge_rspq *q, unsigned int len,
  751. unsigned int drop_thres)
  752. {
  753. struct sk_buff *newskb, *skb;
  754. struct rx_sw_desc *sd = &fl->sdesc[fl->cidx];
  755. dma_addr_t dma_addr = pci_unmap_addr(sd, dma_addr);
  756. newskb = skb = q->pg_skb;
  757. if (!skb && (len <= SGE_RX_COPY_THRES)) {
  758. newskb = alloc_skb(len, GFP_ATOMIC);
  759. if (likely(newskb != NULL)) {
  760. __skb_put(newskb, len);
  761. pci_dma_sync_single_for_cpu(adap->pdev, dma_addr, len,
  762. PCI_DMA_FROMDEVICE);
  763. memcpy(newskb->data, sd->pg_chunk.va, len);
  764. pci_dma_sync_single_for_device(adap->pdev, dma_addr,
  765. len,
  766. PCI_DMA_FROMDEVICE);
  767. } else if (!drop_thres)
  768. return NULL;
  769. recycle:
  770. fl->credits--;
  771. recycle_rx_buf(adap, fl, fl->cidx);
  772. q->rx_recycle_buf++;
  773. return newskb;
  774. }
  775. if (unlikely(q->rx_recycle_buf || (!skb && fl->credits <= drop_thres)))
  776. goto recycle;
  777. prefetch(sd->pg_chunk.p_cnt);
  778. if (!skb)
  779. newskb = alloc_skb(SGE_RX_PULL_LEN, GFP_ATOMIC);
  780. if (unlikely(!newskb)) {
  781. if (!drop_thres)
  782. return NULL;
  783. goto recycle;
  784. }
  785. pci_dma_sync_single_for_cpu(adap->pdev, dma_addr, len,
  786. PCI_DMA_FROMDEVICE);
  787. (*sd->pg_chunk.p_cnt)--;
  788. if (!*sd->pg_chunk.p_cnt && sd->pg_chunk.page != fl->pg_chunk.page)
  789. pci_unmap_page(adap->pdev,
  790. sd->pg_chunk.mapping,
  791. fl->alloc_size,
  792. PCI_DMA_FROMDEVICE);
  793. if (!skb) {
  794. __skb_put(newskb, SGE_RX_PULL_LEN);
  795. memcpy(newskb->data, sd->pg_chunk.va, SGE_RX_PULL_LEN);
  796. skb_fill_page_desc(newskb, 0, sd->pg_chunk.page,
  797. sd->pg_chunk.offset + SGE_RX_PULL_LEN,
  798. len - SGE_RX_PULL_LEN);
  799. newskb->len = len;
  800. newskb->data_len = len - SGE_RX_PULL_LEN;
  801. newskb->truesize += newskb->data_len;
  802. } else {
  803. skb_fill_page_desc(newskb, skb_shinfo(newskb)->nr_frags,
  804. sd->pg_chunk.page,
  805. sd->pg_chunk.offset, len);
  806. newskb->len += len;
  807. newskb->data_len += len;
  808. newskb->truesize += len;
  809. }
  810. fl->credits--;
  811. /*
  812. * We do not refill FLs here, we let the caller do it to overlap a
  813. * prefetch.
  814. */
  815. return newskb;
  816. }
  817. /**
  818. * get_imm_packet - return the next ingress packet buffer from a response
  819. * @resp: the response descriptor containing the packet data
  820. *
  821. * Return a packet containing the immediate data of the given response.
  822. */
  823. static inline struct sk_buff *get_imm_packet(const struct rsp_desc *resp)
  824. {
  825. struct sk_buff *skb = alloc_skb(IMMED_PKT_SIZE, GFP_ATOMIC);
  826. if (skb) {
  827. __skb_put(skb, IMMED_PKT_SIZE);
  828. skb_copy_to_linear_data(skb, resp->imm_data, IMMED_PKT_SIZE);
  829. }
  830. return skb;
  831. }
  832. /**
  833. * calc_tx_descs - calculate the number of Tx descriptors for a packet
  834. * @skb: the packet
  835. *
  836. * Returns the number of Tx descriptors needed for the given Ethernet
  837. * packet. Ethernet packets require addition of WR and CPL headers.
  838. */
  839. static inline unsigned int calc_tx_descs(const struct sk_buff *skb)
  840. {
  841. unsigned int flits;
  842. if (skb->len <= WR_LEN - sizeof(struct cpl_tx_pkt))
  843. return 1;
  844. flits = sgl_len(skb_shinfo(skb)->nr_frags + 1) + 2;
  845. if (skb_shinfo(skb)->gso_size)
  846. flits++;
  847. return flits_to_desc(flits);
  848. }
  849. /**
  850. * make_sgl - populate a scatter/gather list for a packet
  851. * @skb: the packet
  852. * @sgp: the SGL to populate
  853. * @start: start address of skb main body data to include in the SGL
  854. * @len: length of skb main body data to include in the SGL
  855. * @pdev: the PCI device
  856. *
  857. * Generates a scatter/gather list for the buffers that make up a packet
  858. * and returns the SGL size in 8-byte words. The caller must size the SGL
  859. * appropriately.
  860. */
  861. static inline unsigned int make_sgl(const struct sk_buff *skb,
  862. struct sg_ent *sgp, unsigned char *start,
  863. unsigned int len, struct pci_dev *pdev)
  864. {
  865. dma_addr_t mapping;
  866. unsigned int i, j = 0, nfrags;
  867. if (len) {
  868. mapping = pci_map_single(pdev, start, len, PCI_DMA_TODEVICE);
  869. sgp->len[0] = cpu_to_be32(len);
  870. sgp->addr[0] = cpu_to_be64(mapping);
  871. j = 1;
  872. }
  873. nfrags = skb_shinfo(skb)->nr_frags;
  874. for (i = 0; i < nfrags; i++) {
  875. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  876. mapping = pci_map_page(pdev, frag->page, frag->page_offset,
  877. frag->size, PCI_DMA_TODEVICE);
  878. sgp->len[j] = cpu_to_be32(frag->size);
  879. sgp->addr[j] = cpu_to_be64(mapping);
  880. j ^= 1;
  881. if (j == 0)
  882. ++sgp;
  883. }
  884. if (j)
  885. sgp->len[j] = 0;
  886. return ((nfrags + (len != 0)) * 3) / 2 + j;
  887. }
  888. /**
  889. * check_ring_tx_db - check and potentially ring a Tx queue's doorbell
  890. * @adap: the adapter
  891. * @q: the Tx queue
  892. *
  893. * Ring the doorbel if a Tx queue is asleep. There is a natural race,
  894. * where the HW is going to sleep just after we checked, however,
  895. * then the interrupt handler will detect the outstanding TX packet
  896. * and ring the doorbell for us.
  897. *
  898. * When GTS is disabled we unconditionally ring the doorbell.
  899. */
  900. static inline void check_ring_tx_db(struct adapter *adap, struct sge_txq *q)
  901. {
  902. #if USE_GTS
  903. clear_bit(TXQ_LAST_PKT_DB, &q->flags);
  904. if (test_and_set_bit(TXQ_RUNNING, &q->flags) == 0) {
  905. set_bit(TXQ_LAST_PKT_DB, &q->flags);
  906. t3_write_reg(adap, A_SG_KDOORBELL,
  907. F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
  908. }
  909. #else
  910. wmb(); /* write descriptors before telling HW */
  911. t3_write_reg(adap, A_SG_KDOORBELL,
  912. F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
  913. #endif
  914. }
  915. static inline void wr_gen2(struct tx_desc *d, unsigned int gen)
  916. {
  917. #if SGE_NUM_GENBITS == 2
  918. d->flit[TX_DESC_FLITS - 1] = cpu_to_be64(gen);
  919. #endif
  920. }
  921. /**
  922. * write_wr_hdr_sgl - write a WR header and, optionally, SGL
  923. * @ndesc: number of Tx descriptors spanned by the SGL
  924. * @skb: the packet corresponding to the WR
  925. * @d: first Tx descriptor to be written
  926. * @pidx: index of above descriptors
  927. * @q: the SGE Tx queue
  928. * @sgl: the SGL
  929. * @flits: number of flits to the start of the SGL in the first descriptor
  930. * @sgl_flits: the SGL size in flits
  931. * @gen: the Tx descriptor generation
  932. * @wr_hi: top 32 bits of WR header based on WR type (big endian)
  933. * @wr_lo: low 32 bits of WR header based on WR type (big endian)
  934. *
  935. * Write a work request header and an associated SGL. If the SGL is
  936. * small enough to fit into one Tx descriptor it has already been written
  937. * and we just need to write the WR header. Otherwise we distribute the
  938. * SGL across the number of descriptors it spans.
  939. */
  940. static void write_wr_hdr_sgl(unsigned int ndesc, struct sk_buff *skb,
  941. struct tx_desc *d, unsigned int pidx,
  942. const struct sge_txq *q,
  943. const struct sg_ent *sgl,
  944. unsigned int flits, unsigned int sgl_flits,
  945. unsigned int gen, __be32 wr_hi,
  946. __be32 wr_lo)
  947. {
  948. struct work_request_hdr *wrp = (struct work_request_hdr *)d;
  949. struct tx_sw_desc *sd = &q->sdesc[pidx];
  950. sd->skb = skb;
  951. if (need_skb_unmap()) {
  952. sd->fragidx = 0;
  953. sd->addr_idx = 0;
  954. sd->sflit = flits;
  955. }
  956. if (likely(ndesc == 1)) {
  957. sd->eop = 1;
  958. wrp->wr_hi = htonl(F_WR_SOP | F_WR_EOP | V_WR_DATATYPE(1) |
  959. V_WR_SGLSFLT(flits)) | wr_hi;
  960. wmb();
  961. wrp->wr_lo = htonl(V_WR_LEN(flits + sgl_flits) |
  962. V_WR_GEN(gen)) | wr_lo;
  963. wr_gen2(d, gen);
  964. } else {
  965. unsigned int ogen = gen;
  966. const u64 *fp = (const u64 *)sgl;
  967. struct work_request_hdr *wp = wrp;
  968. wrp->wr_hi = htonl(F_WR_SOP | V_WR_DATATYPE(1) |
  969. V_WR_SGLSFLT(flits)) | wr_hi;
  970. while (sgl_flits) {
  971. unsigned int avail = WR_FLITS - flits;
  972. if (avail > sgl_flits)
  973. avail = sgl_flits;
  974. memcpy(&d->flit[flits], fp, avail * sizeof(*fp));
  975. sgl_flits -= avail;
  976. ndesc--;
  977. if (!sgl_flits)
  978. break;
  979. fp += avail;
  980. d++;
  981. sd->eop = 0;
  982. sd++;
  983. if (++pidx == q->size) {
  984. pidx = 0;
  985. gen ^= 1;
  986. d = q->desc;
  987. sd = q->sdesc;
  988. }
  989. sd->skb = skb;
  990. wrp = (struct work_request_hdr *)d;
  991. wrp->wr_hi = htonl(V_WR_DATATYPE(1) |
  992. V_WR_SGLSFLT(1)) | wr_hi;
  993. wrp->wr_lo = htonl(V_WR_LEN(min(WR_FLITS,
  994. sgl_flits + 1)) |
  995. V_WR_GEN(gen)) | wr_lo;
  996. wr_gen2(d, gen);
  997. flits = 1;
  998. }
  999. sd->eop = 1;
  1000. wrp->wr_hi |= htonl(F_WR_EOP);
  1001. wmb();
  1002. wp->wr_lo = htonl(V_WR_LEN(WR_FLITS) | V_WR_GEN(ogen)) | wr_lo;
  1003. wr_gen2((struct tx_desc *)wp, ogen);
  1004. WARN_ON(ndesc != 0);
  1005. }
  1006. }
  1007. /**
  1008. * write_tx_pkt_wr - write a TX_PKT work request
  1009. * @adap: the adapter
  1010. * @skb: the packet to send
  1011. * @pi: the egress interface
  1012. * @pidx: index of the first Tx descriptor to write
  1013. * @gen: the generation value to use
  1014. * @q: the Tx queue
  1015. * @ndesc: number of descriptors the packet will occupy
  1016. * @compl: the value of the COMPL bit to use
  1017. *
  1018. * Generate a TX_PKT work request to send the supplied packet.
  1019. */
  1020. static void write_tx_pkt_wr(struct adapter *adap, struct sk_buff *skb,
  1021. const struct port_info *pi,
  1022. unsigned int pidx, unsigned int gen,
  1023. struct sge_txq *q, unsigned int ndesc,
  1024. unsigned int compl)
  1025. {
  1026. unsigned int flits, sgl_flits, cntrl, tso_info;
  1027. struct sg_ent *sgp, sgl[MAX_SKB_FRAGS / 2 + 1];
  1028. struct tx_desc *d = &q->desc[pidx];
  1029. struct cpl_tx_pkt *cpl = (struct cpl_tx_pkt *)d;
  1030. cpl->len = htonl(skb->len);
  1031. cntrl = V_TXPKT_INTF(pi->port_id);
  1032. if (vlan_tx_tag_present(skb) && pi->vlan_grp)
  1033. cntrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(vlan_tx_tag_get(skb));
  1034. tso_info = V_LSO_MSS(skb_shinfo(skb)->gso_size);
  1035. if (tso_info) {
  1036. int eth_type;
  1037. struct cpl_tx_pkt_lso *hdr = (struct cpl_tx_pkt_lso *)cpl;
  1038. d->flit[2] = 0;
  1039. cntrl |= V_TXPKT_OPCODE(CPL_TX_PKT_LSO);
  1040. hdr->cntrl = htonl(cntrl);
  1041. eth_type = skb_network_offset(skb) == ETH_HLEN ?
  1042. CPL_ETH_II : CPL_ETH_II_VLAN;
  1043. tso_info |= V_LSO_ETH_TYPE(eth_type) |
  1044. V_LSO_IPHDR_WORDS(ip_hdr(skb)->ihl) |
  1045. V_LSO_TCPHDR_WORDS(tcp_hdr(skb)->doff);
  1046. hdr->lso_info = htonl(tso_info);
  1047. flits = 3;
  1048. } else {
  1049. cntrl |= V_TXPKT_OPCODE(CPL_TX_PKT);
  1050. cntrl |= F_TXPKT_IPCSUM_DIS; /* SW calculates IP csum */
  1051. cntrl |= V_TXPKT_L4CSUM_DIS(skb->ip_summed != CHECKSUM_PARTIAL);
  1052. cpl->cntrl = htonl(cntrl);
  1053. if (skb->len <= WR_LEN - sizeof(*cpl)) {
  1054. q->sdesc[pidx].skb = NULL;
  1055. if (!skb->data_len)
  1056. skb_copy_from_linear_data(skb, &d->flit[2],
  1057. skb->len);
  1058. else
  1059. skb_copy_bits(skb, 0, &d->flit[2], skb->len);
  1060. flits = (skb->len + 7) / 8 + 2;
  1061. cpl->wr.wr_hi = htonl(V_WR_BCNTLFLT(skb->len & 7) |
  1062. V_WR_OP(FW_WROPCODE_TUNNEL_TX_PKT)
  1063. | F_WR_SOP | F_WR_EOP | compl);
  1064. wmb();
  1065. cpl->wr.wr_lo = htonl(V_WR_LEN(flits) | V_WR_GEN(gen) |
  1066. V_WR_TID(q->token));
  1067. wr_gen2(d, gen);
  1068. kfree_skb(skb);
  1069. return;
  1070. }
  1071. flits = 2;
  1072. }
  1073. sgp = ndesc == 1 ? (struct sg_ent *)&d->flit[flits] : sgl;
  1074. sgl_flits = make_sgl(skb, sgp, skb->data, skb_headlen(skb), adap->pdev);
  1075. write_wr_hdr_sgl(ndesc, skb, d, pidx, q, sgl, flits, sgl_flits, gen,
  1076. htonl(V_WR_OP(FW_WROPCODE_TUNNEL_TX_PKT) | compl),
  1077. htonl(V_WR_TID(q->token)));
  1078. }
  1079. static inline void t3_stop_tx_queue(struct netdev_queue *txq,
  1080. struct sge_qset *qs, struct sge_txq *q)
  1081. {
  1082. netif_tx_stop_queue(txq);
  1083. set_bit(TXQ_ETH, &qs->txq_stopped);
  1084. q->stops++;
  1085. }
  1086. /**
  1087. * eth_xmit - add a packet to the Ethernet Tx queue
  1088. * @skb: the packet
  1089. * @dev: the egress net device
  1090. *
  1091. * Add a packet to an SGE Tx queue. Runs with softirqs disabled.
  1092. */
  1093. netdev_tx_t t3_eth_xmit(struct sk_buff *skb, struct net_device *dev)
  1094. {
  1095. int qidx;
  1096. unsigned int ndesc, pidx, credits, gen, compl;
  1097. const struct port_info *pi = netdev_priv(dev);
  1098. struct adapter *adap = pi->adapter;
  1099. struct netdev_queue *txq;
  1100. struct sge_qset *qs;
  1101. struct sge_txq *q;
  1102. /*
  1103. * The chip min packet length is 9 octets but play safe and reject
  1104. * anything shorter than an Ethernet header.
  1105. */
  1106. if (unlikely(skb->len < ETH_HLEN)) {
  1107. dev_kfree_skb(skb);
  1108. return NETDEV_TX_OK;
  1109. }
  1110. qidx = skb_get_queue_mapping(skb);
  1111. qs = &pi->qs[qidx];
  1112. q = &qs->txq[TXQ_ETH];
  1113. txq = netdev_get_tx_queue(dev, qidx);
  1114. reclaim_completed_tx(adap, q, TX_RECLAIM_CHUNK);
  1115. credits = q->size - q->in_use;
  1116. ndesc = calc_tx_descs(skb);
  1117. if (unlikely(credits < ndesc)) {
  1118. t3_stop_tx_queue(txq, qs, q);
  1119. dev_err(&adap->pdev->dev,
  1120. "%s: Tx ring %u full while queue awake!\n",
  1121. dev->name, q->cntxt_id & 7);
  1122. return NETDEV_TX_BUSY;
  1123. }
  1124. q->in_use += ndesc;
  1125. if (unlikely(credits - ndesc < q->stop_thres)) {
  1126. t3_stop_tx_queue(txq, qs, q);
  1127. if (should_restart_tx(q) &&
  1128. test_and_clear_bit(TXQ_ETH, &qs->txq_stopped)) {
  1129. q->restarts++;
  1130. netif_tx_start_queue(txq);
  1131. }
  1132. }
  1133. gen = q->gen;
  1134. q->unacked += ndesc;
  1135. compl = (q->unacked & 8) << (S_WR_COMPL - 3);
  1136. q->unacked &= 7;
  1137. pidx = q->pidx;
  1138. q->pidx += ndesc;
  1139. if (q->pidx >= q->size) {
  1140. q->pidx -= q->size;
  1141. q->gen ^= 1;
  1142. }
  1143. /* update port statistics */
  1144. if (skb->ip_summed == CHECKSUM_COMPLETE)
  1145. qs->port_stats[SGE_PSTAT_TX_CSUM]++;
  1146. if (skb_shinfo(skb)->gso_size)
  1147. qs->port_stats[SGE_PSTAT_TSO]++;
  1148. if (vlan_tx_tag_present(skb) && pi->vlan_grp)
  1149. qs->port_stats[SGE_PSTAT_VLANINS]++;
  1150. /*
  1151. * We do not use Tx completion interrupts to free DMAd Tx packets.
  1152. * This is good for performance but means that we rely on new Tx
  1153. * packets arriving to run the destructors of completed packets,
  1154. * which open up space in their sockets' send queues. Sometimes
  1155. * we do not get such new packets causing Tx to stall. A single
  1156. * UDP transmitter is a good example of this situation. We have
  1157. * a clean up timer that periodically reclaims completed packets
  1158. * but it doesn't run often enough (nor do we want it to) to prevent
  1159. * lengthy stalls. A solution to this problem is to run the
  1160. * destructor early, after the packet is queued but before it's DMAd.
  1161. * A cons is that we lie to socket memory accounting, but the amount
  1162. * of extra memory is reasonable (limited by the number of Tx
  1163. * descriptors), the packets do actually get freed quickly by new
  1164. * packets almost always, and for protocols like TCP that wait for
  1165. * acks to really free up the data the extra memory is even less.
  1166. * On the positive side we run the destructors on the sending CPU
  1167. * rather than on a potentially different completing CPU, usually a
  1168. * good thing. We also run them without holding our Tx queue lock,
  1169. * unlike what reclaim_completed_tx() would otherwise do.
  1170. *
  1171. * Run the destructor before telling the DMA engine about the packet
  1172. * to make sure it doesn't complete and get freed prematurely.
  1173. */
  1174. if (likely(!skb_shared(skb)))
  1175. skb_orphan(skb);
  1176. write_tx_pkt_wr(adap, skb, pi, pidx, gen, q, ndesc, compl);
  1177. check_ring_tx_db(adap, q);
  1178. return NETDEV_TX_OK;
  1179. }
  1180. /**
  1181. * write_imm - write a packet into a Tx descriptor as immediate data
  1182. * @d: the Tx descriptor to write
  1183. * @skb: the packet
  1184. * @len: the length of packet data to write as immediate data
  1185. * @gen: the generation bit value to write
  1186. *
  1187. * Writes a packet as immediate data into a Tx descriptor. The packet
  1188. * contains a work request at its beginning. We must write the packet
  1189. * carefully so the SGE doesn't read it accidentally before it's written
  1190. * in its entirety.
  1191. */
  1192. static inline void write_imm(struct tx_desc *d, struct sk_buff *skb,
  1193. unsigned int len, unsigned int gen)
  1194. {
  1195. struct work_request_hdr *from = (struct work_request_hdr *)skb->data;
  1196. struct work_request_hdr *to = (struct work_request_hdr *)d;
  1197. if (likely(!skb->data_len))
  1198. memcpy(&to[1], &from[1], len - sizeof(*from));
  1199. else
  1200. skb_copy_bits(skb, sizeof(*from), &to[1], len - sizeof(*from));
  1201. to->wr_hi = from->wr_hi | htonl(F_WR_SOP | F_WR_EOP |
  1202. V_WR_BCNTLFLT(len & 7));
  1203. wmb();
  1204. to->wr_lo = from->wr_lo | htonl(V_WR_GEN(gen) |
  1205. V_WR_LEN((len + 7) / 8));
  1206. wr_gen2(d, gen);
  1207. kfree_skb(skb);
  1208. }
  1209. /**
  1210. * check_desc_avail - check descriptor availability on a send queue
  1211. * @adap: the adapter
  1212. * @q: the send queue
  1213. * @skb: the packet needing the descriptors
  1214. * @ndesc: the number of Tx descriptors needed
  1215. * @qid: the Tx queue number in its queue set (TXQ_OFLD or TXQ_CTRL)
  1216. *
  1217. * Checks if the requested number of Tx descriptors is available on an
  1218. * SGE send queue. If the queue is already suspended or not enough
  1219. * descriptors are available the packet is queued for later transmission.
  1220. * Must be called with the Tx queue locked.
  1221. *
  1222. * Returns 0 if enough descriptors are available, 1 if there aren't
  1223. * enough descriptors and the packet has been queued, and 2 if the caller
  1224. * needs to retry because there weren't enough descriptors at the
  1225. * beginning of the call but some freed up in the mean time.
  1226. */
  1227. static inline int check_desc_avail(struct adapter *adap, struct sge_txq *q,
  1228. struct sk_buff *skb, unsigned int ndesc,
  1229. unsigned int qid)
  1230. {
  1231. if (unlikely(!skb_queue_empty(&q->sendq))) {
  1232. addq_exit:__skb_queue_tail(&q->sendq, skb);
  1233. return 1;
  1234. }
  1235. if (unlikely(q->size - q->in_use < ndesc)) {
  1236. struct sge_qset *qs = txq_to_qset(q, qid);
  1237. set_bit(qid, &qs->txq_stopped);
  1238. smp_mb__after_clear_bit();
  1239. if (should_restart_tx(q) &&
  1240. test_and_clear_bit(qid, &qs->txq_stopped))
  1241. return 2;
  1242. q->stops++;
  1243. goto addq_exit;
  1244. }
  1245. return 0;
  1246. }
  1247. /**
  1248. * reclaim_completed_tx_imm - reclaim completed control-queue Tx descs
  1249. * @q: the SGE control Tx queue
  1250. *
  1251. * This is a variant of reclaim_completed_tx() that is used for Tx queues
  1252. * that send only immediate data (presently just the control queues) and
  1253. * thus do not have any sk_buffs to release.
  1254. */
  1255. static inline void reclaim_completed_tx_imm(struct sge_txq *q)
  1256. {
  1257. unsigned int reclaim = q->processed - q->cleaned;
  1258. q->in_use -= reclaim;
  1259. q->cleaned += reclaim;
  1260. }
  1261. static inline int immediate(const struct sk_buff *skb)
  1262. {
  1263. return skb->len <= WR_LEN;
  1264. }
  1265. /**
  1266. * ctrl_xmit - send a packet through an SGE control Tx queue
  1267. * @adap: the adapter
  1268. * @q: the control queue
  1269. * @skb: the packet
  1270. *
  1271. * Send a packet through an SGE control Tx queue. Packets sent through
  1272. * a control queue must fit entirely as immediate data in a single Tx
  1273. * descriptor and have no page fragments.
  1274. */
  1275. static int ctrl_xmit(struct adapter *adap, struct sge_txq *q,
  1276. struct sk_buff *skb)
  1277. {
  1278. int ret;
  1279. struct work_request_hdr *wrp = (struct work_request_hdr *)skb->data;
  1280. if (unlikely(!immediate(skb))) {
  1281. WARN_ON(1);
  1282. dev_kfree_skb(skb);
  1283. return NET_XMIT_SUCCESS;
  1284. }
  1285. wrp->wr_hi |= htonl(F_WR_SOP | F_WR_EOP);
  1286. wrp->wr_lo = htonl(V_WR_TID(q->token));
  1287. spin_lock(&q->lock);
  1288. again:reclaim_completed_tx_imm(q);
  1289. ret = check_desc_avail(adap, q, skb, 1, TXQ_CTRL);
  1290. if (unlikely(ret)) {
  1291. if (ret == 1) {
  1292. spin_unlock(&q->lock);
  1293. return NET_XMIT_CN;
  1294. }
  1295. goto again;
  1296. }
  1297. write_imm(&q->desc[q->pidx], skb, skb->len, q->gen);
  1298. q->in_use++;
  1299. if (++q->pidx >= q->size) {
  1300. q->pidx = 0;
  1301. q->gen ^= 1;
  1302. }
  1303. spin_unlock(&q->lock);
  1304. wmb();
  1305. t3_write_reg(adap, A_SG_KDOORBELL,
  1306. F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
  1307. return NET_XMIT_SUCCESS;
  1308. }
  1309. /**
  1310. * restart_ctrlq - restart a suspended control queue
  1311. * @qs: the queue set cotaining the control queue
  1312. *
  1313. * Resumes transmission on a suspended Tx control queue.
  1314. */
  1315. static void restart_ctrlq(unsigned long data)
  1316. {
  1317. struct sk_buff *skb;
  1318. struct sge_qset *qs = (struct sge_qset *)data;
  1319. struct sge_txq *q = &qs->txq[TXQ_CTRL];
  1320. spin_lock(&q->lock);
  1321. again:reclaim_completed_tx_imm(q);
  1322. while (q->in_use < q->size &&
  1323. (skb = __skb_dequeue(&q->sendq)) != NULL) {
  1324. write_imm(&q->desc[q->pidx], skb, skb->len, q->gen);
  1325. if (++q->pidx >= q->size) {
  1326. q->pidx = 0;
  1327. q->gen ^= 1;
  1328. }
  1329. q->in_use++;
  1330. }
  1331. if (!skb_queue_empty(&q->sendq)) {
  1332. set_bit(TXQ_CTRL, &qs->txq_stopped);
  1333. smp_mb__after_clear_bit();
  1334. if (should_restart_tx(q) &&
  1335. test_and_clear_bit(TXQ_CTRL, &qs->txq_stopped))
  1336. goto again;
  1337. q->stops++;
  1338. }
  1339. spin_unlock(&q->lock);
  1340. wmb();
  1341. t3_write_reg(qs->adap, A_SG_KDOORBELL,
  1342. F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
  1343. }
  1344. /*
  1345. * Send a management message through control queue 0
  1346. */
  1347. int t3_mgmt_tx(struct adapter *adap, struct sk_buff *skb)
  1348. {
  1349. int ret;
  1350. local_bh_disable();
  1351. ret = ctrl_xmit(adap, &adap->sge.qs[0].txq[TXQ_CTRL], skb);
  1352. local_bh_enable();
  1353. return ret;
  1354. }
  1355. /**
  1356. * deferred_unmap_destructor - unmap a packet when it is freed
  1357. * @skb: the packet
  1358. *
  1359. * This is the packet destructor used for Tx packets that need to remain
  1360. * mapped until they are freed rather than until their Tx descriptors are
  1361. * freed.
  1362. */
  1363. static void deferred_unmap_destructor(struct sk_buff *skb)
  1364. {
  1365. int i;
  1366. const dma_addr_t *p;
  1367. const struct skb_shared_info *si;
  1368. const struct deferred_unmap_info *dui;
  1369. dui = (struct deferred_unmap_info *)skb->head;
  1370. p = dui->addr;
  1371. if (skb->tail - skb->transport_header)
  1372. pci_unmap_single(dui->pdev, *p++,
  1373. skb->tail - skb->transport_header,
  1374. PCI_DMA_TODEVICE);
  1375. si = skb_shinfo(skb);
  1376. for (i = 0; i < si->nr_frags; i++)
  1377. pci_unmap_page(dui->pdev, *p++, si->frags[i].size,
  1378. PCI_DMA_TODEVICE);
  1379. }
  1380. static void setup_deferred_unmapping(struct sk_buff *skb, struct pci_dev *pdev,
  1381. const struct sg_ent *sgl, int sgl_flits)
  1382. {
  1383. dma_addr_t *p;
  1384. struct deferred_unmap_info *dui;
  1385. dui = (struct deferred_unmap_info *)skb->head;
  1386. dui->pdev = pdev;
  1387. for (p = dui->addr; sgl_flits >= 3; sgl++, sgl_flits -= 3) {
  1388. *p++ = be64_to_cpu(sgl->addr[0]);
  1389. *p++ = be64_to_cpu(sgl->addr[1]);
  1390. }
  1391. if (sgl_flits)
  1392. *p = be64_to_cpu(sgl->addr[0]);
  1393. }
  1394. /**
  1395. * write_ofld_wr - write an offload work request
  1396. * @adap: the adapter
  1397. * @skb: the packet to send
  1398. * @q: the Tx queue
  1399. * @pidx: index of the first Tx descriptor to write
  1400. * @gen: the generation value to use
  1401. * @ndesc: number of descriptors the packet will occupy
  1402. *
  1403. * Write an offload work request to send the supplied packet. The packet
  1404. * data already carry the work request with most fields populated.
  1405. */
  1406. static void write_ofld_wr(struct adapter *adap, struct sk_buff *skb,
  1407. struct sge_txq *q, unsigned int pidx,
  1408. unsigned int gen, unsigned int ndesc)
  1409. {
  1410. unsigned int sgl_flits, flits;
  1411. struct work_request_hdr *from;
  1412. struct sg_ent *sgp, sgl[MAX_SKB_FRAGS / 2 + 1];
  1413. struct tx_desc *d = &q->desc[pidx];
  1414. if (immediate(skb)) {
  1415. q->sdesc[pidx].skb = NULL;
  1416. write_imm(d, skb, skb->len, gen);
  1417. return;
  1418. }
  1419. /* Only TX_DATA builds SGLs */
  1420. from = (struct work_request_hdr *)skb->data;
  1421. memcpy(&d->flit[1], &from[1],
  1422. skb_transport_offset(skb) - sizeof(*from));
  1423. flits = skb_transport_offset(skb) / 8;
  1424. sgp = ndesc == 1 ? (struct sg_ent *)&d->flit[flits] : sgl;
  1425. sgl_flits = make_sgl(skb, sgp, skb_transport_header(skb),
  1426. skb->tail - skb->transport_header,
  1427. adap->pdev);
  1428. if (need_skb_unmap()) {
  1429. setup_deferred_unmapping(skb, adap->pdev, sgp, sgl_flits);
  1430. skb->destructor = deferred_unmap_destructor;
  1431. }
  1432. write_wr_hdr_sgl(ndesc, skb, d, pidx, q, sgl, flits, sgl_flits,
  1433. gen, from->wr_hi, from->wr_lo);
  1434. }
  1435. /**
  1436. * calc_tx_descs_ofld - calculate # of Tx descriptors for an offload packet
  1437. * @skb: the packet
  1438. *
  1439. * Returns the number of Tx descriptors needed for the given offload
  1440. * packet. These packets are already fully constructed.
  1441. */
  1442. static inline unsigned int calc_tx_descs_ofld(const struct sk_buff *skb)
  1443. {
  1444. unsigned int flits, cnt;
  1445. if (skb->len <= WR_LEN)
  1446. return 1; /* packet fits as immediate data */
  1447. flits = skb_transport_offset(skb) / 8; /* headers */
  1448. cnt = skb_shinfo(skb)->nr_frags;
  1449. if (skb->tail != skb->transport_header)
  1450. cnt++;
  1451. return flits_to_desc(flits + sgl_len(cnt));
  1452. }
  1453. /**
  1454. * ofld_xmit - send a packet through an offload queue
  1455. * @adap: the adapter
  1456. * @q: the Tx offload queue
  1457. * @skb: the packet
  1458. *
  1459. * Send an offload packet through an SGE offload queue.
  1460. */
  1461. static int ofld_xmit(struct adapter *adap, struct sge_txq *q,
  1462. struct sk_buff *skb)
  1463. {
  1464. int ret;
  1465. unsigned int ndesc = calc_tx_descs_ofld(skb), pidx, gen;
  1466. spin_lock(&q->lock);
  1467. again: reclaim_completed_tx(adap, q, TX_RECLAIM_CHUNK);
  1468. ret = check_desc_avail(adap, q, skb, ndesc, TXQ_OFLD);
  1469. if (unlikely(ret)) {
  1470. if (ret == 1) {
  1471. skb->priority = ndesc; /* save for restart */
  1472. spin_unlock(&q->lock);
  1473. return NET_XMIT_CN;
  1474. }
  1475. goto again;
  1476. }
  1477. gen = q->gen;
  1478. q->in_use += ndesc;
  1479. pidx = q->pidx;
  1480. q->pidx += ndesc;
  1481. if (q->pidx >= q->size) {
  1482. q->pidx -= q->size;
  1483. q->gen ^= 1;
  1484. }
  1485. spin_unlock(&q->lock);
  1486. write_ofld_wr(adap, skb, q, pidx, gen, ndesc);
  1487. check_ring_tx_db(adap, q);
  1488. return NET_XMIT_SUCCESS;
  1489. }
  1490. /**
  1491. * restart_offloadq - restart a suspended offload queue
  1492. * @qs: the queue set cotaining the offload queue
  1493. *
  1494. * Resumes transmission on a suspended Tx offload queue.
  1495. */
  1496. static void restart_offloadq(unsigned long data)
  1497. {
  1498. struct sk_buff *skb;
  1499. struct sge_qset *qs = (struct sge_qset *)data;
  1500. struct sge_txq *q = &qs->txq[TXQ_OFLD];
  1501. const struct port_info *pi = netdev_priv(qs->netdev);
  1502. struct adapter *adap = pi->adapter;
  1503. spin_lock(&q->lock);
  1504. again: reclaim_completed_tx(adap, q, TX_RECLAIM_CHUNK);
  1505. while ((skb = skb_peek(&q->sendq)) != NULL) {
  1506. unsigned int gen, pidx;
  1507. unsigned int ndesc = skb->priority;
  1508. if (unlikely(q->size - q->in_use < ndesc)) {
  1509. set_bit(TXQ_OFLD, &qs->txq_stopped);
  1510. smp_mb__after_clear_bit();
  1511. if (should_restart_tx(q) &&
  1512. test_and_clear_bit(TXQ_OFLD, &qs->txq_stopped))
  1513. goto again;
  1514. q->stops++;
  1515. break;
  1516. }
  1517. gen = q->gen;
  1518. q->in_use += ndesc;
  1519. pidx = q->pidx;
  1520. q->pidx += ndesc;
  1521. if (q->pidx >= q->size) {
  1522. q->pidx -= q->size;
  1523. q->gen ^= 1;
  1524. }
  1525. __skb_unlink(skb, &q->sendq);
  1526. spin_unlock(&q->lock);
  1527. write_ofld_wr(adap, skb, q, pidx, gen, ndesc);
  1528. spin_lock(&q->lock);
  1529. }
  1530. spin_unlock(&q->lock);
  1531. #if USE_GTS
  1532. set_bit(TXQ_RUNNING, &q->flags);
  1533. set_bit(TXQ_LAST_PKT_DB, &q->flags);
  1534. #endif
  1535. wmb();
  1536. t3_write_reg(adap, A_SG_KDOORBELL,
  1537. F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
  1538. }
  1539. /**
  1540. * queue_set - return the queue set a packet should use
  1541. * @skb: the packet
  1542. *
  1543. * Maps a packet to the SGE queue set it should use. The desired queue
  1544. * set is carried in bits 1-3 in the packet's priority.
  1545. */
  1546. static inline int queue_set(const struct sk_buff *skb)
  1547. {
  1548. return skb->priority >> 1;
  1549. }
  1550. /**
  1551. * is_ctrl_pkt - return whether an offload packet is a control packet
  1552. * @skb: the packet
  1553. *
  1554. * Determines whether an offload packet should use an OFLD or a CTRL
  1555. * Tx queue. This is indicated by bit 0 in the packet's priority.
  1556. */
  1557. static inline int is_ctrl_pkt(const struct sk_buff *skb)
  1558. {
  1559. return skb->priority & 1;
  1560. }
  1561. /**
  1562. * t3_offload_tx - send an offload packet
  1563. * @tdev: the offload device to send to
  1564. * @skb: the packet
  1565. *
  1566. * Sends an offload packet. We use the packet priority to select the
  1567. * appropriate Tx queue as follows: bit 0 indicates whether the packet
  1568. * should be sent as regular or control, bits 1-3 select the queue set.
  1569. */
  1570. int t3_offload_tx(struct t3cdev *tdev, struct sk_buff *skb)
  1571. {
  1572. struct adapter *adap = tdev2adap(tdev);
  1573. struct sge_qset *qs = &adap->sge.qs[queue_set(skb)];
  1574. if (unlikely(is_ctrl_pkt(skb)))
  1575. return ctrl_xmit(adap, &qs->txq[TXQ_CTRL], skb);
  1576. return ofld_xmit(adap, &qs->txq[TXQ_OFLD], skb);
  1577. }
  1578. /**
  1579. * offload_enqueue - add an offload packet to an SGE offload receive queue
  1580. * @q: the SGE response queue
  1581. * @skb: the packet
  1582. *
  1583. * Add a new offload packet to an SGE response queue's offload packet
  1584. * queue. If the packet is the first on the queue it schedules the RX
  1585. * softirq to process the queue.
  1586. */
  1587. static inline void offload_enqueue(struct sge_rspq *q, struct sk_buff *skb)
  1588. {
  1589. int was_empty = skb_queue_empty(&q->rx_queue);
  1590. __skb_queue_tail(&q->rx_queue, skb);
  1591. if (was_empty) {
  1592. struct sge_qset *qs = rspq_to_qset(q);
  1593. napi_schedule(&qs->napi);
  1594. }
  1595. }
  1596. /**
  1597. * deliver_partial_bundle - deliver a (partial) bundle of Rx offload pkts
  1598. * @tdev: the offload device that will be receiving the packets
  1599. * @q: the SGE response queue that assembled the bundle
  1600. * @skbs: the partial bundle
  1601. * @n: the number of packets in the bundle
  1602. *
  1603. * Delivers a (partial) bundle of Rx offload packets to an offload device.
  1604. */
  1605. static inline void deliver_partial_bundle(struct t3cdev *tdev,
  1606. struct sge_rspq *q,
  1607. struct sk_buff *skbs[], int n)
  1608. {
  1609. if (n) {
  1610. q->offload_bundles++;
  1611. tdev->recv(tdev, skbs, n);
  1612. }
  1613. }
  1614. /**
  1615. * ofld_poll - NAPI handler for offload packets in interrupt mode
  1616. * @dev: the network device doing the polling
  1617. * @budget: polling budget
  1618. *
  1619. * The NAPI handler for offload packets when a response queue is serviced
  1620. * by the hard interrupt handler, i.e., when it's operating in non-polling
  1621. * mode. Creates small packet batches and sends them through the offload
  1622. * receive handler. Batches need to be of modest size as we do prefetches
  1623. * on the packets in each.
  1624. */
  1625. static int ofld_poll(struct napi_struct *napi, int budget)
  1626. {
  1627. struct sge_qset *qs = container_of(napi, struct sge_qset, napi);
  1628. struct sge_rspq *q = &qs->rspq;
  1629. struct adapter *adapter = qs->adap;
  1630. int work_done = 0;
  1631. while (work_done < budget) {
  1632. struct sk_buff *skb, *tmp, *skbs[RX_BUNDLE_SIZE];
  1633. struct sk_buff_head queue;
  1634. int ngathered;
  1635. spin_lock_irq(&q->lock);
  1636. __skb_queue_head_init(&queue);
  1637. skb_queue_splice_init(&q->rx_queue, &queue);
  1638. if (skb_queue_empty(&queue)) {
  1639. napi_complete(napi);
  1640. spin_unlock_irq(&q->lock);
  1641. return work_done;
  1642. }
  1643. spin_unlock_irq(&q->lock);
  1644. ngathered = 0;
  1645. skb_queue_walk_safe(&queue, skb, tmp) {
  1646. if (work_done >= budget)
  1647. break;
  1648. work_done++;
  1649. __skb_unlink(skb, &queue);
  1650. prefetch(skb->data);
  1651. skbs[ngathered] = skb;
  1652. if (++ngathered == RX_BUNDLE_SIZE) {
  1653. q->offload_bundles++;
  1654. adapter->tdev.recv(&adapter->tdev, skbs,
  1655. ngathered);
  1656. ngathered = 0;
  1657. }
  1658. }
  1659. if (!skb_queue_empty(&queue)) {
  1660. /* splice remaining packets back onto Rx queue */
  1661. spin_lock_irq(&q->lock);
  1662. skb_queue_splice(&queue, &q->rx_queue);
  1663. spin_unlock_irq(&q->lock);
  1664. }
  1665. deliver_partial_bundle(&adapter->tdev, q, skbs, ngathered);
  1666. }
  1667. return work_done;
  1668. }
  1669. /**
  1670. * rx_offload - process a received offload packet
  1671. * @tdev: the offload device receiving the packet
  1672. * @rq: the response queue that received the packet
  1673. * @skb: the packet
  1674. * @rx_gather: a gather list of packets if we are building a bundle
  1675. * @gather_idx: index of the next available slot in the bundle
  1676. *
  1677. * Process an ingress offload pakcet and add it to the offload ingress
  1678. * queue. Returns the index of the next available slot in the bundle.
  1679. */
  1680. static inline int rx_offload(struct t3cdev *tdev, struct sge_rspq *rq,
  1681. struct sk_buff *skb, struct sk_buff *rx_gather[],
  1682. unsigned int gather_idx)
  1683. {
  1684. skb_reset_mac_header(skb);
  1685. skb_reset_network_header(skb);
  1686. skb_reset_transport_header(skb);
  1687. if (rq->polling) {
  1688. rx_gather[gather_idx++] = skb;
  1689. if (gather_idx == RX_BUNDLE_SIZE) {
  1690. tdev->recv(tdev, rx_gather, RX_BUNDLE_SIZE);
  1691. gather_idx = 0;
  1692. rq->offload_bundles++;
  1693. }
  1694. } else
  1695. offload_enqueue(rq, skb);
  1696. return gather_idx;
  1697. }
  1698. /**
  1699. * restart_tx - check whether to restart suspended Tx queues
  1700. * @qs: the queue set to resume
  1701. *
  1702. * Restarts suspended Tx queues of an SGE queue set if they have enough
  1703. * free resources to resume operation.
  1704. */
  1705. static void restart_tx(struct sge_qset *qs)
  1706. {
  1707. if (test_bit(TXQ_ETH, &qs->txq_stopped) &&
  1708. should_restart_tx(&qs->txq[TXQ_ETH]) &&
  1709. test_and_clear_bit(TXQ_ETH, &qs->txq_stopped)) {
  1710. qs->txq[TXQ_ETH].restarts++;
  1711. if (netif_running(qs->netdev))
  1712. netif_tx_wake_queue(qs->tx_q);
  1713. }
  1714. if (test_bit(TXQ_OFLD, &qs->txq_stopped) &&
  1715. should_restart_tx(&qs->txq[TXQ_OFLD]) &&
  1716. test_and_clear_bit(TXQ_OFLD, &qs->txq_stopped)) {
  1717. qs->txq[TXQ_OFLD].restarts++;
  1718. tasklet_schedule(&qs->txq[TXQ_OFLD].qresume_tsk);
  1719. }
  1720. if (test_bit(TXQ_CTRL, &qs->txq_stopped) &&
  1721. should_restart_tx(&qs->txq[TXQ_CTRL]) &&
  1722. test_and_clear_bit(TXQ_CTRL, &qs->txq_stopped)) {
  1723. qs->txq[TXQ_CTRL].restarts++;
  1724. tasklet_schedule(&qs->txq[TXQ_CTRL].qresume_tsk);
  1725. }
  1726. }
  1727. /**
  1728. * cxgb3_arp_process - process an ARP request probing a private IP address
  1729. * @adapter: the adapter
  1730. * @skb: the skbuff containing the ARP request
  1731. *
  1732. * Check if the ARP request is probing the private IP address
  1733. * dedicated to iSCSI, generate an ARP reply if so.
  1734. */
  1735. static void cxgb3_arp_process(struct port_info *pi, struct sk_buff *skb)
  1736. {
  1737. struct net_device *dev = skb->dev;
  1738. struct arphdr *arp;
  1739. unsigned char *arp_ptr;
  1740. unsigned char *sha;
  1741. __be32 sip, tip;
  1742. if (!dev)
  1743. return;
  1744. skb_reset_network_header(skb);
  1745. arp = arp_hdr(skb);
  1746. if (arp->ar_op != htons(ARPOP_REQUEST))
  1747. return;
  1748. arp_ptr = (unsigned char *)(arp + 1);
  1749. sha = arp_ptr;
  1750. arp_ptr += dev->addr_len;
  1751. memcpy(&sip, arp_ptr, sizeof(sip));
  1752. arp_ptr += sizeof(sip);
  1753. arp_ptr += dev->addr_len;
  1754. memcpy(&tip, arp_ptr, sizeof(tip));
  1755. if (tip != pi->iscsi_ipv4addr)
  1756. return;
  1757. arp_send(ARPOP_REPLY, ETH_P_ARP, sip, dev, tip, sha,
  1758. pi->iscsic.mac_addr, sha);
  1759. }
  1760. static inline int is_arp(struct sk_buff *skb)
  1761. {
  1762. return skb->protocol == htons(ETH_P_ARP);
  1763. }
  1764. static void cxgb3_process_iscsi_prov_pack(struct port_info *pi,
  1765. struct sk_buff *skb)
  1766. {
  1767. if (is_arp(skb)) {
  1768. cxgb3_arp_process(pi, skb);
  1769. return;
  1770. }
  1771. if (pi->iscsic.recv)
  1772. pi->iscsic.recv(pi, skb);
  1773. }
  1774. /**
  1775. * rx_eth - process an ingress ethernet packet
  1776. * @adap: the adapter
  1777. * @rq: the response queue that received the packet
  1778. * @skb: the packet
  1779. * @pad: amount of padding at the start of the buffer
  1780. *
  1781. * Process an ingress ethernet pakcet and deliver it to the stack.
  1782. * The padding is 2 if the packet was delivered in an Rx buffer and 0
  1783. * if it was immediate data in a response.
  1784. */
  1785. static void rx_eth(struct adapter *adap, struct sge_rspq *rq,
  1786. struct sk_buff *skb, int pad, int lro)
  1787. {
  1788. struct cpl_rx_pkt *p = (struct cpl_rx_pkt *)(skb->data + pad);
  1789. struct sge_qset *qs = rspq_to_qset(rq);
  1790. struct port_info *pi;
  1791. skb_pull(skb, sizeof(*p) + pad);
  1792. skb->protocol = eth_type_trans(skb, adap->port[p->iff]);
  1793. pi = netdev_priv(skb->dev);
  1794. if ((pi->rx_offload & T3_RX_CSUM) && p->csum_valid &&
  1795. p->csum == htons(0xffff) && !p->fragment) {
  1796. qs->port_stats[SGE_PSTAT_RX_CSUM_GOOD]++;
  1797. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1798. } else
  1799. skb->ip_summed = CHECKSUM_NONE;
  1800. skb_record_rx_queue(skb, qs - &adap->sge.qs[0]);
  1801. if (unlikely(p->vlan_valid)) {
  1802. struct vlan_group *grp = pi->vlan_grp;
  1803. qs->port_stats[SGE_PSTAT_VLANEX]++;
  1804. if (likely(grp))
  1805. if (lro)
  1806. vlan_gro_receive(&qs->napi, grp,
  1807. ntohs(p->vlan), skb);
  1808. else {
  1809. if (unlikely(pi->iscsic.flags)) {
  1810. unsigned short vtag = ntohs(p->vlan) &
  1811. VLAN_VID_MASK;
  1812. skb->dev = vlan_group_get_device(grp,
  1813. vtag);
  1814. cxgb3_process_iscsi_prov_pack(pi, skb);
  1815. }
  1816. __vlan_hwaccel_rx(skb, grp, ntohs(p->vlan),
  1817. rq->polling);
  1818. }
  1819. else
  1820. dev_kfree_skb_any(skb);
  1821. } else if (rq->polling) {
  1822. if (lro)
  1823. napi_gro_receive(&qs->napi, skb);
  1824. else {
  1825. if (unlikely(pi->iscsic.flags))
  1826. cxgb3_process_iscsi_prov_pack(pi, skb);
  1827. netif_receive_skb(skb);
  1828. }
  1829. } else
  1830. netif_rx(skb);
  1831. }
  1832. static inline int is_eth_tcp(u32 rss)
  1833. {
  1834. return G_HASHTYPE(ntohl(rss)) == RSS_HASH_4_TUPLE;
  1835. }
  1836. /**
  1837. * lro_add_page - add a page chunk to an LRO session
  1838. * @adap: the adapter
  1839. * @qs: the associated queue set
  1840. * @fl: the free list containing the page chunk to add
  1841. * @len: packet length
  1842. * @complete: Indicates the last fragment of a frame
  1843. *
  1844. * Add a received packet contained in a page chunk to an existing LRO
  1845. * session.
  1846. */
  1847. static void lro_add_page(struct adapter *adap, struct sge_qset *qs,
  1848. struct sge_fl *fl, int len, int complete)
  1849. {
  1850. struct rx_sw_desc *sd = &fl->sdesc[fl->cidx];
  1851. struct port_info *pi = netdev_priv(qs->netdev);
  1852. struct sk_buff *skb = NULL;
  1853. struct cpl_rx_pkt *cpl;
  1854. struct skb_frag_struct *rx_frag;
  1855. int nr_frags;
  1856. int offset = 0;
  1857. if (!qs->nomem) {
  1858. skb = napi_get_frags(&qs->napi);
  1859. qs->nomem = !skb;
  1860. }
  1861. fl->credits--;
  1862. pci_dma_sync_single_for_cpu(adap->pdev,
  1863. pci_unmap_addr(sd, dma_addr),
  1864. fl->buf_size - SGE_PG_RSVD,
  1865. PCI_DMA_FROMDEVICE);
  1866. (*sd->pg_chunk.p_cnt)--;
  1867. if (!*sd->pg_chunk.p_cnt && sd->pg_chunk.page != fl->pg_chunk.page)
  1868. pci_unmap_page(adap->pdev,
  1869. sd->pg_chunk.mapping,
  1870. fl->alloc_size,
  1871. PCI_DMA_FROMDEVICE);
  1872. if (!skb) {
  1873. put_page(sd->pg_chunk.page);
  1874. if (complete)
  1875. qs->nomem = 0;
  1876. return;
  1877. }
  1878. rx_frag = skb_shinfo(skb)->frags;
  1879. nr_frags = skb_shinfo(skb)->nr_frags;
  1880. if (!nr_frags) {
  1881. offset = 2 + sizeof(struct cpl_rx_pkt);
  1882. cpl = qs->lro_va = sd->pg_chunk.va + 2;
  1883. if ((pi->rx_offload & T3_RX_CSUM) &&
  1884. cpl->csum_valid && cpl->csum == htons(0xffff)) {
  1885. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1886. qs->port_stats[SGE_PSTAT_RX_CSUM_GOOD]++;
  1887. } else
  1888. skb->ip_summed = CHECKSUM_NONE;
  1889. } else
  1890. cpl = qs->lro_va;
  1891. len -= offset;
  1892. rx_frag += nr_frags;
  1893. rx_frag->page = sd->pg_chunk.page;
  1894. rx_frag->page_offset = sd->pg_chunk.offset + offset;
  1895. rx_frag->size = len;
  1896. skb->len += len;
  1897. skb->data_len += len;
  1898. skb->truesize += len;
  1899. skb_shinfo(skb)->nr_frags++;
  1900. if (!complete)
  1901. return;
  1902. skb_record_rx_queue(skb, qs - &adap->sge.qs[0]);
  1903. if (unlikely(cpl->vlan_valid)) {
  1904. struct vlan_group *grp = pi->vlan_grp;
  1905. if (likely(grp != NULL)) {
  1906. vlan_gro_frags(&qs->napi, grp, ntohs(cpl->vlan));
  1907. return;
  1908. }
  1909. }
  1910. napi_gro_frags(&qs->napi);
  1911. }
  1912. /**
  1913. * handle_rsp_cntrl_info - handles control information in a response
  1914. * @qs: the queue set corresponding to the response
  1915. * @flags: the response control flags
  1916. *
  1917. * Handles the control information of an SGE response, such as GTS
  1918. * indications and completion credits for the queue set's Tx queues.
  1919. * HW coalesces credits, we don't do any extra SW coalescing.
  1920. */
  1921. static inline void handle_rsp_cntrl_info(struct sge_qset *qs, u32 flags)
  1922. {
  1923. unsigned int credits;
  1924. #if USE_GTS
  1925. if (flags & F_RSPD_TXQ0_GTS)
  1926. clear_bit(TXQ_RUNNING, &qs->txq[TXQ_ETH].flags);
  1927. #endif
  1928. credits = G_RSPD_TXQ0_CR(flags);
  1929. if (credits)
  1930. qs->txq[TXQ_ETH].processed += credits;
  1931. credits = G_RSPD_TXQ2_CR(flags);
  1932. if (credits)
  1933. qs->txq[TXQ_CTRL].processed += credits;
  1934. # if USE_GTS
  1935. if (flags & F_RSPD_TXQ1_GTS)
  1936. clear_bit(TXQ_RUNNING, &qs->txq[TXQ_OFLD].flags);
  1937. # endif
  1938. credits = G_RSPD_TXQ1_CR(flags);
  1939. if (credits)
  1940. qs->txq[TXQ_OFLD].processed += credits;
  1941. }
  1942. /**
  1943. * check_ring_db - check if we need to ring any doorbells
  1944. * @adapter: the adapter
  1945. * @qs: the queue set whose Tx queues are to be examined
  1946. * @sleeping: indicates which Tx queue sent GTS
  1947. *
  1948. * Checks if some of a queue set's Tx queues need to ring their doorbells
  1949. * to resume transmission after idling while they still have unprocessed
  1950. * descriptors.
  1951. */
  1952. static void check_ring_db(struct adapter *adap, struct sge_qset *qs,
  1953. unsigned int sleeping)
  1954. {
  1955. if (sleeping & F_RSPD_TXQ0_GTS) {
  1956. struct sge_txq *txq = &qs->txq[TXQ_ETH];
  1957. if (txq->cleaned + txq->in_use != txq->processed &&
  1958. !test_and_set_bit(TXQ_LAST_PKT_DB, &txq->flags)) {
  1959. set_bit(TXQ_RUNNING, &txq->flags);
  1960. t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX |
  1961. V_EGRCNTX(txq->cntxt_id));
  1962. }
  1963. }
  1964. if (sleeping & F_RSPD_TXQ1_GTS) {
  1965. struct sge_txq *txq = &qs->txq[TXQ_OFLD];
  1966. if (txq->cleaned + txq->in_use != txq->processed &&
  1967. !test_and_set_bit(TXQ_LAST_PKT_DB, &txq->flags)) {
  1968. set_bit(TXQ_RUNNING, &txq->flags);
  1969. t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX |
  1970. V_EGRCNTX(txq->cntxt_id));
  1971. }
  1972. }
  1973. }
  1974. /**
  1975. * is_new_response - check if a response is newly written
  1976. * @r: the response descriptor
  1977. * @q: the response queue
  1978. *
  1979. * Returns true if a response descriptor contains a yet unprocessed
  1980. * response.
  1981. */
  1982. static inline int is_new_response(const struct rsp_desc *r,
  1983. const struct sge_rspq *q)
  1984. {
  1985. return (r->intr_gen & F_RSPD_GEN2) == q->gen;
  1986. }
  1987. static inline void clear_rspq_bufstate(struct sge_rspq * const q)
  1988. {
  1989. q->pg_skb = NULL;
  1990. q->rx_recycle_buf = 0;
  1991. }
  1992. #define RSPD_GTS_MASK (F_RSPD_TXQ0_GTS | F_RSPD_TXQ1_GTS)
  1993. #define RSPD_CTRL_MASK (RSPD_GTS_MASK | \
  1994. V_RSPD_TXQ0_CR(M_RSPD_TXQ0_CR) | \
  1995. V_RSPD_TXQ1_CR(M_RSPD_TXQ1_CR) | \
  1996. V_RSPD_TXQ2_CR(M_RSPD_TXQ2_CR))
  1997. /* How long to delay the next interrupt in case of memory shortage, in 0.1us. */
  1998. #define NOMEM_INTR_DELAY 2500
  1999. /**
  2000. * process_responses - process responses from an SGE response queue
  2001. * @adap: the adapter
  2002. * @qs: the queue set to which the response queue belongs
  2003. * @budget: how many responses can be processed in this round
  2004. *
  2005. * Process responses from an SGE response queue up to the supplied budget.
  2006. * Responses include received packets as well as credits and other events
  2007. * for the queues that belong to the response queue's queue set.
  2008. * A negative budget is effectively unlimited.
  2009. *
  2010. * Additionally choose the interrupt holdoff time for the next interrupt
  2011. * on this queue. If the system is under memory shortage use a fairly
  2012. * long delay to help recovery.
  2013. */
  2014. static int process_responses(struct adapter *adap, struct sge_qset *qs,
  2015. int budget)
  2016. {
  2017. struct sge_rspq *q = &qs->rspq;
  2018. struct rsp_desc *r = &q->desc[q->cidx];
  2019. int budget_left = budget;
  2020. unsigned int sleeping = 0;
  2021. struct sk_buff *offload_skbs[RX_BUNDLE_SIZE];
  2022. int ngathered = 0;
  2023. q->next_holdoff = q->holdoff_tmr;
  2024. while (likely(budget_left && is_new_response(r, q))) {
  2025. int packet_complete, eth, ethpad = 2, lro = qs->lro_enabled;
  2026. struct sk_buff *skb = NULL;
  2027. u32 len, flags;
  2028. __be32 rss_hi, rss_lo;
  2029. rmb();
  2030. eth = r->rss_hdr.opcode == CPL_RX_PKT;
  2031. rss_hi = *(const __be32 *)r;
  2032. rss_lo = r->rss_hdr.rss_hash_val;
  2033. flags = ntohl(r->flags);
  2034. if (unlikely(flags & F_RSPD_ASYNC_NOTIF)) {
  2035. skb = alloc_skb(AN_PKT_SIZE, GFP_ATOMIC);
  2036. if (!skb)
  2037. goto no_mem;
  2038. memcpy(__skb_put(skb, AN_PKT_SIZE), r, AN_PKT_SIZE);
  2039. skb->data[0] = CPL_ASYNC_NOTIF;
  2040. rss_hi = htonl(CPL_ASYNC_NOTIF << 24);
  2041. q->async_notif++;
  2042. } else if (flags & F_RSPD_IMM_DATA_VALID) {
  2043. skb = get_imm_packet(r);
  2044. if (unlikely(!skb)) {
  2045. no_mem:
  2046. q->next_holdoff = NOMEM_INTR_DELAY;
  2047. q->nomem++;
  2048. /* consume one credit since we tried */
  2049. budget_left--;
  2050. break;
  2051. }
  2052. q->imm_data++;
  2053. ethpad = 0;
  2054. } else if ((len = ntohl(r->len_cq)) != 0) {
  2055. struct sge_fl *fl;
  2056. lro &= eth && is_eth_tcp(rss_hi);
  2057. fl = (len & F_RSPD_FLQ) ? &qs->fl[1] : &qs->fl[0];
  2058. if (fl->use_pages) {
  2059. void *addr = fl->sdesc[fl->cidx].pg_chunk.va;
  2060. prefetch(addr);
  2061. #if L1_CACHE_BYTES < 128
  2062. prefetch(addr + L1_CACHE_BYTES);
  2063. #endif
  2064. __refill_fl(adap, fl);
  2065. if (lro > 0) {
  2066. lro_add_page(adap, qs, fl,
  2067. G_RSPD_LEN(len),
  2068. flags & F_RSPD_EOP);
  2069. goto next_fl;
  2070. }
  2071. skb = get_packet_pg(adap, fl, q,
  2072. G_RSPD_LEN(len),
  2073. eth ?
  2074. SGE_RX_DROP_THRES : 0);
  2075. q->pg_skb = skb;
  2076. } else
  2077. skb = get_packet(adap, fl, G_RSPD_LEN(len),
  2078. eth ? SGE_RX_DROP_THRES : 0);
  2079. if (unlikely(!skb)) {
  2080. if (!eth)
  2081. goto no_mem;
  2082. q->rx_drops++;
  2083. } else if (unlikely(r->rss_hdr.opcode == CPL_TRACE_PKT))
  2084. __skb_pull(skb, 2);
  2085. next_fl:
  2086. if (++fl->cidx == fl->size)
  2087. fl->cidx = 0;
  2088. } else
  2089. q->pure_rsps++;
  2090. if (flags & RSPD_CTRL_MASK) {
  2091. sleeping |= flags & RSPD_GTS_MASK;
  2092. handle_rsp_cntrl_info(qs, flags);
  2093. }
  2094. r++;
  2095. if (unlikely(++q->cidx == q->size)) {
  2096. q->cidx = 0;
  2097. q->gen ^= 1;
  2098. r = q->desc;
  2099. }
  2100. prefetch(r);
  2101. if (++q->credits >= (q->size / 4)) {
  2102. refill_rspq(adap, q, q->credits);
  2103. q->credits = 0;
  2104. }
  2105. packet_complete = flags &
  2106. (F_RSPD_EOP | F_RSPD_IMM_DATA_VALID |
  2107. F_RSPD_ASYNC_NOTIF);
  2108. if (skb != NULL && packet_complete) {
  2109. if (eth)
  2110. rx_eth(adap, q, skb, ethpad, lro);
  2111. else {
  2112. q->offload_pkts++;
  2113. /* Preserve the RSS info in csum & priority */
  2114. skb->csum = rss_hi;
  2115. skb->priority = rss_lo;
  2116. ngathered = rx_offload(&adap->tdev, q, skb,
  2117. offload_skbs,
  2118. ngathered);
  2119. }
  2120. if (flags & F_RSPD_EOP)
  2121. clear_rspq_bufstate(q);
  2122. }
  2123. --budget_left;
  2124. }
  2125. deliver_partial_bundle(&adap->tdev, q, offload_skbs, ngathered);
  2126. if (sleeping)
  2127. check_ring_db(adap, qs, sleeping);
  2128. smp_mb(); /* commit Tx queue .processed updates */
  2129. if (unlikely(qs->txq_stopped != 0))
  2130. restart_tx(qs);
  2131. budget -= budget_left;
  2132. return budget;
  2133. }
  2134. static inline int is_pure_response(const struct rsp_desc *r)
  2135. {
  2136. __be32 n = r->flags & htonl(F_RSPD_ASYNC_NOTIF | F_RSPD_IMM_DATA_VALID);
  2137. return (n | r->len_cq) == 0;
  2138. }
  2139. /**
  2140. * napi_rx_handler - the NAPI handler for Rx processing
  2141. * @napi: the napi instance
  2142. * @budget: how many packets we can process in this round
  2143. *
  2144. * Handler for new data events when using NAPI.
  2145. */
  2146. static int napi_rx_handler(struct napi_struct *napi, int budget)
  2147. {
  2148. struct sge_qset *qs = container_of(napi, struct sge_qset, napi);
  2149. struct adapter *adap = qs->adap;
  2150. int work_done = process_responses(adap, qs, budget);
  2151. if (likely(work_done < budget)) {
  2152. napi_complete(napi);
  2153. /*
  2154. * Because we don't atomically flush the following
  2155. * write it is possible that in very rare cases it can
  2156. * reach the device in a way that races with a new
  2157. * response being written plus an error interrupt
  2158. * causing the NAPI interrupt handler below to return
  2159. * unhandled status to the OS. To protect against
  2160. * this would require flushing the write and doing
  2161. * both the write and the flush with interrupts off.
  2162. * Way too expensive and unjustifiable given the
  2163. * rarity of the race.
  2164. *
  2165. * The race cannot happen at all with MSI-X.
  2166. */
  2167. t3_write_reg(adap, A_SG_GTS, V_RSPQ(qs->rspq.cntxt_id) |
  2168. V_NEWTIMER(qs->rspq.next_holdoff) |
  2169. V_NEWINDEX(qs->rspq.cidx));
  2170. }
  2171. return work_done;
  2172. }
  2173. /*
  2174. * Returns true if the device is already scheduled for polling.
  2175. */
  2176. static inline int napi_is_scheduled(struct napi_struct *napi)
  2177. {
  2178. return test_bit(NAPI_STATE_SCHED, &napi->state);
  2179. }
  2180. /**
  2181. * process_pure_responses - process pure responses from a response queue
  2182. * @adap: the adapter
  2183. * @qs: the queue set owning the response queue
  2184. * @r: the first pure response to process
  2185. *
  2186. * A simpler version of process_responses() that handles only pure (i.e.,
  2187. * non data-carrying) responses. Such respones are too light-weight to
  2188. * justify calling a softirq under NAPI, so we handle them specially in
  2189. * the interrupt handler. The function is called with a pointer to a
  2190. * response, which the caller must ensure is a valid pure response.
  2191. *
  2192. * Returns 1 if it encounters a valid data-carrying response, 0 otherwise.
  2193. */
  2194. static int process_pure_responses(struct adapter *adap, struct sge_qset *qs,
  2195. struct rsp_desc *r)
  2196. {
  2197. struct sge_rspq *q = &qs->rspq;
  2198. unsigned int sleeping = 0;
  2199. do {
  2200. u32 flags = ntohl(r->flags);
  2201. r++;
  2202. if (unlikely(++q->cidx == q->size)) {
  2203. q->cidx = 0;
  2204. q->gen ^= 1;
  2205. r = q->desc;
  2206. }
  2207. prefetch(r);
  2208. if (flags & RSPD_CTRL_MASK) {
  2209. sleeping |= flags & RSPD_GTS_MASK;
  2210. handle_rsp_cntrl_info(qs, flags);
  2211. }
  2212. q->pure_rsps++;
  2213. if (++q->credits >= (q->size / 4)) {
  2214. refill_rspq(adap, q, q->credits);
  2215. q->credits = 0;
  2216. }
  2217. if (!is_new_response(r, q))
  2218. break;
  2219. rmb();
  2220. } while (is_pure_response(r));
  2221. if (sleeping)
  2222. check_ring_db(adap, qs, sleeping);
  2223. smp_mb(); /* commit Tx queue .processed updates */
  2224. if (unlikely(qs->txq_stopped != 0))
  2225. restart_tx(qs);
  2226. return is_new_response(r, q);
  2227. }
  2228. /**
  2229. * handle_responses - decide what to do with new responses in NAPI mode
  2230. * @adap: the adapter
  2231. * @q: the response queue
  2232. *
  2233. * This is used by the NAPI interrupt handlers to decide what to do with
  2234. * new SGE responses. If there are no new responses it returns -1. If
  2235. * there are new responses and they are pure (i.e., non-data carrying)
  2236. * it handles them straight in hard interrupt context as they are very
  2237. * cheap and don't deliver any packets. Finally, if there are any data
  2238. * signaling responses it schedules the NAPI handler. Returns 1 if it
  2239. * schedules NAPI, 0 if all new responses were pure.
  2240. *
  2241. * The caller must ascertain NAPI is not already running.
  2242. */
  2243. static inline int handle_responses(struct adapter *adap, struct sge_rspq *q)
  2244. {
  2245. struct sge_qset *qs = rspq_to_qset(q);
  2246. struct rsp_desc *r = &q->desc[q->cidx];
  2247. if (!is_new_response(r, q))
  2248. return -1;
  2249. rmb();
  2250. if (is_pure_response(r) && process_pure_responses(adap, qs, r) == 0) {
  2251. t3_write_reg(adap, A_SG_GTS, V_RSPQ(q->cntxt_id) |
  2252. V_NEWTIMER(q->holdoff_tmr) | V_NEWINDEX(q->cidx));
  2253. return 0;
  2254. }
  2255. napi_schedule(&qs->napi);
  2256. return 1;
  2257. }
  2258. /*
  2259. * The MSI-X interrupt handler for an SGE response queue for the non-NAPI case
  2260. * (i.e., response queue serviced in hard interrupt).
  2261. */
  2262. irqreturn_t t3_sge_intr_msix(int irq, void *cookie)
  2263. {
  2264. struct sge_qset *qs = cookie;
  2265. struct adapter *adap = qs->adap;
  2266. struct sge_rspq *q = &qs->rspq;
  2267. spin_lock(&q->lock);
  2268. if (process_responses(adap, qs, -1) == 0)
  2269. q->unhandled_irqs++;
  2270. t3_write_reg(adap, A_SG_GTS, V_RSPQ(q->cntxt_id) |
  2271. V_NEWTIMER(q->next_holdoff) | V_NEWINDEX(q->cidx));
  2272. spin_unlock(&q->lock);
  2273. return IRQ_HANDLED;
  2274. }
  2275. /*
  2276. * The MSI-X interrupt handler for an SGE response queue for the NAPI case
  2277. * (i.e., response queue serviced by NAPI polling).
  2278. */
  2279. static irqreturn_t t3_sge_intr_msix_napi(int irq, void *cookie)
  2280. {
  2281. struct sge_qset *qs = cookie;
  2282. struct sge_rspq *q = &qs->rspq;
  2283. spin_lock(&q->lock);
  2284. if (handle_responses(qs->adap, q) < 0)
  2285. q->unhandled_irqs++;
  2286. spin_unlock(&q->lock);
  2287. return IRQ_HANDLED;
  2288. }
  2289. /*
  2290. * The non-NAPI MSI interrupt handler. This needs to handle data events from
  2291. * SGE response queues as well as error and other async events as they all use
  2292. * the same MSI vector. We use one SGE response queue per port in this mode
  2293. * and protect all response queues with queue 0's lock.
  2294. */
  2295. static irqreturn_t t3_intr_msi(int irq, void *cookie)
  2296. {
  2297. int new_packets = 0;
  2298. struct adapter *adap = cookie;
  2299. struct sge_rspq *q = &adap->sge.qs[0].rspq;
  2300. spin_lock(&q->lock);
  2301. if (process_responses(adap, &adap->sge.qs[0], -1)) {
  2302. t3_write_reg(adap, A_SG_GTS, V_RSPQ(q->cntxt_id) |
  2303. V_NEWTIMER(q->next_holdoff) | V_NEWINDEX(q->cidx));
  2304. new_packets = 1;
  2305. }
  2306. if (adap->params.nports == 2 &&
  2307. process_responses(adap, &adap->sge.qs[1], -1)) {
  2308. struct sge_rspq *q1 = &adap->sge.qs[1].rspq;
  2309. t3_write_reg(adap, A_SG_GTS, V_RSPQ(q1->cntxt_id) |
  2310. V_NEWTIMER(q1->next_holdoff) |
  2311. V_NEWINDEX(q1->cidx));
  2312. new_packets = 1;
  2313. }
  2314. if (!new_packets && t3_slow_intr_handler(adap) == 0)
  2315. q->unhandled_irqs++;
  2316. spin_unlock(&q->lock);
  2317. return IRQ_HANDLED;
  2318. }
  2319. static int rspq_check_napi(struct sge_qset *qs)
  2320. {
  2321. struct sge_rspq *q = &qs->rspq;
  2322. if (!napi_is_scheduled(&qs->napi) &&
  2323. is_new_response(&q->desc[q->cidx], q)) {
  2324. napi_schedule(&qs->napi);
  2325. return 1;
  2326. }
  2327. return 0;
  2328. }
  2329. /*
  2330. * The MSI interrupt handler for the NAPI case (i.e., response queues serviced
  2331. * by NAPI polling). Handles data events from SGE response queues as well as
  2332. * error and other async events as they all use the same MSI vector. We use
  2333. * one SGE response queue per port in this mode and protect all response
  2334. * queues with queue 0's lock.
  2335. */
  2336. static irqreturn_t t3_intr_msi_napi(int irq, void *cookie)
  2337. {
  2338. int new_packets;
  2339. struct adapter *adap = cookie;
  2340. struct sge_rspq *q = &adap->sge.qs[0].rspq;
  2341. spin_lock(&q->lock);
  2342. new_packets = rspq_check_napi(&adap->sge.qs[0]);
  2343. if (adap->params.nports == 2)
  2344. new_packets += rspq_check_napi(&adap->sge.qs[1]);
  2345. if (!new_packets && t3_slow_intr_handler(adap) == 0)
  2346. q->unhandled_irqs++;
  2347. spin_unlock(&q->lock);
  2348. return IRQ_HANDLED;
  2349. }
  2350. /*
  2351. * A helper function that processes responses and issues GTS.
  2352. */
  2353. static inline int process_responses_gts(struct adapter *adap,
  2354. struct sge_rspq *rq)
  2355. {
  2356. int work;
  2357. work = process_responses(adap, rspq_to_qset(rq), -1);
  2358. t3_write_reg(adap, A_SG_GTS, V_RSPQ(rq->cntxt_id) |
  2359. V_NEWTIMER(rq->next_holdoff) | V_NEWINDEX(rq->cidx));
  2360. return work;
  2361. }
  2362. /*
  2363. * The legacy INTx interrupt handler. This needs to handle data events from
  2364. * SGE response queues as well as error and other async events as they all use
  2365. * the same interrupt pin. We use one SGE response queue per port in this mode
  2366. * and protect all response queues with queue 0's lock.
  2367. */
  2368. static irqreturn_t t3_intr(int irq, void *cookie)
  2369. {
  2370. int work_done, w0, w1;
  2371. struct adapter *adap = cookie;
  2372. struct sge_rspq *q0 = &adap->sge.qs[0].rspq;
  2373. struct sge_rspq *q1 = &adap->sge.qs[1].rspq;
  2374. spin_lock(&q0->lock);
  2375. w0 = is_new_response(&q0->desc[q0->cidx], q0);
  2376. w1 = adap->params.nports == 2 &&
  2377. is_new_response(&q1->desc[q1->cidx], q1);
  2378. if (likely(w0 | w1)) {
  2379. t3_write_reg(adap, A_PL_CLI, 0);
  2380. t3_read_reg(adap, A_PL_CLI); /* flush */
  2381. if (likely(w0))
  2382. process_responses_gts(adap, q0);
  2383. if (w1)
  2384. process_responses_gts(adap, q1);
  2385. work_done = w0 | w1;
  2386. } else
  2387. work_done = t3_slow_intr_handler(adap);
  2388. spin_unlock(&q0->lock);
  2389. return IRQ_RETVAL(work_done != 0);
  2390. }
  2391. /*
  2392. * Interrupt handler for legacy INTx interrupts for T3B-based cards.
  2393. * Handles data events from SGE response queues as well as error and other
  2394. * async events as they all use the same interrupt pin. We use one SGE
  2395. * response queue per port in this mode and protect all response queues with
  2396. * queue 0's lock.
  2397. */
  2398. static irqreturn_t t3b_intr(int irq, void *cookie)
  2399. {
  2400. u32 map;
  2401. struct adapter *adap = cookie;
  2402. struct sge_rspq *q0 = &adap->sge.qs[0].rspq;
  2403. t3_write_reg(adap, A_PL_CLI, 0);
  2404. map = t3_read_reg(adap, A_SG_DATA_INTR);
  2405. if (unlikely(!map)) /* shared interrupt, most likely */
  2406. return IRQ_NONE;
  2407. spin_lock(&q0->lock);
  2408. if (unlikely(map & F_ERRINTR))
  2409. t3_slow_intr_handler(adap);
  2410. if (likely(map & 1))
  2411. process_responses_gts(adap, q0);
  2412. if (map & 2)
  2413. process_responses_gts(adap, &adap->sge.qs[1].rspq);
  2414. spin_unlock(&q0->lock);
  2415. return IRQ_HANDLED;
  2416. }
  2417. /*
  2418. * NAPI interrupt handler for legacy INTx interrupts for T3B-based cards.
  2419. * Handles data events from SGE response queues as well as error and other
  2420. * async events as they all use the same interrupt pin. We use one SGE
  2421. * response queue per port in this mode and protect all response queues with
  2422. * queue 0's lock.
  2423. */
  2424. static irqreturn_t t3b_intr_napi(int irq, void *cookie)
  2425. {
  2426. u32 map;
  2427. struct adapter *adap = cookie;
  2428. struct sge_qset *qs0 = &adap->sge.qs[0];
  2429. struct sge_rspq *q0 = &qs0->rspq;
  2430. t3_write_reg(adap, A_PL_CLI, 0);
  2431. map = t3_read_reg(adap, A_SG_DATA_INTR);
  2432. if (unlikely(!map)) /* shared interrupt, most likely */
  2433. return IRQ_NONE;
  2434. spin_lock(&q0->lock);
  2435. if (unlikely(map & F_ERRINTR))
  2436. t3_slow_intr_handler(adap);
  2437. if (likely(map & 1))
  2438. napi_schedule(&qs0->napi);
  2439. if (map & 2)
  2440. napi_schedule(&adap->sge.qs[1].napi);
  2441. spin_unlock(&q0->lock);
  2442. return IRQ_HANDLED;
  2443. }
  2444. /**
  2445. * t3_intr_handler - select the top-level interrupt handler
  2446. * @adap: the adapter
  2447. * @polling: whether using NAPI to service response queues
  2448. *
  2449. * Selects the top-level interrupt handler based on the type of interrupts
  2450. * (MSI-X, MSI, or legacy) and whether NAPI will be used to service the
  2451. * response queues.
  2452. */
  2453. irq_handler_t t3_intr_handler(struct adapter *adap, int polling)
  2454. {
  2455. if (adap->flags & USING_MSIX)
  2456. return polling ? t3_sge_intr_msix_napi : t3_sge_intr_msix;
  2457. if (adap->flags & USING_MSI)
  2458. return polling ? t3_intr_msi_napi : t3_intr_msi;
  2459. if (adap->params.rev > 0)
  2460. return polling ? t3b_intr_napi : t3b_intr;
  2461. return t3_intr;
  2462. }
  2463. #define SGE_PARERR (F_CPPARITYERROR | F_OCPARITYERROR | F_RCPARITYERROR | \
  2464. F_IRPARITYERROR | V_ITPARITYERROR(M_ITPARITYERROR) | \
  2465. V_FLPARITYERROR(M_FLPARITYERROR) | F_LODRBPARITYERROR | \
  2466. F_HIDRBPARITYERROR | F_LORCQPARITYERROR | \
  2467. F_HIRCQPARITYERROR)
  2468. #define SGE_FRAMINGERR (F_UC_REQ_FRAMINGERROR | F_R_REQ_FRAMINGERROR)
  2469. #define SGE_FATALERR (SGE_PARERR | SGE_FRAMINGERR | F_RSPQCREDITOVERFOW | \
  2470. F_RSPQDISABLED)
  2471. /**
  2472. * t3_sge_err_intr_handler - SGE async event interrupt handler
  2473. * @adapter: the adapter
  2474. *
  2475. * Interrupt handler for SGE asynchronous (non-data) events.
  2476. */
  2477. void t3_sge_err_intr_handler(struct adapter *adapter)
  2478. {
  2479. unsigned int v, status = t3_read_reg(adapter, A_SG_INT_CAUSE) &
  2480. ~F_FLEMPTY;
  2481. if (status & SGE_PARERR)
  2482. CH_ALERT(adapter, "SGE parity error (0x%x)\n",
  2483. status & SGE_PARERR);
  2484. if (status & SGE_FRAMINGERR)
  2485. CH_ALERT(adapter, "SGE framing error (0x%x)\n",
  2486. status & SGE_FRAMINGERR);
  2487. if (status & F_RSPQCREDITOVERFOW)
  2488. CH_ALERT(adapter, "SGE response queue credit overflow\n");
  2489. if (status & F_RSPQDISABLED) {
  2490. v = t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS);
  2491. CH_ALERT(adapter,
  2492. "packet delivered to disabled response queue "
  2493. "(0x%x)\n", (v >> S_RSPQ0DISABLED) & 0xff);
  2494. }
  2495. if (status & (F_HIPIODRBDROPERR | F_LOPIODRBDROPERR))
  2496. CH_ALERT(adapter, "SGE dropped %s priority doorbell\n",
  2497. status & F_HIPIODRBDROPERR ? "high" : "lo");
  2498. t3_write_reg(adapter, A_SG_INT_CAUSE, status);
  2499. if (status & SGE_FATALERR)
  2500. t3_fatal_err(adapter);
  2501. }
  2502. /**
  2503. * sge_timer_tx - perform periodic maintenance of an SGE qset
  2504. * @data: the SGE queue set to maintain
  2505. *
  2506. * Runs periodically from a timer to perform maintenance of an SGE queue
  2507. * set. It performs two tasks:
  2508. *
  2509. * Cleans up any completed Tx descriptors that may still be pending.
  2510. * Normal descriptor cleanup happens when new packets are added to a Tx
  2511. * queue so this timer is relatively infrequent and does any cleanup only
  2512. * if the Tx queue has not seen any new packets in a while. We make a
  2513. * best effort attempt to reclaim descriptors, in that we don't wait
  2514. * around if we cannot get a queue's lock (which most likely is because
  2515. * someone else is queueing new packets and so will also handle the clean
  2516. * up). Since control queues use immediate data exclusively we don't
  2517. * bother cleaning them up here.
  2518. *
  2519. */
  2520. static void sge_timer_tx(unsigned long data)
  2521. {
  2522. struct sge_qset *qs = (struct sge_qset *)data;
  2523. struct port_info *pi = netdev_priv(qs->netdev);
  2524. struct adapter *adap = pi->adapter;
  2525. unsigned int tbd[SGE_TXQ_PER_SET] = {0, 0};
  2526. unsigned long next_period;
  2527. if (__netif_tx_trylock(qs->tx_q)) {
  2528. tbd[TXQ_ETH] = reclaim_completed_tx(adap, &qs->txq[TXQ_ETH],
  2529. TX_RECLAIM_TIMER_CHUNK);
  2530. __netif_tx_unlock(qs->tx_q);
  2531. }
  2532. if (spin_trylock(&qs->txq[TXQ_OFLD].lock)) {
  2533. tbd[TXQ_OFLD] = reclaim_completed_tx(adap, &qs->txq[TXQ_OFLD],
  2534. TX_RECLAIM_TIMER_CHUNK);
  2535. spin_unlock(&qs->txq[TXQ_OFLD].lock);
  2536. }
  2537. next_period = TX_RECLAIM_PERIOD >>
  2538. (max(tbd[TXQ_ETH], tbd[TXQ_OFLD]) /
  2539. TX_RECLAIM_TIMER_CHUNK);
  2540. mod_timer(&qs->tx_reclaim_timer, jiffies + next_period);
  2541. }
  2542. /*
  2543. * sge_timer_rx - perform periodic maintenance of an SGE qset
  2544. * @data: the SGE queue set to maintain
  2545. *
  2546. * a) Replenishes Rx queues that have run out due to memory shortage.
  2547. * Normally new Rx buffers are added when existing ones are consumed but
  2548. * when out of memory a queue can become empty. We try to add only a few
  2549. * buffers here, the queue will be replenished fully as these new buffers
  2550. * are used up if memory shortage has subsided.
  2551. *
  2552. * b) Return coalesced response queue credits in case a response queue is
  2553. * starved.
  2554. *
  2555. */
  2556. static void sge_timer_rx(unsigned long data)
  2557. {
  2558. spinlock_t *lock;
  2559. struct sge_qset *qs = (struct sge_qset *)data;
  2560. struct port_info *pi = netdev_priv(qs->netdev);
  2561. struct adapter *adap = pi->adapter;
  2562. u32 status;
  2563. lock = adap->params.rev > 0 ?
  2564. &qs->rspq.lock : &adap->sge.qs[0].rspq.lock;
  2565. if (!spin_trylock_irq(lock))
  2566. goto out;
  2567. if (napi_is_scheduled(&qs->napi))
  2568. goto unlock;
  2569. if (adap->params.rev < 4) {
  2570. status = t3_read_reg(adap, A_SG_RSPQ_FL_STATUS);
  2571. if (status & (1 << qs->rspq.cntxt_id)) {
  2572. qs->rspq.starved++;
  2573. if (qs->rspq.credits) {
  2574. qs->rspq.credits--;
  2575. refill_rspq(adap, &qs->rspq, 1);
  2576. qs->rspq.restarted++;
  2577. t3_write_reg(adap, A_SG_RSPQ_FL_STATUS,
  2578. 1 << qs->rspq.cntxt_id);
  2579. }
  2580. }
  2581. }
  2582. if (qs->fl[0].credits < qs->fl[0].size)
  2583. __refill_fl(adap, &qs->fl[0]);
  2584. if (qs->fl[1].credits < qs->fl[1].size)
  2585. __refill_fl(adap, &qs->fl[1]);
  2586. unlock:
  2587. spin_unlock_irq(lock);
  2588. out:
  2589. mod_timer(&qs->rx_reclaim_timer, jiffies + RX_RECLAIM_PERIOD);
  2590. }
  2591. /**
  2592. * t3_update_qset_coalesce - update coalescing settings for a queue set
  2593. * @qs: the SGE queue set
  2594. * @p: new queue set parameters
  2595. *
  2596. * Update the coalescing settings for an SGE queue set. Nothing is done
  2597. * if the queue set is not initialized yet.
  2598. */
  2599. void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p)
  2600. {
  2601. qs->rspq.holdoff_tmr = max(p->coalesce_usecs * 10, 1U);/* can't be 0 */
  2602. qs->rspq.polling = p->polling;
  2603. qs->napi.poll = p->polling ? napi_rx_handler : ofld_poll;
  2604. }
  2605. /**
  2606. * t3_sge_alloc_qset - initialize an SGE queue set
  2607. * @adapter: the adapter
  2608. * @id: the queue set id
  2609. * @nports: how many Ethernet ports will be using this queue set
  2610. * @irq_vec_idx: the IRQ vector index for response queue interrupts
  2611. * @p: configuration parameters for this queue set
  2612. * @ntxq: number of Tx queues for the queue set
  2613. * @netdev: net device associated with this queue set
  2614. * @netdevq: net device TX queue associated with this queue set
  2615. *
  2616. * Allocate resources and initialize an SGE queue set. A queue set
  2617. * comprises a response queue, two Rx free-buffer queues, and up to 3
  2618. * Tx queues. The Tx queues are assigned roles in the order Ethernet
  2619. * queue, offload queue, and control queue.
  2620. */
  2621. int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
  2622. int irq_vec_idx, const struct qset_params *p,
  2623. int ntxq, struct net_device *dev,
  2624. struct netdev_queue *netdevq)
  2625. {
  2626. int i, avail, ret = -ENOMEM;
  2627. struct sge_qset *q = &adapter->sge.qs[id];
  2628. init_qset_cntxt(q, id);
  2629. setup_timer(&q->tx_reclaim_timer, sge_timer_tx, (unsigned long)q);
  2630. setup_timer(&q->rx_reclaim_timer, sge_timer_rx, (unsigned long)q);
  2631. q->fl[0].desc = alloc_ring(adapter->pdev, p->fl_size,
  2632. sizeof(struct rx_desc),
  2633. sizeof(struct rx_sw_desc),
  2634. &q->fl[0].phys_addr, &q->fl[0].sdesc);
  2635. if (!q->fl[0].desc)
  2636. goto err;
  2637. q->fl[1].desc = alloc_ring(adapter->pdev, p->jumbo_size,
  2638. sizeof(struct rx_desc),
  2639. sizeof(struct rx_sw_desc),
  2640. &q->fl[1].phys_addr, &q->fl[1].sdesc);
  2641. if (!q->fl[1].desc)
  2642. goto err;
  2643. q->rspq.desc = alloc_ring(adapter->pdev, p->rspq_size,
  2644. sizeof(struct rsp_desc), 0,
  2645. &q->rspq.phys_addr, NULL);
  2646. if (!q->rspq.desc)
  2647. goto err;
  2648. for (i = 0; i < ntxq; ++i) {
  2649. /*
  2650. * The control queue always uses immediate data so does not
  2651. * need to keep track of any sk_buffs.
  2652. */
  2653. size_t sz = i == TXQ_CTRL ? 0 : sizeof(struct tx_sw_desc);
  2654. q->txq[i].desc = alloc_ring(adapter->pdev, p->txq_size[i],
  2655. sizeof(struct tx_desc), sz,
  2656. &q->txq[i].phys_addr,
  2657. &q->txq[i].sdesc);
  2658. if (!q->txq[i].desc)
  2659. goto err;
  2660. q->txq[i].gen = 1;
  2661. q->txq[i].size = p->txq_size[i];
  2662. spin_lock_init(&q->txq[i].lock);
  2663. skb_queue_head_init(&q->txq[i].sendq);
  2664. }
  2665. tasklet_init(&q->txq[TXQ_OFLD].qresume_tsk, restart_offloadq,
  2666. (unsigned long)q);
  2667. tasklet_init(&q->txq[TXQ_CTRL].qresume_tsk, restart_ctrlq,
  2668. (unsigned long)q);
  2669. q->fl[0].gen = q->fl[1].gen = 1;
  2670. q->fl[0].size = p->fl_size;
  2671. q->fl[1].size = p->jumbo_size;
  2672. q->rspq.gen = 1;
  2673. q->rspq.size = p->rspq_size;
  2674. spin_lock_init(&q->rspq.lock);
  2675. skb_queue_head_init(&q->rspq.rx_queue);
  2676. q->txq[TXQ_ETH].stop_thres = nports *
  2677. flits_to_desc(sgl_len(MAX_SKB_FRAGS + 1) + 3);
  2678. #if FL0_PG_CHUNK_SIZE > 0
  2679. q->fl[0].buf_size = FL0_PG_CHUNK_SIZE;
  2680. #else
  2681. q->fl[0].buf_size = SGE_RX_SM_BUF_SIZE + sizeof(struct cpl_rx_data);
  2682. #endif
  2683. #if FL1_PG_CHUNK_SIZE > 0
  2684. q->fl[1].buf_size = FL1_PG_CHUNK_SIZE;
  2685. #else
  2686. q->fl[1].buf_size = is_offload(adapter) ?
  2687. (16 * 1024) - SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
  2688. MAX_FRAME_SIZE + 2 + sizeof(struct cpl_rx_pkt);
  2689. #endif
  2690. q->fl[0].use_pages = FL0_PG_CHUNK_SIZE > 0;
  2691. q->fl[1].use_pages = FL1_PG_CHUNK_SIZE > 0;
  2692. q->fl[0].order = FL0_PG_ORDER;
  2693. q->fl[1].order = FL1_PG_ORDER;
  2694. q->fl[0].alloc_size = FL0_PG_ALLOC_SIZE;
  2695. q->fl[1].alloc_size = FL1_PG_ALLOC_SIZE;
  2696. spin_lock_irq(&adapter->sge.reg_lock);
  2697. /* FL threshold comparison uses < */
  2698. ret = t3_sge_init_rspcntxt(adapter, q->rspq.cntxt_id, irq_vec_idx,
  2699. q->rspq.phys_addr, q->rspq.size,
  2700. q->fl[0].buf_size - SGE_PG_RSVD, 1, 0);
  2701. if (ret)
  2702. goto err_unlock;
  2703. for (i = 0; i < SGE_RXQ_PER_SET; ++i) {
  2704. ret = t3_sge_init_flcntxt(adapter, q->fl[i].cntxt_id, 0,
  2705. q->fl[i].phys_addr, q->fl[i].size,
  2706. q->fl[i].buf_size - SGE_PG_RSVD,
  2707. p->cong_thres, 1, 0);
  2708. if (ret)
  2709. goto err_unlock;
  2710. }
  2711. ret = t3_sge_init_ecntxt(adapter, q->txq[TXQ_ETH].cntxt_id, USE_GTS,
  2712. SGE_CNTXT_ETH, id, q->txq[TXQ_ETH].phys_addr,
  2713. q->txq[TXQ_ETH].size, q->txq[TXQ_ETH].token,
  2714. 1, 0);
  2715. if (ret)
  2716. goto err_unlock;
  2717. if (ntxq > 1) {
  2718. ret = t3_sge_init_ecntxt(adapter, q->txq[TXQ_OFLD].cntxt_id,
  2719. USE_GTS, SGE_CNTXT_OFLD, id,
  2720. q->txq[TXQ_OFLD].phys_addr,
  2721. q->txq[TXQ_OFLD].size, 0, 1, 0);
  2722. if (ret)
  2723. goto err_unlock;
  2724. }
  2725. if (ntxq > 2) {
  2726. ret = t3_sge_init_ecntxt(adapter, q->txq[TXQ_CTRL].cntxt_id, 0,
  2727. SGE_CNTXT_CTRL, id,
  2728. q->txq[TXQ_CTRL].phys_addr,
  2729. q->txq[TXQ_CTRL].size,
  2730. q->txq[TXQ_CTRL].token, 1, 0);
  2731. if (ret)
  2732. goto err_unlock;
  2733. }
  2734. spin_unlock_irq(&adapter->sge.reg_lock);
  2735. q->adap = adapter;
  2736. q->netdev = dev;
  2737. q->tx_q = netdevq;
  2738. t3_update_qset_coalesce(q, p);
  2739. avail = refill_fl(adapter, &q->fl[0], q->fl[0].size,
  2740. GFP_KERNEL | __GFP_COMP);
  2741. if (!avail) {
  2742. CH_ALERT(adapter, "free list queue 0 initialization failed\n");
  2743. goto err;
  2744. }
  2745. if (avail < q->fl[0].size)
  2746. CH_WARN(adapter, "free list queue 0 enabled with %d credits\n",
  2747. avail);
  2748. avail = refill_fl(adapter, &q->fl[1], q->fl[1].size,
  2749. GFP_KERNEL | __GFP_COMP);
  2750. if (avail < q->fl[1].size)
  2751. CH_WARN(adapter, "free list queue 1 enabled with %d credits\n",
  2752. avail);
  2753. refill_rspq(adapter, &q->rspq, q->rspq.size - 1);
  2754. t3_write_reg(adapter, A_SG_GTS, V_RSPQ(q->rspq.cntxt_id) |
  2755. V_NEWTIMER(q->rspq.holdoff_tmr));
  2756. return 0;
  2757. err_unlock:
  2758. spin_unlock_irq(&adapter->sge.reg_lock);
  2759. err:
  2760. t3_free_qset(adapter, q);
  2761. return ret;
  2762. }
  2763. /**
  2764. * t3_start_sge_timers - start SGE timer call backs
  2765. * @adap: the adapter
  2766. *
  2767. * Starts each SGE queue set's timer call back
  2768. */
  2769. void t3_start_sge_timers(struct adapter *adap)
  2770. {
  2771. int i;
  2772. for (i = 0; i < SGE_QSETS; ++i) {
  2773. struct sge_qset *q = &adap->sge.qs[i];
  2774. if (q->tx_reclaim_timer.function)
  2775. mod_timer(&q->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
  2776. if (q->rx_reclaim_timer.function)
  2777. mod_timer(&q->rx_reclaim_timer, jiffies + RX_RECLAIM_PERIOD);
  2778. }
  2779. }
  2780. /**
  2781. * t3_stop_sge_timers - stop SGE timer call backs
  2782. * @adap: the adapter
  2783. *
  2784. * Stops each SGE queue set's timer call back
  2785. */
  2786. void t3_stop_sge_timers(struct adapter *adap)
  2787. {
  2788. int i;
  2789. for (i = 0; i < SGE_QSETS; ++i) {
  2790. struct sge_qset *q = &adap->sge.qs[i];
  2791. if (q->tx_reclaim_timer.function)
  2792. del_timer_sync(&q->tx_reclaim_timer);
  2793. if (q->rx_reclaim_timer.function)
  2794. del_timer_sync(&q->rx_reclaim_timer);
  2795. }
  2796. }
  2797. /**
  2798. * t3_free_sge_resources - free SGE resources
  2799. * @adap: the adapter
  2800. *
  2801. * Frees resources used by the SGE queue sets.
  2802. */
  2803. void t3_free_sge_resources(struct adapter *adap)
  2804. {
  2805. int i;
  2806. for (i = 0; i < SGE_QSETS; ++i)
  2807. t3_free_qset(adap, &adap->sge.qs[i]);
  2808. }
  2809. /**
  2810. * t3_sge_start - enable SGE
  2811. * @adap: the adapter
  2812. *
  2813. * Enables the SGE for DMAs. This is the last step in starting packet
  2814. * transfers.
  2815. */
  2816. void t3_sge_start(struct adapter *adap)
  2817. {
  2818. t3_set_reg_field(adap, A_SG_CONTROL, F_GLOBALENABLE, F_GLOBALENABLE);
  2819. }
  2820. /**
  2821. * t3_sge_stop - disable SGE operation
  2822. * @adap: the adapter
  2823. *
  2824. * Disables the DMA engine. This can be called in emeregencies (e.g.,
  2825. * from error interrupts) or from normal process context. In the latter
  2826. * case it also disables any pending queue restart tasklets. Note that
  2827. * if it is called in interrupt context it cannot disable the restart
  2828. * tasklets as it cannot wait, however the tasklets will have no effect
  2829. * since the doorbells are disabled and the driver will call this again
  2830. * later from process context, at which time the tasklets will be stopped
  2831. * if they are still running.
  2832. */
  2833. void t3_sge_stop(struct adapter *adap)
  2834. {
  2835. t3_set_reg_field(adap, A_SG_CONTROL, F_GLOBALENABLE, 0);
  2836. if (!in_interrupt()) {
  2837. int i;
  2838. for (i = 0; i < SGE_QSETS; ++i) {
  2839. struct sge_qset *qs = &adap->sge.qs[i];
  2840. tasklet_kill(&qs->txq[TXQ_OFLD].qresume_tsk);
  2841. tasklet_kill(&qs->txq[TXQ_CTRL].qresume_tsk);
  2842. }
  2843. }
  2844. }
  2845. /**
  2846. * t3_sge_init - initialize SGE
  2847. * @adap: the adapter
  2848. * @p: the SGE parameters
  2849. *
  2850. * Performs SGE initialization needed every time after a chip reset.
  2851. * We do not initialize any of the queue sets here, instead the driver
  2852. * top-level must request those individually. We also do not enable DMA
  2853. * here, that should be done after the queues have been set up.
  2854. */
  2855. void t3_sge_init(struct adapter *adap, struct sge_params *p)
  2856. {
  2857. unsigned int ctrl, ups = ffs(pci_resource_len(adap->pdev, 2) >> 12);
  2858. ctrl = F_DROPPKT | V_PKTSHIFT(2) | F_FLMODE | F_AVOIDCQOVFL |
  2859. F_CQCRDTCTRL | F_CONGMODE | F_TNLFLMODE | F_FATLPERREN |
  2860. V_HOSTPAGESIZE(PAGE_SHIFT - 11) | F_BIGENDIANINGRESS |
  2861. V_USERSPACESIZE(ups ? ups - 1 : 0) | F_ISCSICOALESCING;
  2862. #if SGE_NUM_GENBITS == 1
  2863. ctrl |= F_EGRGENCTRL;
  2864. #endif
  2865. if (adap->params.rev > 0) {
  2866. if (!(adap->flags & (USING_MSIX | USING_MSI)))
  2867. ctrl |= F_ONEINTMULTQ | F_OPTONEINTMULTQ;
  2868. }
  2869. t3_write_reg(adap, A_SG_CONTROL, ctrl);
  2870. t3_write_reg(adap, A_SG_EGR_RCQ_DRB_THRSH, V_HIRCQDRBTHRSH(512) |
  2871. V_LORCQDRBTHRSH(512));
  2872. t3_write_reg(adap, A_SG_TIMER_TICK, core_ticks_per_usec(adap) / 10);
  2873. t3_write_reg(adap, A_SG_CMDQ_CREDIT_TH, V_THRESHOLD(32) |
  2874. V_TIMEOUT(200 * core_ticks_per_usec(adap)));
  2875. t3_write_reg(adap, A_SG_HI_DRB_HI_THRSH,
  2876. adap->params.rev < T3_REV_C ? 1000 : 500);
  2877. t3_write_reg(adap, A_SG_HI_DRB_LO_THRSH, 256);
  2878. t3_write_reg(adap, A_SG_LO_DRB_HI_THRSH, 1000);
  2879. t3_write_reg(adap, A_SG_LO_DRB_LO_THRSH, 256);
  2880. t3_write_reg(adap, A_SG_OCO_BASE, V_BASE1(0xfff));
  2881. t3_write_reg(adap, A_SG_DRB_PRI_THRESH, 63 * 1024);
  2882. }
  2883. /**
  2884. * t3_sge_prep - one-time SGE initialization
  2885. * @adap: the associated adapter
  2886. * @p: SGE parameters
  2887. *
  2888. * Performs one-time initialization of SGE SW state. Includes determining
  2889. * defaults for the assorted SGE parameters, which admins can change until
  2890. * they are used to initialize the SGE.
  2891. */
  2892. void t3_sge_prep(struct adapter *adap, struct sge_params *p)
  2893. {
  2894. int i;
  2895. p->max_pkt_size = (16 * 1024) - sizeof(struct cpl_rx_data) -
  2896. SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
  2897. for (i = 0; i < SGE_QSETS; ++i) {
  2898. struct qset_params *q = p->qset + i;
  2899. q->polling = adap->params.rev > 0;
  2900. q->coalesce_usecs = 5;
  2901. q->rspq_size = 1024;
  2902. q->fl_size = 1024;
  2903. q->jumbo_size = 512;
  2904. q->txq_size[TXQ_ETH] = 1024;
  2905. q->txq_size[TXQ_OFLD] = 1024;
  2906. q->txq_size[TXQ_CTRL] = 256;
  2907. q->cong_thres = 0;
  2908. }
  2909. spin_lock_init(&adap->sge.reg_lock);
  2910. }
  2911. /**
  2912. * t3_get_desc - dump an SGE descriptor for debugging purposes
  2913. * @qs: the queue set
  2914. * @qnum: identifies the specific queue (0..2: Tx, 3:response, 4..5: Rx)
  2915. * @idx: the descriptor index in the queue
  2916. * @data: where to dump the descriptor contents
  2917. *
  2918. * Dumps the contents of a HW descriptor of an SGE queue. Returns the
  2919. * size of the descriptor.
  2920. */
  2921. int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx,
  2922. unsigned char *data)
  2923. {
  2924. if (qnum >= 6)
  2925. return -EINVAL;
  2926. if (qnum < 3) {
  2927. if (!qs->txq[qnum].desc || idx >= qs->txq[qnum].size)
  2928. return -EINVAL;
  2929. memcpy(data, &qs->txq[qnum].desc[idx], sizeof(struct tx_desc));
  2930. return sizeof(struct tx_desc);
  2931. }
  2932. if (qnum == 3) {
  2933. if (!qs->rspq.desc || idx >= qs->rspq.size)
  2934. return -EINVAL;
  2935. memcpy(data, &qs->rspq.desc[idx], sizeof(struct rsp_desc));
  2936. return sizeof(struct rsp_desc);
  2937. }
  2938. qnum -= 4;
  2939. if (!qs->fl[qnum].desc || idx >= qs->fl[qnum].size)
  2940. return -EINVAL;
  2941. memcpy(data, &qs->fl[qnum].desc[idx], sizeof(struct rx_desc));
  2942. return sizeof(struct rx_desc);
  2943. }