iwl3945-base.c 220 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/ieee80211_radiotap.h>
  42. #include <net/lib80211.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #define DRV_NAME "iwl3945"
  46. #include "iwl-fh.h"
  47. #include "iwl-3945-fh.h"
  48. #include "iwl-commands.h"
  49. #include "iwl-3945.h"
  50. #include "iwl-helpers.h"
  51. #include "iwl-core.h"
  52. #include "iwl-dev.h"
  53. static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
  54. struct iwl_tx_queue *txq);
  55. /*
  56. * module name, copyright, version, etc.
  57. */
  58. #define DRV_DESCRIPTION \
  59. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  60. #ifdef CONFIG_IWL3945_DEBUG
  61. #define VD "d"
  62. #else
  63. #define VD
  64. #endif
  65. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  66. #define VS "s"
  67. #else
  68. #define VS
  69. #endif
  70. #define IWL39_VERSION "1.2.26k" VD VS
  71. #define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
  72. #define DRV_AUTHOR "<ilw@linux.intel.com>"
  73. #define DRV_VERSION IWL39_VERSION
  74. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  75. MODULE_VERSION(DRV_VERSION);
  76. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  77. MODULE_LICENSE("GPL");
  78. /* module parameters */
  79. struct iwl_mod_params iwl3945_mod_params = {
  80. .num_of_queues = IWL39_MAX_NUM_QUEUES,
  81. /* the rest are 0 by default */
  82. };
  83. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  84. * DMA services
  85. *
  86. * Theory of operation
  87. *
  88. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  89. * of buffer descriptors, each of which points to one or more data buffers for
  90. * the device to read from or fill. Driver and device exchange status of each
  91. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  92. * entries in each circular buffer, to protect against confusing empty and full
  93. * queue states.
  94. *
  95. * The device reads or writes the data in the queues via the device's several
  96. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  97. *
  98. * For Tx queue, there are low mark and high mark limits. If, after queuing
  99. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  100. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  101. * Tx queue resumed.
  102. *
  103. * The 3945 operates with six queues: One receive queue, one transmit queue
  104. * (#4) for sending commands to the device firmware, and four transmit queues
  105. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  106. ***************************************************/
  107. int iwl3945_x2_queue_used(const struct iwl_queue *q, int i)
  108. {
  109. return q->write_ptr > q->read_ptr ?
  110. (i >= q->read_ptr && i < q->write_ptr) :
  111. !(i < q->read_ptr && i >= q->write_ptr);
  112. }
  113. /**
  114. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  115. */
  116. static int iwl3945_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
  117. int count, int slots_num, u32 id)
  118. {
  119. q->n_bd = count;
  120. q->n_window = slots_num;
  121. q->id = id;
  122. /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
  123. * and iwl_queue_dec_wrap are broken. */
  124. BUG_ON(!is_power_of_2(count));
  125. /* slots_num must be power-of-two size, otherwise
  126. * get_cmd_index is broken. */
  127. BUG_ON(!is_power_of_2(slots_num));
  128. q->low_mark = q->n_window / 4;
  129. if (q->low_mark < 4)
  130. q->low_mark = 4;
  131. q->high_mark = q->n_window / 8;
  132. if (q->high_mark < 2)
  133. q->high_mark = 2;
  134. q->write_ptr = q->read_ptr = 0;
  135. return 0;
  136. }
  137. /**
  138. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  139. */
  140. static int iwl3945_tx_queue_alloc(struct iwl_priv *priv,
  141. struct iwl_tx_queue *txq, u32 id)
  142. {
  143. struct pci_dev *dev = priv->pci_dev;
  144. /* Driver private data, only for Tx (not command) queues,
  145. * not shared with device. */
  146. if (id != IWL_CMD_QUEUE_NUM) {
  147. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  148. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  149. if (!txq->txb) {
  150. IWL_ERR(priv, "kmalloc for auxiliary BD "
  151. "structures failed\n");
  152. goto error;
  153. }
  154. } else
  155. txq->txb = NULL;
  156. /* Circular buffer of transmit frame descriptors (TFDs),
  157. * shared with device */
  158. txq->tfds39 = pci_alloc_consistent(dev,
  159. sizeof(txq->tfds39[0]) * TFD_QUEUE_SIZE_MAX,
  160. &txq->q.dma_addr);
  161. if (!txq->tfds39) {
  162. IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n",
  163. sizeof(txq->tfds39[0]) * TFD_QUEUE_SIZE_MAX);
  164. goto error;
  165. }
  166. txq->q.id = id;
  167. return 0;
  168. error:
  169. kfree(txq->txb);
  170. txq->txb = NULL;
  171. return -ENOMEM;
  172. }
  173. /**
  174. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  175. */
  176. int iwl3945_tx_queue_init(struct iwl_priv *priv,
  177. struct iwl_tx_queue *txq, int slots_num, u32 txq_id)
  178. {
  179. int len, i;
  180. int rc = 0;
  181. /*
  182. * Alloc buffer array for commands (Tx or other types of commands).
  183. * For the command queue (#4), allocate command space + one big
  184. * command for scan, since scan command is very huge; the system will
  185. * not have two scans at the same time, so only one is needed.
  186. * For data Tx queues (all other queues), no super-size command
  187. * space is needed.
  188. */
  189. len = sizeof(struct iwl_cmd);
  190. for (i = 0; i <= slots_num; i++) {
  191. if (i == slots_num) {
  192. if (txq_id == IWL_CMD_QUEUE_NUM)
  193. len += IWL_MAX_SCAN_SIZE;
  194. else
  195. continue;
  196. }
  197. txq->cmd[i] = kmalloc(len, GFP_KERNEL);
  198. if (!txq->cmd[i])
  199. goto err;
  200. }
  201. /* Alloc driver data array and TFD circular buffer */
  202. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  203. if (rc)
  204. goto err;
  205. txq->need_update = 0;
  206. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  207. * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
  208. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  209. /* Initialize queue high/low-water, head/tail indexes */
  210. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  211. /* Tell device where to find queue, enable DMA channel. */
  212. iwl3945_hw_tx_queue_init(priv, txq);
  213. return 0;
  214. err:
  215. for (i = 0; i < slots_num; i++) {
  216. kfree(txq->cmd[i]);
  217. txq->cmd[i] = NULL;
  218. }
  219. if (txq_id == IWL_CMD_QUEUE_NUM) {
  220. kfree(txq->cmd[slots_num]);
  221. txq->cmd[slots_num] = NULL;
  222. }
  223. return -ENOMEM;
  224. }
  225. /**
  226. * iwl3945_tx_queue_free - Deallocate DMA queue.
  227. * @txq: Transmit queue to deallocate.
  228. *
  229. * Empty queue by removing and destroying all BD's.
  230. * Free all buffers.
  231. * 0-fill, but do not free "txq" descriptor structure.
  232. */
  233. void iwl3945_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  234. {
  235. struct iwl_queue *q = &txq->q;
  236. struct pci_dev *dev = priv->pci_dev;
  237. int len, i;
  238. if (q->n_bd == 0)
  239. return;
  240. /* first, empty all BD's */
  241. for (; q->write_ptr != q->read_ptr;
  242. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
  243. iwl3945_hw_txq_free_tfd(priv, txq);
  244. len = sizeof(struct iwl_cmd) * q->n_window;
  245. if (q->id == IWL_CMD_QUEUE_NUM)
  246. len += IWL_MAX_SCAN_SIZE;
  247. /* De-alloc array of command/tx buffers */
  248. for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
  249. kfree(txq->cmd[i]);
  250. /* De-alloc circular buffer of TFDs */
  251. if (txq->q.n_bd)
  252. pci_free_consistent(dev, sizeof(struct iwl3945_tfd) *
  253. txq->q.n_bd, txq->tfds39, txq->q.dma_addr);
  254. /* De-alloc array of per-TFD driver data */
  255. kfree(txq->txb);
  256. txq->txb = NULL;
  257. /* 0-fill queue descriptor structure */
  258. memset(txq, 0, sizeof(*txq));
  259. }
  260. /*************** STATION TABLE MANAGEMENT ****
  261. * mac80211 should be examined to determine if sta_info is duplicating
  262. * the functionality provided here
  263. */
  264. /**************************************************************/
  265. #if 0 /* temporary disable till we add real remove station */
  266. /**
  267. * iwl3945_remove_station - Remove driver's knowledge of station.
  268. *
  269. * NOTE: This does not remove station from device's station table.
  270. */
  271. static u8 iwl3945_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
  272. {
  273. int index = IWL_INVALID_STATION;
  274. int i;
  275. unsigned long flags;
  276. spin_lock_irqsave(&priv->sta_lock, flags);
  277. if (is_ap)
  278. index = IWL_AP_ID;
  279. else if (is_broadcast_ether_addr(addr))
  280. index = priv->hw_params.bcast_sta_id;
  281. else
  282. for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++)
  283. if (priv->stations_39[i].used &&
  284. !compare_ether_addr(priv->stations_39[i].sta.sta.addr,
  285. addr)) {
  286. index = i;
  287. break;
  288. }
  289. if (unlikely(index == IWL_INVALID_STATION))
  290. goto out;
  291. if (priv->stations_39[index].used) {
  292. priv->stations_39[index].used = 0;
  293. priv->num_stations--;
  294. }
  295. BUG_ON(priv->num_stations < 0);
  296. out:
  297. spin_unlock_irqrestore(&priv->sta_lock, flags);
  298. return 0;
  299. }
  300. #endif
  301. /**
  302. * iwl3945_clear_stations_table - Clear the driver's station table
  303. *
  304. * NOTE: This does not clear or otherwise alter the device's station table.
  305. */
  306. static void iwl3945_clear_stations_table(struct iwl_priv *priv)
  307. {
  308. unsigned long flags;
  309. spin_lock_irqsave(&priv->sta_lock, flags);
  310. priv->num_stations = 0;
  311. memset(priv->stations_39, 0, sizeof(priv->stations_39));
  312. spin_unlock_irqrestore(&priv->sta_lock, flags);
  313. }
  314. /**
  315. * iwl3945_add_station - Add station to station tables in driver and device
  316. */
  317. u8 iwl3945_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap, u8 flags)
  318. {
  319. int i;
  320. int index = IWL_INVALID_STATION;
  321. struct iwl3945_station_entry *station;
  322. unsigned long flags_spin;
  323. u8 rate;
  324. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  325. if (is_ap)
  326. index = IWL_AP_ID;
  327. else if (is_broadcast_ether_addr(addr))
  328. index = priv->hw_params.bcast_sta_id;
  329. else
  330. for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++) {
  331. if (!compare_ether_addr(priv->stations_39[i].sta.sta.addr,
  332. addr)) {
  333. index = i;
  334. break;
  335. }
  336. if (!priv->stations_39[i].used &&
  337. index == IWL_INVALID_STATION)
  338. index = i;
  339. }
  340. /* These two conditions has the same outcome but keep them separate
  341. since they have different meaning */
  342. if (unlikely(index == IWL_INVALID_STATION)) {
  343. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  344. return index;
  345. }
  346. if (priv->stations_39[index].used &&
  347. !compare_ether_addr(priv->stations_39[index].sta.sta.addr, addr)) {
  348. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  349. return index;
  350. }
  351. IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
  352. station = &priv->stations_39[index];
  353. station->used = 1;
  354. priv->num_stations++;
  355. /* Set up the REPLY_ADD_STA command to send to device */
  356. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  357. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  358. station->sta.mode = 0;
  359. station->sta.sta.sta_id = index;
  360. station->sta.station_flags = 0;
  361. if (priv->band == IEEE80211_BAND_5GHZ)
  362. rate = IWL_RATE_6M_PLCP;
  363. else
  364. rate = IWL_RATE_1M_PLCP;
  365. /* Turn on both antennas for the station... */
  366. station->sta.rate_n_flags =
  367. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  368. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  369. /* Add station to device's station table */
  370. iwl3945_send_add_station(priv, &station->sta, flags);
  371. return index;
  372. }
  373. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  374. #define IWL_CMD(x) case x: return #x
  375. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  376. /**
  377. * iwl3945_enqueue_hcmd - enqueue a uCode command
  378. * @priv: device private data point
  379. * @cmd: a point to the ucode command structure
  380. *
  381. * The function returns < 0 values to indicate the operation is
  382. * failed. On success, it turns the index (> 0) of command in the
  383. * command queue.
  384. */
  385. static int iwl3945_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
  386. {
  387. struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  388. struct iwl_queue *q = &txq->q;
  389. struct iwl3945_tfd *tfd;
  390. struct iwl_cmd *out_cmd;
  391. u32 idx;
  392. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  393. dma_addr_t phys_addr;
  394. int pad;
  395. int ret, len;
  396. unsigned long flags;
  397. /* If any of the command structures end up being larger than
  398. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  399. * we will need to increase the size of the TFD entries */
  400. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  401. !(cmd->meta.flags & CMD_SIZE_HUGE));
  402. if (iwl_is_rfkill(priv)) {
  403. IWL_DEBUG_INFO("Not sending command - RF KILL");
  404. return -EIO;
  405. }
  406. if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  407. IWL_ERR(priv, "No space for Tx\n");
  408. return -ENOSPC;
  409. }
  410. spin_lock_irqsave(&priv->hcmd_lock, flags);
  411. tfd = &txq->tfds39[q->write_ptr];
  412. memset(tfd, 0, sizeof(*tfd));
  413. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  414. out_cmd = txq->cmd[idx];
  415. out_cmd->hdr.cmd = cmd->id;
  416. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  417. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  418. /* At this point, the out_cmd now has all of the incoming cmd
  419. * information */
  420. out_cmd->hdr.flags = 0;
  421. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  422. INDEX_TO_SEQ(q->write_ptr));
  423. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  424. out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
  425. len = (idx == TFD_CMD_SLOTS) ?
  426. IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd);
  427. phys_addr = pci_map_single(priv->pci_dev, out_cmd,
  428. len, PCI_DMA_TODEVICE);
  429. pci_unmap_addr_set(&out_cmd->meta, mapping, phys_addr);
  430. pci_unmap_len_set(&out_cmd->meta, len, len);
  431. phys_addr += offsetof(struct iwl_cmd, hdr);
  432. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  433. pad = U32_PAD(cmd->len);
  434. tfd->control_flags |= cpu_to_le32(TFD_CTL_PAD_SET(pad));
  435. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  436. "%d bytes at %d[%d]:%d\n",
  437. get_cmd_string(out_cmd->hdr.cmd),
  438. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  439. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  440. txq->need_update = 1;
  441. /* Increment and update queue's write index */
  442. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  443. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  444. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  445. return ret ? ret : idx;
  446. }
  447. static int iwl3945_send_cmd_async(struct iwl_priv *priv,
  448. struct iwl_host_cmd *cmd)
  449. {
  450. int ret;
  451. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  452. /* An asynchronous command can not expect an SKB to be set. */
  453. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  454. /* An asynchronous command MUST have a callback. */
  455. BUG_ON(!cmd->meta.u.callback);
  456. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  457. return -EBUSY;
  458. ret = iwl3945_enqueue_hcmd(priv, cmd);
  459. if (ret < 0) {
  460. IWL_ERR(priv,
  461. "Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  462. get_cmd_string(cmd->id), ret);
  463. return ret;
  464. }
  465. return 0;
  466. }
  467. static int iwl3945_send_cmd_sync(struct iwl_priv *priv,
  468. struct iwl_host_cmd *cmd)
  469. {
  470. int cmd_idx;
  471. int ret;
  472. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  473. /* A synchronous command can not have a callback set. */
  474. BUG_ON(cmd->meta.u.callback != NULL);
  475. if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
  476. IWL_ERR(priv,
  477. "Error sending %s: Already sending a host command\n",
  478. get_cmd_string(cmd->id));
  479. ret = -EBUSY;
  480. goto out;
  481. }
  482. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  483. if (cmd->meta.flags & CMD_WANT_SKB)
  484. cmd->meta.source = &cmd->meta;
  485. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  486. if (cmd_idx < 0) {
  487. ret = cmd_idx;
  488. IWL_ERR(priv,
  489. "Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  490. get_cmd_string(cmd->id), ret);
  491. goto out;
  492. }
  493. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  494. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  495. HOST_COMPLETE_TIMEOUT);
  496. if (!ret) {
  497. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  498. IWL_ERR(priv, "Error sending %s: time out after %dms\n",
  499. get_cmd_string(cmd->id),
  500. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  501. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  502. ret = -ETIMEDOUT;
  503. goto cancel;
  504. }
  505. }
  506. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  507. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  508. get_cmd_string(cmd->id));
  509. ret = -ECANCELED;
  510. goto fail;
  511. }
  512. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  513. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  514. get_cmd_string(cmd->id));
  515. ret = -EIO;
  516. goto fail;
  517. }
  518. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  519. IWL_ERR(priv, "Error: Response NULL in '%s'\n",
  520. get_cmd_string(cmd->id));
  521. ret = -EIO;
  522. goto cancel;
  523. }
  524. ret = 0;
  525. goto out;
  526. cancel:
  527. if (cmd->meta.flags & CMD_WANT_SKB) {
  528. struct iwl_cmd *qcmd;
  529. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  530. * TX cmd queue. Otherwise in case the cmd comes
  531. * in later, it will possibly set an invalid
  532. * address (cmd->meta.source). */
  533. qcmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  534. qcmd->meta.flags &= ~CMD_WANT_SKB;
  535. }
  536. fail:
  537. if (cmd->meta.u.skb) {
  538. dev_kfree_skb_any(cmd->meta.u.skb);
  539. cmd->meta.u.skb = NULL;
  540. }
  541. out:
  542. clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
  543. return ret;
  544. }
  545. int iwl3945_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
  546. {
  547. if (cmd->meta.flags & CMD_ASYNC)
  548. return iwl3945_send_cmd_async(priv, cmd);
  549. return iwl3945_send_cmd_sync(priv, cmd);
  550. }
  551. int iwl3945_send_cmd_pdu(struct iwl_priv *priv, u8 id, u16 len, const void *data)
  552. {
  553. struct iwl_host_cmd cmd = {
  554. .id = id,
  555. .len = len,
  556. .data = data,
  557. };
  558. return iwl3945_send_cmd_sync(priv, &cmd);
  559. }
  560. static int __must_check iwl3945_send_cmd_u32(struct iwl_priv *priv, u8 id, u32 val)
  561. {
  562. struct iwl_host_cmd cmd = {
  563. .id = id,
  564. .len = sizeof(val),
  565. .data = &val,
  566. };
  567. return iwl3945_send_cmd_sync(priv, &cmd);
  568. }
  569. int iwl3945_send_statistics_request(struct iwl_priv *priv)
  570. {
  571. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  572. }
  573. /**
  574. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  575. * @band: 2.4 or 5 GHz band
  576. * @channel: Any channel valid for the requested band
  577. * In addition to setting the staging RXON, priv->band is also set.
  578. *
  579. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  580. * in the staging RXON flag structure based on the band
  581. */
  582. static int iwl3945_set_rxon_channel(struct iwl_priv *priv,
  583. enum ieee80211_band band,
  584. u16 channel)
  585. {
  586. if (!iwl3945_get_channel_info(priv, band, channel)) {
  587. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  588. channel, band);
  589. return -EINVAL;
  590. }
  591. if ((le16_to_cpu(priv->staging39_rxon.channel) == channel) &&
  592. (priv->band == band))
  593. return 0;
  594. priv->staging39_rxon.channel = cpu_to_le16(channel);
  595. if (band == IEEE80211_BAND_5GHZ)
  596. priv->staging39_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  597. else
  598. priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  599. priv->band = band;
  600. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  601. return 0;
  602. }
  603. /**
  604. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  605. *
  606. * NOTE: This is really only useful during development and can eventually
  607. * be #ifdef'd out once the driver is stable and folks aren't actively
  608. * making changes
  609. */
  610. static int iwl3945_check_rxon_cmd(struct iwl_priv *priv)
  611. {
  612. int error = 0;
  613. int counter = 1;
  614. struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
  615. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  616. error |= le32_to_cpu(rxon->flags &
  617. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  618. RXON_FLG_RADAR_DETECT_MSK));
  619. if (error)
  620. IWL_WARN(priv, "check 24G fields %d | %d\n",
  621. counter++, error);
  622. } else {
  623. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  624. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  625. if (error)
  626. IWL_WARN(priv, "check 52 fields %d | %d\n",
  627. counter++, error);
  628. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  629. if (error)
  630. IWL_WARN(priv, "check 52 CCK %d | %d\n",
  631. counter++, error);
  632. }
  633. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  634. if (error)
  635. IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
  636. /* make sure basic rates 6Mbps and 1Mbps are supported */
  637. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  638. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  639. if (error)
  640. IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
  641. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  642. if (error)
  643. IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
  644. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  645. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  646. if (error)
  647. IWL_WARN(priv, "check CCK and short slot %d | %d\n",
  648. counter++, error);
  649. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  650. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  651. if (error)
  652. IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
  653. counter++, error);
  654. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  655. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  656. if (error)
  657. IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
  658. counter++, error);
  659. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  660. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  661. RXON_FLG_ANT_A_MSK)) == 0);
  662. if (error)
  663. IWL_WARN(priv, "check antenna %d %d\n", counter++, error);
  664. if (error)
  665. IWL_WARN(priv, "Tuning to channel %d\n",
  666. le16_to_cpu(rxon->channel));
  667. if (error) {
  668. IWL_ERR(priv, "Not a valid rxon_assoc_cmd field values\n");
  669. return -1;
  670. }
  671. return 0;
  672. }
  673. /**
  674. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  675. * @priv: staging_rxon is compared to active_rxon
  676. *
  677. * If the RXON structure is changing enough to require a new tune,
  678. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  679. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  680. */
  681. static int iwl3945_full_rxon_required(struct iwl_priv *priv)
  682. {
  683. /* These items are only settable from the full RXON command */
  684. if (!(iwl3945_is_associated(priv)) ||
  685. compare_ether_addr(priv->staging39_rxon.bssid_addr,
  686. priv->active39_rxon.bssid_addr) ||
  687. compare_ether_addr(priv->staging39_rxon.node_addr,
  688. priv->active39_rxon.node_addr) ||
  689. compare_ether_addr(priv->staging39_rxon.wlap_bssid_addr,
  690. priv->active39_rxon.wlap_bssid_addr) ||
  691. (priv->staging39_rxon.dev_type != priv->active39_rxon.dev_type) ||
  692. (priv->staging39_rxon.channel != priv->active39_rxon.channel) ||
  693. (priv->staging39_rxon.air_propagation !=
  694. priv->active39_rxon.air_propagation) ||
  695. (priv->staging39_rxon.assoc_id != priv->active39_rxon.assoc_id))
  696. return 1;
  697. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  698. * be updated with the RXON_ASSOC command -- however only some
  699. * flag transitions are allowed using RXON_ASSOC */
  700. /* Check if we are not switching bands */
  701. if ((priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  702. (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK))
  703. return 1;
  704. /* Check if we are switching association toggle */
  705. if ((priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  706. (priv->active39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  707. return 1;
  708. return 0;
  709. }
  710. static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
  711. {
  712. int rc = 0;
  713. struct iwl_rx_packet *res = NULL;
  714. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  715. struct iwl_host_cmd cmd = {
  716. .id = REPLY_RXON_ASSOC,
  717. .len = sizeof(rxon_assoc),
  718. .meta.flags = CMD_WANT_SKB,
  719. .data = &rxon_assoc,
  720. };
  721. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging39_rxon;
  722. const struct iwl3945_rxon_cmd *rxon2 = &priv->active39_rxon;
  723. if ((rxon1->flags == rxon2->flags) &&
  724. (rxon1->filter_flags == rxon2->filter_flags) &&
  725. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  726. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  727. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  728. return 0;
  729. }
  730. rxon_assoc.flags = priv->staging39_rxon.flags;
  731. rxon_assoc.filter_flags = priv->staging39_rxon.filter_flags;
  732. rxon_assoc.ofdm_basic_rates = priv->staging39_rxon.ofdm_basic_rates;
  733. rxon_assoc.cck_basic_rates = priv->staging39_rxon.cck_basic_rates;
  734. rxon_assoc.reserved = 0;
  735. rc = iwl3945_send_cmd_sync(priv, &cmd);
  736. if (rc)
  737. return rc;
  738. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  739. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  740. IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
  741. rc = -EIO;
  742. }
  743. priv->alloc_rxb_skb--;
  744. dev_kfree_skb_any(cmd.meta.u.skb);
  745. return rc;
  746. }
  747. /**
  748. * iwl3945_commit_rxon - commit staging_rxon to hardware
  749. *
  750. * The RXON command in staging_rxon is committed to the hardware and
  751. * the active_rxon structure is updated with the new data. This
  752. * function correctly transitions out of the RXON_ASSOC_MSK state if
  753. * a HW tune is required based on the RXON structure changes.
  754. */
  755. static int iwl3945_commit_rxon(struct iwl_priv *priv)
  756. {
  757. /* cast away the const for active_rxon in this function */
  758. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active39_rxon;
  759. int rc = 0;
  760. if (!iwl_is_alive(priv))
  761. return -1;
  762. /* always get timestamp with Rx frame */
  763. priv->staging39_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  764. /* select antenna */
  765. priv->staging39_rxon.flags &=
  766. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  767. priv->staging39_rxon.flags |= iwl3945_get_antenna_flags(priv);
  768. rc = iwl3945_check_rxon_cmd(priv);
  769. if (rc) {
  770. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  771. return -EINVAL;
  772. }
  773. /* If we don't need to send a full RXON, we can use
  774. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  775. * and other flags for the current radio configuration. */
  776. if (!iwl3945_full_rxon_required(priv)) {
  777. rc = iwl3945_send_rxon_assoc(priv);
  778. if (rc) {
  779. IWL_ERR(priv, "Error setting RXON_ASSOC "
  780. "configuration (%d).\n", rc);
  781. return rc;
  782. }
  783. memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
  784. return 0;
  785. }
  786. /* If we are currently associated and the new config requires
  787. * an RXON_ASSOC and the new config wants the associated mask enabled,
  788. * we must clear the associated from the active configuration
  789. * before we apply the new config */
  790. if (iwl3945_is_associated(priv) &&
  791. (priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  792. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  793. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  794. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  795. sizeof(struct iwl3945_rxon_cmd),
  796. &priv->active39_rxon);
  797. /* If the mask clearing failed then we set
  798. * active_rxon back to what it was previously */
  799. if (rc) {
  800. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  801. IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
  802. "configuration (%d).\n", rc);
  803. return rc;
  804. }
  805. }
  806. IWL_DEBUG_INFO("Sending RXON\n"
  807. "* with%s RXON_FILTER_ASSOC_MSK\n"
  808. "* channel = %d\n"
  809. "* bssid = %pM\n",
  810. ((priv->staging39_rxon.filter_flags &
  811. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  812. le16_to_cpu(priv->staging39_rxon.channel),
  813. priv->staging_rxon.bssid_addr);
  814. /* Apply the new configuration */
  815. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  816. sizeof(struct iwl3945_rxon_cmd), &priv->staging39_rxon);
  817. if (rc) {
  818. IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
  819. return rc;
  820. }
  821. memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
  822. iwl3945_clear_stations_table(priv);
  823. /* If we issue a new RXON command which required a tune then we must
  824. * send a new TXPOWER command or we won't be able to Tx any frames */
  825. rc = iwl3945_hw_reg_send_txpower(priv);
  826. if (rc) {
  827. IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
  828. return rc;
  829. }
  830. /* Add the broadcast address so we can send broadcast frames */
  831. if (iwl3945_add_station(priv, iwl_bcast_addr, 0, 0) ==
  832. IWL_INVALID_STATION) {
  833. IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
  834. return -EIO;
  835. }
  836. /* If we have set the ASSOC_MSK and we are in BSS mode then
  837. * add the IWL_AP_ID to the station rate table */
  838. if (iwl3945_is_associated(priv) &&
  839. (priv->iw_mode == NL80211_IFTYPE_STATION))
  840. if (iwl3945_add_station(priv, priv->active39_rxon.bssid_addr, 1, 0)
  841. == IWL_INVALID_STATION) {
  842. IWL_ERR(priv, "Error adding AP address for transmit\n");
  843. return -EIO;
  844. }
  845. /* Init the hardware's rate fallback order based on the band */
  846. rc = iwl3945_init_hw_rate_table(priv);
  847. if (rc) {
  848. IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
  849. return -EIO;
  850. }
  851. return 0;
  852. }
  853. static int iwl3945_send_bt_config(struct iwl_priv *priv)
  854. {
  855. struct iwl_bt_cmd bt_cmd = {
  856. .flags = 3,
  857. .lead_time = 0xAA,
  858. .max_kill = 1,
  859. .kill_ack_mask = 0,
  860. .kill_cts_mask = 0,
  861. };
  862. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  863. sizeof(bt_cmd), &bt_cmd);
  864. }
  865. static int iwl3945_send_scan_abort(struct iwl_priv *priv)
  866. {
  867. int rc = 0;
  868. struct iwl_rx_packet *res;
  869. struct iwl_host_cmd cmd = {
  870. .id = REPLY_SCAN_ABORT_CMD,
  871. .meta.flags = CMD_WANT_SKB,
  872. };
  873. /* If there isn't a scan actively going on in the hardware
  874. * then we are in between scan bands and not actually
  875. * actively scanning, so don't send the abort command */
  876. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  877. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  878. return 0;
  879. }
  880. rc = iwl3945_send_cmd_sync(priv, &cmd);
  881. if (rc) {
  882. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  883. return rc;
  884. }
  885. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  886. if (res->u.status != CAN_ABORT_STATUS) {
  887. /* The scan abort will return 1 for success or
  888. * 2 for "failure". A failure condition can be
  889. * due to simply not being in an active scan which
  890. * can occur if we send the scan abort before we
  891. * the microcode has notified us that a scan is
  892. * completed. */
  893. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  894. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  895. clear_bit(STATUS_SCAN_HW, &priv->status);
  896. }
  897. dev_kfree_skb_any(cmd.meta.u.skb);
  898. return rc;
  899. }
  900. static int iwl3945_add_sta_sync_callback(struct iwl_priv *priv,
  901. struct iwl_cmd *cmd, struct sk_buff *skb)
  902. {
  903. struct iwl_rx_packet *res = NULL;
  904. if (!skb) {
  905. IWL_ERR(priv, "Error: Response NULL in REPLY_ADD_STA.\n");
  906. return 1;
  907. }
  908. res = (struct iwl_rx_packet *)skb->data;
  909. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  910. IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n",
  911. res->hdr.flags);
  912. return 1;
  913. }
  914. switch (res->u.add_sta.status) {
  915. case ADD_STA_SUCCESS_MSK:
  916. break;
  917. default:
  918. break;
  919. }
  920. /* We didn't cache the SKB; let the caller free it */
  921. return 1;
  922. }
  923. int iwl3945_send_add_station(struct iwl_priv *priv,
  924. struct iwl3945_addsta_cmd *sta, u8 flags)
  925. {
  926. struct iwl_rx_packet *res = NULL;
  927. int rc = 0;
  928. struct iwl_host_cmd cmd = {
  929. .id = REPLY_ADD_STA,
  930. .len = sizeof(struct iwl3945_addsta_cmd),
  931. .meta.flags = flags,
  932. .data = sta,
  933. };
  934. if (flags & CMD_ASYNC)
  935. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  936. else
  937. cmd.meta.flags |= CMD_WANT_SKB;
  938. rc = iwl3945_send_cmd(priv, &cmd);
  939. if (rc || (flags & CMD_ASYNC))
  940. return rc;
  941. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  942. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  943. IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n",
  944. res->hdr.flags);
  945. rc = -EIO;
  946. }
  947. if (rc == 0) {
  948. switch (res->u.add_sta.status) {
  949. case ADD_STA_SUCCESS_MSK:
  950. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  951. break;
  952. default:
  953. rc = -EIO;
  954. IWL_WARN(priv, "REPLY_ADD_STA failed\n");
  955. break;
  956. }
  957. }
  958. priv->alloc_rxb_skb--;
  959. dev_kfree_skb_any(cmd.meta.u.skb);
  960. return rc;
  961. }
  962. static int iwl3945_update_sta_key_info(struct iwl_priv *priv,
  963. struct ieee80211_key_conf *keyconf,
  964. u8 sta_id)
  965. {
  966. unsigned long flags;
  967. __le16 key_flags = 0;
  968. switch (keyconf->alg) {
  969. case ALG_CCMP:
  970. key_flags |= STA_KEY_FLG_CCMP;
  971. key_flags |= cpu_to_le16(
  972. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  973. key_flags &= ~STA_KEY_FLG_INVALID;
  974. break;
  975. case ALG_TKIP:
  976. case ALG_WEP:
  977. default:
  978. return -EINVAL;
  979. }
  980. spin_lock_irqsave(&priv->sta_lock, flags);
  981. priv->stations_39[sta_id].keyinfo.alg = keyconf->alg;
  982. priv->stations_39[sta_id].keyinfo.keylen = keyconf->keylen;
  983. memcpy(priv->stations_39[sta_id].keyinfo.key, keyconf->key,
  984. keyconf->keylen);
  985. memcpy(priv->stations_39[sta_id].sta.key.key, keyconf->key,
  986. keyconf->keylen);
  987. priv->stations_39[sta_id].sta.key.key_flags = key_flags;
  988. priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  989. priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  990. spin_unlock_irqrestore(&priv->sta_lock, flags);
  991. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  992. iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
  993. return 0;
  994. }
  995. static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
  996. {
  997. unsigned long flags;
  998. spin_lock_irqsave(&priv->sta_lock, flags);
  999. memset(&priv->stations_39[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1000. memset(&priv->stations_39[sta_id].sta.key, 0,
  1001. sizeof(struct iwl4965_keyinfo));
  1002. priv->stations_39[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1003. priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1004. priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1005. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1006. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1007. iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
  1008. return 0;
  1009. }
  1010. static void iwl3945_clear_free_frames(struct iwl_priv *priv)
  1011. {
  1012. struct list_head *element;
  1013. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1014. priv->frames_count);
  1015. while (!list_empty(&priv->free_frames)) {
  1016. element = priv->free_frames.next;
  1017. list_del(element);
  1018. kfree(list_entry(element, struct iwl3945_frame, list));
  1019. priv->frames_count--;
  1020. }
  1021. if (priv->frames_count) {
  1022. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  1023. priv->frames_count);
  1024. priv->frames_count = 0;
  1025. }
  1026. }
  1027. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
  1028. {
  1029. struct iwl3945_frame *frame;
  1030. struct list_head *element;
  1031. if (list_empty(&priv->free_frames)) {
  1032. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1033. if (!frame) {
  1034. IWL_ERR(priv, "Could not allocate frame!\n");
  1035. return NULL;
  1036. }
  1037. priv->frames_count++;
  1038. return frame;
  1039. }
  1040. element = priv->free_frames.next;
  1041. list_del(element);
  1042. return list_entry(element, struct iwl3945_frame, list);
  1043. }
  1044. static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
  1045. {
  1046. memset(frame, 0, sizeof(*frame));
  1047. list_add(&frame->list, &priv->free_frames);
  1048. }
  1049. unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
  1050. struct ieee80211_hdr *hdr,
  1051. int left)
  1052. {
  1053. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1054. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  1055. (priv->iw_mode != NL80211_IFTYPE_AP)))
  1056. return 0;
  1057. if (priv->ibss_beacon->len > left)
  1058. return 0;
  1059. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1060. return priv->ibss_beacon->len;
  1061. }
  1062. static u8 iwl3945_rate_get_lowest_plcp(struct iwl_priv *priv)
  1063. {
  1064. u8 i;
  1065. int rate_mask;
  1066. /* Set rate mask*/
  1067. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1068. rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
  1069. else
  1070. rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
  1071. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1072. i = iwl3945_rates[i].next_ieee) {
  1073. if (rate_mask & (1 << i))
  1074. return iwl3945_rates[i].plcp;
  1075. }
  1076. /* No valid rate was found. Assign the lowest one */
  1077. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1078. return IWL_RATE_1M_PLCP;
  1079. else
  1080. return IWL_RATE_6M_PLCP;
  1081. }
  1082. static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
  1083. {
  1084. struct iwl3945_frame *frame;
  1085. unsigned int frame_size;
  1086. int rc;
  1087. u8 rate;
  1088. frame = iwl3945_get_free_frame(priv);
  1089. if (!frame) {
  1090. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  1091. "command.\n");
  1092. return -ENOMEM;
  1093. }
  1094. rate = iwl3945_rate_get_lowest_plcp(priv);
  1095. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1096. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1097. &frame->u.cmd[0]);
  1098. iwl3945_free_frame(priv, frame);
  1099. return rc;
  1100. }
  1101. /******************************************************************************
  1102. *
  1103. * EEPROM related functions
  1104. *
  1105. ******************************************************************************/
  1106. static void get_eeprom_mac(struct iwl_priv *priv, u8 *mac)
  1107. {
  1108. memcpy(mac, priv->eeprom39.mac_address, 6);
  1109. }
  1110. /*
  1111. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1112. * embedded controller) as EEPROM reader; each read is a series of pulses
  1113. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1114. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1115. * simply claims ownership, which should be safe when this function is called
  1116. * (i.e. before loading uCode!).
  1117. */
  1118. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
  1119. {
  1120. _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1121. return 0;
  1122. }
  1123. /**
  1124. * iwl3945_eeprom_init - read EEPROM contents
  1125. *
  1126. * Load the EEPROM contents from adapter into priv->eeprom39
  1127. *
  1128. * NOTE: This routine uses the non-debug IO access functions.
  1129. */
  1130. int iwl3945_eeprom_init(struct iwl_priv *priv)
  1131. {
  1132. u16 *e = (u16 *)&priv->eeprom39;
  1133. u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
  1134. int sz = sizeof(priv->eeprom39);
  1135. int ret;
  1136. u16 addr;
  1137. /* The EEPROM structure has several padding buffers within it
  1138. * and when adding new EEPROM maps is subject to programmer errors
  1139. * which may be very difficult to identify without explicitly
  1140. * checking the resulting size of the eeprom map. */
  1141. BUILD_BUG_ON(sizeof(priv->eeprom39) != IWL_EEPROM_IMAGE_SIZE);
  1142. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1143. IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
  1144. return -ENOENT;
  1145. }
  1146. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1147. ret = iwl3945_eeprom_acquire_semaphore(priv);
  1148. if (ret < 0) {
  1149. IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
  1150. return -ENOENT;
  1151. }
  1152. /* eeprom is an array of 16bit values */
  1153. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1154. u32 r;
  1155. _iwl_write32(priv, CSR_EEPROM_REG,
  1156. CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
  1157. _iwl_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1158. ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
  1159. CSR_EEPROM_REG_READ_VALID_MSK,
  1160. IWL_EEPROM_ACCESS_TIMEOUT);
  1161. if (ret < 0) {
  1162. IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
  1163. return ret;
  1164. }
  1165. r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
  1166. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1167. }
  1168. return 0;
  1169. }
  1170. static void iwl3945_unset_hw_params(struct iwl_priv *priv)
  1171. {
  1172. if (priv->shared_virt)
  1173. pci_free_consistent(priv->pci_dev,
  1174. sizeof(struct iwl3945_shared),
  1175. priv->shared_virt,
  1176. priv->shared_phys);
  1177. }
  1178. /**
  1179. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1180. *
  1181. * return : set the bit for each supported rate insert in ie
  1182. */
  1183. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1184. u16 basic_rate, int *left)
  1185. {
  1186. u16 ret_rates = 0, bit;
  1187. int i;
  1188. u8 *cnt = ie;
  1189. u8 *rates = ie + 1;
  1190. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1191. if (bit & supported_rate) {
  1192. ret_rates |= bit;
  1193. rates[*cnt] = iwl3945_rates[i].ieee |
  1194. ((bit & basic_rate) ? 0x80 : 0x00);
  1195. (*cnt)++;
  1196. (*left)--;
  1197. if ((*left <= 0) ||
  1198. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1199. break;
  1200. }
  1201. }
  1202. return ret_rates;
  1203. }
  1204. /**
  1205. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1206. */
  1207. static u16 iwl3945_fill_probe_req(struct iwl_priv *priv,
  1208. struct ieee80211_mgmt *frame,
  1209. int left)
  1210. {
  1211. int len = 0;
  1212. u8 *pos = NULL;
  1213. u16 active_rates, ret_rates, cck_rates;
  1214. /* Make sure there is enough space for the probe request,
  1215. * two mandatory IEs and the data */
  1216. left -= 24;
  1217. if (left < 0)
  1218. return 0;
  1219. len += 24;
  1220. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1221. memcpy(frame->da, iwl_bcast_addr, ETH_ALEN);
  1222. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1223. memcpy(frame->bssid, iwl_bcast_addr, ETH_ALEN);
  1224. frame->seq_ctrl = 0;
  1225. /* fill in our indirect SSID IE */
  1226. /* ...next IE... */
  1227. left -= 2;
  1228. if (left < 0)
  1229. return 0;
  1230. len += 2;
  1231. pos = &(frame->u.probe_req.variable[0]);
  1232. *pos++ = WLAN_EID_SSID;
  1233. *pos++ = 0;
  1234. /* fill in supported rate */
  1235. /* ...next IE... */
  1236. left -= 2;
  1237. if (left < 0)
  1238. return 0;
  1239. /* ... fill it in... */
  1240. *pos++ = WLAN_EID_SUPP_RATES;
  1241. *pos = 0;
  1242. priv->active_rate = priv->rates_mask;
  1243. active_rates = priv->active_rate;
  1244. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1245. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1246. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1247. priv->active_rate_basic, &left);
  1248. active_rates &= ~ret_rates;
  1249. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1250. priv->active_rate_basic, &left);
  1251. active_rates &= ~ret_rates;
  1252. len += 2 + *pos;
  1253. pos += (*pos) + 1;
  1254. if (active_rates == 0)
  1255. goto fill_end;
  1256. /* fill in supported extended rate */
  1257. /* ...next IE... */
  1258. left -= 2;
  1259. if (left < 0)
  1260. return 0;
  1261. /* ... fill it in... */
  1262. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1263. *pos = 0;
  1264. iwl3945_supported_rate_to_ie(pos, active_rates,
  1265. priv->active_rate_basic, &left);
  1266. if (*pos > 0)
  1267. len += 2 + *pos;
  1268. fill_end:
  1269. return (u16)len;
  1270. }
  1271. /*
  1272. * QoS support
  1273. */
  1274. static int iwl3945_send_qos_params_command(struct iwl_priv *priv,
  1275. struct iwl_qosparam_cmd *qos)
  1276. {
  1277. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1278. sizeof(struct iwl_qosparam_cmd), qos);
  1279. }
  1280. static void iwl3945_activate_qos(struct iwl_priv *priv, u8 force)
  1281. {
  1282. unsigned long flags;
  1283. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1284. return;
  1285. spin_lock_irqsave(&priv->lock, flags);
  1286. priv->qos_data.def_qos_parm.qos_flags = 0;
  1287. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1288. !priv->qos_data.qos_cap.q_AP.txop_request)
  1289. priv->qos_data.def_qos_parm.qos_flags |=
  1290. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1291. if (priv->qos_data.qos_active)
  1292. priv->qos_data.def_qos_parm.qos_flags |=
  1293. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1294. spin_unlock_irqrestore(&priv->lock, flags);
  1295. if (force || iwl3945_is_associated(priv)) {
  1296. IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n",
  1297. priv->qos_data.qos_active);
  1298. iwl3945_send_qos_params_command(priv,
  1299. &(priv->qos_data.def_qos_parm));
  1300. }
  1301. }
  1302. /*
  1303. * Power management (not Tx power!) functions
  1304. */
  1305. #define MSEC_TO_USEC 1024
  1306. #define NOSLP __constant_cpu_to_le16(0), 0, 0
  1307. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
  1308. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1309. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1310. __constant_cpu_to_le32(X1), \
  1311. __constant_cpu_to_le32(X2), \
  1312. __constant_cpu_to_le32(X3), \
  1313. __constant_cpu_to_le32(X4)}
  1314. /* default power management (not Tx power) table values */
  1315. /* for TIM 0-10 */
  1316. static struct iwl_power_vec_entry range_0[IWL39_POWER_AC] = {
  1317. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1318. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1319. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1320. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1321. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1322. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1323. };
  1324. /* for TIM > 10 */
  1325. static struct iwl_power_vec_entry range_1[IWL39_POWER_AC] = {
  1326. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1327. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1328. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1329. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1330. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1331. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1332. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1333. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1334. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1335. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1336. };
  1337. int iwl3945_power_init_handle(struct iwl_priv *priv)
  1338. {
  1339. int rc = 0, i;
  1340. struct iwl3945_power_mgr *pow_data;
  1341. int size = sizeof(struct iwl_power_vec_entry) * IWL39_POWER_AC;
  1342. u16 pci_pm;
  1343. IWL_DEBUG_POWER("Initialize power \n");
  1344. pow_data = &(priv->power_data_39);
  1345. memset(pow_data, 0, sizeof(*pow_data));
  1346. pow_data->active_index = IWL_POWER_RANGE_0;
  1347. pow_data->dtim_val = 0xffff;
  1348. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1349. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1350. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1351. if (rc != 0)
  1352. return 0;
  1353. else {
  1354. struct iwl_powertable_cmd *cmd;
  1355. IWL_DEBUG_POWER("adjust power command flags\n");
  1356. for (i = 0; i < IWL39_POWER_AC; i++) {
  1357. cmd = &pow_data->pwr_range_0[i].cmd;
  1358. if (pci_pm & 0x1)
  1359. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1360. else
  1361. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1362. }
  1363. }
  1364. return rc;
  1365. }
  1366. static int iwl3945_update_power_cmd(struct iwl_priv *priv,
  1367. struct iwl_powertable_cmd *cmd, u32 mode)
  1368. {
  1369. int rc = 0, i;
  1370. u8 skip;
  1371. u32 max_sleep = 0;
  1372. struct iwl_power_vec_entry *range;
  1373. u8 period = 0;
  1374. struct iwl3945_power_mgr *pow_data;
  1375. if (mode > IWL_POWER_INDEX_5) {
  1376. IWL_DEBUG_POWER("Error invalid power mode \n");
  1377. return -1;
  1378. }
  1379. pow_data = &(priv->power_data_39);
  1380. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1381. range = &pow_data->pwr_range_0[0];
  1382. else
  1383. range = &pow_data->pwr_range_1[1];
  1384. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1385. #ifdef IWL_MAC80211_DISABLE
  1386. if (priv->assoc_network != NULL) {
  1387. unsigned long flags;
  1388. period = priv->assoc_network->tim.tim_period;
  1389. }
  1390. #endif /*IWL_MAC80211_DISABLE */
  1391. skip = range[mode].no_dtim;
  1392. if (period == 0) {
  1393. period = 1;
  1394. skip = 0;
  1395. }
  1396. if (skip == 0) {
  1397. max_sleep = period;
  1398. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1399. } else {
  1400. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1401. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1402. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1403. }
  1404. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1405. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1406. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1407. }
  1408. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1409. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1410. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1411. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1412. le32_to_cpu(cmd->sleep_interval[0]),
  1413. le32_to_cpu(cmd->sleep_interval[1]),
  1414. le32_to_cpu(cmd->sleep_interval[2]),
  1415. le32_to_cpu(cmd->sleep_interval[3]),
  1416. le32_to_cpu(cmd->sleep_interval[4]));
  1417. return rc;
  1418. }
  1419. static int iwl3945_send_power_mode(struct iwl_priv *priv, u32 mode)
  1420. {
  1421. u32 uninitialized_var(final_mode);
  1422. int rc;
  1423. struct iwl_powertable_cmd cmd;
  1424. /* If on battery, set to 3,
  1425. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1426. * else user level */
  1427. switch (mode) {
  1428. case IWL39_POWER_BATTERY:
  1429. final_mode = IWL_POWER_INDEX_3;
  1430. break;
  1431. case IWL39_POWER_AC:
  1432. final_mode = IWL_POWER_MODE_CAM;
  1433. break;
  1434. default:
  1435. final_mode = mode;
  1436. break;
  1437. }
  1438. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1439. /* FIXME use get_hcmd_size 3945 command is 4 bytes shorter */
  1440. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD,
  1441. sizeof(struct iwl3945_powertable_cmd), &cmd);
  1442. if (final_mode == IWL_POWER_MODE_CAM)
  1443. clear_bit(STATUS_POWER_PMI, &priv->status);
  1444. else
  1445. set_bit(STATUS_POWER_PMI, &priv->status);
  1446. return rc;
  1447. }
  1448. /**
  1449. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1450. *
  1451. * NOTE: priv->mutex is not required before calling this function
  1452. */
  1453. static int iwl3945_scan_cancel(struct iwl_priv *priv)
  1454. {
  1455. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1456. clear_bit(STATUS_SCANNING, &priv->status);
  1457. return 0;
  1458. }
  1459. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1460. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1461. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1462. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1463. queue_work(priv->workqueue, &priv->abort_scan);
  1464. } else
  1465. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1466. return test_bit(STATUS_SCANNING, &priv->status);
  1467. }
  1468. return 0;
  1469. }
  1470. /**
  1471. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1472. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1473. *
  1474. * NOTE: priv->mutex must be held before calling this function
  1475. */
  1476. static int iwl3945_scan_cancel_timeout(struct iwl_priv *priv, unsigned long ms)
  1477. {
  1478. unsigned long now = jiffies;
  1479. int ret;
  1480. ret = iwl3945_scan_cancel(priv);
  1481. if (ret && ms) {
  1482. mutex_unlock(&priv->mutex);
  1483. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1484. test_bit(STATUS_SCANNING, &priv->status))
  1485. msleep(1);
  1486. mutex_lock(&priv->mutex);
  1487. return test_bit(STATUS_SCANNING, &priv->status);
  1488. }
  1489. return ret;
  1490. }
  1491. #define MAX_UCODE_BEACON_INTERVAL 1024
  1492. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1493. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1494. {
  1495. u16 new_val = 0;
  1496. u16 beacon_factor = 0;
  1497. beacon_factor =
  1498. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1499. / MAX_UCODE_BEACON_INTERVAL;
  1500. new_val = beacon_val / beacon_factor;
  1501. return cpu_to_le16(new_val);
  1502. }
  1503. static void iwl3945_setup_rxon_timing(struct iwl_priv *priv)
  1504. {
  1505. u64 interval_tm_unit;
  1506. u64 tsf, result;
  1507. unsigned long flags;
  1508. struct ieee80211_conf *conf = NULL;
  1509. u16 beacon_int = 0;
  1510. conf = ieee80211_get_hw_conf(priv->hw);
  1511. spin_lock_irqsave(&priv->lock, flags);
  1512. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  1513. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1514. tsf = priv->timestamp;
  1515. beacon_int = priv->beacon_int;
  1516. spin_unlock_irqrestore(&priv->lock, flags);
  1517. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  1518. if (beacon_int == 0) {
  1519. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1520. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1521. } else {
  1522. priv->rxon_timing.beacon_interval =
  1523. cpu_to_le16(beacon_int);
  1524. priv->rxon_timing.beacon_interval =
  1525. iwl3945_adjust_beacon_interval(
  1526. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1527. }
  1528. priv->rxon_timing.atim_window = 0;
  1529. } else {
  1530. priv->rxon_timing.beacon_interval =
  1531. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1532. /* TODO: we need to get atim_window from upper stack
  1533. * for now we set to 0 */
  1534. priv->rxon_timing.atim_window = 0;
  1535. }
  1536. interval_tm_unit =
  1537. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1538. result = do_div(tsf, interval_tm_unit);
  1539. priv->rxon_timing.beacon_init_val =
  1540. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1541. IWL_DEBUG_ASSOC
  1542. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1543. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1544. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1545. le16_to_cpu(priv->rxon_timing.atim_window));
  1546. }
  1547. static int iwl3945_scan_initiate(struct iwl_priv *priv)
  1548. {
  1549. if (!iwl_is_ready_rf(priv)) {
  1550. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1551. return -EIO;
  1552. }
  1553. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1554. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1555. return -EAGAIN;
  1556. }
  1557. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1558. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1559. "Queuing.\n");
  1560. return -EAGAIN;
  1561. }
  1562. IWL_DEBUG_INFO("Starting scan...\n");
  1563. if (priv->cfg->sku & IWL_SKU_G)
  1564. priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
  1565. if (priv->cfg->sku & IWL_SKU_A)
  1566. priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
  1567. set_bit(STATUS_SCANNING, &priv->status);
  1568. priv->scan_start = jiffies;
  1569. priv->scan_pass_start = priv->scan_start;
  1570. queue_work(priv->workqueue, &priv->request_scan);
  1571. return 0;
  1572. }
  1573. static int iwl3945_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
  1574. {
  1575. struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
  1576. if (hw_decrypt)
  1577. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1578. else
  1579. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1580. return 0;
  1581. }
  1582. static void iwl3945_set_flags_for_phymode(struct iwl_priv *priv,
  1583. enum ieee80211_band band)
  1584. {
  1585. if (band == IEEE80211_BAND_5GHZ) {
  1586. priv->staging39_rxon.flags &=
  1587. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1588. | RXON_FLG_CCK_MSK);
  1589. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1590. } else {
  1591. /* Copied from iwl3945_bg_post_associate() */
  1592. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1593. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1594. else
  1595. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1596. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1597. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1598. priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1599. priv->staging39_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1600. priv->staging39_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1601. }
  1602. }
  1603. /*
  1604. * initialize rxon structure with default values from eeprom
  1605. */
  1606. static void iwl3945_connection_init_rx_config(struct iwl_priv *priv,
  1607. int mode)
  1608. {
  1609. const struct iwl_channel_info *ch_info;
  1610. memset(&priv->staging39_rxon, 0, sizeof(priv->staging39_rxon));
  1611. switch (mode) {
  1612. case NL80211_IFTYPE_AP:
  1613. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_AP;
  1614. break;
  1615. case NL80211_IFTYPE_STATION:
  1616. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1617. priv->staging39_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1618. break;
  1619. case NL80211_IFTYPE_ADHOC:
  1620. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1621. priv->staging39_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1622. priv->staging39_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1623. RXON_FILTER_ACCEPT_GRP_MSK;
  1624. break;
  1625. case NL80211_IFTYPE_MONITOR:
  1626. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1627. priv->staging39_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1628. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1629. break;
  1630. default:
  1631. IWL_ERR(priv, "Unsupported interface type %d\n", mode);
  1632. break;
  1633. }
  1634. #if 0
  1635. /* TODO: Figure out when short_preamble would be set and cache from
  1636. * that */
  1637. if (!hw_to_local(priv->hw)->short_preamble)
  1638. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1639. else
  1640. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1641. #endif
  1642. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1643. le16_to_cpu(priv->active39_rxon.channel));
  1644. if (!ch_info)
  1645. ch_info = &priv->channel_info[0];
  1646. /*
  1647. * in some case A channels are all non IBSS
  1648. * in this case force B/G channel
  1649. */
  1650. if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info)))
  1651. ch_info = &priv->channel_info[0];
  1652. priv->staging39_rxon.channel = cpu_to_le16(ch_info->channel);
  1653. if (is_channel_a_band(ch_info))
  1654. priv->band = IEEE80211_BAND_5GHZ;
  1655. else
  1656. priv->band = IEEE80211_BAND_2GHZ;
  1657. iwl3945_set_flags_for_phymode(priv, priv->band);
  1658. priv->staging39_rxon.ofdm_basic_rates =
  1659. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1660. priv->staging39_rxon.cck_basic_rates =
  1661. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1662. }
  1663. static int iwl3945_set_mode(struct iwl_priv *priv, int mode)
  1664. {
  1665. if (mode == NL80211_IFTYPE_ADHOC) {
  1666. const struct iwl_channel_info *ch_info;
  1667. ch_info = iwl3945_get_channel_info(priv,
  1668. priv->band,
  1669. le16_to_cpu(priv->staging39_rxon.channel));
  1670. if (!ch_info || !is_channel_ibss(ch_info)) {
  1671. IWL_ERR(priv, "channel %d not IBSS channel\n",
  1672. le16_to_cpu(priv->staging39_rxon.channel));
  1673. return -EINVAL;
  1674. }
  1675. }
  1676. iwl3945_connection_init_rx_config(priv, mode);
  1677. memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1678. iwl3945_clear_stations_table(priv);
  1679. /* don't commit rxon if rf-kill is on*/
  1680. if (!iwl_is_ready_rf(priv))
  1681. return -EAGAIN;
  1682. cancel_delayed_work(&priv->scan_check);
  1683. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  1684. IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
  1685. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  1686. return -EAGAIN;
  1687. }
  1688. iwl3945_commit_rxon(priv);
  1689. return 0;
  1690. }
  1691. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
  1692. struct ieee80211_tx_info *info,
  1693. struct iwl_cmd *cmd,
  1694. struct sk_buff *skb_frag,
  1695. int last_frag)
  1696. {
  1697. struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
  1698. struct iwl3945_hw_key *keyinfo =
  1699. &priv->stations_39[info->control.hw_key->hw_key_idx].keyinfo;
  1700. switch (keyinfo->alg) {
  1701. case ALG_CCMP:
  1702. tx->sec_ctl = TX_CMD_SEC_CCM;
  1703. memcpy(tx->key, keyinfo->key, keyinfo->keylen);
  1704. IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
  1705. break;
  1706. case ALG_TKIP:
  1707. #if 0
  1708. tx->sec_ctl = TX_CMD_SEC_TKIP;
  1709. if (last_frag)
  1710. memcpy(tx->tkip_mic.byte, skb_frag->tail - 8,
  1711. 8);
  1712. else
  1713. memset(tx->tkip_mic.byte, 0, 8);
  1714. #endif
  1715. break;
  1716. case ALG_WEP:
  1717. tx->sec_ctl = TX_CMD_SEC_WEP |
  1718. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  1719. if (keyinfo->keylen == 13)
  1720. tx->sec_ctl |= TX_CMD_SEC_KEY128;
  1721. memcpy(&tx->key[3], keyinfo->key, keyinfo->keylen);
  1722. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  1723. "with key %d\n", info->control.hw_key->hw_key_idx);
  1724. break;
  1725. default:
  1726. IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
  1727. break;
  1728. }
  1729. }
  1730. /*
  1731. * handle build REPLY_TX command notification.
  1732. */
  1733. static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
  1734. struct iwl_cmd *cmd,
  1735. struct ieee80211_tx_info *info,
  1736. struct ieee80211_hdr *hdr, u8 std_id)
  1737. {
  1738. struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
  1739. __le32 tx_flags = tx->tx_flags;
  1740. __le16 fc = hdr->frame_control;
  1741. u8 rc_flags = info->control.rates[0].flags;
  1742. tx->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1743. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  1744. tx_flags |= TX_CMD_FLG_ACK_MSK;
  1745. if (ieee80211_is_mgmt(fc))
  1746. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1747. if (ieee80211_is_probe_resp(fc) &&
  1748. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  1749. tx_flags |= TX_CMD_FLG_TSF_MSK;
  1750. } else {
  1751. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  1752. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1753. }
  1754. tx->sta_id = std_id;
  1755. if (ieee80211_has_morefrags(fc))
  1756. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  1757. if (ieee80211_is_data_qos(fc)) {
  1758. u8 *qc = ieee80211_get_qos_ctl(hdr);
  1759. tx->tid_tspec = qc[0] & 0xf;
  1760. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  1761. } else {
  1762. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1763. }
  1764. if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  1765. tx_flags |= TX_CMD_FLG_RTS_MSK;
  1766. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  1767. } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  1768. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  1769. tx_flags |= TX_CMD_FLG_CTS_MSK;
  1770. }
  1771. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  1772. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  1773. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  1774. if (ieee80211_is_mgmt(fc)) {
  1775. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  1776. tx->timeout.pm_frame_timeout = cpu_to_le16(3);
  1777. else
  1778. tx->timeout.pm_frame_timeout = cpu_to_le16(2);
  1779. } else {
  1780. tx->timeout.pm_frame_timeout = 0;
  1781. #ifdef CONFIG_IWL3945_LEDS
  1782. priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
  1783. #endif
  1784. }
  1785. tx->driver_txop = 0;
  1786. tx->tx_flags = tx_flags;
  1787. tx->next_frame_len = 0;
  1788. }
  1789. /**
  1790. * iwl3945_get_sta_id - Find station's index within station table
  1791. */
  1792. static int iwl3945_get_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr)
  1793. {
  1794. int sta_id;
  1795. u16 fc = le16_to_cpu(hdr->frame_control);
  1796. /* If this frame is broadcast or management, use broadcast station id */
  1797. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  1798. is_multicast_ether_addr(hdr->addr1))
  1799. return priv->hw_params.bcast_sta_id;
  1800. switch (priv->iw_mode) {
  1801. /* If we are a client station in a BSS network, use the special
  1802. * AP station entry (that's the only station we communicate with) */
  1803. case NL80211_IFTYPE_STATION:
  1804. return IWL_AP_ID;
  1805. /* If we are an AP, then find the station, or use BCAST */
  1806. case NL80211_IFTYPE_AP:
  1807. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  1808. if (sta_id != IWL_INVALID_STATION)
  1809. return sta_id;
  1810. return priv->hw_params.bcast_sta_id;
  1811. /* If this frame is going out to an IBSS network, find the station,
  1812. * or create a new station table entry */
  1813. case NL80211_IFTYPE_ADHOC: {
  1814. /* Create new station table entry */
  1815. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  1816. if (sta_id != IWL_INVALID_STATION)
  1817. return sta_id;
  1818. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  1819. if (sta_id != IWL_INVALID_STATION)
  1820. return sta_id;
  1821. IWL_DEBUG_DROP("Station %pM not in station map. "
  1822. "Defaulting to broadcast...\n",
  1823. hdr->addr1);
  1824. iwl_print_hex_dump(priv, IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  1825. return priv->hw_params.bcast_sta_id;
  1826. }
  1827. /* If we are in monitor mode, use BCAST. This is required for
  1828. * packet injection. */
  1829. case NL80211_IFTYPE_MONITOR:
  1830. return priv->hw_params.bcast_sta_id;
  1831. default:
  1832. IWL_WARN(priv, "Unknown mode of operation: %d\n",
  1833. priv->iw_mode);
  1834. return priv->hw_params.bcast_sta_id;
  1835. }
  1836. }
  1837. /*
  1838. * start REPLY_TX command process
  1839. */
  1840. static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
  1841. {
  1842. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1843. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1844. struct iwl3945_tfd *tfd;
  1845. struct iwl3945_tx_cmd *tx;
  1846. struct iwl_tx_queue *txq = NULL;
  1847. struct iwl_queue *q = NULL;
  1848. struct iwl_cmd *out_cmd = NULL;
  1849. dma_addr_t phys_addr;
  1850. dma_addr_t txcmd_phys;
  1851. int txq_id = skb_get_queue_mapping(skb);
  1852. u16 len, idx, len_org, hdr_len;
  1853. u8 id;
  1854. u8 unicast;
  1855. u8 sta_id;
  1856. u8 tid = 0;
  1857. u16 seq_number = 0;
  1858. __le16 fc;
  1859. u8 wait_write_ptr = 0;
  1860. u8 *qc = NULL;
  1861. unsigned long flags;
  1862. int rc;
  1863. spin_lock_irqsave(&priv->lock, flags);
  1864. if (iwl_is_rfkill(priv)) {
  1865. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  1866. goto drop_unlock;
  1867. }
  1868. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  1869. IWL_ERR(priv, "ERROR: No TX rate available.\n");
  1870. goto drop_unlock;
  1871. }
  1872. unicast = !is_multicast_ether_addr(hdr->addr1);
  1873. id = 0;
  1874. fc = hdr->frame_control;
  1875. #ifdef CONFIG_IWL3945_DEBUG
  1876. if (ieee80211_is_auth(fc))
  1877. IWL_DEBUG_TX("Sending AUTH frame\n");
  1878. else if (ieee80211_is_assoc_req(fc))
  1879. IWL_DEBUG_TX("Sending ASSOC frame\n");
  1880. else if (ieee80211_is_reassoc_req(fc))
  1881. IWL_DEBUG_TX("Sending REASSOC frame\n");
  1882. #endif
  1883. /* drop all data frame if we are not associated */
  1884. if (ieee80211_is_data(fc) &&
  1885. (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
  1886. (!iwl3945_is_associated(priv) ||
  1887. ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
  1888. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  1889. goto drop_unlock;
  1890. }
  1891. spin_unlock_irqrestore(&priv->lock, flags);
  1892. hdr_len = ieee80211_hdrlen(fc);
  1893. /* Find (or create) index into station table for destination station */
  1894. sta_id = iwl3945_get_sta_id(priv, hdr);
  1895. if (sta_id == IWL_INVALID_STATION) {
  1896. IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
  1897. hdr->addr1);
  1898. goto drop;
  1899. }
  1900. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  1901. if (ieee80211_is_data_qos(fc)) {
  1902. qc = ieee80211_get_qos_ctl(hdr);
  1903. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  1904. seq_number = priv->stations_39[sta_id].tid[tid].seq_number &
  1905. IEEE80211_SCTL_SEQ;
  1906. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  1907. (hdr->seq_ctrl &
  1908. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  1909. seq_number += 0x10;
  1910. }
  1911. /* Descriptor for chosen Tx queue */
  1912. txq = &priv->txq[txq_id];
  1913. q = &txq->q;
  1914. spin_lock_irqsave(&priv->lock, flags);
  1915. /* Set up first empty TFD within this queue's circular TFD buffer */
  1916. tfd = &txq->tfds39[q->write_ptr];
  1917. memset(tfd, 0, sizeof(*tfd));
  1918. idx = get_cmd_index(q, q->write_ptr, 0);
  1919. /* Set up driver data for this TFD */
  1920. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
  1921. txq->txb[q->write_ptr].skb[0] = skb;
  1922. /* Init first empty entry in queue's array of Tx/cmd buffers */
  1923. out_cmd = txq->cmd[idx];
  1924. tx = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
  1925. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  1926. memset(tx, 0, sizeof(*tx));
  1927. /*
  1928. * Set up the Tx-command (not MAC!) header.
  1929. * Store the chosen Tx queue and TFD index within the sequence field;
  1930. * after Tx, uCode's Tx response will return this value so driver can
  1931. * locate the frame within the tx queue and do post-tx processing.
  1932. */
  1933. out_cmd->hdr.cmd = REPLY_TX;
  1934. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  1935. INDEX_TO_SEQ(q->write_ptr)));
  1936. /* Copy MAC header from skb into command buffer */
  1937. memcpy(tx->hdr, hdr, hdr_len);
  1938. /*
  1939. * Use the first empty entry in this queue's command buffer array
  1940. * to contain the Tx command and MAC header concatenated together
  1941. * (payload data will be in another buffer).
  1942. * Size of this varies, due to varying MAC header length.
  1943. * If end is not dword aligned, we'll have 2 extra bytes at the end
  1944. * of the MAC header (device reads on dword boundaries).
  1945. * We'll tell device about this padding later.
  1946. */
  1947. len = sizeof(struct iwl3945_tx_cmd) +
  1948. sizeof(struct iwl_cmd_header) + hdr_len;
  1949. len_org = len;
  1950. len = (len + 3) & ~3;
  1951. if (len_org != len)
  1952. len_org = 1;
  1953. else
  1954. len_org = 0;
  1955. /* Physical address of this Tx command's header (not MAC header!),
  1956. * within command buffer array. */
  1957. txcmd_phys = pci_map_single(priv->pci_dev,
  1958. out_cmd, sizeof(struct iwl_cmd),
  1959. PCI_DMA_TODEVICE);
  1960. pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys);
  1961. pci_unmap_len_set(&out_cmd->meta, len, sizeof(struct iwl_cmd));
  1962. /* Add buffer containing Tx command and MAC(!) header to TFD's
  1963. * first entry */
  1964. txcmd_phys += offsetof(struct iwl_cmd, hdr);
  1965. /* Add buffer containing Tx command and MAC(!) header to TFD's
  1966. * first entry */
  1967. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  1968. if (info->control.hw_key)
  1969. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
  1970. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  1971. * if any (802.11 null frames have no payload). */
  1972. len = skb->len - hdr_len;
  1973. if (len) {
  1974. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  1975. len, PCI_DMA_TODEVICE);
  1976. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  1977. }
  1978. if (!len)
  1979. /* If there is no payload, then we use only one Tx buffer */
  1980. tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(1));
  1981. else
  1982. /* Else use 2 buffers.
  1983. * Tell 3945 about any padding after MAC header */
  1984. tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(2) |
  1985. TFD_CTL_PAD_SET(U32_PAD(len)));
  1986. /* Total # bytes to be transmitted */
  1987. len = (u16)skb->len;
  1988. tx->len = cpu_to_le16(len);
  1989. /* TODO need this for burst mode later on */
  1990. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
  1991. /* set is_hcca to 0; it probably will never be implemented */
  1992. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  1993. tx->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  1994. tx->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  1995. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  1996. txq->need_update = 1;
  1997. if (qc)
  1998. priv->stations_39[sta_id].tid[tid].seq_number = seq_number;
  1999. } else {
  2000. wait_write_ptr = 1;
  2001. txq->need_update = 0;
  2002. }
  2003. iwl_print_hex_dump(priv, IWL_DL_TX, tx, sizeof(*tx));
  2004. iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx->hdr,
  2005. ieee80211_hdrlen(fc));
  2006. /* Tell device the write index *just past* this latest filled TFD */
  2007. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  2008. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2009. spin_unlock_irqrestore(&priv->lock, flags);
  2010. if (rc)
  2011. return rc;
  2012. if ((iwl_queue_space(q) < q->high_mark)
  2013. && priv->mac80211_registered) {
  2014. if (wait_write_ptr) {
  2015. spin_lock_irqsave(&priv->lock, flags);
  2016. txq->need_update = 1;
  2017. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2018. spin_unlock_irqrestore(&priv->lock, flags);
  2019. }
  2020. ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
  2021. }
  2022. return 0;
  2023. drop_unlock:
  2024. spin_unlock_irqrestore(&priv->lock, flags);
  2025. drop:
  2026. return -1;
  2027. }
  2028. static void iwl3945_set_rate(struct iwl_priv *priv)
  2029. {
  2030. const struct ieee80211_supported_band *sband = NULL;
  2031. struct ieee80211_rate *rate;
  2032. int i;
  2033. sband = iwl_get_hw_mode(priv, priv->band);
  2034. if (!sband) {
  2035. IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
  2036. return;
  2037. }
  2038. priv->active_rate = 0;
  2039. priv->active_rate_basic = 0;
  2040. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2041. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2042. for (i = 0; i < sband->n_bitrates; i++) {
  2043. rate = &sband->bitrates[i];
  2044. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2045. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2046. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2047. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2048. priv->active_rate |= (1 << rate->hw_value);
  2049. }
  2050. }
  2051. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2052. priv->active_rate, priv->active_rate_basic);
  2053. /*
  2054. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2055. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2056. * OFDM
  2057. */
  2058. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2059. priv->staging39_rxon.cck_basic_rates =
  2060. ((priv->active_rate_basic &
  2061. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2062. else
  2063. priv->staging39_rxon.cck_basic_rates =
  2064. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2065. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2066. priv->staging39_rxon.ofdm_basic_rates =
  2067. ((priv->active_rate_basic &
  2068. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2069. IWL_FIRST_OFDM_RATE) & 0xFF;
  2070. else
  2071. priv->staging39_rxon.ofdm_basic_rates =
  2072. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2073. }
  2074. static void iwl3945_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
  2075. {
  2076. unsigned long flags;
  2077. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2078. return;
  2079. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2080. disable_radio ? "OFF" : "ON");
  2081. if (disable_radio) {
  2082. iwl3945_scan_cancel(priv);
  2083. /* FIXME: This is a workaround for AP */
  2084. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  2085. spin_lock_irqsave(&priv->lock, flags);
  2086. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2087. CSR_UCODE_SW_BIT_RFKILL);
  2088. spin_unlock_irqrestore(&priv->lock, flags);
  2089. iwl_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2090. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2091. }
  2092. return;
  2093. }
  2094. spin_lock_irqsave(&priv->lock, flags);
  2095. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2096. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2097. spin_unlock_irqrestore(&priv->lock, flags);
  2098. /* wake up ucode */
  2099. msleep(10);
  2100. spin_lock_irqsave(&priv->lock, flags);
  2101. iwl_read32(priv, CSR_UCODE_DRV_GP1);
  2102. if (!iwl_grab_nic_access(priv))
  2103. iwl_release_nic_access(priv);
  2104. spin_unlock_irqrestore(&priv->lock, flags);
  2105. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2106. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2107. "disabled by HW switch\n");
  2108. return;
  2109. }
  2110. if (priv->is_open)
  2111. queue_work(priv->workqueue, &priv->restart);
  2112. return;
  2113. }
  2114. void iwl3945_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb,
  2115. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2116. {
  2117. u16 fc =
  2118. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2119. if (priv->active39_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2120. return;
  2121. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2122. return;
  2123. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2124. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2125. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2126. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2127. RX_RES_STATUS_BAD_ICV_MIC)
  2128. stats->flag |= RX_FLAG_MMIC_ERROR;
  2129. case RX_RES_STATUS_SEC_TYPE_WEP:
  2130. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2131. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2132. RX_RES_STATUS_DECRYPT_OK) {
  2133. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2134. stats->flag |= RX_FLAG_DECRYPTED;
  2135. }
  2136. break;
  2137. default:
  2138. break;
  2139. }
  2140. }
  2141. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2142. #include "iwl-spectrum.h"
  2143. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2144. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2145. #define TIME_UNIT 1024
  2146. /*
  2147. * extended beacon time format
  2148. * time in usec will be changed into a 32-bit value in 8:24 format
  2149. * the high 1 byte is the beacon counts
  2150. * the lower 3 bytes is the time in usec within one beacon interval
  2151. */
  2152. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2153. {
  2154. u32 quot;
  2155. u32 rem;
  2156. u32 interval = beacon_interval * 1024;
  2157. if (!interval || !usec)
  2158. return 0;
  2159. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2160. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2161. return (quot << 24) + rem;
  2162. }
  2163. /* base is usually what we get from ucode with each received frame,
  2164. * the same as HW timer counter counting down
  2165. */
  2166. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2167. {
  2168. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2169. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2170. u32 interval = beacon_interval * TIME_UNIT;
  2171. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2172. (addon & BEACON_TIME_MASK_HIGH);
  2173. if (base_low > addon_low)
  2174. res += base_low - addon_low;
  2175. else if (base_low < addon_low) {
  2176. res += interval + base_low - addon_low;
  2177. res += (1 << 24);
  2178. } else
  2179. res += (1 << 24);
  2180. return cpu_to_le32(res);
  2181. }
  2182. static int iwl3945_get_measurement(struct iwl_priv *priv,
  2183. struct ieee80211_measurement_params *params,
  2184. u8 type)
  2185. {
  2186. struct iwl_spectrum_cmd spectrum;
  2187. struct iwl_rx_packet *res;
  2188. struct iwl_host_cmd cmd = {
  2189. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2190. .data = (void *)&spectrum,
  2191. .meta.flags = CMD_WANT_SKB,
  2192. };
  2193. u32 add_time = le64_to_cpu(params->start_time);
  2194. int rc;
  2195. int spectrum_resp_status;
  2196. int duration = le16_to_cpu(params->duration);
  2197. if (iwl3945_is_associated(priv))
  2198. add_time =
  2199. iwl3945_usecs_to_beacons(
  2200. le64_to_cpu(params->start_time) - priv->last_tsf,
  2201. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2202. memset(&spectrum, 0, sizeof(spectrum));
  2203. spectrum.channel_count = cpu_to_le16(1);
  2204. spectrum.flags =
  2205. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2206. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2207. cmd.len = sizeof(spectrum);
  2208. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2209. if (iwl3945_is_associated(priv))
  2210. spectrum.start_time =
  2211. iwl3945_add_beacon_time(priv->last_beacon_time,
  2212. add_time,
  2213. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2214. else
  2215. spectrum.start_time = 0;
  2216. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2217. spectrum.channels[0].channel = params->channel;
  2218. spectrum.channels[0].type = type;
  2219. if (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2220. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2221. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2222. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2223. if (rc)
  2224. return rc;
  2225. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  2226. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2227. IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
  2228. rc = -EIO;
  2229. }
  2230. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2231. switch (spectrum_resp_status) {
  2232. case 0: /* Command will be handled */
  2233. if (res->u.spectrum.id != 0xff) {
  2234. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2235. res->u.spectrum.id);
  2236. priv->measurement_status &= ~MEASUREMENT_READY;
  2237. }
  2238. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2239. rc = 0;
  2240. break;
  2241. case 1: /* Command will not be handled */
  2242. rc = -EAGAIN;
  2243. break;
  2244. }
  2245. dev_kfree_skb_any(cmd.meta.u.skb);
  2246. return rc;
  2247. }
  2248. #endif
  2249. static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
  2250. struct iwl_rx_mem_buffer *rxb)
  2251. {
  2252. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2253. struct iwl_alive_resp *palive;
  2254. struct delayed_work *pwork;
  2255. palive = &pkt->u.alive_frame;
  2256. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2257. "0x%01X 0x%01X\n",
  2258. palive->is_valid, palive->ver_type,
  2259. palive->ver_subtype);
  2260. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2261. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2262. memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
  2263. sizeof(struct iwl_alive_resp));
  2264. pwork = &priv->init_alive_start;
  2265. } else {
  2266. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2267. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2268. sizeof(struct iwl_alive_resp));
  2269. pwork = &priv->alive_start;
  2270. iwl3945_disable_events(priv);
  2271. }
  2272. /* We delay the ALIVE response by 5ms to
  2273. * give the HW RF Kill time to activate... */
  2274. if (palive->is_valid == UCODE_VALID_OK)
  2275. queue_delayed_work(priv->workqueue, pwork,
  2276. msecs_to_jiffies(5));
  2277. else
  2278. IWL_WARN(priv, "uCode did not respond OK.\n");
  2279. }
  2280. static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
  2281. struct iwl_rx_mem_buffer *rxb)
  2282. {
  2283. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2284. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2285. return;
  2286. }
  2287. static void iwl3945_rx_reply_error(struct iwl_priv *priv,
  2288. struct iwl_rx_mem_buffer *rxb)
  2289. {
  2290. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2291. IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
  2292. "seq 0x%04X ser 0x%08X\n",
  2293. le32_to_cpu(pkt->u.err_resp.error_type),
  2294. get_cmd_string(pkt->u.err_resp.cmd_id),
  2295. pkt->u.err_resp.cmd_id,
  2296. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2297. le32_to_cpu(pkt->u.err_resp.error_info));
  2298. }
  2299. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2300. static void iwl3945_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  2301. {
  2302. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2303. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active39_rxon;
  2304. struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
  2305. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2306. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2307. rxon->channel = csa->channel;
  2308. priv->staging39_rxon.channel = csa->channel;
  2309. }
  2310. static void iwl3945_rx_spectrum_measure_notif(struct iwl_priv *priv,
  2311. struct iwl_rx_mem_buffer *rxb)
  2312. {
  2313. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2314. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2315. struct iwl_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2316. if (!report->state) {
  2317. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2318. "Spectrum Measure Notification: Start\n");
  2319. return;
  2320. }
  2321. memcpy(&priv->measure_report, report, sizeof(*report));
  2322. priv->measurement_status |= MEASUREMENT_READY;
  2323. #endif
  2324. }
  2325. static void iwl3945_rx_pm_sleep_notif(struct iwl_priv *priv,
  2326. struct iwl_rx_mem_buffer *rxb)
  2327. {
  2328. #ifdef CONFIG_IWL3945_DEBUG
  2329. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2330. struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2331. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2332. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2333. #endif
  2334. }
  2335. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
  2336. struct iwl_rx_mem_buffer *rxb)
  2337. {
  2338. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2339. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2340. "notification for %s:\n",
  2341. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2342. iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw,
  2343. le32_to_cpu(pkt->len));
  2344. }
  2345. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2346. {
  2347. struct iwl_priv *priv =
  2348. container_of(work, struct iwl_priv, beacon_update);
  2349. struct sk_buff *beacon;
  2350. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2351. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  2352. if (!beacon) {
  2353. IWL_ERR(priv, "update beacon failed\n");
  2354. return;
  2355. }
  2356. mutex_lock(&priv->mutex);
  2357. /* new beacon skb is allocated every time; dispose previous.*/
  2358. if (priv->ibss_beacon)
  2359. dev_kfree_skb(priv->ibss_beacon);
  2360. priv->ibss_beacon = beacon;
  2361. mutex_unlock(&priv->mutex);
  2362. iwl3945_send_beacon_cmd(priv);
  2363. }
  2364. static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
  2365. struct iwl_rx_mem_buffer *rxb)
  2366. {
  2367. #ifdef CONFIG_IWL3945_DEBUG
  2368. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2369. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2370. u8 rate = beacon->beacon_notify_hdr.rate;
  2371. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2372. "tsf %d %d rate %d\n",
  2373. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2374. beacon->beacon_notify_hdr.failure_frame,
  2375. le32_to_cpu(beacon->ibss_mgr_status),
  2376. le32_to_cpu(beacon->high_tsf),
  2377. le32_to_cpu(beacon->low_tsf), rate);
  2378. #endif
  2379. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  2380. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2381. queue_work(priv->workqueue, &priv->beacon_update);
  2382. }
  2383. /* Service response to REPLY_SCAN_CMD (0x80) */
  2384. static void iwl3945_rx_reply_scan(struct iwl_priv *priv,
  2385. struct iwl_rx_mem_buffer *rxb)
  2386. {
  2387. #ifdef CONFIG_IWL3945_DEBUG
  2388. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2389. struct iwl_scanreq_notification *notif =
  2390. (struct iwl_scanreq_notification *)pkt->u.raw;
  2391. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  2392. #endif
  2393. }
  2394. /* Service SCAN_START_NOTIFICATION (0x82) */
  2395. static void iwl3945_rx_scan_start_notif(struct iwl_priv *priv,
  2396. struct iwl_rx_mem_buffer *rxb)
  2397. {
  2398. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2399. struct iwl_scanstart_notification *notif =
  2400. (struct iwl_scanstart_notification *)pkt->u.raw;
  2401. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2402. IWL_DEBUG_SCAN("Scan start: "
  2403. "%d [802.11%s] "
  2404. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2405. notif->channel,
  2406. notif->band ? "bg" : "a",
  2407. notif->tsf_high,
  2408. notif->tsf_low, notif->status, notif->beacon_timer);
  2409. }
  2410. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2411. static void iwl3945_rx_scan_results_notif(struct iwl_priv *priv,
  2412. struct iwl_rx_mem_buffer *rxb)
  2413. {
  2414. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2415. struct iwl_scanresults_notification *notif =
  2416. (struct iwl_scanresults_notification *)pkt->u.raw;
  2417. IWL_DEBUG_SCAN("Scan ch.res: "
  2418. "%d [802.11%s] "
  2419. "(TSF: 0x%08X:%08X) - %d "
  2420. "elapsed=%lu usec (%dms since last)\n",
  2421. notif->channel,
  2422. notif->band ? "bg" : "a",
  2423. le32_to_cpu(notif->tsf_high),
  2424. le32_to_cpu(notif->tsf_low),
  2425. le32_to_cpu(notif->statistics[0]),
  2426. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2427. jiffies_to_msecs(elapsed_jiffies
  2428. (priv->last_scan_jiffies, jiffies)));
  2429. priv->last_scan_jiffies = jiffies;
  2430. priv->next_scan_jiffies = 0;
  2431. }
  2432. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2433. static void iwl3945_rx_scan_complete_notif(struct iwl_priv *priv,
  2434. struct iwl_rx_mem_buffer *rxb)
  2435. {
  2436. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2437. struct iwl_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2438. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2439. scan_notif->scanned_channels,
  2440. scan_notif->tsf_low,
  2441. scan_notif->tsf_high, scan_notif->status);
  2442. /* The HW is no longer scanning */
  2443. clear_bit(STATUS_SCAN_HW, &priv->status);
  2444. /* The scan completion notification came in, so kill that timer... */
  2445. cancel_delayed_work(&priv->scan_check);
  2446. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2447. (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
  2448. "2.4" : "5.2",
  2449. jiffies_to_msecs(elapsed_jiffies
  2450. (priv->scan_pass_start, jiffies)));
  2451. /* Remove this scanned band from the list of pending
  2452. * bands to scan, band G precedes A in order of scanning
  2453. * as seen in iwl3945_bg_request_scan */
  2454. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
  2455. priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
  2456. else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
  2457. priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
  2458. /* If a request to abort was given, or the scan did not succeed
  2459. * then we reset the scan state machine and terminate,
  2460. * re-queuing another scan if one has been requested */
  2461. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2462. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2463. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2464. } else {
  2465. /* If there are more bands on this scan pass reschedule */
  2466. if (priv->scan_bands > 0)
  2467. goto reschedule;
  2468. }
  2469. priv->last_scan_jiffies = jiffies;
  2470. priv->next_scan_jiffies = 0;
  2471. IWL_DEBUG_INFO("Setting scan to off\n");
  2472. clear_bit(STATUS_SCANNING, &priv->status);
  2473. IWL_DEBUG_INFO("Scan took %dms\n",
  2474. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2475. queue_work(priv->workqueue, &priv->scan_completed);
  2476. return;
  2477. reschedule:
  2478. priv->scan_pass_start = jiffies;
  2479. queue_work(priv->workqueue, &priv->request_scan);
  2480. }
  2481. /* Handle notification from uCode that card's power state is changing
  2482. * due to software, hardware, or critical temperature RFKILL */
  2483. static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
  2484. struct iwl_rx_mem_buffer *rxb)
  2485. {
  2486. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2487. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2488. unsigned long status = priv->status;
  2489. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2490. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2491. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2492. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2493. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2494. if (flags & HW_CARD_DISABLED)
  2495. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2496. else
  2497. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2498. if (flags & SW_CARD_DISABLED)
  2499. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2500. else
  2501. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2502. iwl3945_scan_cancel(priv);
  2503. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2504. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2505. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2506. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2507. queue_work(priv->workqueue, &priv->rf_kill);
  2508. else
  2509. wake_up_interruptible(&priv->wait_command_queue);
  2510. }
  2511. /**
  2512. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2513. *
  2514. * Setup the RX handlers for each of the reply types sent from the uCode
  2515. * to the host.
  2516. *
  2517. * This function chains into the hardware specific files for them to setup
  2518. * any hardware specific handlers as well.
  2519. */
  2520. static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
  2521. {
  2522. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  2523. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  2524. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  2525. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  2526. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  2527. iwl3945_rx_spectrum_measure_notif;
  2528. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  2529. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  2530. iwl3945_rx_pm_debug_statistics_notif;
  2531. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  2532. /*
  2533. * The same handler is used for both the REPLY to a discrete
  2534. * statistics request from the host as well as for the periodic
  2535. * statistics notifications (after received beacons) from the uCode.
  2536. */
  2537. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  2538. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  2539. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  2540. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  2541. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  2542. iwl3945_rx_scan_results_notif;
  2543. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  2544. iwl3945_rx_scan_complete_notif;
  2545. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  2546. /* Set up hardware specific Rx handlers */
  2547. iwl3945_hw_rx_handler_setup(priv);
  2548. }
  2549. /**
  2550. * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
  2551. * When FW advances 'R' index, all entries between old and new 'R' index
  2552. * need to be reclaimed.
  2553. */
  2554. static void iwl3945_cmd_queue_reclaim(struct iwl_priv *priv,
  2555. int txq_id, int index)
  2556. {
  2557. struct iwl_tx_queue *txq = &priv->txq[txq_id];
  2558. struct iwl_queue *q = &txq->q;
  2559. int nfreed = 0;
  2560. if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
  2561. IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
  2562. "is out of range [0-%d] %d %d.\n", txq_id,
  2563. index, q->n_bd, q->write_ptr, q->read_ptr);
  2564. return;
  2565. }
  2566. for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
  2567. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2568. if (nfreed > 1) {
  2569. IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", index,
  2570. q->write_ptr, q->read_ptr);
  2571. queue_work(priv->workqueue, &priv->restart);
  2572. break;
  2573. }
  2574. nfreed++;
  2575. }
  2576. }
  2577. /**
  2578. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2579. * @rxb: Rx buffer to reclaim
  2580. *
  2581. * If an Rx buffer has an async callback associated with it the callback
  2582. * will be executed. The attached skb (if present) will only be freed
  2583. * if the callback returns 1
  2584. */
  2585. static void iwl3945_tx_cmd_complete(struct iwl_priv *priv,
  2586. struct iwl_rx_mem_buffer *rxb)
  2587. {
  2588. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2589. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2590. int txq_id = SEQ_TO_QUEUE(sequence);
  2591. int index = SEQ_TO_INDEX(sequence);
  2592. int huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
  2593. int cmd_index;
  2594. struct iwl_cmd *cmd;
  2595. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  2596. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  2597. cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  2598. /* Input error checking is done when commands are added to queue. */
  2599. if (cmd->meta.flags & CMD_WANT_SKB) {
  2600. cmd->meta.source->u.skb = rxb->skb;
  2601. rxb->skb = NULL;
  2602. } else if (cmd->meta.u.callback &&
  2603. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  2604. rxb->skb = NULL;
  2605. iwl3945_cmd_queue_reclaim(priv, txq_id, index);
  2606. if (!(cmd->meta.flags & CMD_ASYNC)) {
  2607. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  2608. wake_up_interruptible(&priv->wait_command_queue);
  2609. }
  2610. }
  2611. /************************** RX-FUNCTIONS ****************************/
  2612. /*
  2613. * Rx theory of operation
  2614. *
  2615. * The host allocates 32 DMA target addresses and passes the host address
  2616. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  2617. * 0 to 31
  2618. *
  2619. * Rx Queue Indexes
  2620. * The host/firmware share two index registers for managing the Rx buffers.
  2621. *
  2622. * The READ index maps to the first position that the firmware may be writing
  2623. * to -- the driver can read up to (but not including) this position and get
  2624. * good data.
  2625. * The READ index is managed by the firmware once the card is enabled.
  2626. *
  2627. * The WRITE index maps to the last position the driver has read from -- the
  2628. * position preceding WRITE is the last slot the firmware can place a packet.
  2629. *
  2630. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2631. * WRITE = READ.
  2632. *
  2633. * During initialization, the host sets up the READ queue position to the first
  2634. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  2635. *
  2636. * When the firmware places a packet in a buffer, it will advance the READ index
  2637. * and fire the RX interrupt. The driver can then query the READ index and
  2638. * process as many packets as possible, moving the WRITE index forward as it
  2639. * resets the Rx queue buffers with new memory.
  2640. *
  2641. * The management in the driver is as follows:
  2642. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2643. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2644. * to replenish the iwl->rxq->rx_free.
  2645. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  2646. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  2647. * 'processed' and 'read' driver indexes as well)
  2648. * + A received packet is processed and handed to the kernel network stack,
  2649. * detached from the iwl->rxq. The driver 'processed' index is updated.
  2650. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2651. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2652. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  2653. * were enough free buffers and RX_STALLED is set it is cleared.
  2654. *
  2655. *
  2656. * Driver sequence:
  2657. *
  2658. * iwl3945_rx_queue_alloc() Allocates rx_free
  2659. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2660. * iwl3945_rx_queue_restock
  2661. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  2662. * queue, updates firmware pointers, and updates
  2663. * the WRITE index. If insufficient rx_free buffers
  2664. * are available, schedules iwl3945_rx_replenish
  2665. *
  2666. * -- enable interrupts --
  2667. * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
  2668. * READ INDEX, detaching the SKB from the pool.
  2669. * Moves the packet buffer from queue to rx_used.
  2670. * Calls iwl3945_rx_queue_restock to refill any empty
  2671. * slots.
  2672. * ...
  2673. *
  2674. */
  2675. /**
  2676. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  2677. */
  2678. static int iwl3945_rx_queue_space(const struct iwl_rx_queue *q)
  2679. {
  2680. int s = q->read - q->write;
  2681. if (s <= 0)
  2682. s += RX_QUEUE_SIZE;
  2683. /* keep some buffer to not confuse full and empty queue */
  2684. s -= 2;
  2685. if (s < 0)
  2686. s = 0;
  2687. return s;
  2688. }
  2689. /**
  2690. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  2691. */
  2692. int iwl3945_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
  2693. {
  2694. u32 reg = 0;
  2695. int rc = 0;
  2696. unsigned long flags;
  2697. spin_lock_irqsave(&q->lock, flags);
  2698. if (q->need_update == 0)
  2699. goto exit_unlock;
  2700. /* If power-saving is in use, make sure device is awake */
  2701. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  2702. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  2703. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2704. iwl_set_bit(priv, CSR_GP_CNTRL,
  2705. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2706. goto exit_unlock;
  2707. }
  2708. rc = iwl_grab_nic_access(priv);
  2709. if (rc)
  2710. goto exit_unlock;
  2711. /* Device expects a multiple of 8 */
  2712. iwl_write_direct32(priv, FH39_RSCSR_CHNL0_WPTR,
  2713. q->write & ~0x7);
  2714. iwl_release_nic_access(priv);
  2715. /* Else device is assumed to be awake */
  2716. } else
  2717. /* Device expects a multiple of 8 */
  2718. iwl_write32(priv, FH39_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  2719. q->need_update = 0;
  2720. exit_unlock:
  2721. spin_unlock_irqrestore(&q->lock, flags);
  2722. return rc;
  2723. }
  2724. /**
  2725. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  2726. */
  2727. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
  2728. dma_addr_t dma_addr)
  2729. {
  2730. return cpu_to_le32((u32)dma_addr);
  2731. }
  2732. /**
  2733. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  2734. *
  2735. * If there are slots in the RX queue that need to be restocked,
  2736. * and we have free pre-allocated buffers, fill the ranks as much
  2737. * as we can, pulling from rx_free.
  2738. *
  2739. * This moves the 'write' index forward to catch up with 'processed', and
  2740. * also updates the memory address in the firmware to reference the new
  2741. * target buffer.
  2742. */
  2743. static int iwl3945_rx_queue_restock(struct iwl_priv *priv)
  2744. {
  2745. struct iwl_rx_queue *rxq = &priv->rxq;
  2746. struct list_head *element;
  2747. struct iwl_rx_mem_buffer *rxb;
  2748. unsigned long flags;
  2749. int write, rc;
  2750. spin_lock_irqsave(&rxq->lock, flags);
  2751. write = rxq->write & ~0x7;
  2752. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  2753. /* Get next free Rx buffer, remove from free list */
  2754. element = rxq->rx_free.next;
  2755. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  2756. list_del(element);
  2757. /* Point to Rx buffer via next RBD in circular buffer */
  2758. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr);
  2759. rxq->queue[rxq->write] = rxb;
  2760. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  2761. rxq->free_count--;
  2762. }
  2763. spin_unlock_irqrestore(&rxq->lock, flags);
  2764. /* If the pre-allocated buffer pool is dropping low, schedule to
  2765. * refill it */
  2766. if (rxq->free_count <= RX_LOW_WATERMARK)
  2767. queue_work(priv->workqueue, &priv->rx_replenish);
  2768. /* If we've added more space for the firmware to place data, tell it.
  2769. * Increment device's write pointer in multiples of 8. */
  2770. if ((write != (rxq->write & ~0x7))
  2771. || (abs(rxq->write - rxq->read) > 7)) {
  2772. spin_lock_irqsave(&rxq->lock, flags);
  2773. rxq->need_update = 1;
  2774. spin_unlock_irqrestore(&rxq->lock, flags);
  2775. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  2776. if (rc)
  2777. return rc;
  2778. }
  2779. return 0;
  2780. }
  2781. /**
  2782. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  2783. *
  2784. * When moving to rx_free an SKB is allocated for the slot.
  2785. *
  2786. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  2787. * This is called as a scheduled work item (except for during initialization)
  2788. */
  2789. static void iwl3945_rx_allocate(struct iwl_priv *priv)
  2790. {
  2791. struct iwl_rx_queue *rxq = &priv->rxq;
  2792. struct list_head *element;
  2793. struct iwl_rx_mem_buffer *rxb;
  2794. unsigned long flags;
  2795. spin_lock_irqsave(&rxq->lock, flags);
  2796. while (!list_empty(&rxq->rx_used)) {
  2797. element = rxq->rx_used.next;
  2798. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  2799. /* Alloc a new receive buffer */
  2800. rxb->skb =
  2801. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  2802. if (!rxb->skb) {
  2803. if (net_ratelimit())
  2804. IWL_CRIT(priv, ": Can not allocate SKB buffers\n");
  2805. /* We don't reschedule replenish work here -- we will
  2806. * call the restock method and if it still needs
  2807. * more buffers it will schedule replenish */
  2808. break;
  2809. }
  2810. /* If radiotap head is required, reserve some headroom here.
  2811. * The physical head count is a variable rx_stats->phy_count.
  2812. * We reserve 4 bytes here. Plus these extra bytes, the
  2813. * headroom of the physical head should be enough for the
  2814. * radiotap head that iwl3945 supported. See iwl3945_rt.
  2815. */
  2816. skb_reserve(rxb->skb, 4);
  2817. priv->alloc_rxb_skb++;
  2818. list_del(element);
  2819. /* Get physical address of RB/SKB */
  2820. rxb->real_dma_addr =
  2821. pci_map_single(priv->pci_dev, rxb->skb->data,
  2822. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  2823. list_add_tail(&rxb->list, &rxq->rx_free);
  2824. rxq->free_count++;
  2825. }
  2826. spin_unlock_irqrestore(&rxq->lock, flags);
  2827. }
  2828. /*
  2829. * this should be called while priv->lock is locked
  2830. */
  2831. static void __iwl3945_rx_replenish(void *data)
  2832. {
  2833. struct iwl_priv *priv = data;
  2834. iwl3945_rx_allocate(priv);
  2835. iwl3945_rx_queue_restock(priv);
  2836. }
  2837. void iwl3945_rx_replenish(void *data)
  2838. {
  2839. struct iwl_priv *priv = data;
  2840. unsigned long flags;
  2841. iwl3945_rx_allocate(priv);
  2842. spin_lock_irqsave(&priv->lock, flags);
  2843. iwl3945_rx_queue_restock(priv);
  2844. spin_unlock_irqrestore(&priv->lock, flags);
  2845. }
  2846. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  2847. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  2848. * This free routine walks the list of POOL entries and if SKB is set to
  2849. * non NULL it is unmapped and freed
  2850. */
  2851. static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  2852. {
  2853. int i;
  2854. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  2855. if (rxq->pool[i].skb != NULL) {
  2856. pci_unmap_single(priv->pci_dev,
  2857. rxq->pool[i].real_dma_addr,
  2858. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  2859. dev_kfree_skb(rxq->pool[i].skb);
  2860. }
  2861. }
  2862. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  2863. rxq->dma_addr);
  2864. rxq->bd = NULL;
  2865. }
  2866. int iwl3945_rx_queue_alloc(struct iwl_priv *priv)
  2867. {
  2868. struct iwl_rx_queue *rxq = &priv->rxq;
  2869. struct pci_dev *dev = priv->pci_dev;
  2870. int i;
  2871. spin_lock_init(&rxq->lock);
  2872. INIT_LIST_HEAD(&rxq->rx_free);
  2873. INIT_LIST_HEAD(&rxq->rx_used);
  2874. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  2875. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  2876. if (!rxq->bd)
  2877. return -ENOMEM;
  2878. /* Fill the rx_used queue with _all_ of the Rx buffers */
  2879. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  2880. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  2881. /* Set us so that we have processed and used all buffers, but have
  2882. * not restocked the Rx queue with fresh buffers */
  2883. rxq->read = rxq->write = 0;
  2884. rxq->free_count = 0;
  2885. rxq->need_update = 0;
  2886. return 0;
  2887. }
  2888. void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  2889. {
  2890. unsigned long flags;
  2891. int i;
  2892. spin_lock_irqsave(&rxq->lock, flags);
  2893. INIT_LIST_HEAD(&rxq->rx_free);
  2894. INIT_LIST_HEAD(&rxq->rx_used);
  2895. /* Fill the rx_used queue with _all_ of the Rx buffers */
  2896. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  2897. /* In the reset function, these buffers may have been allocated
  2898. * to an SKB, so we need to unmap and free potential storage */
  2899. if (rxq->pool[i].skb != NULL) {
  2900. pci_unmap_single(priv->pci_dev,
  2901. rxq->pool[i].real_dma_addr,
  2902. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  2903. priv->alloc_rxb_skb--;
  2904. dev_kfree_skb(rxq->pool[i].skb);
  2905. rxq->pool[i].skb = NULL;
  2906. }
  2907. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  2908. }
  2909. /* Set us so that we have processed and used all buffers, but have
  2910. * not restocked the Rx queue with fresh buffers */
  2911. rxq->read = rxq->write = 0;
  2912. rxq->free_count = 0;
  2913. spin_unlock_irqrestore(&rxq->lock, flags);
  2914. }
  2915. /* Convert linear signal-to-noise ratio into dB */
  2916. static u8 ratio2dB[100] = {
  2917. /* 0 1 2 3 4 5 6 7 8 9 */
  2918. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  2919. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  2920. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  2921. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  2922. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  2923. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  2924. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  2925. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  2926. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  2927. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  2928. };
  2929. /* Calculates a relative dB value from a ratio of linear
  2930. * (i.e. not dB) signal levels.
  2931. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  2932. int iwl3945_calc_db_from_ratio(int sig_ratio)
  2933. {
  2934. /* 1000:1 or higher just report as 60 dB */
  2935. if (sig_ratio >= 1000)
  2936. return 60;
  2937. /* 100:1 or higher, divide by 10 and use table,
  2938. * add 20 dB to make up for divide by 10 */
  2939. if (sig_ratio >= 100)
  2940. return 20 + (int)ratio2dB[sig_ratio/10];
  2941. /* We shouldn't see this */
  2942. if (sig_ratio < 1)
  2943. return 0;
  2944. /* Use table for ratios 1:1 - 99:1 */
  2945. return (int)ratio2dB[sig_ratio];
  2946. }
  2947. #define PERFECT_RSSI (-20) /* dBm */
  2948. #define WORST_RSSI (-95) /* dBm */
  2949. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  2950. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  2951. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  2952. * about formulas used below. */
  2953. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  2954. {
  2955. int sig_qual;
  2956. int degradation = PERFECT_RSSI - rssi_dbm;
  2957. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  2958. * as indicator; formula is (signal dbm - noise dbm).
  2959. * SNR at or above 40 is a great signal (100%).
  2960. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  2961. * Weakest usable signal is usually 10 - 15 dB SNR. */
  2962. if (noise_dbm) {
  2963. if (rssi_dbm - noise_dbm >= 40)
  2964. return 100;
  2965. else if (rssi_dbm < noise_dbm)
  2966. return 0;
  2967. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  2968. /* Else use just the signal level.
  2969. * This formula is a least squares fit of data points collected and
  2970. * compared with a reference system that had a percentage (%) display
  2971. * for signal quality. */
  2972. } else
  2973. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  2974. (15 * RSSI_RANGE + 62 * degradation)) /
  2975. (RSSI_RANGE * RSSI_RANGE);
  2976. if (sig_qual > 100)
  2977. sig_qual = 100;
  2978. else if (sig_qual < 1)
  2979. sig_qual = 0;
  2980. return sig_qual;
  2981. }
  2982. /**
  2983. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  2984. *
  2985. * Uses the priv->rx_handlers callback function array to invoke
  2986. * the appropriate handlers, including command responses,
  2987. * frame-received notifications, and other notifications.
  2988. */
  2989. static void iwl3945_rx_handle(struct iwl_priv *priv)
  2990. {
  2991. struct iwl_rx_mem_buffer *rxb;
  2992. struct iwl_rx_packet *pkt;
  2993. struct iwl_rx_queue *rxq = &priv->rxq;
  2994. u32 r, i;
  2995. int reclaim;
  2996. unsigned long flags;
  2997. u8 fill_rx = 0;
  2998. u32 count = 8;
  2999. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3000. * buffer that the driver may process (last buffer filled by ucode). */
  3001. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  3002. i = rxq->read;
  3003. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3004. fill_rx = 1;
  3005. /* Rx interrupt, but nothing sent from uCode */
  3006. if (i == r)
  3007. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3008. while (i != r) {
  3009. rxb = rxq->queue[i];
  3010. /* If an RXB doesn't have a Rx queue slot associated with it,
  3011. * then a bug has been introduced in the queue refilling
  3012. * routines -- catch it here */
  3013. BUG_ON(rxb == NULL);
  3014. rxq->queue[i] = NULL;
  3015. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->real_dma_addr,
  3016. IWL_RX_BUF_SIZE,
  3017. PCI_DMA_FROMDEVICE);
  3018. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  3019. /* Reclaim a command buffer only if this packet is a response
  3020. * to a (driver-originated) command.
  3021. * If the packet (e.g. Rx frame) originated from uCode,
  3022. * there is no command buffer to reclaim.
  3023. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3024. * but apparently a few don't get set; catch them here. */
  3025. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3026. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3027. (pkt->hdr.cmd != REPLY_TX);
  3028. /* Based on type of command response or notification,
  3029. * handle those that need handling via function in
  3030. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3031. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3032. IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
  3033. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3034. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3035. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3036. } else {
  3037. /* No handling needed */
  3038. IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
  3039. "r %d i %d No handler needed for %s, 0x%02x\n",
  3040. r, i, get_cmd_string(pkt->hdr.cmd),
  3041. pkt->hdr.cmd);
  3042. }
  3043. if (reclaim) {
  3044. /* Invoke any callbacks, transfer the skb to caller, and
  3045. * fire off the (possibly) blocking iwl3945_send_cmd()
  3046. * as we reclaim the driver command queue */
  3047. if (rxb && rxb->skb)
  3048. iwl3945_tx_cmd_complete(priv, rxb);
  3049. else
  3050. IWL_WARN(priv, "Claim null rxb?\n");
  3051. }
  3052. /* For now we just don't re-use anything. We can tweak this
  3053. * later to try and re-use notification packets and SKBs that
  3054. * fail to Rx correctly */
  3055. if (rxb->skb != NULL) {
  3056. priv->alloc_rxb_skb--;
  3057. dev_kfree_skb_any(rxb->skb);
  3058. rxb->skb = NULL;
  3059. }
  3060. pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
  3061. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3062. spin_lock_irqsave(&rxq->lock, flags);
  3063. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3064. spin_unlock_irqrestore(&rxq->lock, flags);
  3065. i = (i + 1) & RX_QUEUE_MASK;
  3066. /* If there are a lot of unused frames,
  3067. * restock the Rx queue so ucode won't assert. */
  3068. if (fill_rx) {
  3069. count++;
  3070. if (count >= 8) {
  3071. priv->rxq.read = i;
  3072. __iwl3945_rx_replenish(priv);
  3073. count = 0;
  3074. }
  3075. }
  3076. }
  3077. /* Backtrack one entry */
  3078. priv->rxq.read = i;
  3079. iwl3945_rx_queue_restock(priv);
  3080. }
  3081. /**
  3082. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3083. */
  3084. static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
  3085. struct iwl_tx_queue *txq)
  3086. {
  3087. u32 reg = 0;
  3088. int rc = 0;
  3089. int txq_id = txq->q.id;
  3090. if (txq->need_update == 0)
  3091. return rc;
  3092. /* if we're trying to save power */
  3093. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3094. /* wake up nic if it's powered down ...
  3095. * uCode will wake up, and interrupt us again, so next
  3096. * time we'll skip this part. */
  3097. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  3098. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3099. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3100. iwl_set_bit(priv, CSR_GP_CNTRL,
  3101. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3102. return rc;
  3103. }
  3104. /* restore this queue's parameters in nic hardware. */
  3105. rc = iwl_grab_nic_access(priv);
  3106. if (rc)
  3107. return rc;
  3108. iwl_write_direct32(priv, HBUS_TARG_WRPTR,
  3109. txq->q.write_ptr | (txq_id << 8));
  3110. iwl_release_nic_access(priv);
  3111. /* else not in power-save mode, uCode will never sleep when we're
  3112. * trying to tx (during RFKILL, we're not trying to tx). */
  3113. } else
  3114. iwl_write32(priv, HBUS_TARG_WRPTR,
  3115. txq->q.write_ptr | (txq_id << 8));
  3116. txq->need_update = 0;
  3117. return rc;
  3118. }
  3119. #ifdef CONFIG_IWL3945_DEBUG
  3120. static void iwl3945_print_rx_config_cmd(struct iwl_priv *priv,
  3121. struct iwl3945_rxon_cmd *rxon)
  3122. {
  3123. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3124. iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3125. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3126. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3127. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3128. le32_to_cpu(rxon->filter_flags));
  3129. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3130. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3131. rxon->ofdm_basic_rates);
  3132. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3133. IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
  3134. IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  3135. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3136. }
  3137. #endif
  3138. static void iwl3945_enable_interrupts(struct iwl_priv *priv)
  3139. {
  3140. IWL_DEBUG_ISR("Enabling interrupts\n");
  3141. set_bit(STATUS_INT_ENABLED, &priv->status);
  3142. iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3143. }
  3144. /* call this function to flush any scheduled tasklet */
  3145. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  3146. {
  3147. /* wait to make sure we flush pending tasklet*/
  3148. synchronize_irq(priv->pci_dev->irq);
  3149. tasklet_kill(&priv->irq_tasklet);
  3150. }
  3151. static inline void iwl3945_disable_interrupts(struct iwl_priv *priv)
  3152. {
  3153. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3154. /* disable interrupts from uCode/NIC to host */
  3155. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  3156. /* acknowledge/clear/reset any interrupts still pending
  3157. * from uCode or flow handler (Rx/Tx DMA) */
  3158. iwl_write32(priv, CSR_INT, 0xffffffff);
  3159. iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3160. IWL_DEBUG_ISR("Disabled interrupts\n");
  3161. }
  3162. static const char *desc_lookup(int i)
  3163. {
  3164. switch (i) {
  3165. case 1:
  3166. return "FAIL";
  3167. case 2:
  3168. return "BAD_PARAM";
  3169. case 3:
  3170. return "BAD_CHECKSUM";
  3171. case 4:
  3172. return "NMI_INTERRUPT";
  3173. case 5:
  3174. return "SYSASSERT";
  3175. case 6:
  3176. return "FATAL_ERROR";
  3177. }
  3178. return "UNKNOWN";
  3179. }
  3180. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3181. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3182. static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
  3183. {
  3184. u32 i;
  3185. u32 desc, time, count, base, data1;
  3186. u32 blink1, blink2, ilink1, ilink2;
  3187. int rc;
  3188. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3189. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3190. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  3191. return;
  3192. }
  3193. rc = iwl_grab_nic_access(priv);
  3194. if (rc) {
  3195. IWL_WARN(priv, "Can not read from adapter at this time.\n");
  3196. return;
  3197. }
  3198. count = iwl_read_targ_mem(priv, base);
  3199. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3200. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  3201. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  3202. priv->status, count);
  3203. }
  3204. IWL_ERR(priv, "Desc Time asrtPC blink2 "
  3205. "ilink1 nmiPC Line\n");
  3206. for (i = ERROR_START_OFFSET;
  3207. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3208. i += ERROR_ELEM_SIZE) {
  3209. desc = iwl_read_targ_mem(priv, base + i);
  3210. time =
  3211. iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3212. blink1 =
  3213. iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3214. blink2 =
  3215. iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3216. ilink1 =
  3217. iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3218. ilink2 =
  3219. iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3220. data1 =
  3221. iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3222. IWL_ERR(priv,
  3223. "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3224. desc_lookup(desc), desc, time, blink1, blink2,
  3225. ilink1, ilink2, data1);
  3226. }
  3227. iwl_release_nic_access(priv);
  3228. }
  3229. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3230. /**
  3231. * iwl3945_print_event_log - Dump error event log to syslog
  3232. *
  3233. * NOTE: Must be called with iwl_grab_nic_access() already obtained!
  3234. */
  3235. static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
  3236. u32 num_events, u32 mode)
  3237. {
  3238. u32 i;
  3239. u32 base; /* SRAM byte address of event log header */
  3240. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3241. u32 ptr; /* SRAM byte address of log data */
  3242. u32 ev, time, data; /* event log data */
  3243. if (num_events == 0)
  3244. return;
  3245. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3246. if (mode == 0)
  3247. event_size = 2 * sizeof(u32);
  3248. else
  3249. event_size = 3 * sizeof(u32);
  3250. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3251. /* "time" is actually "data" for mode 0 (no timestamp).
  3252. * place event id # at far right for easier visual parsing. */
  3253. for (i = 0; i < num_events; i++) {
  3254. ev = iwl_read_targ_mem(priv, ptr);
  3255. ptr += sizeof(u32);
  3256. time = iwl_read_targ_mem(priv, ptr);
  3257. ptr += sizeof(u32);
  3258. if (mode == 0) {
  3259. /* data, ev */
  3260. IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
  3261. } else {
  3262. data = iwl_read_targ_mem(priv, ptr);
  3263. ptr += sizeof(u32);
  3264. IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev);
  3265. }
  3266. }
  3267. }
  3268. static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
  3269. {
  3270. int rc;
  3271. u32 base; /* SRAM byte address of event log header */
  3272. u32 capacity; /* event log capacity in # entries */
  3273. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3274. u32 num_wraps; /* # times uCode wrapped to top of log */
  3275. u32 next_entry; /* index of next entry to be written by uCode */
  3276. u32 size; /* # entries that we'll print */
  3277. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3278. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3279. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  3280. return;
  3281. }
  3282. rc = iwl_grab_nic_access(priv);
  3283. if (rc) {
  3284. IWL_WARN(priv, "Can not read from adapter at this time.\n");
  3285. return;
  3286. }
  3287. /* event log header */
  3288. capacity = iwl_read_targ_mem(priv, base);
  3289. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3290. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3291. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3292. size = num_wraps ? capacity : next_entry;
  3293. /* bail out if nothing in log */
  3294. if (size == 0) {
  3295. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  3296. iwl_release_nic_access(priv);
  3297. return;
  3298. }
  3299. IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
  3300. size, num_wraps);
  3301. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3302. * i.e the next one that uCode would fill. */
  3303. if (num_wraps)
  3304. iwl3945_print_event_log(priv, next_entry,
  3305. capacity - next_entry, mode);
  3306. /* (then/else) start at top of log */
  3307. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3308. iwl_release_nic_access(priv);
  3309. }
  3310. /**
  3311. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3312. */
  3313. static void iwl3945_irq_handle_error(struct iwl_priv *priv)
  3314. {
  3315. /* Set the FW error flag -- cleared on iwl3945_down */
  3316. set_bit(STATUS_FW_ERROR, &priv->status);
  3317. /* Cancel currently queued command. */
  3318. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3319. #ifdef CONFIG_IWL3945_DEBUG
  3320. if (priv->debug_level & IWL_DL_FW_ERRORS) {
  3321. iwl3945_dump_nic_error_log(priv);
  3322. iwl3945_dump_nic_event_log(priv);
  3323. iwl3945_print_rx_config_cmd(priv, &priv->staging39_rxon);
  3324. }
  3325. #endif
  3326. wake_up_interruptible(&priv->wait_command_queue);
  3327. /* Keep the restart process from trying to send host
  3328. * commands by clearing the INIT status bit */
  3329. clear_bit(STATUS_READY, &priv->status);
  3330. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3331. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3332. "Restarting adapter due to uCode error.\n");
  3333. if (iwl3945_is_associated(priv)) {
  3334. memcpy(&priv->recovery39_rxon, &priv->active39_rxon,
  3335. sizeof(priv->recovery39_rxon));
  3336. priv->error_recovering = 1;
  3337. }
  3338. queue_work(priv->workqueue, &priv->restart);
  3339. }
  3340. }
  3341. static void iwl3945_error_recovery(struct iwl_priv *priv)
  3342. {
  3343. unsigned long flags;
  3344. memcpy(&priv->staging39_rxon, &priv->recovery39_rxon,
  3345. sizeof(priv->staging39_rxon));
  3346. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3347. iwl3945_commit_rxon(priv);
  3348. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3349. spin_lock_irqsave(&priv->lock, flags);
  3350. priv->assoc_id = le16_to_cpu(priv->staging39_rxon.assoc_id);
  3351. priv->error_recovering = 0;
  3352. spin_unlock_irqrestore(&priv->lock, flags);
  3353. }
  3354. static void iwl3945_irq_tasklet(struct iwl_priv *priv)
  3355. {
  3356. u32 inta, handled = 0;
  3357. u32 inta_fh;
  3358. unsigned long flags;
  3359. #ifdef CONFIG_IWL3945_DEBUG
  3360. u32 inta_mask;
  3361. #endif
  3362. spin_lock_irqsave(&priv->lock, flags);
  3363. /* Ack/clear/reset pending uCode interrupts.
  3364. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3365. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3366. inta = iwl_read32(priv, CSR_INT);
  3367. iwl_write32(priv, CSR_INT, inta);
  3368. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3369. * Any new interrupts that happen after this, either while we're
  3370. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3371. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3372. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3373. #ifdef CONFIG_IWL3945_DEBUG
  3374. if (priv->debug_level & IWL_DL_ISR) {
  3375. /* just for debug */
  3376. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  3377. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3378. inta, inta_mask, inta_fh);
  3379. }
  3380. #endif
  3381. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3382. * atomic, make sure that inta covers all the interrupts that
  3383. * we've discovered, even if FH interrupt came in just after
  3384. * reading CSR_INT. */
  3385. if (inta_fh & CSR39_FH_INT_RX_MASK)
  3386. inta |= CSR_INT_BIT_FH_RX;
  3387. if (inta_fh & CSR39_FH_INT_TX_MASK)
  3388. inta |= CSR_INT_BIT_FH_TX;
  3389. /* Now service all interrupt bits discovered above. */
  3390. if (inta & CSR_INT_BIT_HW_ERR) {
  3391. IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
  3392. /* Tell the device to stop sending interrupts */
  3393. iwl3945_disable_interrupts(priv);
  3394. iwl3945_irq_handle_error(priv);
  3395. handled |= CSR_INT_BIT_HW_ERR;
  3396. spin_unlock_irqrestore(&priv->lock, flags);
  3397. return;
  3398. }
  3399. #ifdef CONFIG_IWL3945_DEBUG
  3400. if (priv->debug_level & (IWL_DL_ISR)) {
  3401. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3402. if (inta & CSR_INT_BIT_SCD)
  3403. IWL_DEBUG_ISR("Scheduler finished to transmit "
  3404. "the frame/frames.\n");
  3405. /* Alive notification via Rx interrupt will do the real work */
  3406. if (inta & CSR_INT_BIT_ALIVE)
  3407. IWL_DEBUG_ISR("Alive interrupt\n");
  3408. }
  3409. #endif
  3410. /* Safely ignore these bits for debug checks below */
  3411. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  3412. /* Error detected by uCode */
  3413. if (inta & CSR_INT_BIT_SW_ERR) {
  3414. IWL_ERR(priv, "Microcode SW error detected. "
  3415. "Restarting 0x%X.\n", inta);
  3416. iwl3945_irq_handle_error(priv);
  3417. handled |= CSR_INT_BIT_SW_ERR;
  3418. }
  3419. /* uCode wakes up after power-down sleep */
  3420. if (inta & CSR_INT_BIT_WAKEUP) {
  3421. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3422. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  3423. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  3424. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  3425. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  3426. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  3427. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  3428. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  3429. handled |= CSR_INT_BIT_WAKEUP;
  3430. }
  3431. /* All uCode command responses, including Tx command responses,
  3432. * Rx "responses" (frame-received notification), and other
  3433. * notifications from uCode come through here*/
  3434. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3435. iwl3945_rx_handle(priv);
  3436. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3437. }
  3438. if (inta & CSR_INT_BIT_FH_TX) {
  3439. IWL_DEBUG_ISR("Tx interrupt\n");
  3440. iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3441. if (!iwl_grab_nic_access(priv)) {
  3442. iwl_write_direct32(priv, FH39_TCSR_CREDIT
  3443. (FH39_SRVC_CHNL), 0x0);
  3444. iwl_release_nic_access(priv);
  3445. }
  3446. handled |= CSR_INT_BIT_FH_TX;
  3447. }
  3448. if (inta & ~handled)
  3449. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  3450. if (inta & ~CSR_INI_SET_MASK) {
  3451. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  3452. inta & ~CSR_INI_SET_MASK);
  3453. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  3454. }
  3455. /* Re-enable all interrupts */
  3456. /* only Re-enable if disabled by irq */
  3457. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3458. iwl3945_enable_interrupts(priv);
  3459. #ifdef CONFIG_IWL3945_DEBUG
  3460. if (priv->debug_level & (IWL_DL_ISR)) {
  3461. inta = iwl_read32(priv, CSR_INT);
  3462. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  3463. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3464. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  3465. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  3466. }
  3467. #endif
  3468. spin_unlock_irqrestore(&priv->lock, flags);
  3469. }
  3470. static irqreturn_t iwl3945_isr(int irq, void *data)
  3471. {
  3472. struct iwl_priv *priv = data;
  3473. u32 inta, inta_mask;
  3474. u32 inta_fh;
  3475. if (!priv)
  3476. return IRQ_NONE;
  3477. spin_lock(&priv->lock);
  3478. /* Disable (but don't clear!) interrupts here to avoid
  3479. * back-to-back ISRs and sporadic interrupts from our NIC.
  3480. * If we have something to service, the tasklet will re-enable ints.
  3481. * If we *don't* have something, we'll re-enable before leaving here. */
  3482. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  3483. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  3484. /* Discover which interrupts are active/pending */
  3485. inta = iwl_read32(priv, CSR_INT);
  3486. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3487. /* Ignore interrupt if there's nothing in NIC to service.
  3488. * This may be due to IRQ shared with another device,
  3489. * or due to sporadic interrupts thrown from our NIC. */
  3490. if (!inta && !inta_fh) {
  3491. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  3492. goto none;
  3493. }
  3494. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  3495. /* Hardware disappeared */
  3496. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  3497. goto unplugged;
  3498. }
  3499. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3500. inta, inta_mask, inta_fh);
  3501. inta &= ~CSR_INT_BIT_SCD;
  3502. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  3503. if (likely(inta || inta_fh))
  3504. tasklet_schedule(&priv->irq_tasklet);
  3505. unplugged:
  3506. spin_unlock(&priv->lock);
  3507. return IRQ_HANDLED;
  3508. none:
  3509. /* re-enable interrupts here since we don't have anything to service. */
  3510. /* only Re-enable if disabled by irq */
  3511. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3512. iwl3945_enable_interrupts(priv);
  3513. spin_unlock(&priv->lock);
  3514. return IRQ_NONE;
  3515. }
  3516. /************************** EEPROM BANDS ****************************
  3517. *
  3518. * The iwl3945_eeprom_band definitions below provide the mapping from the
  3519. * EEPROM contents to the specific channel number supported for each
  3520. * band.
  3521. *
  3522. * For example, iwl3945_priv->eeprom39.band_3_channels[4] from the band_3
  3523. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  3524. * The specific geography and calibration information for that channel
  3525. * is contained in the eeprom map itself.
  3526. *
  3527. * During init, we copy the eeprom information and channel map
  3528. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  3529. *
  3530. * channel_map_24/52 provides the index in the channel_info array for a
  3531. * given channel. We have to have two separate maps as there is channel
  3532. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  3533. * band_2
  3534. *
  3535. * A value of 0xff stored in the channel_map indicates that the channel
  3536. * is not supported by the hardware at all.
  3537. *
  3538. * A value of 0xfe in the channel_map indicates that the channel is not
  3539. * valid for Tx with the current hardware. This means that
  3540. * while the system can tune and receive on a given channel, it may not
  3541. * be able to associate or transmit any frames on that
  3542. * channel. There is no corresponding channel information for that
  3543. * entry.
  3544. *
  3545. *********************************************************************/
  3546. /* 2.4 GHz */
  3547. static const u8 iwl3945_eeprom_band_1[14] = {
  3548. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  3549. };
  3550. /* 5.2 GHz bands */
  3551. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  3552. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  3553. };
  3554. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  3555. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  3556. };
  3557. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  3558. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  3559. };
  3560. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  3561. 145, 149, 153, 157, 161, 165
  3562. };
  3563. static void iwl3945_init_band_reference(const struct iwl_priv *priv, int band,
  3564. int *eeprom_ch_count,
  3565. const struct iwl_eeprom_channel
  3566. **eeprom_ch_info,
  3567. const u8 **eeprom_ch_index)
  3568. {
  3569. switch (band) {
  3570. case 1: /* 2.4GHz band */
  3571. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  3572. *eeprom_ch_info = priv->eeprom39.band_1_channels;
  3573. *eeprom_ch_index = iwl3945_eeprom_band_1;
  3574. break;
  3575. case 2: /* 4.9GHz band */
  3576. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  3577. *eeprom_ch_info = priv->eeprom39.band_2_channels;
  3578. *eeprom_ch_index = iwl3945_eeprom_band_2;
  3579. break;
  3580. case 3: /* 5.2GHz band */
  3581. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  3582. *eeprom_ch_info = priv->eeprom39.band_3_channels;
  3583. *eeprom_ch_index = iwl3945_eeprom_band_3;
  3584. break;
  3585. case 4: /* 5.5GHz band */
  3586. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  3587. *eeprom_ch_info = priv->eeprom39.band_4_channels;
  3588. *eeprom_ch_index = iwl3945_eeprom_band_4;
  3589. break;
  3590. case 5: /* 5.7GHz band */
  3591. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  3592. *eeprom_ch_info = priv->eeprom39.band_5_channels;
  3593. *eeprom_ch_index = iwl3945_eeprom_band_5;
  3594. break;
  3595. default:
  3596. BUG();
  3597. return;
  3598. }
  3599. }
  3600. /**
  3601. * iwl3945_get_channel_info - Find driver's private channel info
  3602. *
  3603. * Based on band and channel number.
  3604. */
  3605. const struct iwl_channel_info *
  3606. iwl3945_get_channel_info(const struct iwl_priv *priv,
  3607. enum ieee80211_band band, u16 channel)
  3608. {
  3609. int i;
  3610. switch (band) {
  3611. case IEEE80211_BAND_5GHZ:
  3612. for (i = 14; i < priv->channel_count; i++) {
  3613. if (priv->channel_info[i].channel == channel)
  3614. return &priv->channel_info[i];
  3615. }
  3616. break;
  3617. case IEEE80211_BAND_2GHZ:
  3618. if (channel >= 1 && channel <= 14)
  3619. return &priv->channel_info[channel - 1];
  3620. break;
  3621. case IEEE80211_NUM_BANDS:
  3622. WARN_ON(1);
  3623. }
  3624. return NULL;
  3625. }
  3626. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  3627. ? # x " " : "")
  3628. /**
  3629. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  3630. */
  3631. static int iwl3945_init_channel_map(struct iwl_priv *priv)
  3632. {
  3633. int eeprom_ch_count = 0;
  3634. const u8 *eeprom_ch_index = NULL;
  3635. const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
  3636. int band, ch;
  3637. struct iwl_channel_info *ch_info;
  3638. if (priv->channel_count) {
  3639. IWL_DEBUG_INFO("Channel map already initialized.\n");
  3640. return 0;
  3641. }
  3642. if (priv->eeprom39.version < 0x2f) {
  3643. IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
  3644. priv->eeprom39.version);
  3645. return -EINVAL;
  3646. }
  3647. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  3648. priv->channel_count =
  3649. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  3650. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  3651. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  3652. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  3653. ARRAY_SIZE(iwl3945_eeprom_band_5);
  3654. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  3655. priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) *
  3656. priv->channel_count, GFP_KERNEL);
  3657. if (!priv->channel_info) {
  3658. IWL_ERR(priv, "Could not allocate channel_info\n");
  3659. priv->channel_count = 0;
  3660. return -ENOMEM;
  3661. }
  3662. ch_info = priv->channel_info;
  3663. /* Loop through the 5 EEPROM bands adding them in order to the
  3664. * channel map we maintain (that contains additional information than
  3665. * what just in the EEPROM) */
  3666. for (band = 1; band <= 5; band++) {
  3667. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  3668. &eeprom_ch_info, &eeprom_ch_index);
  3669. /* Loop through each band adding each of the channels */
  3670. for (ch = 0; ch < eeprom_ch_count; ch++) {
  3671. ch_info->channel = eeprom_ch_index[ch];
  3672. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  3673. IEEE80211_BAND_5GHZ;
  3674. /* permanently store EEPROM's channel regulatory flags
  3675. * and max power in channel info database. */
  3676. ch_info->eeprom = eeprom_ch_info[ch];
  3677. /* Copy the run-time flags so they are there even on
  3678. * invalid channels */
  3679. ch_info->flags = eeprom_ch_info[ch].flags;
  3680. if (!(is_channel_valid(ch_info))) {
  3681. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  3682. "No traffic\n",
  3683. ch_info->channel,
  3684. ch_info->flags,
  3685. is_channel_a_band(ch_info) ?
  3686. "5.2" : "2.4");
  3687. ch_info++;
  3688. continue;
  3689. }
  3690. /* Initialize regulatory-based run-time data */
  3691. ch_info->max_power_avg = ch_info->curr_txpow =
  3692. eeprom_ch_info[ch].max_power_avg;
  3693. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  3694. ch_info->min_power = 0;
  3695. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  3696. " %ddBm): Ad-Hoc %ssupported\n",
  3697. ch_info->channel,
  3698. is_channel_a_band(ch_info) ?
  3699. "5.2" : "2.4",
  3700. CHECK_AND_PRINT(VALID),
  3701. CHECK_AND_PRINT(IBSS),
  3702. CHECK_AND_PRINT(ACTIVE),
  3703. CHECK_AND_PRINT(RADAR),
  3704. CHECK_AND_PRINT(WIDE),
  3705. CHECK_AND_PRINT(DFS),
  3706. eeprom_ch_info[ch].flags,
  3707. eeprom_ch_info[ch].max_power_avg,
  3708. ((eeprom_ch_info[ch].
  3709. flags & EEPROM_CHANNEL_IBSS)
  3710. && !(eeprom_ch_info[ch].
  3711. flags & EEPROM_CHANNEL_RADAR))
  3712. ? "" : "not ");
  3713. /* Set the user_txpower_limit to the highest power
  3714. * supported by any channel */
  3715. if (eeprom_ch_info[ch].max_power_avg >
  3716. priv->user_txpower_limit)
  3717. priv->user_txpower_limit =
  3718. eeprom_ch_info[ch].max_power_avg;
  3719. ch_info++;
  3720. }
  3721. }
  3722. /* Set up txpower settings in driver for all channels */
  3723. if (iwl3945_txpower_set_from_eeprom(priv))
  3724. return -EIO;
  3725. return 0;
  3726. }
  3727. /*
  3728. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  3729. */
  3730. static void iwl3945_free_channel_map(struct iwl_priv *priv)
  3731. {
  3732. kfree(priv->channel_info);
  3733. priv->channel_count = 0;
  3734. }
  3735. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  3736. * sending probe req. This should be set long enough to hear probe responses
  3737. * from more than one AP. */
  3738. #define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
  3739. #define IWL_ACTIVE_DWELL_TIME_52 (20)
  3740. #define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
  3741. #define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
  3742. /* For faster active scanning, scan will move to the next channel if fewer than
  3743. * PLCP_QUIET_THRESH packets are heard on this channel within
  3744. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  3745. * time if it's a quiet channel (nothing responded to our probe, and there's
  3746. * no other traffic).
  3747. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  3748. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  3749. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
  3750. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  3751. * Must be set longer than active dwell time.
  3752. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  3753. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  3754. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  3755. #define IWL_PASSIVE_DWELL_BASE (100)
  3756. #define IWL_CHANNEL_TUNE_TIME 5
  3757. #define IWL_SCAN_PROBE_MASK(n) (BIT(n) | (BIT(n) - BIT(1)))
  3758. static inline u16 iwl3945_get_active_dwell_time(struct iwl_priv *priv,
  3759. enum ieee80211_band band,
  3760. u8 n_probes)
  3761. {
  3762. if (band == IEEE80211_BAND_5GHZ)
  3763. return IWL_ACTIVE_DWELL_TIME_52 +
  3764. IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
  3765. else
  3766. return IWL_ACTIVE_DWELL_TIME_24 +
  3767. IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
  3768. }
  3769. static u16 iwl3945_get_passive_dwell_time(struct iwl_priv *priv,
  3770. enum ieee80211_band band)
  3771. {
  3772. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  3773. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  3774. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  3775. if (iwl3945_is_associated(priv)) {
  3776. /* If we're associated, we clamp the maximum passive
  3777. * dwell time to be 98% of the beacon interval (minus
  3778. * 2 * channel tune time) */
  3779. passive = priv->beacon_int;
  3780. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  3781. passive = IWL_PASSIVE_DWELL_BASE;
  3782. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  3783. }
  3784. return passive;
  3785. }
  3786. static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
  3787. enum ieee80211_band band,
  3788. u8 is_active, u8 n_probes,
  3789. struct iwl3945_scan_channel *scan_ch)
  3790. {
  3791. const struct ieee80211_channel *channels = NULL;
  3792. const struct ieee80211_supported_band *sband;
  3793. const struct iwl_channel_info *ch_info;
  3794. u16 passive_dwell = 0;
  3795. u16 active_dwell = 0;
  3796. int added, i;
  3797. sband = iwl_get_hw_mode(priv, band);
  3798. if (!sband)
  3799. return 0;
  3800. channels = sband->channels;
  3801. active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
  3802. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  3803. if (passive_dwell <= active_dwell)
  3804. passive_dwell = active_dwell + 1;
  3805. for (i = 0, added = 0; i < sband->n_channels; i++) {
  3806. if (channels[i].flags & IEEE80211_CHAN_DISABLED)
  3807. continue;
  3808. scan_ch->channel = channels[i].hw_value;
  3809. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  3810. if (!is_channel_valid(ch_info)) {
  3811. IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
  3812. scan_ch->channel);
  3813. continue;
  3814. }
  3815. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  3816. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  3817. /* If passive , set up for auto-switch
  3818. * and use long active_dwell time.
  3819. */
  3820. if (!is_active || is_channel_passive(ch_info) ||
  3821. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
  3822. scan_ch->type = 0; /* passive */
  3823. if (IWL_UCODE_API(priv->ucode_ver) == 1)
  3824. scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
  3825. } else {
  3826. scan_ch->type = 1; /* active */
  3827. }
  3828. /* Set direct probe bits. These may be used both for active
  3829. * scan channels (probes gets sent right away),
  3830. * or for passive channels (probes get se sent only after
  3831. * hearing clear Rx packet).*/
  3832. if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
  3833. if (n_probes)
  3834. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  3835. } else {
  3836. /* uCode v1 does not allow setting direct probe bits on
  3837. * passive channel. */
  3838. if ((scan_ch->type & 1) && n_probes)
  3839. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  3840. }
  3841. /* Set txpower levels to defaults */
  3842. scan_ch->tpc.dsp_atten = 110;
  3843. /* scan_pwr_info->tpc.dsp_atten; */
  3844. /*scan_pwr_info->tpc.tx_gain; */
  3845. if (band == IEEE80211_BAND_5GHZ)
  3846. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  3847. else {
  3848. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  3849. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  3850. * power level:
  3851. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  3852. */
  3853. }
  3854. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  3855. scan_ch->channel,
  3856. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  3857. (scan_ch->type & 1) ?
  3858. active_dwell : passive_dwell);
  3859. scan_ch++;
  3860. added++;
  3861. }
  3862. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  3863. return added;
  3864. }
  3865. static void iwl3945_init_hw_rates(struct iwl_priv *priv,
  3866. struct ieee80211_rate *rates)
  3867. {
  3868. int i;
  3869. for (i = 0; i < IWL_RATE_COUNT; i++) {
  3870. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  3871. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  3872. rates[i].hw_value_short = i;
  3873. rates[i].flags = 0;
  3874. if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  3875. /*
  3876. * If CCK != 1M then set short preamble rate flag.
  3877. */
  3878. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  3879. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  3880. }
  3881. }
  3882. }
  3883. /**
  3884. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  3885. */
  3886. static int iwl3945_init_geos(struct iwl_priv *priv)
  3887. {
  3888. struct iwl_channel_info *ch;
  3889. struct ieee80211_supported_band *sband;
  3890. struct ieee80211_channel *channels;
  3891. struct ieee80211_channel *geo_ch;
  3892. struct ieee80211_rate *rates;
  3893. int i = 0;
  3894. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  3895. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  3896. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  3897. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3898. return 0;
  3899. }
  3900. channels = kzalloc(sizeof(struct ieee80211_channel) *
  3901. priv->channel_count, GFP_KERNEL);
  3902. if (!channels)
  3903. return -ENOMEM;
  3904. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  3905. GFP_KERNEL);
  3906. if (!rates) {
  3907. kfree(channels);
  3908. return -ENOMEM;
  3909. }
  3910. /* 5.2GHz channels start after the 2.4GHz channels */
  3911. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  3912. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  3913. /* just OFDM */
  3914. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  3915. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  3916. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  3917. sband->channels = channels;
  3918. /* OFDM & CCK */
  3919. sband->bitrates = rates;
  3920. sband->n_bitrates = IWL_RATE_COUNT;
  3921. priv->ieee_channels = channels;
  3922. priv->ieee_rates = rates;
  3923. iwl3945_init_hw_rates(priv, rates);
  3924. for (i = 0; i < priv->channel_count; i++) {
  3925. ch = &priv->channel_info[i];
  3926. /* FIXME: might be removed if scan is OK*/
  3927. if (!is_channel_valid(ch))
  3928. continue;
  3929. if (is_channel_a_band(ch))
  3930. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  3931. else
  3932. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  3933. geo_ch = &sband->channels[sband->n_channels++];
  3934. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  3935. geo_ch->max_power = ch->max_power_avg;
  3936. geo_ch->max_antenna_gain = 0xff;
  3937. geo_ch->hw_value = ch->channel;
  3938. if (is_channel_valid(ch)) {
  3939. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  3940. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  3941. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  3942. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  3943. if (ch->flags & EEPROM_CHANNEL_RADAR)
  3944. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  3945. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  3946. priv->max_channel_txpower_limit =
  3947. ch->max_power_avg;
  3948. } else {
  3949. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  3950. }
  3951. /* Save flags for reg domain usage */
  3952. geo_ch->orig_flags = geo_ch->flags;
  3953. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  3954. ch->channel, geo_ch->center_freq,
  3955. is_channel_a_band(ch) ? "5.2" : "2.4",
  3956. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  3957. "restricted" : "valid",
  3958. geo_ch->flags);
  3959. }
  3960. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  3961. priv->cfg->sku & IWL_SKU_A) {
  3962. IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
  3963. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  3964. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  3965. priv->cfg->sku &= ~IWL_SKU_A;
  3966. }
  3967. IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  3968. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  3969. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  3970. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  3971. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  3972. &priv->bands[IEEE80211_BAND_2GHZ];
  3973. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  3974. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  3975. &priv->bands[IEEE80211_BAND_5GHZ];
  3976. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3977. return 0;
  3978. }
  3979. /*
  3980. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  3981. */
  3982. static void iwl3945_free_geos(struct iwl_priv *priv)
  3983. {
  3984. kfree(priv->ieee_channels);
  3985. kfree(priv->ieee_rates);
  3986. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3987. }
  3988. /******************************************************************************
  3989. *
  3990. * uCode download functions
  3991. *
  3992. ******************************************************************************/
  3993. static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
  3994. {
  3995. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  3996. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  3997. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  3998. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  3999. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4000. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4001. }
  4002. /**
  4003. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4004. * looking at all data.
  4005. */
  4006. static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
  4007. {
  4008. u32 val;
  4009. u32 save_len = len;
  4010. int rc = 0;
  4011. u32 errcnt;
  4012. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4013. rc = iwl_grab_nic_access(priv);
  4014. if (rc)
  4015. return rc;
  4016. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4017. IWL39_RTC_INST_LOWER_BOUND);
  4018. errcnt = 0;
  4019. for (; len > 0; len -= sizeof(u32), image++) {
  4020. /* read data comes through single port, auto-incr addr */
  4021. /* NOTE: Use the debugless read so we don't flood kernel log
  4022. * if IWL_DL_IO is set */
  4023. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4024. if (val != le32_to_cpu(*image)) {
  4025. IWL_ERR(priv, "uCode INST section is invalid at "
  4026. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4027. save_len - len, val, le32_to_cpu(*image));
  4028. rc = -EIO;
  4029. errcnt++;
  4030. if (errcnt >= 20)
  4031. break;
  4032. }
  4033. }
  4034. iwl_release_nic_access(priv);
  4035. if (!errcnt)
  4036. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4037. return rc;
  4038. }
  4039. /**
  4040. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4041. * using sample data 100 bytes apart. If these sample points are good,
  4042. * it's a pretty good bet that everything between them is good, too.
  4043. */
  4044. static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  4045. {
  4046. u32 val;
  4047. int rc = 0;
  4048. u32 errcnt = 0;
  4049. u32 i;
  4050. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4051. rc = iwl_grab_nic_access(priv);
  4052. if (rc)
  4053. return rc;
  4054. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4055. /* read data comes through single port, auto-incr addr */
  4056. /* NOTE: Use the debugless read so we don't flood kernel log
  4057. * if IWL_DL_IO is set */
  4058. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4059. i + IWL39_RTC_INST_LOWER_BOUND);
  4060. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4061. if (val != le32_to_cpu(*image)) {
  4062. #if 0 /* Enable this if you want to see details */
  4063. IWL_ERR(priv, "uCode INST section is invalid at "
  4064. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4065. i, val, *image);
  4066. #endif
  4067. rc = -EIO;
  4068. errcnt++;
  4069. if (errcnt >= 3)
  4070. break;
  4071. }
  4072. }
  4073. iwl_release_nic_access(priv);
  4074. return rc;
  4075. }
  4076. /**
  4077. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4078. * and verify its contents
  4079. */
  4080. static int iwl3945_verify_ucode(struct iwl_priv *priv)
  4081. {
  4082. __le32 *image;
  4083. u32 len;
  4084. int rc = 0;
  4085. /* Try bootstrap */
  4086. image = (__le32 *)priv->ucode_boot.v_addr;
  4087. len = priv->ucode_boot.len;
  4088. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4089. if (rc == 0) {
  4090. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4091. return 0;
  4092. }
  4093. /* Try initialize */
  4094. image = (__le32 *)priv->ucode_init.v_addr;
  4095. len = priv->ucode_init.len;
  4096. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4097. if (rc == 0) {
  4098. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4099. return 0;
  4100. }
  4101. /* Try runtime/protocol */
  4102. image = (__le32 *)priv->ucode_code.v_addr;
  4103. len = priv->ucode_code.len;
  4104. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4105. if (rc == 0) {
  4106. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4107. return 0;
  4108. }
  4109. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4110. /* Since nothing seems to match, show first several data entries in
  4111. * instruction SRAM, so maybe visual inspection will give a clue.
  4112. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4113. image = (__le32 *)priv->ucode_boot.v_addr;
  4114. len = priv->ucode_boot.len;
  4115. rc = iwl3945_verify_inst_full(priv, image, len);
  4116. return rc;
  4117. }
  4118. static void iwl3945_nic_start(struct iwl_priv *priv)
  4119. {
  4120. /* Remove all resets to allow NIC to operate */
  4121. iwl_write32(priv, CSR_RESET, 0);
  4122. }
  4123. /**
  4124. * iwl3945_read_ucode - Read uCode images from disk file.
  4125. *
  4126. * Copy into buffers for card to fetch via bus-mastering
  4127. */
  4128. static int iwl3945_read_ucode(struct iwl_priv *priv)
  4129. {
  4130. struct iwl_ucode *ucode;
  4131. int ret = -EINVAL, index;
  4132. const struct firmware *ucode_raw;
  4133. /* firmware file name contains uCode/driver compatibility version */
  4134. const char *name_pre = priv->cfg->fw_name_pre;
  4135. const unsigned int api_max = priv->cfg->ucode_api_max;
  4136. const unsigned int api_min = priv->cfg->ucode_api_min;
  4137. char buf[25];
  4138. u8 *src;
  4139. size_t len;
  4140. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4141. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4142. * request_firmware() is synchronous, file is in memory on return. */
  4143. for (index = api_max; index >= api_min; index--) {
  4144. sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
  4145. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  4146. if (ret < 0) {
  4147. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  4148. buf, ret);
  4149. if (ret == -ENOENT)
  4150. continue;
  4151. else
  4152. goto error;
  4153. } else {
  4154. if (index < api_max)
  4155. IWL_ERR(priv, "Loaded firmware %s, "
  4156. "which is deprecated. "
  4157. " Please use API v%u instead.\n",
  4158. buf, api_max);
  4159. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4160. buf, ucode_raw->size);
  4161. break;
  4162. }
  4163. }
  4164. if (ret < 0)
  4165. goto error;
  4166. /* Make sure that we got at least our header! */
  4167. if (ucode_raw->size < sizeof(*ucode)) {
  4168. IWL_ERR(priv, "File size way too small!\n");
  4169. ret = -EINVAL;
  4170. goto err_release;
  4171. }
  4172. /* Data from ucode file: header followed by uCode images */
  4173. ucode = (void *)ucode_raw->data;
  4174. priv->ucode_ver = le32_to_cpu(ucode->ver);
  4175. api_ver = IWL_UCODE_API(priv->ucode_ver);
  4176. inst_size = le32_to_cpu(ucode->inst_size);
  4177. data_size = le32_to_cpu(ucode->data_size);
  4178. init_size = le32_to_cpu(ucode->init_size);
  4179. init_data_size = le32_to_cpu(ucode->init_data_size);
  4180. boot_size = le32_to_cpu(ucode->boot_size);
  4181. /* api_ver should match the api version forming part of the
  4182. * firmware filename ... but we don't check for that and only rely
  4183. * on the API version read from firware header from here on forward */
  4184. if (api_ver < api_min || api_ver > api_max) {
  4185. IWL_ERR(priv, "Driver unable to support your firmware API. "
  4186. "Driver supports v%u, firmware is v%u.\n",
  4187. api_max, api_ver);
  4188. priv->ucode_ver = 0;
  4189. ret = -EINVAL;
  4190. goto err_release;
  4191. }
  4192. if (api_ver != api_max)
  4193. IWL_ERR(priv, "Firmware has old API version. Expected %u, "
  4194. "got %u. New firmware can be obtained "
  4195. "from http://www.intellinuxwireless.org.\n",
  4196. api_max, api_ver);
  4197. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  4198. IWL_UCODE_MAJOR(priv->ucode_ver),
  4199. IWL_UCODE_MINOR(priv->ucode_ver),
  4200. IWL_UCODE_API(priv->ucode_ver),
  4201. IWL_UCODE_SERIAL(priv->ucode_ver));
  4202. IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n",
  4203. priv->ucode_ver);
  4204. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4205. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4206. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4207. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4208. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4209. /* Verify size of file vs. image size info in file's header */
  4210. if (ucode_raw->size < sizeof(*ucode) +
  4211. inst_size + data_size + init_size +
  4212. init_data_size + boot_size) {
  4213. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4214. (int)ucode_raw->size);
  4215. ret = -EINVAL;
  4216. goto err_release;
  4217. }
  4218. /* Verify that uCode images will fit in card's SRAM */
  4219. if (inst_size > IWL39_MAX_INST_SIZE) {
  4220. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4221. inst_size);
  4222. ret = -EINVAL;
  4223. goto err_release;
  4224. }
  4225. if (data_size > IWL39_MAX_DATA_SIZE) {
  4226. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4227. data_size);
  4228. ret = -EINVAL;
  4229. goto err_release;
  4230. }
  4231. if (init_size > IWL39_MAX_INST_SIZE) {
  4232. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4233. init_size);
  4234. ret = -EINVAL;
  4235. goto err_release;
  4236. }
  4237. if (init_data_size > IWL39_MAX_DATA_SIZE) {
  4238. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4239. init_data_size);
  4240. ret = -EINVAL;
  4241. goto err_release;
  4242. }
  4243. if (boot_size > IWL39_MAX_BSM_SIZE) {
  4244. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4245. boot_size);
  4246. ret = -EINVAL;
  4247. goto err_release;
  4248. }
  4249. /* Allocate ucode buffers for card's bus-master loading ... */
  4250. /* Runtime instructions and 2 copies of data:
  4251. * 1) unmodified from disk
  4252. * 2) backup cache for save/restore during power-downs */
  4253. priv->ucode_code.len = inst_size;
  4254. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4255. priv->ucode_data.len = data_size;
  4256. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4257. priv->ucode_data_backup.len = data_size;
  4258. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4259. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4260. !priv->ucode_data_backup.v_addr)
  4261. goto err_pci_alloc;
  4262. /* Initialization instructions and data */
  4263. if (init_size && init_data_size) {
  4264. priv->ucode_init.len = init_size;
  4265. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4266. priv->ucode_init_data.len = init_data_size;
  4267. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4268. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4269. goto err_pci_alloc;
  4270. }
  4271. /* Bootstrap (instructions only, no data) */
  4272. if (boot_size) {
  4273. priv->ucode_boot.len = boot_size;
  4274. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4275. if (!priv->ucode_boot.v_addr)
  4276. goto err_pci_alloc;
  4277. }
  4278. /* Copy images into buffers for card's bus-master reads ... */
  4279. /* Runtime instructions (first block of data in file) */
  4280. src = &ucode->data[0];
  4281. len = priv->ucode_code.len;
  4282. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4283. memcpy(priv->ucode_code.v_addr, src, len);
  4284. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4285. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4286. /* Runtime data (2nd block)
  4287. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4288. src = &ucode->data[inst_size];
  4289. len = priv->ucode_data.len;
  4290. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4291. memcpy(priv->ucode_data.v_addr, src, len);
  4292. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4293. /* Initialization instructions (3rd block) */
  4294. if (init_size) {
  4295. src = &ucode->data[inst_size + data_size];
  4296. len = priv->ucode_init.len;
  4297. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4298. len);
  4299. memcpy(priv->ucode_init.v_addr, src, len);
  4300. }
  4301. /* Initialization data (4th block) */
  4302. if (init_data_size) {
  4303. src = &ucode->data[inst_size + data_size + init_size];
  4304. len = priv->ucode_init_data.len;
  4305. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4306. (int)len);
  4307. memcpy(priv->ucode_init_data.v_addr, src, len);
  4308. }
  4309. /* Bootstrap instructions (5th block) */
  4310. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4311. len = priv->ucode_boot.len;
  4312. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4313. (int)len);
  4314. memcpy(priv->ucode_boot.v_addr, src, len);
  4315. /* We have our copies now, allow OS release its copies */
  4316. release_firmware(ucode_raw);
  4317. return 0;
  4318. err_pci_alloc:
  4319. IWL_ERR(priv, "failed to allocate pci memory\n");
  4320. ret = -ENOMEM;
  4321. iwl3945_dealloc_ucode_pci(priv);
  4322. err_release:
  4323. release_firmware(ucode_raw);
  4324. error:
  4325. return ret;
  4326. }
  4327. /**
  4328. * iwl3945_set_ucode_ptrs - Set uCode address location
  4329. *
  4330. * Tell initialization uCode where to find runtime uCode.
  4331. *
  4332. * BSM registers initially contain pointers to initialization uCode.
  4333. * We need to replace them to load runtime uCode inst and data,
  4334. * and to save runtime data when powering down.
  4335. */
  4336. static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
  4337. {
  4338. dma_addr_t pinst;
  4339. dma_addr_t pdata;
  4340. int rc = 0;
  4341. unsigned long flags;
  4342. /* bits 31:0 for 3945 */
  4343. pinst = priv->ucode_code.p_addr;
  4344. pdata = priv->ucode_data_backup.p_addr;
  4345. spin_lock_irqsave(&priv->lock, flags);
  4346. rc = iwl_grab_nic_access(priv);
  4347. if (rc) {
  4348. spin_unlock_irqrestore(&priv->lock, flags);
  4349. return rc;
  4350. }
  4351. /* Tell bootstrap uCode where to find image to load */
  4352. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4353. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4354. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  4355. priv->ucode_data.len);
  4356. /* Inst byte count must be last to set up, bit 31 signals uCode
  4357. * that all new ptr/size info is in place */
  4358. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  4359. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  4360. iwl_release_nic_access(priv);
  4361. spin_unlock_irqrestore(&priv->lock, flags);
  4362. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  4363. return rc;
  4364. }
  4365. /**
  4366. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  4367. *
  4368. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  4369. *
  4370. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  4371. */
  4372. static void iwl3945_init_alive_start(struct iwl_priv *priv)
  4373. {
  4374. /* Check alive response for "valid" sign from uCode */
  4375. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  4376. /* We had an error bringing up the hardware, so take it
  4377. * all the way back down so we can try again */
  4378. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  4379. goto restart;
  4380. }
  4381. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  4382. * This is a paranoid check, because we would not have gotten the
  4383. * "initialize" alive if code weren't properly loaded. */
  4384. if (iwl3945_verify_ucode(priv)) {
  4385. /* Runtime instruction load was bad;
  4386. * take it all the way back down so we can try again */
  4387. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  4388. goto restart;
  4389. }
  4390. /* Send pointers to protocol/runtime uCode image ... init code will
  4391. * load and launch runtime uCode, which will send us another "Alive"
  4392. * notification. */
  4393. IWL_DEBUG_INFO("Initialization Alive received.\n");
  4394. if (iwl3945_set_ucode_ptrs(priv)) {
  4395. /* Runtime instruction load won't happen;
  4396. * take it all the way back down so we can try again */
  4397. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  4398. goto restart;
  4399. }
  4400. return;
  4401. restart:
  4402. queue_work(priv->workqueue, &priv->restart);
  4403. }
  4404. /* temporary */
  4405. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw,
  4406. struct sk_buff *skb);
  4407. /**
  4408. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  4409. * from protocol/runtime uCode (initialization uCode's
  4410. * Alive gets handled by iwl3945_init_alive_start()).
  4411. */
  4412. static void iwl3945_alive_start(struct iwl_priv *priv)
  4413. {
  4414. int rc = 0;
  4415. int thermal_spin = 0;
  4416. u32 rfkill;
  4417. IWL_DEBUG_INFO("Runtime Alive received.\n");
  4418. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  4419. /* We had an error bringing up the hardware, so take it
  4420. * all the way back down so we can try again */
  4421. IWL_DEBUG_INFO("Alive failed.\n");
  4422. goto restart;
  4423. }
  4424. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  4425. * This is a paranoid check, because we would not have gotten the
  4426. * "runtime" alive if code weren't properly loaded. */
  4427. if (iwl3945_verify_ucode(priv)) {
  4428. /* Runtime instruction load was bad;
  4429. * take it all the way back down so we can try again */
  4430. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  4431. goto restart;
  4432. }
  4433. iwl3945_clear_stations_table(priv);
  4434. rc = iwl_grab_nic_access(priv);
  4435. if (rc) {
  4436. IWL_WARN(priv, "Can not read RFKILL status from adapter\n");
  4437. return;
  4438. }
  4439. rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
  4440. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  4441. iwl_release_nic_access(priv);
  4442. if (rfkill & 0x1) {
  4443. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4444. /* if RFKILL is not on, then wait for thermal
  4445. * sensor in adapter to kick in */
  4446. while (iwl3945_hw_get_temperature(priv) == 0) {
  4447. thermal_spin++;
  4448. udelay(10);
  4449. }
  4450. if (thermal_spin)
  4451. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  4452. thermal_spin * 10);
  4453. } else
  4454. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4455. /* After the ALIVE response, we can send commands to 3945 uCode */
  4456. set_bit(STATUS_ALIVE, &priv->status);
  4457. /* Clear out the uCode error bit if it is set */
  4458. clear_bit(STATUS_FW_ERROR, &priv->status);
  4459. if (iwl_is_rfkill(priv))
  4460. return;
  4461. ieee80211_wake_queues(priv->hw);
  4462. priv->active_rate = priv->rates_mask;
  4463. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  4464. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  4465. if (iwl3945_is_associated(priv)) {
  4466. struct iwl3945_rxon_cmd *active_rxon =
  4467. (struct iwl3945_rxon_cmd *)(&priv->active39_rxon);
  4468. memcpy(&priv->staging39_rxon, &priv->active39_rxon,
  4469. sizeof(priv->staging39_rxon));
  4470. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4471. } else {
  4472. /* Initialize our rx_config data */
  4473. iwl3945_connection_init_rx_config(priv, priv->iw_mode);
  4474. memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  4475. }
  4476. /* Configure Bluetooth device coexistence support */
  4477. iwl3945_send_bt_config(priv);
  4478. /* Configure the adapter for unassociated operation */
  4479. iwl3945_commit_rxon(priv);
  4480. iwl3945_reg_txpower_periodic(priv);
  4481. iwl3945_led_register(priv);
  4482. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  4483. set_bit(STATUS_READY, &priv->status);
  4484. wake_up_interruptible(&priv->wait_command_queue);
  4485. if (priv->error_recovering)
  4486. iwl3945_error_recovery(priv);
  4487. /* reassociate for ADHOC mode */
  4488. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  4489. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  4490. priv->vif);
  4491. if (beacon)
  4492. iwl3945_mac_beacon_update(priv->hw, beacon);
  4493. }
  4494. return;
  4495. restart:
  4496. queue_work(priv->workqueue, &priv->restart);
  4497. }
  4498. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
  4499. static void __iwl3945_down(struct iwl_priv *priv)
  4500. {
  4501. unsigned long flags;
  4502. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  4503. struct ieee80211_conf *conf = NULL;
  4504. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  4505. conf = ieee80211_get_hw_conf(priv->hw);
  4506. if (!exit_pending)
  4507. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4508. iwl3945_led_unregister(priv);
  4509. iwl3945_clear_stations_table(priv);
  4510. /* Unblock any waiting calls */
  4511. wake_up_interruptible_all(&priv->wait_command_queue);
  4512. /* Wipe out the EXIT_PENDING status bit if we are not actually
  4513. * exiting the module */
  4514. if (!exit_pending)
  4515. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4516. /* stop and reset the on-board processor */
  4517. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  4518. /* tell the device to stop sending interrupts */
  4519. spin_lock_irqsave(&priv->lock, flags);
  4520. iwl3945_disable_interrupts(priv);
  4521. spin_unlock_irqrestore(&priv->lock, flags);
  4522. iwl_synchronize_irq(priv);
  4523. if (priv->mac80211_registered)
  4524. ieee80211_stop_queues(priv->hw);
  4525. /* If we have not previously called iwl3945_init() then
  4526. * clear all bits but the RF Kill and SUSPEND bits and return */
  4527. if (!iwl_is_init(priv)) {
  4528. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4529. STATUS_RF_KILL_HW |
  4530. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4531. STATUS_RF_KILL_SW |
  4532. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4533. STATUS_GEO_CONFIGURED |
  4534. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4535. STATUS_IN_SUSPEND |
  4536. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4537. STATUS_EXIT_PENDING;
  4538. goto exit;
  4539. }
  4540. /* ...otherwise clear out all the status bits but the RF Kill and
  4541. * SUSPEND bits and continue taking the NIC down. */
  4542. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4543. STATUS_RF_KILL_HW |
  4544. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4545. STATUS_RF_KILL_SW |
  4546. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4547. STATUS_GEO_CONFIGURED |
  4548. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4549. STATUS_IN_SUSPEND |
  4550. test_bit(STATUS_FW_ERROR, &priv->status) <<
  4551. STATUS_FW_ERROR |
  4552. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4553. STATUS_EXIT_PENDING;
  4554. spin_lock_irqsave(&priv->lock, flags);
  4555. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  4556. spin_unlock_irqrestore(&priv->lock, flags);
  4557. iwl3945_hw_txq_ctx_stop(priv);
  4558. iwl3945_hw_rxq_stop(priv);
  4559. spin_lock_irqsave(&priv->lock, flags);
  4560. if (!iwl_grab_nic_access(priv)) {
  4561. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  4562. APMG_CLK_VAL_DMA_CLK_RQT);
  4563. iwl_release_nic_access(priv);
  4564. }
  4565. spin_unlock_irqrestore(&priv->lock, flags);
  4566. udelay(5);
  4567. priv->cfg->ops->lib->apm_ops.reset(priv);
  4568. exit:
  4569. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  4570. if (priv->ibss_beacon)
  4571. dev_kfree_skb(priv->ibss_beacon);
  4572. priv->ibss_beacon = NULL;
  4573. /* clear out any free frames */
  4574. iwl3945_clear_free_frames(priv);
  4575. }
  4576. static void iwl3945_down(struct iwl_priv *priv)
  4577. {
  4578. mutex_lock(&priv->mutex);
  4579. __iwl3945_down(priv);
  4580. mutex_unlock(&priv->mutex);
  4581. iwl3945_cancel_deferred_work(priv);
  4582. }
  4583. #define MAX_HW_RESTARTS 5
  4584. static int __iwl3945_up(struct iwl_priv *priv)
  4585. {
  4586. int rc, i;
  4587. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4588. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  4589. return -EIO;
  4590. }
  4591. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  4592. IWL_WARN(priv, "Radio disabled by SW RF kill (module "
  4593. "parameter)\n");
  4594. return -ENODEV;
  4595. }
  4596. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  4597. IWL_ERR(priv, "ucode not available for device bring up\n");
  4598. return -EIO;
  4599. }
  4600. /* If platform's RF_KILL switch is NOT set to KILL */
  4601. if (iwl_read32(priv, CSR_GP_CNTRL) &
  4602. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  4603. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4604. else {
  4605. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4606. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  4607. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  4608. return -ENODEV;
  4609. }
  4610. }
  4611. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  4612. rc = iwl3945_hw_nic_init(priv);
  4613. if (rc) {
  4614. IWL_ERR(priv, "Unable to int nic\n");
  4615. return rc;
  4616. }
  4617. /* make sure rfkill handshake bits are cleared */
  4618. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4619. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  4620. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  4621. /* clear (again), then enable host interrupts */
  4622. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  4623. iwl3945_enable_interrupts(priv);
  4624. /* really make sure rfkill handshake bits are cleared */
  4625. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4626. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4627. /* Copy original ucode data image from disk into backup cache.
  4628. * This will be used to initialize the on-board processor's
  4629. * data SRAM for a clean start when the runtime program first loads. */
  4630. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  4631. priv->ucode_data.len);
  4632. /* We return success when we resume from suspend and rf_kill is on. */
  4633. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  4634. return 0;
  4635. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  4636. iwl3945_clear_stations_table(priv);
  4637. /* load bootstrap state machine,
  4638. * load bootstrap program into processor's memory,
  4639. * prepare to load the "initialize" uCode */
  4640. priv->cfg->ops->lib->load_ucode(priv);
  4641. if (rc) {
  4642. IWL_ERR(priv,
  4643. "Unable to set up bootstrap uCode: %d\n", rc);
  4644. continue;
  4645. }
  4646. /* start card; "initialize" will load runtime ucode */
  4647. iwl3945_nic_start(priv);
  4648. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  4649. return 0;
  4650. }
  4651. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4652. __iwl3945_down(priv);
  4653. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4654. /* tried to restart and config the device for as long as our
  4655. * patience could withstand */
  4656. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  4657. return -EIO;
  4658. }
  4659. /*****************************************************************************
  4660. *
  4661. * Workqueue callbacks
  4662. *
  4663. *****************************************************************************/
  4664. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  4665. {
  4666. struct iwl_priv *priv =
  4667. container_of(data, struct iwl_priv, init_alive_start.work);
  4668. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4669. return;
  4670. mutex_lock(&priv->mutex);
  4671. iwl3945_init_alive_start(priv);
  4672. mutex_unlock(&priv->mutex);
  4673. }
  4674. static void iwl3945_bg_alive_start(struct work_struct *data)
  4675. {
  4676. struct iwl_priv *priv =
  4677. container_of(data, struct iwl_priv, alive_start.work);
  4678. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4679. return;
  4680. mutex_lock(&priv->mutex);
  4681. iwl3945_alive_start(priv);
  4682. mutex_unlock(&priv->mutex);
  4683. }
  4684. static void iwl3945_bg_rf_kill(struct work_struct *work)
  4685. {
  4686. struct iwl_priv *priv = container_of(work, struct iwl_priv, rf_kill);
  4687. wake_up_interruptible(&priv->wait_command_queue);
  4688. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4689. return;
  4690. mutex_lock(&priv->mutex);
  4691. if (!iwl_is_rfkill(priv)) {
  4692. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  4693. "HW and/or SW RF Kill no longer active, restarting "
  4694. "device\n");
  4695. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  4696. queue_work(priv->workqueue, &priv->restart);
  4697. } else {
  4698. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  4699. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  4700. "disabled by SW switch\n");
  4701. else
  4702. IWL_WARN(priv, "Radio Frequency Kill Switch is On:\n"
  4703. "Kill switch must be turned off for "
  4704. "wireless networking to work.\n");
  4705. }
  4706. mutex_unlock(&priv->mutex);
  4707. iwl3945_rfkill_set_hw_state(priv);
  4708. }
  4709. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  4710. static void iwl3945_bg_scan_check(struct work_struct *data)
  4711. {
  4712. struct iwl_priv *priv =
  4713. container_of(data, struct iwl_priv, scan_check.work);
  4714. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4715. return;
  4716. mutex_lock(&priv->mutex);
  4717. if (test_bit(STATUS_SCANNING, &priv->status) ||
  4718. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  4719. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  4720. "Scan completion watchdog resetting adapter (%dms)\n",
  4721. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  4722. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  4723. iwl3945_send_scan_abort(priv);
  4724. }
  4725. mutex_unlock(&priv->mutex);
  4726. }
  4727. static void iwl3945_bg_request_scan(struct work_struct *data)
  4728. {
  4729. struct iwl_priv *priv =
  4730. container_of(data, struct iwl_priv, request_scan);
  4731. struct iwl_host_cmd cmd = {
  4732. .id = REPLY_SCAN_CMD,
  4733. .len = sizeof(struct iwl3945_scan_cmd),
  4734. .meta.flags = CMD_SIZE_HUGE,
  4735. };
  4736. int rc = 0;
  4737. struct iwl3945_scan_cmd *scan;
  4738. struct ieee80211_conf *conf = NULL;
  4739. u8 n_probes = 2;
  4740. enum ieee80211_band band;
  4741. DECLARE_SSID_BUF(ssid);
  4742. conf = ieee80211_get_hw_conf(priv->hw);
  4743. mutex_lock(&priv->mutex);
  4744. if (!iwl_is_ready(priv)) {
  4745. IWL_WARN(priv, "request scan called when driver not ready.\n");
  4746. goto done;
  4747. }
  4748. /* Make sure the scan wasn't canceled before this queued work
  4749. * was given the chance to run... */
  4750. if (!test_bit(STATUS_SCANNING, &priv->status))
  4751. goto done;
  4752. /* This should never be called or scheduled if there is currently
  4753. * a scan active in the hardware. */
  4754. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  4755. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  4756. "Ignoring second request.\n");
  4757. rc = -EIO;
  4758. goto done;
  4759. }
  4760. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4761. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  4762. goto done;
  4763. }
  4764. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  4765. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  4766. goto done;
  4767. }
  4768. if (iwl_is_rfkill(priv)) {
  4769. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  4770. goto done;
  4771. }
  4772. if (!test_bit(STATUS_READY, &priv->status)) {
  4773. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  4774. goto done;
  4775. }
  4776. if (!priv->scan_bands) {
  4777. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  4778. goto done;
  4779. }
  4780. if (!priv->scan39) {
  4781. priv->scan39 = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  4782. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  4783. if (!priv->scan39) {
  4784. rc = -ENOMEM;
  4785. goto done;
  4786. }
  4787. }
  4788. scan = priv->scan39;
  4789. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  4790. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  4791. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  4792. if (iwl3945_is_associated(priv)) {
  4793. u16 interval = 0;
  4794. u32 extra;
  4795. u32 suspend_time = 100;
  4796. u32 scan_suspend_time = 100;
  4797. unsigned long flags;
  4798. IWL_DEBUG_INFO("Scanning while associated...\n");
  4799. spin_lock_irqsave(&priv->lock, flags);
  4800. interval = priv->beacon_int;
  4801. spin_unlock_irqrestore(&priv->lock, flags);
  4802. scan->suspend_time = 0;
  4803. scan->max_out_time = cpu_to_le32(200 * 1024);
  4804. if (!interval)
  4805. interval = suspend_time;
  4806. /*
  4807. * suspend time format:
  4808. * 0-19: beacon interval in usec (time before exec.)
  4809. * 20-23: 0
  4810. * 24-31: number of beacons (suspend between channels)
  4811. */
  4812. extra = (suspend_time / interval) << 24;
  4813. scan_suspend_time = 0xFF0FFFFF &
  4814. (extra | ((suspend_time % interval) * 1024));
  4815. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  4816. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  4817. scan_suspend_time, interval);
  4818. }
  4819. /* We should add the ability for user to lock to PASSIVE ONLY */
  4820. if (priv->one_direct_scan) {
  4821. IWL_DEBUG_SCAN
  4822. ("Kicking off one direct scan for '%s'\n",
  4823. print_ssid(ssid, priv->direct_ssid,
  4824. priv->direct_ssid_len));
  4825. scan->direct_scan[0].id = WLAN_EID_SSID;
  4826. scan->direct_scan[0].len = priv->direct_ssid_len;
  4827. memcpy(scan->direct_scan[0].ssid,
  4828. priv->direct_ssid, priv->direct_ssid_len);
  4829. n_probes++;
  4830. } else
  4831. IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
  4832. /* We don't build a direct scan probe request; the uCode will do
  4833. * that based on the direct_mask added to each channel entry */
  4834. scan->tx_cmd.len = cpu_to_le16(
  4835. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  4836. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  4837. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  4838. scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
  4839. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  4840. /* flags + rate selection */
  4841. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
  4842. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  4843. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  4844. scan->good_CRC_th = 0;
  4845. band = IEEE80211_BAND_2GHZ;
  4846. } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
  4847. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  4848. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  4849. band = IEEE80211_BAND_5GHZ;
  4850. } else {
  4851. IWL_WARN(priv, "Invalid scan band count\n");
  4852. goto done;
  4853. }
  4854. /* select Rx antennas */
  4855. scan->flags |= iwl3945_get_antenna_flags(priv);
  4856. if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
  4857. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  4858. scan->channel_count =
  4859. iwl3945_get_channels_for_scan(priv, band, 1, /* active */
  4860. n_probes,
  4861. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  4862. if (scan->channel_count == 0) {
  4863. IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
  4864. goto done;
  4865. }
  4866. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  4867. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  4868. cmd.data = scan;
  4869. scan->len = cpu_to_le16(cmd.len);
  4870. set_bit(STATUS_SCAN_HW, &priv->status);
  4871. rc = iwl3945_send_cmd_sync(priv, &cmd);
  4872. if (rc)
  4873. goto done;
  4874. queue_delayed_work(priv->workqueue, &priv->scan_check,
  4875. IWL_SCAN_CHECK_WATCHDOG);
  4876. mutex_unlock(&priv->mutex);
  4877. return;
  4878. done:
  4879. /* can not perform scan make sure we clear scanning
  4880. * bits from status so next scan request can be performed.
  4881. * if we dont clear scanning status bit here all next scan
  4882. * will fail
  4883. */
  4884. clear_bit(STATUS_SCAN_HW, &priv->status);
  4885. clear_bit(STATUS_SCANNING, &priv->status);
  4886. /* inform mac80211 scan aborted */
  4887. queue_work(priv->workqueue, &priv->scan_completed);
  4888. mutex_unlock(&priv->mutex);
  4889. }
  4890. static void iwl3945_bg_up(struct work_struct *data)
  4891. {
  4892. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  4893. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4894. return;
  4895. mutex_lock(&priv->mutex);
  4896. __iwl3945_up(priv);
  4897. mutex_unlock(&priv->mutex);
  4898. iwl3945_rfkill_set_hw_state(priv);
  4899. }
  4900. static void iwl3945_bg_restart(struct work_struct *data)
  4901. {
  4902. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  4903. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4904. return;
  4905. iwl3945_down(priv);
  4906. queue_work(priv->workqueue, &priv->up);
  4907. }
  4908. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  4909. {
  4910. struct iwl_priv *priv =
  4911. container_of(data, struct iwl_priv, rx_replenish);
  4912. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4913. return;
  4914. mutex_lock(&priv->mutex);
  4915. iwl3945_rx_replenish(priv);
  4916. mutex_unlock(&priv->mutex);
  4917. }
  4918. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  4919. static void iwl3945_post_associate(struct iwl_priv *priv)
  4920. {
  4921. int rc = 0;
  4922. struct ieee80211_conf *conf = NULL;
  4923. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  4924. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  4925. return;
  4926. }
  4927. IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
  4928. priv->assoc_id, priv->active39_rxon.bssid_addr);
  4929. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4930. return;
  4931. if (!priv->vif || !priv->is_open)
  4932. return;
  4933. iwl3945_scan_cancel_timeout(priv, 200);
  4934. conf = ieee80211_get_hw_conf(priv->hw);
  4935. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4936. iwl3945_commit_rxon(priv);
  4937. memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
  4938. iwl3945_setup_rxon_timing(priv);
  4939. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  4940. sizeof(priv->rxon_timing), &priv->rxon_timing);
  4941. if (rc)
  4942. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  4943. "Attempting to continue.\n");
  4944. priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  4945. priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  4946. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  4947. priv->assoc_id, priv->beacon_int);
  4948. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  4949. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  4950. else
  4951. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  4952. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  4953. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  4954. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  4955. else
  4956. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  4957. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  4958. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  4959. }
  4960. iwl3945_commit_rxon(priv);
  4961. switch (priv->iw_mode) {
  4962. case NL80211_IFTYPE_STATION:
  4963. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  4964. break;
  4965. case NL80211_IFTYPE_ADHOC:
  4966. priv->assoc_id = 1;
  4967. iwl3945_add_station(priv, priv->bssid, 0, 0);
  4968. iwl3945_sync_sta(priv, IWL_STA_ID,
  4969. (priv->band == IEEE80211_BAND_5GHZ) ?
  4970. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  4971. CMD_ASYNC);
  4972. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  4973. iwl3945_send_beacon_cmd(priv);
  4974. break;
  4975. default:
  4976. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  4977. __func__, priv->iw_mode);
  4978. break;
  4979. }
  4980. iwl3945_activate_qos(priv, 0);
  4981. /* we have just associated, don't start scan too early */
  4982. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  4983. }
  4984. static void iwl3945_bg_abort_scan(struct work_struct *work)
  4985. {
  4986. struct iwl_priv *priv = container_of(work, struct iwl_priv, abort_scan);
  4987. if (!iwl_is_ready(priv))
  4988. return;
  4989. mutex_lock(&priv->mutex);
  4990. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  4991. iwl3945_send_scan_abort(priv);
  4992. mutex_unlock(&priv->mutex);
  4993. }
  4994. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
  4995. static void iwl3945_bg_scan_completed(struct work_struct *work)
  4996. {
  4997. struct iwl_priv *priv =
  4998. container_of(work, struct iwl_priv, scan_completed);
  4999. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5000. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5001. return;
  5002. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  5003. iwl3945_mac_config(priv->hw, 0);
  5004. ieee80211_scan_completed(priv->hw);
  5005. /* Since setting the TXPOWER may have been deferred while
  5006. * performing the scan, fire one off */
  5007. mutex_lock(&priv->mutex);
  5008. iwl3945_hw_reg_send_txpower(priv);
  5009. mutex_unlock(&priv->mutex);
  5010. }
  5011. /*****************************************************************************
  5012. *
  5013. * mac80211 entry point functions
  5014. *
  5015. *****************************************************************************/
  5016. #define UCODE_READY_TIMEOUT (2 * HZ)
  5017. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5018. {
  5019. struct iwl_priv *priv = hw->priv;
  5020. int ret;
  5021. IWL_DEBUG_MAC80211("enter\n");
  5022. if (pci_enable_device(priv->pci_dev)) {
  5023. IWL_ERR(priv, "Fail to pci_enable_device\n");
  5024. return -ENODEV;
  5025. }
  5026. pci_restore_state(priv->pci_dev);
  5027. pci_enable_msi(priv->pci_dev);
  5028. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  5029. DRV_NAME, priv);
  5030. if (ret) {
  5031. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  5032. goto out_disable_msi;
  5033. }
  5034. /* we should be verifying the device is ready to be opened */
  5035. mutex_lock(&priv->mutex);
  5036. memset(&priv->staging39_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  5037. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  5038. * ucode filename and max sizes are card-specific. */
  5039. if (!priv->ucode_code.len) {
  5040. ret = iwl3945_read_ucode(priv);
  5041. if (ret) {
  5042. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  5043. mutex_unlock(&priv->mutex);
  5044. goto out_release_irq;
  5045. }
  5046. }
  5047. ret = __iwl3945_up(priv);
  5048. mutex_unlock(&priv->mutex);
  5049. iwl3945_rfkill_set_hw_state(priv);
  5050. if (ret)
  5051. goto out_release_irq;
  5052. IWL_DEBUG_INFO("Start UP work.\n");
  5053. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  5054. return 0;
  5055. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  5056. * mac80211 will not be run successfully. */
  5057. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  5058. test_bit(STATUS_READY, &priv->status),
  5059. UCODE_READY_TIMEOUT);
  5060. if (!ret) {
  5061. if (!test_bit(STATUS_READY, &priv->status)) {
  5062. IWL_ERR(priv,
  5063. "Wait for START_ALIVE timeout after %dms.\n",
  5064. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  5065. ret = -ETIMEDOUT;
  5066. goto out_release_irq;
  5067. }
  5068. }
  5069. priv->is_open = 1;
  5070. IWL_DEBUG_MAC80211("leave\n");
  5071. return 0;
  5072. out_release_irq:
  5073. free_irq(priv->pci_dev->irq, priv);
  5074. out_disable_msi:
  5075. pci_disable_msi(priv->pci_dev);
  5076. pci_disable_device(priv->pci_dev);
  5077. priv->is_open = 0;
  5078. IWL_DEBUG_MAC80211("leave - failed\n");
  5079. return ret;
  5080. }
  5081. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5082. {
  5083. struct iwl_priv *priv = hw->priv;
  5084. IWL_DEBUG_MAC80211("enter\n");
  5085. if (!priv->is_open) {
  5086. IWL_DEBUG_MAC80211("leave - skip\n");
  5087. return;
  5088. }
  5089. priv->is_open = 0;
  5090. if (iwl_is_ready_rf(priv)) {
  5091. /* stop mac, cancel any scan request and clear
  5092. * RXON_FILTER_ASSOC_MSK BIT
  5093. */
  5094. mutex_lock(&priv->mutex);
  5095. iwl3945_scan_cancel_timeout(priv, 100);
  5096. mutex_unlock(&priv->mutex);
  5097. }
  5098. iwl3945_down(priv);
  5099. flush_workqueue(priv->workqueue);
  5100. free_irq(priv->pci_dev->irq, priv);
  5101. pci_disable_msi(priv->pci_dev);
  5102. pci_save_state(priv->pci_dev);
  5103. pci_disable_device(priv->pci_dev);
  5104. IWL_DEBUG_MAC80211("leave\n");
  5105. }
  5106. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  5107. {
  5108. struct iwl_priv *priv = hw->priv;
  5109. IWL_DEBUG_MAC80211("enter\n");
  5110. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5111. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  5112. if (iwl3945_tx_skb(priv, skb))
  5113. dev_kfree_skb_any(skb);
  5114. IWL_DEBUG_MAC80211("leave\n");
  5115. return NETDEV_TX_OK;
  5116. }
  5117. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5118. struct ieee80211_if_init_conf *conf)
  5119. {
  5120. struct iwl_priv *priv = hw->priv;
  5121. unsigned long flags;
  5122. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5123. if (priv->vif) {
  5124. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5125. return -EOPNOTSUPP;
  5126. }
  5127. spin_lock_irqsave(&priv->lock, flags);
  5128. priv->vif = conf->vif;
  5129. priv->iw_mode = conf->type;
  5130. spin_unlock_irqrestore(&priv->lock, flags);
  5131. mutex_lock(&priv->mutex);
  5132. if (conf->mac_addr) {
  5133. IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
  5134. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5135. }
  5136. if (iwl_is_ready(priv))
  5137. iwl3945_set_mode(priv, conf->type);
  5138. mutex_unlock(&priv->mutex);
  5139. IWL_DEBUG_MAC80211("leave\n");
  5140. return 0;
  5141. }
  5142. /**
  5143. * iwl3945_mac_config - mac80211 config callback
  5144. *
  5145. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5146. * be set inappropriately and the driver currently sets the hardware up to
  5147. * use it whenever needed.
  5148. */
  5149. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
  5150. {
  5151. struct iwl_priv *priv = hw->priv;
  5152. const struct iwl_channel_info *ch_info;
  5153. struct ieee80211_conf *conf = &hw->conf;
  5154. unsigned long flags;
  5155. int ret = 0;
  5156. mutex_lock(&priv->mutex);
  5157. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5158. if (!iwl_is_ready(priv)) {
  5159. IWL_DEBUG_MAC80211("leave - not ready\n");
  5160. ret = -EIO;
  5161. goto out;
  5162. }
  5163. if (unlikely(!iwl3945_mod_params.disable_hw_scan &&
  5164. test_bit(STATUS_SCANNING, &priv->status))) {
  5165. IWL_DEBUG_MAC80211("leave - scanning\n");
  5166. set_bit(STATUS_CONF_PENDING, &priv->status);
  5167. mutex_unlock(&priv->mutex);
  5168. return 0;
  5169. }
  5170. spin_lock_irqsave(&priv->lock, flags);
  5171. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5172. conf->channel->hw_value);
  5173. if (!is_channel_valid(ch_info)) {
  5174. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
  5175. conf->channel->hw_value, conf->channel->band);
  5176. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5177. spin_unlock_irqrestore(&priv->lock, flags);
  5178. ret = -EINVAL;
  5179. goto out;
  5180. }
  5181. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5182. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5183. /* The list of supported rates and rate mask can be different
  5184. * for each phymode; since the phymode may have changed, reset
  5185. * the rate mask to what mac80211 lists */
  5186. iwl3945_set_rate(priv);
  5187. spin_unlock_irqrestore(&priv->lock, flags);
  5188. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5189. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5190. iwl3945_hw_channel_switch(priv, conf->channel);
  5191. goto out;
  5192. }
  5193. #endif
  5194. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5195. if (!conf->radio_enabled) {
  5196. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5197. goto out;
  5198. }
  5199. if (iwl_is_rfkill(priv)) {
  5200. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5201. ret = -EIO;
  5202. goto out;
  5203. }
  5204. iwl3945_set_rate(priv);
  5205. if (memcmp(&priv->active39_rxon,
  5206. &priv->staging39_rxon, sizeof(priv->staging39_rxon)))
  5207. iwl3945_commit_rxon(priv);
  5208. else
  5209. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5210. IWL_DEBUG_MAC80211("leave\n");
  5211. out:
  5212. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5213. mutex_unlock(&priv->mutex);
  5214. return ret;
  5215. }
  5216. static void iwl3945_config_ap(struct iwl_priv *priv)
  5217. {
  5218. int rc = 0;
  5219. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5220. return;
  5221. /* The following should be done only at AP bring up */
  5222. if (!(iwl3945_is_associated(priv))) {
  5223. /* RXON - unassoc (to set timing command) */
  5224. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5225. iwl3945_commit_rxon(priv);
  5226. /* RXON Timing */
  5227. memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
  5228. iwl3945_setup_rxon_timing(priv);
  5229. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5230. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5231. if (rc)
  5232. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  5233. "Attempting to continue.\n");
  5234. /* FIXME: what should be the assoc_id for AP? */
  5235. priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5236. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5237. priv->staging39_rxon.flags |=
  5238. RXON_FLG_SHORT_PREAMBLE_MSK;
  5239. else
  5240. priv->staging39_rxon.flags &=
  5241. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5242. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5243. if (priv->assoc_capability &
  5244. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5245. priv->staging39_rxon.flags |=
  5246. RXON_FLG_SHORT_SLOT_MSK;
  5247. else
  5248. priv->staging39_rxon.flags &=
  5249. ~RXON_FLG_SHORT_SLOT_MSK;
  5250. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  5251. priv->staging39_rxon.flags &=
  5252. ~RXON_FLG_SHORT_SLOT_MSK;
  5253. }
  5254. /* restore RXON assoc */
  5255. priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5256. iwl3945_commit_rxon(priv);
  5257. iwl3945_add_station(priv, iwl_bcast_addr, 0, 0);
  5258. }
  5259. iwl3945_send_beacon_cmd(priv);
  5260. /* FIXME - we need to add code here to detect a totally new
  5261. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5262. * clear sta table, add BCAST sta... */
  5263. }
  5264. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5265. struct ieee80211_vif *vif,
  5266. struct ieee80211_if_conf *conf)
  5267. {
  5268. struct iwl_priv *priv = hw->priv;
  5269. int rc;
  5270. if (conf == NULL)
  5271. return -EIO;
  5272. if (priv->vif != vif) {
  5273. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5274. return 0;
  5275. }
  5276. /* handle this temporarily here */
  5277. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  5278. conf->changed & IEEE80211_IFCC_BEACON) {
  5279. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  5280. if (!beacon)
  5281. return -ENOMEM;
  5282. mutex_lock(&priv->mutex);
  5283. rc = iwl3945_mac_beacon_update(hw, beacon);
  5284. mutex_unlock(&priv->mutex);
  5285. if (rc)
  5286. return rc;
  5287. }
  5288. if (!iwl_is_alive(priv))
  5289. return -EAGAIN;
  5290. mutex_lock(&priv->mutex);
  5291. if (conf->bssid)
  5292. IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
  5293. /*
  5294. * very dubious code was here; the probe filtering flag is never set:
  5295. *
  5296. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5297. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5298. */
  5299. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  5300. if (!conf->bssid) {
  5301. conf->bssid = priv->mac_addr;
  5302. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5303. IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
  5304. conf->bssid);
  5305. }
  5306. if (priv->ibss_beacon)
  5307. dev_kfree_skb(priv->ibss_beacon);
  5308. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  5309. }
  5310. if (iwl_is_rfkill(priv))
  5311. goto done;
  5312. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5313. !is_multicast_ether_addr(conf->bssid)) {
  5314. /* If there is currently a HW scan going on in the background
  5315. * then we need to cancel it else the RXON below will fail. */
  5316. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5317. IWL_WARN(priv, "Aborted scan still in progress "
  5318. "after 100ms\n");
  5319. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5320. mutex_unlock(&priv->mutex);
  5321. return -EAGAIN;
  5322. }
  5323. memcpy(priv->staging39_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5324. /* TODO: Audit driver for usage of these members and see
  5325. * if mac80211 deprecates them (priv->bssid looks like it
  5326. * shouldn't be there, but I haven't scanned the IBSS code
  5327. * to verify) - jpk */
  5328. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5329. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5330. iwl3945_config_ap(priv);
  5331. else {
  5332. rc = iwl3945_commit_rxon(priv);
  5333. if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
  5334. iwl3945_add_station(priv,
  5335. priv->active39_rxon.bssid_addr, 1, 0);
  5336. }
  5337. } else {
  5338. iwl3945_scan_cancel_timeout(priv, 100);
  5339. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5340. iwl3945_commit_rxon(priv);
  5341. }
  5342. done:
  5343. IWL_DEBUG_MAC80211("leave\n");
  5344. mutex_unlock(&priv->mutex);
  5345. return 0;
  5346. }
  5347. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5348. unsigned int changed_flags,
  5349. unsigned int *total_flags,
  5350. int mc_count, struct dev_addr_list *mc_list)
  5351. {
  5352. struct iwl_priv *priv = hw->priv;
  5353. __le32 *filter_flags = &priv->staging39_rxon.filter_flags;
  5354. IWL_DEBUG_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
  5355. changed_flags, *total_flags);
  5356. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  5357. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  5358. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  5359. else
  5360. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  5361. }
  5362. if (changed_flags & FIF_ALLMULTI) {
  5363. if (*total_flags & FIF_ALLMULTI)
  5364. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  5365. else
  5366. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  5367. }
  5368. if (changed_flags & FIF_CONTROL) {
  5369. if (*total_flags & FIF_CONTROL)
  5370. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  5371. else
  5372. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  5373. }
  5374. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  5375. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  5376. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  5377. else
  5378. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  5379. }
  5380. /* We avoid iwl_commit_rxon here to commit the new filter flags
  5381. * since mac80211 will call ieee80211_hw_config immediately.
  5382. * (mc_list is not supported at this time). Otherwise, we need to
  5383. * queue a background iwl_commit_rxon work.
  5384. */
  5385. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  5386. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  5387. }
  5388. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5389. struct ieee80211_if_init_conf *conf)
  5390. {
  5391. struct iwl_priv *priv = hw->priv;
  5392. IWL_DEBUG_MAC80211("enter\n");
  5393. mutex_lock(&priv->mutex);
  5394. if (iwl_is_ready_rf(priv)) {
  5395. iwl3945_scan_cancel_timeout(priv, 100);
  5396. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5397. iwl3945_commit_rxon(priv);
  5398. }
  5399. if (priv->vif == conf->vif) {
  5400. priv->vif = NULL;
  5401. memset(priv->bssid, 0, ETH_ALEN);
  5402. }
  5403. mutex_unlock(&priv->mutex);
  5404. IWL_DEBUG_MAC80211("leave\n");
  5405. }
  5406. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  5407. static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
  5408. struct ieee80211_vif *vif,
  5409. struct ieee80211_bss_conf *bss_conf,
  5410. u32 changes)
  5411. {
  5412. struct iwl_priv *priv = hw->priv;
  5413. IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
  5414. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  5415. IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
  5416. bss_conf->use_short_preamble);
  5417. if (bss_conf->use_short_preamble)
  5418. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5419. else
  5420. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5421. }
  5422. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  5423. IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
  5424. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  5425. priv->staging39_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  5426. else
  5427. priv->staging39_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  5428. }
  5429. if (changes & BSS_CHANGED_ASSOC) {
  5430. IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
  5431. /* This should never happen as this function should
  5432. * never be called from interrupt context. */
  5433. if (WARN_ON_ONCE(in_interrupt()))
  5434. return;
  5435. if (bss_conf->assoc) {
  5436. priv->assoc_id = bss_conf->aid;
  5437. priv->beacon_int = bss_conf->beacon_int;
  5438. priv->timestamp = bss_conf->timestamp;
  5439. priv->assoc_capability = bss_conf->assoc_capability;
  5440. priv->next_scan_jiffies = jiffies +
  5441. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  5442. mutex_lock(&priv->mutex);
  5443. iwl3945_post_associate(priv);
  5444. mutex_unlock(&priv->mutex);
  5445. } else {
  5446. priv->assoc_id = 0;
  5447. IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
  5448. }
  5449. } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
  5450. IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
  5451. iwl3945_send_rxon_assoc(priv);
  5452. }
  5453. }
  5454. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  5455. {
  5456. int rc = 0;
  5457. unsigned long flags;
  5458. struct iwl_priv *priv = hw->priv;
  5459. DECLARE_SSID_BUF(ssid_buf);
  5460. IWL_DEBUG_MAC80211("enter\n");
  5461. mutex_lock(&priv->mutex);
  5462. spin_lock_irqsave(&priv->lock, flags);
  5463. if (!iwl_is_ready_rf(priv)) {
  5464. rc = -EIO;
  5465. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  5466. goto out_unlock;
  5467. }
  5468. /* we don't schedule scan within next_scan_jiffies period */
  5469. if (priv->next_scan_jiffies &&
  5470. time_after(priv->next_scan_jiffies, jiffies)) {
  5471. rc = -EAGAIN;
  5472. goto out_unlock;
  5473. }
  5474. /* if we just finished scan ask for delay for a broadcast scan */
  5475. if ((len == 0) && priv->last_scan_jiffies &&
  5476. time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
  5477. jiffies)) {
  5478. rc = -EAGAIN;
  5479. goto out_unlock;
  5480. }
  5481. if (len) {
  5482. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  5483. print_ssid(ssid_buf, ssid, len), (int)len);
  5484. priv->one_direct_scan = 1;
  5485. priv->direct_ssid_len = (u8)
  5486. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  5487. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  5488. } else
  5489. priv->one_direct_scan = 0;
  5490. rc = iwl3945_scan_initiate(priv);
  5491. IWL_DEBUG_MAC80211("leave\n");
  5492. out_unlock:
  5493. spin_unlock_irqrestore(&priv->lock, flags);
  5494. mutex_unlock(&priv->mutex);
  5495. return rc;
  5496. }
  5497. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  5498. const u8 *local_addr, const u8 *addr,
  5499. struct ieee80211_key_conf *key)
  5500. {
  5501. struct iwl_priv *priv = hw->priv;
  5502. int rc = 0;
  5503. u8 sta_id;
  5504. IWL_DEBUG_MAC80211("enter\n");
  5505. if (iwl3945_mod_params.sw_crypto) {
  5506. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  5507. return -EOPNOTSUPP;
  5508. }
  5509. if (is_zero_ether_addr(addr))
  5510. /* only support pairwise keys */
  5511. return -EOPNOTSUPP;
  5512. sta_id = iwl3945_hw_find_station(priv, addr);
  5513. if (sta_id == IWL_INVALID_STATION) {
  5514. IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
  5515. addr);
  5516. return -EINVAL;
  5517. }
  5518. mutex_lock(&priv->mutex);
  5519. iwl3945_scan_cancel_timeout(priv, 100);
  5520. switch (cmd) {
  5521. case SET_KEY:
  5522. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  5523. if (!rc) {
  5524. iwl3945_set_rxon_hwcrypto(priv, 1);
  5525. iwl3945_commit_rxon(priv);
  5526. key->hw_key_idx = sta_id;
  5527. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  5528. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  5529. }
  5530. break;
  5531. case DISABLE_KEY:
  5532. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  5533. if (!rc) {
  5534. iwl3945_set_rxon_hwcrypto(priv, 0);
  5535. iwl3945_commit_rxon(priv);
  5536. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  5537. }
  5538. break;
  5539. default:
  5540. rc = -EINVAL;
  5541. }
  5542. IWL_DEBUG_MAC80211("leave\n");
  5543. mutex_unlock(&priv->mutex);
  5544. return rc;
  5545. }
  5546. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  5547. const struct ieee80211_tx_queue_params *params)
  5548. {
  5549. struct iwl_priv *priv = hw->priv;
  5550. unsigned long flags;
  5551. int q;
  5552. IWL_DEBUG_MAC80211("enter\n");
  5553. if (!iwl_is_ready_rf(priv)) {
  5554. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5555. return -EIO;
  5556. }
  5557. if (queue >= AC_NUM) {
  5558. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  5559. return 0;
  5560. }
  5561. q = AC_NUM - 1 - queue;
  5562. spin_lock_irqsave(&priv->lock, flags);
  5563. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  5564. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  5565. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  5566. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  5567. cpu_to_le16((params->txop * 32));
  5568. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  5569. priv->qos_data.qos_active = 1;
  5570. spin_unlock_irqrestore(&priv->lock, flags);
  5571. mutex_lock(&priv->mutex);
  5572. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5573. iwl3945_activate_qos(priv, 1);
  5574. else if (priv->assoc_id && iwl3945_is_associated(priv))
  5575. iwl3945_activate_qos(priv, 0);
  5576. mutex_unlock(&priv->mutex);
  5577. IWL_DEBUG_MAC80211("leave\n");
  5578. return 0;
  5579. }
  5580. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  5581. struct ieee80211_tx_queue_stats *stats)
  5582. {
  5583. struct iwl_priv *priv = hw->priv;
  5584. int i, avail;
  5585. struct iwl_tx_queue *txq;
  5586. struct iwl_queue *q;
  5587. unsigned long flags;
  5588. IWL_DEBUG_MAC80211("enter\n");
  5589. if (!iwl_is_ready_rf(priv)) {
  5590. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5591. return -EIO;
  5592. }
  5593. spin_lock_irqsave(&priv->lock, flags);
  5594. for (i = 0; i < AC_NUM; i++) {
  5595. txq = &priv->txq[i];
  5596. q = &txq->q;
  5597. avail = iwl_queue_space(q);
  5598. stats[i].len = q->n_window - avail;
  5599. stats[i].limit = q->n_window - q->high_mark;
  5600. stats[i].count = q->n_window;
  5601. }
  5602. spin_unlock_irqrestore(&priv->lock, flags);
  5603. IWL_DEBUG_MAC80211("leave\n");
  5604. return 0;
  5605. }
  5606. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  5607. {
  5608. struct iwl_priv *priv = hw->priv;
  5609. unsigned long flags;
  5610. mutex_lock(&priv->mutex);
  5611. IWL_DEBUG_MAC80211("enter\n");
  5612. iwl_reset_qos(priv);
  5613. spin_lock_irqsave(&priv->lock, flags);
  5614. priv->assoc_id = 0;
  5615. priv->assoc_capability = 0;
  5616. priv->call_post_assoc_from_beacon = 0;
  5617. /* new association get rid of ibss beacon skb */
  5618. if (priv->ibss_beacon)
  5619. dev_kfree_skb(priv->ibss_beacon);
  5620. priv->ibss_beacon = NULL;
  5621. priv->beacon_int = priv->hw->conf.beacon_int;
  5622. priv->timestamp = 0;
  5623. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  5624. priv->beacon_int = 0;
  5625. spin_unlock_irqrestore(&priv->lock, flags);
  5626. if (!iwl_is_ready_rf(priv)) {
  5627. IWL_DEBUG_MAC80211("leave - not ready\n");
  5628. mutex_unlock(&priv->mutex);
  5629. return;
  5630. }
  5631. /* we are restarting association process
  5632. * clear RXON_FILTER_ASSOC_MSK bit
  5633. */
  5634. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  5635. iwl3945_scan_cancel_timeout(priv, 100);
  5636. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5637. iwl3945_commit_rxon(priv);
  5638. }
  5639. /* Per mac80211.h: This is only used in IBSS mode... */
  5640. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5641. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  5642. mutex_unlock(&priv->mutex);
  5643. return;
  5644. }
  5645. iwl3945_set_rate(priv);
  5646. mutex_unlock(&priv->mutex);
  5647. IWL_DEBUG_MAC80211("leave\n");
  5648. }
  5649. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  5650. {
  5651. struct iwl_priv *priv = hw->priv;
  5652. unsigned long flags;
  5653. IWL_DEBUG_MAC80211("enter\n");
  5654. if (!iwl_is_ready_rf(priv)) {
  5655. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5656. return -EIO;
  5657. }
  5658. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5659. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  5660. return -EIO;
  5661. }
  5662. spin_lock_irqsave(&priv->lock, flags);
  5663. if (priv->ibss_beacon)
  5664. dev_kfree_skb(priv->ibss_beacon);
  5665. priv->ibss_beacon = skb;
  5666. priv->assoc_id = 0;
  5667. IWL_DEBUG_MAC80211("leave\n");
  5668. spin_unlock_irqrestore(&priv->lock, flags);
  5669. iwl_reset_qos(priv);
  5670. iwl3945_post_associate(priv);
  5671. return 0;
  5672. }
  5673. /*****************************************************************************
  5674. *
  5675. * sysfs attributes
  5676. *
  5677. *****************************************************************************/
  5678. #ifdef CONFIG_IWL3945_DEBUG
  5679. /*
  5680. * The following adds a new attribute to the sysfs representation
  5681. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  5682. * used for controlling the debug level.
  5683. *
  5684. * See the level definitions in iwl for details.
  5685. */
  5686. static ssize_t show_debug_level(struct device *d,
  5687. struct device_attribute *attr, char *buf)
  5688. {
  5689. struct iwl_priv *priv = d->driver_data;
  5690. return sprintf(buf, "0x%08X\n", priv->debug_level);
  5691. }
  5692. static ssize_t store_debug_level(struct device *d,
  5693. struct device_attribute *attr,
  5694. const char *buf, size_t count)
  5695. {
  5696. struct iwl_priv *priv = d->driver_data;
  5697. unsigned long val;
  5698. int ret;
  5699. ret = strict_strtoul(buf, 0, &val);
  5700. if (ret)
  5701. IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
  5702. else
  5703. priv->debug_level = val;
  5704. return strnlen(buf, count);
  5705. }
  5706. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  5707. show_debug_level, store_debug_level);
  5708. #endif /* CONFIG_IWL3945_DEBUG */
  5709. static ssize_t show_temperature(struct device *d,
  5710. struct device_attribute *attr, char *buf)
  5711. {
  5712. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5713. if (!iwl_is_alive(priv))
  5714. return -EAGAIN;
  5715. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  5716. }
  5717. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  5718. static ssize_t show_tx_power(struct device *d,
  5719. struct device_attribute *attr, char *buf)
  5720. {
  5721. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5722. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  5723. }
  5724. static ssize_t store_tx_power(struct device *d,
  5725. struct device_attribute *attr,
  5726. const char *buf, size_t count)
  5727. {
  5728. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5729. char *p = (char *)buf;
  5730. u32 val;
  5731. val = simple_strtoul(p, &p, 10);
  5732. if (p == buf)
  5733. IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
  5734. else
  5735. iwl3945_hw_reg_set_txpower(priv, val);
  5736. return count;
  5737. }
  5738. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  5739. static ssize_t show_flags(struct device *d,
  5740. struct device_attribute *attr, char *buf)
  5741. {
  5742. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5743. return sprintf(buf, "0x%04X\n", priv->active39_rxon.flags);
  5744. }
  5745. static ssize_t store_flags(struct device *d,
  5746. struct device_attribute *attr,
  5747. const char *buf, size_t count)
  5748. {
  5749. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5750. u32 flags = simple_strtoul(buf, NULL, 0);
  5751. mutex_lock(&priv->mutex);
  5752. if (le32_to_cpu(priv->staging39_rxon.flags) != flags) {
  5753. /* Cancel any currently running scans... */
  5754. if (iwl3945_scan_cancel_timeout(priv, 100))
  5755. IWL_WARN(priv, "Could not cancel scan.\n");
  5756. else {
  5757. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  5758. flags);
  5759. priv->staging39_rxon.flags = cpu_to_le32(flags);
  5760. iwl3945_commit_rxon(priv);
  5761. }
  5762. }
  5763. mutex_unlock(&priv->mutex);
  5764. return count;
  5765. }
  5766. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  5767. static ssize_t show_filter_flags(struct device *d,
  5768. struct device_attribute *attr, char *buf)
  5769. {
  5770. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5771. return sprintf(buf, "0x%04X\n",
  5772. le32_to_cpu(priv->active39_rxon.filter_flags));
  5773. }
  5774. static ssize_t store_filter_flags(struct device *d,
  5775. struct device_attribute *attr,
  5776. const char *buf, size_t count)
  5777. {
  5778. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5779. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  5780. mutex_lock(&priv->mutex);
  5781. if (le32_to_cpu(priv->staging39_rxon.filter_flags) != filter_flags) {
  5782. /* Cancel any currently running scans... */
  5783. if (iwl3945_scan_cancel_timeout(priv, 100))
  5784. IWL_WARN(priv, "Could not cancel scan.\n");
  5785. else {
  5786. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  5787. "0x%04X\n", filter_flags);
  5788. priv->staging39_rxon.filter_flags =
  5789. cpu_to_le32(filter_flags);
  5790. iwl3945_commit_rxon(priv);
  5791. }
  5792. }
  5793. mutex_unlock(&priv->mutex);
  5794. return count;
  5795. }
  5796. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  5797. store_filter_flags);
  5798. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  5799. static ssize_t show_measurement(struct device *d,
  5800. struct device_attribute *attr, char *buf)
  5801. {
  5802. struct iwl_priv *priv = dev_get_drvdata(d);
  5803. struct iwl_spectrum_notification measure_report;
  5804. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  5805. u8 *data = (u8 *)&measure_report;
  5806. unsigned long flags;
  5807. spin_lock_irqsave(&priv->lock, flags);
  5808. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  5809. spin_unlock_irqrestore(&priv->lock, flags);
  5810. return 0;
  5811. }
  5812. memcpy(&measure_report, &priv->measure_report, size);
  5813. priv->measurement_status = 0;
  5814. spin_unlock_irqrestore(&priv->lock, flags);
  5815. while (size && (PAGE_SIZE - len)) {
  5816. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  5817. PAGE_SIZE - len, 1);
  5818. len = strlen(buf);
  5819. if (PAGE_SIZE - len)
  5820. buf[len++] = '\n';
  5821. ofs += 16;
  5822. size -= min(size, 16U);
  5823. }
  5824. return len;
  5825. }
  5826. static ssize_t store_measurement(struct device *d,
  5827. struct device_attribute *attr,
  5828. const char *buf, size_t count)
  5829. {
  5830. struct iwl_priv *priv = dev_get_drvdata(d);
  5831. struct ieee80211_measurement_params params = {
  5832. .channel = le16_to_cpu(priv->active39_rxon.channel),
  5833. .start_time = cpu_to_le64(priv->last_tsf),
  5834. .duration = cpu_to_le16(1),
  5835. };
  5836. u8 type = IWL_MEASURE_BASIC;
  5837. u8 buffer[32];
  5838. u8 channel;
  5839. if (count) {
  5840. char *p = buffer;
  5841. strncpy(buffer, buf, min(sizeof(buffer), count));
  5842. channel = simple_strtoul(p, NULL, 0);
  5843. if (channel)
  5844. params.channel = channel;
  5845. p = buffer;
  5846. while (*p && *p != ' ')
  5847. p++;
  5848. if (*p)
  5849. type = simple_strtoul(p + 1, NULL, 0);
  5850. }
  5851. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  5852. "channel %d (for '%s')\n", type, params.channel, buf);
  5853. iwl3945_get_measurement(priv, &params, type);
  5854. return count;
  5855. }
  5856. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  5857. show_measurement, store_measurement);
  5858. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  5859. static ssize_t store_retry_rate(struct device *d,
  5860. struct device_attribute *attr,
  5861. const char *buf, size_t count)
  5862. {
  5863. struct iwl_priv *priv = dev_get_drvdata(d);
  5864. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  5865. if (priv->retry_rate <= 0)
  5866. priv->retry_rate = 1;
  5867. return count;
  5868. }
  5869. static ssize_t show_retry_rate(struct device *d,
  5870. struct device_attribute *attr, char *buf)
  5871. {
  5872. struct iwl_priv *priv = dev_get_drvdata(d);
  5873. return sprintf(buf, "%d", priv->retry_rate);
  5874. }
  5875. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  5876. store_retry_rate);
  5877. static ssize_t store_power_level(struct device *d,
  5878. struct device_attribute *attr,
  5879. const char *buf, size_t count)
  5880. {
  5881. struct iwl_priv *priv = dev_get_drvdata(d);
  5882. int rc;
  5883. int mode;
  5884. mode = simple_strtoul(buf, NULL, 0);
  5885. mutex_lock(&priv->mutex);
  5886. if (!iwl_is_ready(priv)) {
  5887. rc = -EAGAIN;
  5888. goto out;
  5889. }
  5890. if ((mode < 1) || (mode > IWL39_POWER_LIMIT) ||
  5891. (mode == IWL39_POWER_AC))
  5892. mode = IWL39_POWER_AC;
  5893. else
  5894. mode |= IWL_POWER_ENABLED;
  5895. if (mode != priv->power_mode) {
  5896. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  5897. if (rc) {
  5898. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  5899. goto out;
  5900. }
  5901. priv->power_mode = mode;
  5902. }
  5903. rc = count;
  5904. out:
  5905. mutex_unlock(&priv->mutex);
  5906. return rc;
  5907. }
  5908. #define MAX_WX_STRING 80
  5909. /* Values are in microsecond */
  5910. static const s32 timeout_duration[] = {
  5911. 350000,
  5912. 250000,
  5913. 75000,
  5914. 37000,
  5915. 25000,
  5916. };
  5917. static const s32 period_duration[] = {
  5918. 400000,
  5919. 700000,
  5920. 1000000,
  5921. 1000000,
  5922. 1000000
  5923. };
  5924. static ssize_t show_power_level(struct device *d,
  5925. struct device_attribute *attr, char *buf)
  5926. {
  5927. struct iwl_priv *priv = dev_get_drvdata(d);
  5928. int level = IWL_POWER_LEVEL(priv->power_mode);
  5929. char *p = buf;
  5930. p += sprintf(p, "%d ", level);
  5931. switch (level) {
  5932. case IWL_POWER_MODE_CAM:
  5933. case IWL39_POWER_AC:
  5934. p += sprintf(p, "(AC)");
  5935. break;
  5936. case IWL39_POWER_BATTERY:
  5937. p += sprintf(p, "(BATTERY)");
  5938. break;
  5939. default:
  5940. p += sprintf(p,
  5941. "(Timeout %dms, Period %dms)",
  5942. timeout_duration[level - 1] / 1000,
  5943. period_duration[level - 1] / 1000);
  5944. }
  5945. if (!(priv->power_mode & IWL_POWER_ENABLED))
  5946. p += sprintf(p, " OFF\n");
  5947. else
  5948. p += sprintf(p, " \n");
  5949. return p - buf + 1;
  5950. }
  5951. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  5952. store_power_level);
  5953. static ssize_t show_channels(struct device *d,
  5954. struct device_attribute *attr, char *buf)
  5955. {
  5956. /* all this shit doesn't belong into sysfs anyway */
  5957. return 0;
  5958. }
  5959. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  5960. static ssize_t show_statistics(struct device *d,
  5961. struct device_attribute *attr, char *buf)
  5962. {
  5963. struct iwl_priv *priv = dev_get_drvdata(d);
  5964. u32 size = sizeof(struct iwl3945_notif_statistics);
  5965. u32 len = 0, ofs = 0;
  5966. u8 *data = (u8 *)&priv->statistics_39;
  5967. int rc = 0;
  5968. if (!iwl_is_alive(priv))
  5969. return -EAGAIN;
  5970. mutex_lock(&priv->mutex);
  5971. rc = iwl3945_send_statistics_request(priv);
  5972. mutex_unlock(&priv->mutex);
  5973. if (rc) {
  5974. len = sprintf(buf,
  5975. "Error sending statistics request: 0x%08X\n", rc);
  5976. return len;
  5977. }
  5978. while (size && (PAGE_SIZE - len)) {
  5979. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  5980. PAGE_SIZE - len, 1);
  5981. len = strlen(buf);
  5982. if (PAGE_SIZE - len)
  5983. buf[len++] = '\n';
  5984. ofs += 16;
  5985. size -= min(size, 16U);
  5986. }
  5987. return len;
  5988. }
  5989. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  5990. static ssize_t show_antenna(struct device *d,
  5991. struct device_attribute *attr, char *buf)
  5992. {
  5993. struct iwl_priv *priv = dev_get_drvdata(d);
  5994. if (!iwl_is_alive(priv))
  5995. return -EAGAIN;
  5996. return sprintf(buf, "%d\n", priv->antenna);
  5997. }
  5998. static ssize_t store_antenna(struct device *d,
  5999. struct device_attribute *attr,
  6000. const char *buf, size_t count)
  6001. {
  6002. int ant;
  6003. struct iwl_priv *priv = dev_get_drvdata(d);
  6004. if (count == 0)
  6005. return 0;
  6006. if (sscanf(buf, "%1i", &ant) != 1) {
  6007. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6008. return count;
  6009. }
  6010. if ((ant >= 0) && (ant <= 2)) {
  6011. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6012. priv->antenna = (enum iwl3945_antenna)ant;
  6013. } else
  6014. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6015. return count;
  6016. }
  6017. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6018. static ssize_t show_status(struct device *d,
  6019. struct device_attribute *attr, char *buf)
  6020. {
  6021. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  6022. if (!iwl_is_alive(priv))
  6023. return -EAGAIN;
  6024. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6025. }
  6026. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6027. static ssize_t dump_error_log(struct device *d,
  6028. struct device_attribute *attr,
  6029. const char *buf, size_t count)
  6030. {
  6031. char *p = (char *)buf;
  6032. if (p[0] == '1')
  6033. iwl3945_dump_nic_error_log((struct iwl_priv *)d->driver_data);
  6034. return strnlen(buf, count);
  6035. }
  6036. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6037. static ssize_t dump_event_log(struct device *d,
  6038. struct device_attribute *attr,
  6039. const char *buf, size_t count)
  6040. {
  6041. char *p = (char *)buf;
  6042. if (p[0] == '1')
  6043. iwl3945_dump_nic_event_log((struct iwl_priv *)d->driver_data);
  6044. return strnlen(buf, count);
  6045. }
  6046. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6047. /*****************************************************************************
  6048. *
  6049. * driver setup and tear down
  6050. *
  6051. *****************************************************************************/
  6052. static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
  6053. {
  6054. priv->workqueue = create_workqueue(DRV_NAME);
  6055. init_waitqueue_head(&priv->wait_command_queue);
  6056. INIT_WORK(&priv->up, iwl3945_bg_up);
  6057. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6058. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6059. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6060. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6061. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6062. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6063. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6064. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6065. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6066. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6067. iwl3945_hw_setup_deferred_work(priv);
  6068. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6069. iwl3945_irq_tasklet, (unsigned long)priv);
  6070. }
  6071. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
  6072. {
  6073. iwl3945_hw_cancel_deferred_work(priv);
  6074. cancel_delayed_work_sync(&priv->init_alive_start);
  6075. cancel_delayed_work(&priv->scan_check);
  6076. cancel_delayed_work(&priv->alive_start);
  6077. cancel_work_sync(&priv->beacon_update);
  6078. }
  6079. static struct attribute *iwl3945_sysfs_entries[] = {
  6080. &dev_attr_antenna.attr,
  6081. &dev_attr_channels.attr,
  6082. &dev_attr_dump_errors.attr,
  6083. &dev_attr_dump_events.attr,
  6084. &dev_attr_flags.attr,
  6085. &dev_attr_filter_flags.attr,
  6086. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6087. &dev_attr_measurement.attr,
  6088. #endif
  6089. &dev_attr_power_level.attr,
  6090. &dev_attr_retry_rate.attr,
  6091. &dev_attr_statistics.attr,
  6092. &dev_attr_status.attr,
  6093. &dev_attr_temperature.attr,
  6094. &dev_attr_tx_power.attr,
  6095. #ifdef CONFIG_IWL3945_DEBUG
  6096. &dev_attr_debug_level.attr,
  6097. #endif
  6098. NULL
  6099. };
  6100. static struct attribute_group iwl3945_attribute_group = {
  6101. .name = NULL, /* put in device directory */
  6102. .attrs = iwl3945_sysfs_entries,
  6103. };
  6104. static struct ieee80211_ops iwl3945_hw_ops = {
  6105. .tx = iwl3945_mac_tx,
  6106. .start = iwl3945_mac_start,
  6107. .stop = iwl3945_mac_stop,
  6108. .add_interface = iwl3945_mac_add_interface,
  6109. .remove_interface = iwl3945_mac_remove_interface,
  6110. .config = iwl3945_mac_config,
  6111. .config_interface = iwl3945_mac_config_interface,
  6112. .configure_filter = iwl3945_configure_filter,
  6113. .set_key = iwl3945_mac_set_key,
  6114. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6115. .conf_tx = iwl3945_mac_conf_tx,
  6116. .reset_tsf = iwl3945_mac_reset_tsf,
  6117. .bss_info_changed = iwl3945_bss_info_changed,
  6118. .hw_scan = iwl3945_mac_hw_scan
  6119. };
  6120. static int iwl3945_init_drv(struct iwl_priv *priv)
  6121. {
  6122. int ret;
  6123. priv->retry_rate = 1;
  6124. priv->ibss_beacon = NULL;
  6125. spin_lock_init(&priv->lock);
  6126. spin_lock_init(&priv->power_data.lock);
  6127. spin_lock_init(&priv->sta_lock);
  6128. spin_lock_init(&priv->hcmd_lock);
  6129. INIT_LIST_HEAD(&priv->free_frames);
  6130. mutex_init(&priv->mutex);
  6131. /* Clear the driver's (not device's) station table */
  6132. iwl3945_clear_stations_table(priv);
  6133. priv->data_retry_limit = -1;
  6134. priv->ieee_channels = NULL;
  6135. priv->ieee_rates = NULL;
  6136. priv->band = IEEE80211_BAND_2GHZ;
  6137. priv->iw_mode = NL80211_IFTYPE_STATION;
  6138. iwl_reset_qos(priv);
  6139. priv->qos_data.qos_active = 0;
  6140. priv->qos_data.qos_cap.val = 0;
  6141. priv->rates_mask = IWL_RATES_MASK;
  6142. /* If power management is turned on, default to AC mode */
  6143. priv->power_mode = IWL_POWER_AC;
  6144. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6145. ret = iwl3945_init_channel_map(priv);
  6146. if (ret) {
  6147. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  6148. goto err;
  6149. }
  6150. ret = iwl3945_init_geos(priv);
  6151. if (ret) {
  6152. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  6153. goto err_free_channel_map;
  6154. }
  6155. return 0;
  6156. err_free_channel_map:
  6157. iwl3945_free_channel_map(priv);
  6158. err:
  6159. return ret;
  6160. }
  6161. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6162. {
  6163. int err = 0;
  6164. struct iwl_priv *priv;
  6165. struct ieee80211_hw *hw;
  6166. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  6167. unsigned long flags;
  6168. /***********************
  6169. * 1. Allocating HW data
  6170. * ********************/
  6171. /* mac80211 allocates memory for this device instance, including
  6172. * space for this driver's private structure */
  6173. hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
  6174. if (hw == NULL) {
  6175. printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
  6176. err = -ENOMEM;
  6177. goto out;
  6178. }
  6179. priv = hw->priv;
  6180. SET_IEEE80211_DEV(hw, &pdev->dev);
  6181. if ((iwl3945_mod_params.num_of_queues > IWL39_MAX_NUM_QUEUES) ||
  6182. (iwl3945_mod_params.num_of_queues < IWL_MIN_NUM_QUEUES)) {
  6183. IWL_ERR(priv,
  6184. "invalid queues_num, should be between %d and %d\n",
  6185. IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
  6186. err = -EINVAL;
  6187. goto out;
  6188. }
  6189. /*
  6190. * Disabling hardware scan means that mac80211 will perform scans
  6191. * "the hard way", rather than using device's scan.
  6192. */
  6193. if (iwl3945_mod_params.disable_hw_scan) {
  6194. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6195. iwl3945_hw_ops.hw_scan = NULL;
  6196. }
  6197. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6198. priv->cfg = cfg;
  6199. priv->pci_dev = pdev;
  6200. #ifdef CONFIG_IWL3945_DEBUG
  6201. priv->debug_level = iwl3945_mod_params.debug;
  6202. atomic_set(&priv->restrict_refcnt, 0);
  6203. #endif
  6204. hw->rate_control_algorithm = "iwl-3945-rs";
  6205. hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
  6206. /* Select antenna (may be helpful if only one antenna is connected) */
  6207. priv->antenna = (enum iwl3945_antenna)iwl3945_mod_params.antenna;
  6208. /* Tell mac80211 our characteristics */
  6209. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  6210. IEEE80211_HW_NOISE_DBM;
  6211. hw->wiphy->interface_modes =
  6212. BIT(NL80211_IFTYPE_STATION) |
  6213. BIT(NL80211_IFTYPE_ADHOC);
  6214. hw->wiphy->fw_handles_regulatory = true;
  6215. /* 4 EDCA QOS priorities */
  6216. hw->queues = 4;
  6217. /***************************
  6218. * 2. Initializing PCI bus
  6219. * *************************/
  6220. if (pci_enable_device(pdev)) {
  6221. err = -ENODEV;
  6222. goto out_ieee80211_free_hw;
  6223. }
  6224. pci_set_master(pdev);
  6225. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6226. if (!err)
  6227. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6228. if (err) {
  6229. IWL_WARN(priv, "No suitable DMA available.\n");
  6230. goto out_pci_disable_device;
  6231. }
  6232. pci_set_drvdata(pdev, priv);
  6233. err = pci_request_regions(pdev, DRV_NAME);
  6234. if (err)
  6235. goto out_pci_disable_device;
  6236. /***********************
  6237. * 3. Read REV Register
  6238. * ********************/
  6239. priv->hw_base = pci_iomap(pdev, 0, 0);
  6240. if (!priv->hw_base) {
  6241. err = -ENODEV;
  6242. goto out_pci_release_regions;
  6243. }
  6244. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6245. (unsigned long long) pci_resource_len(pdev, 0));
  6246. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6247. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6248. * PCI Tx retries from interfering with C3 CPU state */
  6249. pci_write_config_byte(pdev, 0x41, 0x00);
  6250. /* amp init */
  6251. err = priv->cfg->ops->lib->apm_ops.init(priv);
  6252. if (err < 0) {
  6253. IWL_DEBUG_INFO("Failed to init APMG\n");
  6254. goto out_iounmap;
  6255. }
  6256. /***********************
  6257. * 4. Read EEPROM
  6258. * ********************/
  6259. /* Read the EEPROM */
  6260. err = iwl3945_eeprom_init(priv);
  6261. if (err) {
  6262. IWL_ERR(priv, "Unable to init EEPROM\n");
  6263. goto out_remove_sysfs;
  6264. }
  6265. /* MAC Address location in EEPROM same for 3945/4965 */
  6266. get_eeprom_mac(priv, priv->mac_addr);
  6267. IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
  6268. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6269. /***********************
  6270. * 5. Setup HW Constants
  6271. * ********************/
  6272. /* Device-specific setup */
  6273. if (iwl3945_hw_set_hw_params(priv)) {
  6274. IWL_ERR(priv, "failed to set hw settings\n");
  6275. goto out_iounmap;
  6276. }
  6277. /***********************
  6278. * 6. Setup priv
  6279. * ********************/
  6280. err = iwl3945_init_drv(priv);
  6281. if (err) {
  6282. IWL_ERR(priv, "initializing driver failed\n");
  6283. goto out_free_geos;
  6284. }
  6285. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
  6286. priv->cfg->name);
  6287. /***********************************
  6288. * 7. Initialize Module Parameters
  6289. * **********************************/
  6290. /* Initialize module parameter values here */
  6291. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6292. if (iwl3945_mod_params.disable) {
  6293. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6294. IWL_DEBUG_INFO("Radio disabled.\n");
  6295. }
  6296. /***********************
  6297. * 8. Setup Services
  6298. * ********************/
  6299. spin_lock_irqsave(&priv->lock, flags);
  6300. iwl3945_disable_interrupts(priv);
  6301. spin_unlock_irqrestore(&priv->lock, flags);
  6302. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6303. if (err) {
  6304. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  6305. goto out_release_irq;
  6306. }
  6307. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6308. iwl3945_setup_deferred_work(priv);
  6309. iwl3945_setup_rx_handlers(priv);
  6310. /***********************
  6311. * 9. Conclude
  6312. * ********************/
  6313. pci_save_state(pdev);
  6314. pci_disable_device(pdev);
  6315. /*********************************
  6316. * 10. Setup and Register mac80211
  6317. * *******************************/
  6318. err = ieee80211_register_hw(priv->hw);
  6319. if (err) {
  6320. IWL_ERR(priv, "Failed to register network device: %d\n", err);
  6321. goto out_remove_sysfs;
  6322. }
  6323. priv->hw->conf.beacon_int = 100;
  6324. priv->mac80211_registered = 1;
  6325. err = iwl3945_rfkill_init(priv);
  6326. if (err)
  6327. IWL_ERR(priv, "Unable to initialize RFKILL system. "
  6328. "Ignoring error: %d\n", err);
  6329. return 0;
  6330. out_remove_sysfs:
  6331. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6332. out_free_geos:
  6333. iwl3945_free_geos(priv);
  6334. out_release_irq:
  6335. destroy_workqueue(priv->workqueue);
  6336. priv->workqueue = NULL;
  6337. iwl3945_unset_hw_params(priv);
  6338. out_iounmap:
  6339. pci_iounmap(pdev, priv->hw_base);
  6340. out_pci_release_regions:
  6341. pci_release_regions(pdev);
  6342. out_pci_disable_device:
  6343. pci_disable_device(pdev);
  6344. pci_set_drvdata(pdev, NULL);
  6345. out_ieee80211_free_hw:
  6346. ieee80211_free_hw(priv->hw);
  6347. out:
  6348. return err;
  6349. }
  6350. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  6351. {
  6352. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6353. unsigned long flags;
  6354. if (!priv)
  6355. return;
  6356. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  6357. set_bit(STATUS_EXIT_PENDING, &priv->status);
  6358. if (priv->mac80211_registered) {
  6359. ieee80211_unregister_hw(priv->hw);
  6360. priv->mac80211_registered = 0;
  6361. } else {
  6362. iwl3945_down(priv);
  6363. }
  6364. /* make sure we flush any pending irq or
  6365. * tasklet for the driver
  6366. */
  6367. spin_lock_irqsave(&priv->lock, flags);
  6368. iwl3945_disable_interrupts(priv);
  6369. spin_unlock_irqrestore(&priv->lock, flags);
  6370. iwl_synchronize_irq(priv);
  6371. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6372. iwl3945_rfkill_unregister(priv);
  6373. iwl3945_dealloc_ucode_pci(priv);
  6374. if (priv->rxq.bd)
  6375. iwl3945_rx_queue_free(priv, &priv->rxq);
  6376. iwl3945_hw_txq_ctx_free(priv);
  6377. iwl3945_unset_hw_params(priv);
  6378. iwl3945_clear_stations_table(priv);
  6379. /*netif_stop_queue(dev); */
  6380. flush_workqueue(priv->workqueue);
  6381. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  6382. * priv->workqueue... so we can't take down the workqueue
  6383. * until now... */
  6384. destroy_workqueue(priv->workqueue);
  6385. priv->workqueue = NULL;
  6386. pci_iounmap(pdev, priv->hw_base);
  6387. pci_release_regions(pdev);
  6388. pci_disable_device(pdev);
  6389. pci_set_drvdata(pdev, NULL);
  6390. iwl3945_free_channel_map(priv);
  6391. iwl3945_free_geos(priv);
  6392. kfree(priv->scan39);
  6393. if (priv->ibss_beacon)
  6394. dev_kfree_skb(priv->ibss_beacon);
  6395. ieee80211_free_hw(priv->hw);
  6396. }
  6397. #ifdef CONFIG_PM
  6398. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  6399. {
  6400. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6401. if (priv->is_open) {
  6402. set_bit(STATUS_IN_SUSPEND, &priv->status);
  6403. iwl3945_mac_stop(priv->hw);
  6404. priv->is_open = 1;
  6405. }
  6406. pci_set_power_state(pdev, PCI_D3hot);
  6407. return 0;
  6408. }
  6409. static int iwl3945_pci_resume(struct pci_dev *pdev)
  6410. {
  6411. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6412. pci_set_power_state(pdev, PCI_D0);
  6413. if (priv->is_open)
  6414. iwl3945_mac_start(priv->hw);
  6415. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  6416. return 0;
  6417. }
  6418. #endif /* CONFIG_PM */
  6419. /*************** RFKILL FUNCTIONS **********/
  6420. #ifdef CONFIG_IWL3945_RFKILL
  6421. /* software rf-kill from user */
  6422. static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
  6423. {
  6424. struct iwl_priv *priv = data;
  6425. int err = 0;
  6426. if (!priv->rfkill)
  6427. return 0;
  6428. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  6429. return 0;
  6430. IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state);
  6431. mutex_lock(&priv->mutex);
  6432. switch (state) {
  6433. case RFKILL_STATE_UNBLOCKED:
  6434. if (iwl_is_rfkill_hw(priv)) {
  6435. err = -EBUSY;
  6436. goto out_unlock;
  6437. }
  6438. iwl3945_radio_kill_sw(priv, 0);
  6439. break;
  6440. case RFKILL_STATE_SOFT_BLOCKED:
  6441. iwl3945_radio_kill_sw(priv, 1);
  6442. break;
  6443. default:
  6444. IWL_WARN(priv, "received unexpected RFKILL state %d\n", state);
  6445. break;
  6446. }
  6447. out_unlock:
  6448. mutex_unlock(&priv->mutex);
  6449. return err;
  6450. }
  6451. int iwl3945_rfkill_init(struct iwl_priv *priv)
  6452. {
  6453. struct device *device = wiphy_dev(priv->hw->wiphy);
  6454. int ret = 0;
  6455. BUG_ON(device == NULL);
  6456. IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
  6457. priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
  6458. if (!priv->rfkill) {
  6459. IWL_ERR(priv, "Unable to allocate rfkill device.\n");
  6460. ret = -ENOMEM;
  6461. goto error;
  6462. }
  6463. priv->rfkill->name = priv->cfg->name;
  6464. priv->rfkill->data = priv;
  6465. priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
  6466. priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
  6467. priv->rfkill->user_claim_unsupported = 1;
  6468. priv->rfkill->dev.class->suspend = NULL;
  6469. priv->rfkill->dev.class->resume = NULL;
  6470. ret = rfkill_register(priv->rfkill);
  6471. if (ret) {
  6472. IWL_ERR(priv, "Unable to register rfkill: %d\n", ret);
  6473. goto freed_rfkill;
  6474. }
  6475. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6476. return ret;
  6477. freed_rfkill:
  6478. if (priv->rfkill != NULL)
  6479. rfkill_free(priv->rfkill);
  6480. priv->rfkill = NULL;
  6481. error:
  6482. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6483. return ret;
  6484. }
  6485. void iwl3945_rfkill_unregister(struct iwl_priv *priv)
  6486. {
  6487. if (priv->rfkill)
  6488. rfkill_unregister(priv->rfkill);
  6489. priv->rfkill = NULL;
  6490. }
  6491. /* set rf-kill to the right state. */
  6492. void iwl3945_rfkill_set_hw_state(struct iwl_priv *priv)
  6493. {
  6494. if (!priv->rfkill)
  6495. return;
  6496. if (iwl_is_rfkill_hw(priv)) {
  6497. rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
  6498. return;
  6499. }
  6500. if (!iwl_is_rfkill_sw(priv))
  6501. rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
  6502. else
  6503. rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
  6504. }
  6505. #endif
  6506. /*****************************************************************************
  6507. *
  6508. * driver and module entry point
  6509. *
  6510. *****************************************************************************/
  6511. static struct pci_driver iwl3945_driver = {
  6512. .name = DRV_NAME,
  6513. .id_table = iwl3945_hw_card_ids,
  6514. .probe = iwl3945_pci_probe,
  6515. .remove = __devexit_p(iwl3945_pci_remove),
  6516. #ifdef CONFIG_PM
  6517. .suspend = iwl3945_pci_suspend,
  6518. .resume = iwl3945_pci_resume,
  6519. #endif
  6520. };
  6521. static int __init iwl3945_init(void)
  6522. {
  6523. int ret;
  6524. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  6525. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  6526. ret = iwl3945_rate_control_register();
  6527. if (ret) {
  6528. printk(KERN_ERR DRV_NAME
  6529. "Unable to register rate control algorithm: %d\n", ret);
  6530. return ret;
  6531. }
  6532. ret = pci_register_driver(&iwl3945_driver);
  6533. if (ret) {
  6534. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  6535. goto error_register;
  6536. }
  6537. return ret;
  6538. error_register:
  6539. iwl3945_rate_control_unregister();
  6540. return ret;
  6541. }
  6542. static void __exit iwl3945_exit(void)
  6543. {
  6544. pci_unregister_driver(&iwl3945_driver);
  6545. iwl3945_rate_control_unregister();
  6546. }
  6547. MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
  6548. module_param_named(antenna, iwl3945_mod_params.antenna, int, 0444);
  6549. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  6550. module_param_named(disable, iwl3945_mod_params.disable, int, 0444);
  6551. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  6552. module_param_named(hwcrypto, iwl3945_mod_params.sw_crypto, int, 0444);
  6553. MODULE_PARM_DESC(hwcrypto,
  6554. "using hardware crypto engine (default 0 [software])\n");
  6555. module_param_named(debug, iwl3945_mod_params.debug, uint, 0444);
  6556. MODULE_PARM_DESC(debug, "debug output mask");
  6557. module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, int, 0444);
  6558. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  6559. module_param_named(queues_num, iwl3945_mod_params.num_of_queues, int, 0444);
  6560. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  6561. module_exit(iwl3945_exit);
  6562. module_init(iwl3945_init);