falcon.c 82 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2006-2010 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/bitops.h>
  11. #include <linux/delay.h>
  12. #include <linux/pci.h>
  13. #include <linux/module.h>
  14. #include <linux/seq_file.h>
  15. #include <linux/i2c.h>
  16. #include <linux/mii.h>
  17. #include <linux/slab.h>
  18. #include "net_driver.h"
  19. #include "bitfield.h"
  20. #include "efx.h"
  21. #include "nic.h"
  22. #include "farch_regs.h"
  23. #include "io.h"
  24. #include "phy.h"
  25. #include "workarounds.h"
  26. #include "selftest.h"
  27. #include "mdio_10g.h"
  28. /* Hardware control for SFC4000 (aka Falcon). */
  29. /**************************************************************************
  30. *
  31. * MAC stats DMA format
  32. *
  33. **************************************************************************
  34. */
  35. #define FALCON_MAC_STATS_SIZE 0x100
  36. #define XgRxOctets_offset 0x0
  37. #define XgRxOctets_WIDTH 48
  38. #define XgRxOctetsOK_offset 0x8
  39. #define XgRxOctetsOK_WIDTH 48
  40. #define XgRxPkts_offset 0x10
  41. #define XgRxPkts_WIDTH 32
  42. #define XgRxPktsOK_offset 0x14
  43. #define XgRxPktsOK_WIDTH 32
  44. #define XgRxBroadcastPkts_offset 0x18
  45. #define XgRxBroadcastPkts_WIDTH 32
  46. #define XgRxMulticastPkts_offset 0x1C
  47. #define XgRxMulticastPkts_WIDTH 32
  48. #define XgRxUnicastPkts_offset 0x20
  49. #define XgRxUnicastPkts_WIDTH 32
  50. #define XgRxUndersizePkts_offset 0x24
  51. #define XgRxUndersizePkts_WIDTH 32
  52. #define XgRxOversizePkts_offset 0x28
  53. #define XgRxOversizePkts_WIDTH 32
  54. #define XgRxJabberPkts_offset 0x2C
  55. #define XgRxJabberPkts_WIDTH 32
  56. #define XgRxUndersizeFCSerrorPkts_offset 0x30
  57. #define XgRxUndersizeFCSerrorPkts_WIDTH 32
  58. #define XgRxDropEvents_offset 0x34
  59. #define XgRxDropEvents_WIDTH 32
  60. #define XgRxFCSerrorPkts_offset 0x38
  61. #define XgRxFCSerrorPkts_WIDTH 32
  62. #define XgRxAlignError_offset 0x3C
  63. #define XgRxAlignError_WIDTH 32
  64. #define XgRxSymbolError_offset 0x40
  65. #define XgRxSymbolError_WIDTH 32
  66. #define XgRxInternalMACError_offset 0x44
  67. #define XgRxInternalMACError_WIDTH 32
  68. #define XgRxControlPkts_offset 0x48
  69. #define XgRxControlPkts_WIDTH 32
  70. #define XgRxPausePkts_offset 0x4C
  71. #define XgRxPausePkts_WIDTH 32
  72. #define XgRxPkts64Octets_offset 0x50
  73. #define XgRxPkts64Octets_WIDTH 32
  74. #define XgRxPkts65to127Octets_offset 0x54
  75. #define XgRxPkts65to127Octets_WIDTH 32
  76. #define XgRxPkts128to255Octets_offset 0x58
  77. #define XgRxPkts128to255Octets_WIDTH 32
  78. #define XgRxPkts256to511Octets_offset 0x5C
  79. #define XgRxPkts256to511Octets_WIDTH 32
  80. #define XgRxPkts512to1023Octets_offset 0x60
  81. #define XgRxPkts512to1023Octets_WIDTH 32
  82. #define XgRxPkts1024to15xxOctets_offset 0x64
  83. #define XgRxPkts1024to15xxOctets_WIDTH 32
  84. #define XgRxPkts15xxtoMaxOctets_offset 0x68
  85. #define XgRxPkts15xxtoMaxOctets_WIDTH 32
  86. #define XgRxLengthError_offset 0x6C
  87. #define XgRxLengthError_WIDTH 32
  88. #define XgTxPkts_offset 0x80
  89. #define XgTxPkts_WIDTH 32
  90. #define XgTxOctets_offset 0x88
  91. #define XgTxOctets_WIDTH 48
  92. #define XgTxMulticastPkts_offset 0x90
  93. #define XgTxMulticastPkts_WIDTH 32
  94. #define XgTxBroadcastPkts_offset 0x94
  95. #define XgTxBroadcastPkts_WIDTH 32
  96. #define XgTxUnicastPkts_offset 0x98
  97. #define XgTxUnicastPkts_WIDTH 32
  98. #define XgTxControlPkts_offset 0x9C
  99. #define XgTxControlPkts_WIDTH 32
  100. #define XgTxPausePkts_offset 0xA0
  101. #define XgTxPausePkts_WIDTH 32
  102. #define XgTxPkts64Octets_offset 0xA4
  103. #define XgTxPkts64Octets_WIDTH 32
  104. #define XgTxPkts65to127Octets_offset 0xA8
  105. #define XgTxPkts65to127Octets_WIDTH 32
  106. #define XgTxPkts128to255Octets_offset 0xAC
  107. #define XgTxPkts128to255Octets_WIDTH 32
  108. #define XgTxPkts256to511Octets_offset 0xB0
  109. #define XgTxPkts256to511Octets_WIDTH 32
  110. #define XgTxPkts512to1023Octets_offset 0xB4
  111. #define XgTxPkts512to1023Octets_WIDTH 32
  112. #define XgTxPkts1024to15xxOctets_offset 0xB8
  113. #define XgTxPkts1024to15xxOctets_WIDTH 32
  114. #define XgTxPkts1519toMaxOctets_offset 0xBC
  115. #define XgTxPkts1519toMaxOctets_WIDTH 32
  116. #define XgTxUndersizePkts_offset 0xC0
  117. #define XgTxUndersizePkts_WIDTH 32
  118. #define XgTxOversizePkts_offset 0xC4
  119. #define XgTxOversizePkts_WIDTH 32
  120. #define XgTxNonTcpUdpPkt_offset 0xC8
  121. #define XgTxNonTcpUdpPkt_WIDTH 16
  122. #define XgTxMacSrcErrPkt_offset 0xCC
  123. #define XgTxMacSrcErrPkt_WIDTH 16
  124. #define XgTxIpSrcErrPkt_offset 0xD0
  125. #define XgTxIpSrcErrPkt_WIDTH 16
  126. #define XgDmaDone_offset 0xD4
  127. #define XgDmaDone_WIDTH 32
  128. #define FALCON_XMAC_STATS_DMA_FLAG(efx) \
  129. (*(u32 *)((efx)->stats_buffer.addr + XgDmaDone_offset))
  130. #define FALCON_STAT_OFFSET(falcon_stat) EFX_VAL(falcon_stat, offset)
  131. #define FALCON_STAT_WIDTH(falcon_stat) EFX_VAL(falcon_stat, WIDTH)
  132. /* Retrieve statistic from statistics block */
  133. #define FALCON_STAT(efx, falcon_stat, efx_stat) do { \
  134. if (FALCON_STAT_WIDTH(falcon_stat) == 16) \
  135. (efx)->mac_stats.efx_stat += le16_to_cpu( \
  136. *((__force __le16 *) \
  137. (efx->stats_buffer.addr + \
  138. FALCON_STAT_OFFSET(falcon_stat)))); \
  139. else if (FALCON_STAT_WIDTH(falcon_stat) == 32) \
  140. (efx)->mac_stats.efx_stat += le32_to_cpu( \
  141. *((__force __le32 *) \
  142. (efx->stats_buffer.addr + \
  143. FALCON_STAT_OFFSET(falcon_stat)))); \
  144. else \
  145. (efx)->mac_stats.efx_stat += le64_to_cpu( \
  146. *((__force __le64 *) \
  147. (efx->stats_buffer.addr + \
  148. FALCON_STAT_OFFSET(falcon_stat)))); \
  149. } while (0)
  150. /**************************************************************************
  151. *
  152. * Basic SPI command set and bit definitions
  153. *
  154. *************************************************************************/
  155. #define SPI_WRSR 0x01 /* Write status register */
  156. #define SPI_WRITE 0x02 /* Write data to memory array */
  157. #define SPI_READ 0x03 /* Read data from memory array */
  158. #define SPI_WRDI 0x04 /* Reset write enable latch */
  159. #define SPI_RDSR 0x05 /* Read status register */
  160. #define SPI_WREN 0x06 /* Set write enable latch */
  161. #define SPI_SST_EWSR 0x50 /* SST: Enable write to status register */
  162. #define SPI_STATUS_WPEN 0x80 /* Write-protect pin enabled */
  163. #define SPI_STATUS_BP2 0x10 /* Block protection bit 2 */
  164. #define SPI_STATUS_BP1 0x08 /* Block protection bit 1 */
  165. #define SPI_STATUS_BP0 0x04 /* Block protection bit 0 */
  166. #define SPI_STATUS_WEN 0x02 /* State of the write enable latch */
  167. #define SPI_STATUS_NRDY 0x01 /* Device busy flag */
  168. /**************************************************************************
  169. *
  170. * Non-volatile memory layout
  171. *
  172. **************************************************************************
  173. */
  174. /* SFC4000 flash is partitioned into:
  175. * 0-0x400 chip and board config (see struct falcon_nvconfig)
  176. * 0x400-0x8000 unused (or may contain VPD if EEPROM not present)
  177. * 0x8000-end boot code (mapped to PCI expansion ROM)
  178. * SFC4000 small EEPROM (size < 0x400) is used for VPD only.
  179. * SFC4000 large EEPROM (size >= 0x400) is partitioned into:
  180. * 0-0x400 chip and board config
  181. * configurable VPD
  182. * 0x800-0x1800 boot config
  183. * Aside from the chip and board config, all of these are optional and may
  184. * be absent or truncated depending on the devices used.
  185. */
  186. #define FALCON_NVCONFIG_END 0x400U
  187. #define FALCON_FLASH_BOOTCODE_START 0x8000U
  188. #define FALCON_EEPROM_BOOTCONFIG_START 0x800U
  189. #define FALCON_EEPROM_BOOTCONFIG_END 0x1800U
  190. /* Board configuration v2 (v1 is obsolete; later versions are compatible) */
  191. struct falcon_nvconfig_board_v2 {
  192. __le16 nports;
  193. u8 port0_phy_addr;
  194. u8 port0_phy_type;
  195. u8 port1_phy_addr;
  196. u8 port1_phy_type;
  197. __le16 asic_sub_revision;
  198. __le16 board_revision;
  199. } __packed;
  200. /* Board configuration v3 extra information */
  201. struct falcon_nvconfig_board_v3 {
  202. __le32 spi_device_type[2];
  203. } __packed;
  204. /* Bit numbers for spi_device_type */
  205. #define SPI_DEV_TYPE_SIZE_LBN 0
  206. #define SPI_DEV_TYPE_SIZE_WIDTH 5
  207. #define SPI_DEV_TYPE_ADDR_LEN_LBN 6
  208. #define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2
  209. #define SPI_DEV_TYPE_ERASE_CMD_LBN 8
  210. #define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8
  211. #define SPI_DEV_TYPE_ERASE_SIZE_LBN 16
  212. #define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5
  213. #define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24
  214. #define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5
  215. #define SPI_DEV_TYPE_FIELD(type, field) \
  216. (((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field)))
  217. #define FALCON_NVCONFIG_OFFSET 0x300
  218. #define FALCON_NVCONFIG_BOARD_MAGIC_NUM 0xFA1C
  219. struct falcon_nvconfig {
  220. efx_oword_t ee_vpd_cfg_reg; /* 0x300 */
  221. u8 mac_address[2][8]; /* 0x310 */
  222. efx_oword_t pcie_sd_ctl0123_reg; /* 0x320 */
  223. efx_oword_t pcie_sd_ctl45_reg; /* 0x330 */
  224. efx_oword_t pcie_pcs_ctl_stat_reg; /* 0x340 */
  225. efx_oword_t hw_init_reg; /* 0x350 */
  226. efx_oword_t nic_stat_reg; /* 0x360 */
  227. efx_oword_t glb_ctl_reg; /* 0x370 */
  228. efx_oword_t srm_cfg_reg; /* 0x380 */
  229. efx_oword_t spare_reg; /* 0x390 */
  230. __le16 board_magic_num; /* 0x3A0 */
  231. __le16 board_struct_ver;
  232. __le16 board_checksum;
  233. struct falcon_nvconfig_board_v2 board_v2;
  234. efx_oword_t ee_base_page_reg; /* 0x3B0 */
  235. struct falcon_nvconfig_board_v3 board_v3; /* 0x3C0 */
  236. } __packed;
  237. /*************************************************************************/
  238. static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method);
  239. static void falcon_reconfigure_mac_wrapper(struct efx_nic *efx);
  240. static const unsigned int
  241. /* "Large" EEPROM device: Atmel AT25640 or similar
  242. * 8 KB, 16-bit address, 32 B write block */
  243. large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
  244. | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
  245. | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
  246. /* Default flash device: Atmel AT25F1024
  247. * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
  248. default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
  249. | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
  250. | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
  251. | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
  252. | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
  253. /**************************************************************************
  254. *
  255. * I2C bus - this is a bit-bashing interface using GPIO pins
  256. * Note that it uses the output enables to tristate the outputs
  257. * SDA is the data pin and SCL is the clock
  258. *
  259. **************************************************************************
  260. */
  261. static void falcon_setsda(void *data, int state)
  262. {
  263. struct efx_nic *efx = (struct efx_nic *)data;
  264. efx_oword_t reg;
  265. efx_reado(efx, &reg, FR_AB_GPIO_CTL);
  266. EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
  267. efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
  268. }
  269. static void falcon_setscl(void *data, int state)
  270. {
  271. struct efx_nic *efx = (struct efx_nic *)data;
  272. efx_oword_t reg;
  273. efx_reado(efx, &reg, FR_AB_GPIO_CTL);
  274. EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
  275. efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
  276. }
  277. static int falcon_getsda(void *data)
  278. {
  279. struct efx_nic *efx = (struct efx_nic *)data;
  280. efx_oword_t reg;
  281. efx_reado(efx, &reg, FR_AB_GPIO_CTL);
  282. return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
  283. }
  284. static int falcon_getscl(void *data)
  285. {
  286. struct efx_nic *efx = (struct efx_nic *)data;
  287. efx_oword_t reg;
  288. efx_reado(efx, &reg, FR_AB_GPIO_CTL);
  289. return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
  290. }
  291. static const struct i2c_algo_bit_data falcon_i2c_bit_operations = {
  292. .setsda = falcon_setsda,
  293. .setscl = falcon_setscl,
  294. .getsda = falcon_getsda,
  295. .getscl = falcon_getscl,
  296. .udelay = 5,
  297. /* Wait up to 50 ms for slave to let us pull SCL high */
  298. .timeout = DIV_ROUND_UP(HZ, 20),
  299. };
  300. static void falcon_push_irq_moderation(struct efx_channel *channel)
  301. {
  302. efx_dword_t timer_cmd;
  303. struct efx_nic *efx = channel->efx;
  304. /* Set timer register */
  305. if (channel->irq_moderation) {
  306. EFX_POPULATE_DWORD_2(timer_cmd,
  307. FRF_AB_TC_TIMER_MODE,
  308. FFE_BB_TIMER_MODE_INT_HLDOFF,
  309. FRF_AB_TC_TIMER_VAL,
  310. channel->irq_moderation - 1);
  311. } else {
  312. EFX_POPULATE_DWORD_2(timer_cmd,
  313. FRF_AB_TC_TIMER_MODE,
  314. FFE_BB_TIMER_MODE_DIS,
  315. FRF_AB_TC_TIMER_VAL, 0);
  316. }
  317. BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
  318. efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
  319. channel->channel);
  320. }
  321. static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
  322. static void falcon_prepare_flush(struct efx_nic *efx)
  323. {
  324. falcon_deconfigure_mac_wrapper(efx);
  325. /* Wait for the tx and rx fifo's to get to the next packet boundary
  326. * (~1ms without back-pressure), then to drain the remainder of the
  327. * fifo's at data path speeds (negligible), with a healthy margin. */
  328. msleep(10);
  329. }
  330. /* Acknowledge a legacy interrupt from Falcon
  331. *
  332. * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
  333. *
  334. * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
  335. * BIU. Interrupt acknowledge is read sensitive so must write instead
  336. * (then read to ensure the BIU collector is flushed)
  337. *
  338. * NB most hardware supports MSI interrupts
  339. */
  340. static inline void falcon_irq_ack_a1(struct efx_nic *efx)
  341. {
  342. efx_dword_t reg;
  343. EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
  344. efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
  345. efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
  346. }
  347. static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
  348. {
  349. struct efx_nic *efx = dev_id;
  350. efx_oword_t *int_ker = efx->irq_status.addr;
  351. int syserr;
  352. int queues;
  353. /* Check to see if this is our interrupt. If it isn't, we
  354. * exit without having touched the hardware.
  355. */
  356. if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
  357. netif_vdbg(efx, intr, efx->net_dev,
  358. "IRQ %d on CPU %d not for me\n", irq,
  359. raw_smp_processor_id());
  360. return IRQ_NONE;
  361. }
  362. efx->last_irq_cpu = raw_smp_processor_id();
  363. netif_vdbg(efx, intr, efx->net_dev,
  364. "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
  365. irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
  366. if (!likely(ACCESS_ONCE(efx->irq_soft_enabled)))
  367. return IRQ_HANDLED;
  368. /* Check to see if we have a serious error condition */
  369. syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
  370. if (unlikely(syserr))
  371. return efx_farch_fatal_interrupt(efx);
  372. /* Determine interrupting queues, clear interrupt status
  373. * register and acknowledge the device interrupt.
  374. */
  375. BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
  376. queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
  377. EFX_ZERO_OWORD(*int_ker);
  378. wmb(); /* Ensure the vector is cleared before interrupt ack */
  379. falcon_irq_ack_a1(efx);
  380. if (queues & 1)
  381. efx_schedule_channel_irq(efx_get_channel(efx, 0));
  382. if (queues & 2)
  383. efx_schedule_channel_irq(efx_get_channel(efx, 1));
  384. return IRQ_HANDLED;
  385. }
  386. /**************************************************************************
  387. *
  388. * EEPROM/flash
  389. *
  390. **************************************************************************
  391. */
  392. #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
  393. static int falcon_spi_poll(struct efx_nic *efx)
  394. {
  395. efx_oword_t reg;
  396. efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
  397. return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
  398. }
  399. /* Wait for SPI command completion */
  400. static int falcon_spi_wait(struct efx_nic *efx)
  401. {
  402. /* Most commands will finish quickly, so we start polling at
  403. * very short intervals. Sometimes the command may have to
  404. * wait for VPD or expansion ROM access outside of our
  405. * control, so we allow up to 100 ms. */
  406. unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
  407. int i;
  408. for (i = 0; i < 10; i++) {
  409. if (!falcon_spi_poll(efx))
  410. return 0;
  411. udelay(10);
  412. }
  413. for (;;) {
  414. if (!falcon_spi_poll(efx))
  415. return 0;
  416. if (time_after_eq(jiffies, timeout)) {
  417. netif_err(efx, hw, efx->net_dev,
  418. "timed out waiting for SPI\n");
  419. return -ETIMEDOUT;
  420. }
  421. schedule_timeout_uninterruptible(1);
  422. }
  423. }
  424. static int
  425. falcon_spi_cmd(struct efx_nic *efx, const struct falcon_spi_device *spi,
  426. unsigned int command, int address,
  427. const void *in, void *out, size_t len)
  428. {
  429. bool addressed = (address >= 0);
  430. bool reading = (out != NULL);
  431. efx_oword_t reg;
  432. int rc;
  433. /* Input validation */
  434. if (len > FALCON_SPI_MAX_LEN)
  435. return -EINVAL;
  436. /* Check that previous command is not still running */
  437. rc = falcon_spi_poll(efx);
  438. if (rc)
  439. return rc;
  440. /* Program address register, if we have an address */
  441. if (addressed) {
  442. EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
  443. efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
  444. }
  445. /* Program data register, if we have data */
  446. if (in != NULL) {
  447. memcpy(&reg, in, len);
  448. efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
  449. }
  450. /* Issue read/write command */
  451. EFX_POPULATE_OWORD_7(reg,
  452. FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
  453. FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
  454. FRF_AB_EE_SPI_HCMD_DABCNT, len,
  455. FRF_AB_EE_SPI_HCMD_READ, reading,
  456. FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
  457. FRF_AB_EE_SPI_HCMD_ADBCNT,
  458. (addressed ? spi->addr_len : 0),
  459. FRF_AB_EE_SPI_HCMD_ENC, command);
  460. efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
  461. /* Wait for read/write to complete */
  462. rc = falcon_spi_wait(efx);
  463. if (rc)
  464. return rc;
  465. /* Read data */
  466. if (out != NULL) {
  467. efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
  468. memcpy(out, &reg, len);
  469. }
  470. return 0;
  471. }
  472. static inline u8
  473. falcon_spi_munge_command(const struct falcon_spi_device *spi,
  474. const u8 command, const unsigned int address)
  475. {
  476. return command | (((address >> 8) & spi->munge_address) << 3);
  477. }
  478. static int
  479. falcon_spi_read(struct efx_nic *efx, const struct falcon_spi_device *spi,
  480. loff_t start, size_t len, size_t *retlen, u8 *buffer)
  481. {
  482. size_t block_len, pos = 0;
  483. unsigned int command;
  484. int rc = 0;
  485. while (pos < len) {
  486. block_len = min(len - pos, FALCON_SPI_MAX_LEN);
  487. command = falcon_spi_munge_command(spi, SPI_READ, start + pos);
  488. rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL,
  489. buffer + pos, block_len);
  490. if (rc)
  491. break;
  492. pos += block_len;
  493. /* Avoid locking up the system */
  494. cond_resched();
  495. if (signal_pending(current)) {
  496. rc = -EINTR;
  497. break;
  498. }
  499. }
  500. if (retlen)
  501. *retlen = pos;
  502. return rc;
  503. }
  504. #ifdef CONFIG_SFC_MTD
  505. struct falcon_mtd_partition {
  506. struct efx_mtd_partition common;
  507. const struct falcon_spi_device *spi;
  508. size_t offset;
  509. };
  510. #define to_falcon_mtd_partition(mtd) \
  511. container_of(mtd, struct falcon_mtd_partition, common.mtd)
  512. static size_t
  513. falcon_spi_write_limit(const struct falcon_spi_device *spi, size_t start)
  514. {
  515. return min(FALCON_SPI_MAX_LEN,
  516. (spi->block_size - (start & (spi->block_size - 1))));
  517. }
  518. /* Wait up to 10 ms for buffered write completion */
  519. static int
  520. falcon_spi_wait_write(struct efx_nic *efx, const struct falcon_spi_device *spi)
  521. {
  522. unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
  523. u8 status;
  524. int rc;
  525. for (;;) {
  526. rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
  527. &status, sizeof(status));
  528. if (rc)
  529. return rc;
  530. if (!(status & SPI_STATUS_NRDY))
  531. return 0;
  532. if (time_after_eq(jiffies, timeout)) {
  533. netif_err(efx, hw, efx->net_dev,
  534. "SPI write timeout on device %d"
  535. " last status=0x%02x\n",
  536. spi->device_id, status);
  537. return -ETIMEDOUT;
  538. }
  539. schedule_timeout_uninterruptible(1);
  540. }
  541. }
  542. static int
  543. falcon_spi_write(struct efx_nic *efx, const struct falcon_spi_device *spi,
  544. loff_t start, size_t len, size_t *retlen, const u8 *buffer)
  545. {
  546. u8 verify_buffer[FALCON_SPI_MAX_LEN];
  547. size_t block_len, pos = 0;
  548. unsigned int command;
  549. int rc = 0;
  550. while (pos < len) {
  551. rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
  552. if (rc)
  553. break;
  554. block_len = min(len - pos,
  555. falcon_spi_write_limit(spi, start + pos));
  556. command = falcon_spi_munge_command(spi, SPI_WRITE, start + pos);
  557. rc = falcon_spi_cmd(efx, spi, command, start + pos,
  558. buffer + pos, NULL, block_len);
  559. if (rc)
  560. break;
  561. rc = falcon_spi_wait_write(efx, spi);
  562. if (rc)
  563. break;
  564. command = falcon_spi_munge_command(spi, SPI_READ, start + pos);
  565. rc = falcon_spi_cmd(efx, spi, command, start + pos,
  566. NULL, verify_buffer, block_len);
  567. if (memcmp(verify_buffer, buffer + pos, block_len)) {
  568. rc = -EIO;
  569. break;
  570. }
  571. pos += block_len;
  572. /* Avoid locking up the system */
  573. cond_resched();
  574. if (signal_pending(current)) {
  575. rc = -EINTR;
  576. break;
  577. }
  578. }
  579. if (retlen)
  580. *retlen = pos;
  581. return rc;
  582. }
  583. static int
  584. falcon_spi_slow_wait(struct falcon_mtd_partition *part, bool uninterruptible)
  585. {
  586. const struct falcon_spi_device *spi = part->spi;
  587. struct efx_nic *efx = part->common.mtd.priv;
  588. u8 status;
  589. int rc, i;
  590. /* Wait up to 4s for flash/EEPROM to finish a slow operation. */
  591. for (i = 0; i < 40; i++) {
  592. __set_current_state(uninterruptible ?
  593. TASK_UNINTERRUPTIBLE : TASK_INTERRUPTIBLE);
  594. schedule_timeout(HZ / 10);
  595. rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
  596. &status, sizeof(status));
  597. if (rc)
  598. return rc;
  599. if (!(status & SPI_STATUS_NRDY))
  600. return 0;
  601. if (signal_pending(current))
  602. return -EINTR;
  603. }
  604. pr_err("%s: timed out waiting for %s\n",
  605. part->common.name, part->common.dev_type_name);
  606. return -ETIMEDOUT;
  607. }
  608. static int
  609. falcon_spi_unlock(struct efx_nic *efx, const struct falcon_spi_device *spi)
  610. {
  611. const u8 unlock_mask = (SPI_STATUS_BP2 | SPI_STATUS_BP1 |
  612. SPI_STATUS_BP0);
  613. u8 status;
  614. int rc;
  615. rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
  616. &status, sizeof(status));
  617. if (rc)
  618. return rc;
  619. if (!(status & unlock_mask))
  620. return 0; /* already unlocked */
  621. rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
  622. if (rc)
  623. return rc;
  624. rc = falcon_spi_cmd(efx, spi, SPI_SST_EWSR, -1, NULL, NULL, 0);
  625. if (rc)
  626. return rc;
  627. status &= ~unlock_mask;
  628. rc = falcon_spi_cmd(efx, spi, SPI_WRSR, -1, &status,
  629. NULL, sizeof(status));
  630. if (rc)
  631. return rc;
  632. rc = falcon_spi_wait_write(efx, spi);
  633. if (rc)
  634. return rc;
  635. return 0;
  636. }
  637. #define FALCON_SPI_VERIFY_BUF_LEN 16
  638. static int
  639. falcon_spi_erase(struct falcon_mtd_partition *part, loff_t start, size_t len)
  640. {
  641. const struct falcon_spi_device *spi = part->spi;
  642. struct efx_nic *efx = part->common.mtd.priv;
  643. unsigned pos, block_len;
  644. u8 empty[FALCON_SPI_VERIFY_BUF_LEN];
  645. u8 buffer[FALCON_SPI_VERIFY_BUF_LEN];
  646. int rc;
  647. if (len != spi->erase_size)
  648. return -EINVAL;
  649. if (spi->erase_command == 0)
  650. return -EOPNOTSUPP;
  651. rc = falcon_spi_unlock(efx, spi);
  652. if (rc)
  653. return rc;
  654. rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
  655. if (rc)
  656. return rc;
  657. rc = falcon_spi_cmd(efx, spi, spi->erase_command, start, NULL,
  658. NULL, 0);
  659. if (rc)
  660. return rc;
  661. rc = falcon_spi_slow_wait(part, false);
  662. /* Verify the entire region has been wiped */
  663. memset(empty, 0xff, sizeof(empty));
  664. for (pos = 0; pos < len; pos += block_len) {
  665. block_len = min(len - pos, sizeof(buffer));
  666. rc = falcon_spi_read(efx, spi, start + pos, block_len,
  667. NULL, buffer);
  668. if (rc)
  669. return rc;
  670. if (memcmp(empty, buffer, block_len))
  671. return -EIO;
  672. /* Avoid locking up the system */
  673. cond_resched();
  674. if (signal_pending(current))
  675. return -EINTR;
  676. }
  677. return rc;
  678. }
  679. static void falcon_mtd_rename(struct efx_mtd_partition *part)
  680. {
  681. struct efx_nic *efx = part->mtd.priv;
  682. snprintf(part->name, sizeof(part->name), "%s %s",
  683. efx->name, part->type_name);
  684. }
  685. static int falcon_mtd_read(struct mtd_info *mtd, loff_t start,
  686. size_t len, size_t *retlen, u8 *buffer)
  687. {
  688. struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
  689. struct efx_nic *efx = mtd->priv;
  690. struct falcon_nic_data *nic_data = efx->nic_data;
  691. int rc;
  692. rc = mutex_lock_interruptible(&nic_data->spi_lock);
  693. if (rc)
  694. return rc;
  695. rc = falcon_spi_read(efx, part->spi, part->offset + start,
  696. len, retlen, buffer);
  697. mutex_unlock(&nic_data->spi_lock);
  698. return rc;
  699. }
  700. static int falcon_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len)
  701. {
  702. struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
  703. struct efx_nic *efx = mtd->priv;
  704. struct falcon_nic_data *nic_data = efx->nic_data;
  705. int rc;
  706. rc = mutex_lock_interruptible(&nic_data->spi_lock);
  707. if (rc)
  708. return rc;
  709. rc = falcon_spi_erase(part, part->offset + start, len);
  710. mutex_unlock(&nic_data->spi_lock);
  711. return rc;
  712. }
  713. static int falcon_mtd_write(struct mtd_info *mtd, loff_t start,
  714. size_t len, size_t *retlen, const u8 *buffer)
  715. {
  716. struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
  717. struct efx_nic *efx = mtd->priv;
  718. struct falcon_nic_data *nic_data = efx->nic_data;
  719. int rc;
  720. rc = mutex_lock_interruptible(&nic_data->spi_lock);
  721. if (rc)
  722. return rc;
  723. rc = falcon_spi_write(efx, part->spi, part->offset + start,
  724. len, retlen, buffer);
  725. mutex_unlock(&nic_data->spi_lock);
  726. return rc;
  727. }
  728. static int falcon_mtd_sync(struct mtd_info *mtd)
  729. {
  730. struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd);
  731. struct efx_nic *efx = mtd->priv;
  732. struct falcon_nic_data *nic_data = efx->nic_data;
  733. int rc;
  734. mutex_lock(&nic_data->spi_lock);
  735. rc = falcon_spi_slow_wait(part, true);
  736. mutex_unlock(&nic_data->spi_lock);
  737. return rc;
  738. }
  739. static int falcon_mtd_probe(struct efx_nic *efx)
  740. {
  741. struct falcon_nic_data *nic_data = efx->nic_data;
  742. struct falcon_mtd_partition *parts;
  743. struct falcon_spi_device *spi;
  744. size_t n_parts;
  745. int rc = -ENODEV;
  746. ASSERT_RTNL();
  747. /* Allocate space for maximum number of partitions */
  748. parts = kcalloc(2, sizeof(*parts), GFP_KERNEL);
  749. n_parts = 0;
  750. spi = &nic_data->spi_flash;
  751. if (falcon_spi_present(spi) && spi->size > FALCON_FLASH_BOOTCODE_START) {
  752. parts[n_parts].spi = spi;
  753. parts[n_parts].offset = FALCON_FLASH_BOOTCODE_START;
  754. parts[n_parts].common.dev_type_name = "flash";
  755. parts[n_parts].common.type_name = "sfc_flash_bootrom";
  756. parts[n_parts].common.mtd.type = MTD_NORFLASH;
  757. parts[n_parts].common.mtd.flags = MTD_CAP_NORFLASH;
  758. parts[n_parts].common.mtd.size = spi->size - FALCON_FLASH_BOOTCODE_START;
  759. parts[n_parts].common.mtd.erasesize = spi->erase_size;
  760. n_parts++;
  761. }
  762. spi = &nic_data->spi_eeprom;
  763. if (falcon_spi_present(spi) && spi->size > FALCON_EEPROM_BOOTCONFIG_START) {
  764. parts[n_parts].spi = spi;
  765. parts[n_parts].offset = FALCON_EEPROM_BOOTCONFIG_START;
  766. parts[n_parts].common.dev_type_name = "EEPROM";
  767. parts[n_parts].common.type_name = "sfc_bootconfig";
  768. parts[n_parts].common.mtd.type = MTD_RAM;
  769. parts[n_parts].common.mtd.flags = MTD_CAP_RAM;
  770. parts[n_parts].common.mtd.size =
  771. min(spi->size, FALCON_EEPROM_BOOTCONFIG_END) -
  772. FALCON_EEPROM_BOOTCONFIG_START;
  773. parts[n_parts].common.mtd.erasesize = spi->erase_size;
  774. n_parts++;
  775. }
  776. rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
  777. if (rc)
  778. kfree(parts);
  779. return rc;
  780. }
  781. #endif /* CONFIG_SFC_MTD */
  782. /**************************************************************************
  783. *
  784. * XMAC operations
  785. *
  786. **************************************************************************
  787. */
  788. /* Configure the XAUI driver that is an output from Falcon */
  789. static void falcon_setup_xaui(struct efx_nic *efx)
  790. {
  791. efx_oword_t sdctl, txdrv;
  792. /* Move the XAUI into low power, unless there is no PHY, in
  793. * which case the XAUI will have to drive a cable. */
  794. if (efx->phy_type == PHY_TYPE_NONE)
  795. return;
  796. efx_reado(efx, &sdctl, FR_AB_XX_SD_CTL);
  797. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
  798. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
  799. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
  800. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
  801. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
  802. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
  803. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
  804. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
  805. efx_writeo(efx, &sdctl, FR_AB_XX_SD_CTL);
  806. EFX_POPULATE_OWORD_8(txdrv,
  807. FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF,
  808. FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF,
  809. FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF,
  810. FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF,
  811. FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF,
  812. FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF,
  813. FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF,
  814. FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF);
  815. efx_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL);
  816. }
  817. int falcon_reset_xaui(struct efx_nic *efx)
  818. {
  819. struct falcon_nic_data *nic_data = efx->nic_data;
  820. efx_oword_t reg;
  821. int count;
  822. /* Don't fetch MAC statistics over an XMAC reset */
  823. WARN_ON(nic_data->stats_disable_count == 0);
  824. /* Start reset sequence */
  825. EFX_POPULATE_OWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);
  826. efx_writeo(efx, &reg, FR_AB_XX_PWR_RST);
  827. /* Wait up to 10 ms for completion, then reinitialise */
  828. for (count = 0; count < 1000; count++) {
  829. efx_reado(efx, &reg, FR_AB_XX_PWR_RST);
  830. if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 &&
  831. EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) {
  832. falcon_setup_xaui(efx);
  833. return 0;
  834. }
  835. udelay(10);
  836. }
  837. netif_err(efx, hw, efx->net_dev,
  838. "timed out waiting for XAUI/XGXS reset\n");
  839. return -ETIMEDOUT;
  840. }
  841. static void falcon_ack_status_intr(struct efx_nic *efx)
  842. {
  843. struct falcon_nic_data *nic_data = efx->nic_data;
  844. efx_oword_t reg;
  845. if ((efx_nic_rev(efx) != EFX_REV_FALCON_B0) || LOOPBACK_INTERNAL(efx))
  846. return;
  847. /* We expect xgmii faults if the wireside link is down */
  848. if (!efx->link_state.up)
  849. return;
  850. /* We can only use this interrupt to signal the negative edge of
  851. * xaui_align [we have to poll the positive edge]. */
  852. if (nic_data->xmac_poll_required)
  853. return;
  854. efx_reado(efx, &reg, FR_AB_XM_MGT_INT_MSK);
  855. }
  856. static bool falcon_xgxs_link_ok(struct efx_nic *efx)
  857. {
  858. efx_oword_t reg;
  859. bool align_done, link_ok = false;
  860. int sync_status;
  861. /* Read link status */
  862. efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
  863. align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE);
  864. sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT);
  865. if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES))
  866. link_ok = true;
  867. /* Clear link status ready for next read */
  868. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);
  869. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);
  870. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);
  871. efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
  872. return link_ok;
  873. }
  874. static bool falcon_xmac_link_ok(struct efx_nic *efx)
  875. {
  876. /*
  877. * Check MAC's XGXS link status except when using XGMII loopback
  878. * which bypasses the XGXS block.
  879. * If possible, check PHY's XGXS link status except when using
  880. * MAC loopback.
  881. */
  882. return (efx->loopback_mode == LOOPBACK_XGMII ||
  883. falcon_xgxs_link_ok(efx)) &&
  884. (!(efx->mdio.mmds & (1 << MDIO_MMD_PHYXS)) ||
  885. LOOPBACK_INTERNAL(efx) ||
  886. efx_mdio_phyxgxs_lane_sync(efx));
  887. }
  888. static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
  889. {
  890. unsigned int max_frame_len;
  891. efx_oword_t reg;
  892. bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX);
  893. bool tx_fc = !!(efx->link_state.fc & EFX_FC_TX);
  894. /* Configure MAC - cut-thru mode is hard wired on */
  895. EFX_POPULATE_OWORD_3(reg,
  896. FRF_AB_XM_RX_JUMBO_MODE, 1,
  897. FRF_AB_XM_TX_STAT_EN, 1,
  898. FRF_AB_XM_RX_STAT_EN, 1);
  899. efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
  900. /* Configure TX */
  901. EFX_POPULATE_OWORD_6(reg,
  902. FRF_AB_XM_TXEN, 1,
  903. FRF_AB_XM_TX_PRMBL, 1,
  904. FRF_AB_XM_AUTO_PAD, 1,
  905. FRF_AB_XM_TXCRC, 1,
  906. FRF_AB_XM_FCNTL, tx_fc,
  907. FRF_AB_XM_IPG, 0x3);
  908. efx_writeo(efx, &reg, FR_AB_XM_TX_CFG);
  909. /* Configure RX */
  910. EFX_POPULATE_OWORD_5(reg,
  911. FRF_AB_XM_RXEN, 1,
  912. FRF_AB_XM_AUTO_DEPAD, 0,
  913. FRF_AB_XM_ACPT_ALL_MCAST, 1,
  914. FRF_AB_XM_ACPT_ALL_UCAST, !efx->unicast_filter,
  915. FRF_AB_XM_PASS_CRC_ERR, 1);
  916. efx_writeo(efx, &reg, FR_AB_XM_RX_CFG);
  917. /* Set frame length */
  918. max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
  919. EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);
  920. efx_writeo(efx, &reg, FR_AB_XM_RX_PARAM);
  921. EFX_POPULATE_OWORD_2(reg,
  922. FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,
  923. FRF_AB_XM_TX_JUMBO_MODE, 1);
  924. efx_writeo(efx, &reg, FR_AB_XM_TX_PARAM);
  925. EFX_POPULATE_OWORD_2(reg,
  926. FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
  927. FRF_AB_XM_DIS_FCNTL, !rx_fc);
  928. efx_writeo(efx, &reg, FR_AB_XM_FC);
  929. /* Set MAC address */
  930. memcpy(&reg, &efx->net_dev->dev_addr[0], 4);
  931. efx_writeo(efx, &reg, FR_AB_XM_ADR_LO);
  932. memcpy(&reg, &efx->net_dev->dev_addr[4], 2);
  933. efx_writeo(efx, &reg, FR_AB_XM_ADR_HI);
  934. }
  935. static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
  936. {
  937. efx_oword_t reg;
  938. bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
  939. bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
  940. bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
  941. bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
  942. /* XGXS block is flaky and will need to be reset if moving
  943. * into our out of XGMII, XGXS or XAUI loopbacks. */
  944. efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
  945. old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN);
  946. old_xgmii_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN);
  947. efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
  948. old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA);
  949. /* The PHY driver may have turned XAUI off */
  950. if ((xgxs_loopback != old_xgxs_loopback) ||
  951. (xaui_loopback != old_xaui_loopback) ||
  952. (xgmii_loopback != old_xgmii_loopback))
  953. falcon_reset_xaui(efx);
  954. efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
  955. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG,
  956. (xgxs_loopback || xaui_loopback) ?
  957. FFE_AB_XX_FORCE_SIG_ALL_LANES : 0);
  958. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback);
  959. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback);
  960. efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
  961. efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
  962. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback);
  963. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback);
  964. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback);
  965. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback);
  966. efx_writeo(efx, &reg, FR_AB_XX_SD_CTL);
  967. }
  968. /* Try to bring up the Falcon side of the Falcon-Phy XAUI link */
  969. static bool falcon_xmac_link_ok_retry(struct efx_nic *efx, int tries)
  970. {
  971. bool mac_up = falcon_xmac_link_ok(efx);
  972. if (LOOPBACK_MASK(efx) & LOOPBACKS_EXTERNAL(efx) & LOOPBACKS_WS ||
  973. efx_phy_mode_disabled(efx->phy_mode))
  974. /* XAUI link is expected to be down */
  975. return mac_up;
  976. falcon_stop_nic_stats(efx);
  977. while (!mac_up && tries) {
  978. netif_dbg(efx, hw, efx->net_dev, "bashing xaui\n");
  979. falcon_reset_xaui(efx);
  980. udelay(200);
  981. mac_up = falcon_xmac_link_ok(efx);
  982. --tries;
  983. }
  984. falcon_start_nic_stats(efx);
  985. return mac_up;
  986. }
  987. static bool falcon_xmac_check_fault(struct efx_nic *efx)
  988. {
  989. return !falcon_xmac_link_ok_retry(efx, 5);
  990. }
  991. static int falcon_reconfigure_xmac(struct efx_nic *efx)
  992. {
  993. struct falcon_nic_data *nic_data = efx->nic_data;
  994. efx_farch_filter_sync_rx_mode(efx);
  995. falcon_reconfigure_xgxs_core(efx);
  996. falcon_reconfigure_xmac_core(efx);
  997. falcon_reconfigure_mac_wrapper(efx);
  998. nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 5);
  999. falcon_ack_status_intr(efx);
  1000. return 0;
  1001. }
  1002. static void falcon_update_stats_xmac(struct efx_nic *efx)
  1003. {
  1004. struct efx_mac_stats *mac_stats = &efx->mac_stats;
  1005. /* Update MAC stats from DMAed values */
  1006. FALCON_STAT(efx, XgRxOctets, rx_bytes);
  1007. FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
  1008. FALCON_STAT(efx, XgRxPkts, rx_packets);
  1009. FALCON_STAT(efx, XgRxPktsOK, rx_good);
  1010. FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
  1011. FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
  1012. FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
  1013. FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
  1014. FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
  1015. FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
  1016. FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
  1017. FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
  1018. FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
  1019. FALCON_STAT(efx, XgRxAlignError, rx_align_error);
  1020. FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
  1021. FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
  1022. FALCON_STAT(efx, XgRxControlPkts, rx_control);
  1023. FALCON_STAT(efx, XgRxPausePkts, rx_pause);
  1024. FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
  1025. FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
  1026. FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
  1027. FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
  1028. FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
  1029. FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
  1030. FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
  1031. FALCON_STAT(efx, XgRxLengthError, rx_length_error);
  1032. FALCON_STAT(efx, XgTxPkts, tx_packets);
  1033. FALCON_STAT(efx, XgTxOctets, tx_bytes);
  1034. FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
  1035. FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
  1036. FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
  1037. FALCON_STAT(efx, XgTxControlPkts, tx_control);
  1038. FALCON_STAT(efx, XgTxPausePkts, tx_pause);
  1039. FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
  1040. FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
  1041. FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
  1042. FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
  1043. FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
  1044. FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
  1045. FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
  1046. FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
  1047. FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
  1048. FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
  1049. FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
  1050. FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);
  1051. /* Update derived statistics */
  1052. efx_update_diff_stat(&mac_stats->tx_good_bytes,
  1053. mac_stats->tx_bytes - mac_stats->tx_bad_bytes -
  1054. mac_stats->tx_control * 64);
  1055. efx_update_diff_stat(&mac_stats->rx_bad_bytes,
  1056. mac_stats->rx_bytes - mac_stats->rx_good_bytes -
  1057. mac_stats->rx_control * 64);
  1058. }
  1059. static void falcon_poll_xmac(struct efx_nic *efx)
  1060. {
  1061. struct falcon_nic_data *nic_data = efx->nic_data;
  1062. /* We expect xgmii faults if the wireside link is down */
  1063. if (!efx->link_state.up || !nic_data->xmac_poll_required)
  1064. return;
  1065. nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 1);
  1066. falcon_ack_status_intr(efx);
  1067. }
  1068. /**************************************************************************
  1069. *
  1070. * MAC wrapper
  1071. *
  1072. **************************************************************************
  1073. */
  1074. static void falcon_push_multicast_hash(struct efx_nic *efx)
  1075. {
  1076. union efx_multicast_hash *mc_hash = &efx->multicast_hash;
  1077. WARN_ON(!mutex_is_locked(&efx->mac_lock));
  1078. efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
  1079. efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
  1080. }
  1081. static void falcon_reset_macs(struct efx_nic *efx)
  1082. {
  1083. struct falcon_nic_data *nic_data = efx->nic_data;
  1084. efx_oword_t reg, mac_ctrl;
  1085. int count;
  1086. if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
  1087. /* It's not safe to use GLB_CTL_REG to reset the
  1088. * macs, so instead use the internal MAC resets
  1089. */
  1090. EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
  1091. efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
  1092. for (count = 0; count < 10000; count++) {
  1093. efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
  1094. if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
  1095. 0)
  1096. return;
  1097. udelay(10);
  1098. }
  1099. netif_err(efx, hw, efx->net_dev,
  1100. "timed out waiting for XMAC core reset\n");
  1101. }
  1102. /* Mac stats will fail whist the TX fifo is draining */
  1103. WARN_ON(nic_data->stats_disable_count == 0);
  1104. efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
  1105. EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);
  1106. efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
  1107. efx_reado(efx, &reg, FR_AB_GLB_CTL);
  1108. EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
  1109. EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
  1110. EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
  1111. efx_writeo(efx, &reg, FR_AB_GLB_CTL);
  1112. count = 0;
  1113. while (1) {
  1114. efx_reado(efx, &reg, FR_AB_GLB_CTL);
  1115. if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
  1116. !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
  1117. !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
  1118. netif_dbg(efx, hw, efx->net_dev,
  1119. "Completed MAC reset after %d loops\n",
  1120. count);
  1121. break;
  1122. }
  1123. if (count > 20) {
  1124. netif_err(efx, hw, efx->net_dev, "MAC reset failed\n");
  1125. break;
  1126. }
  1127. count++;
  1128. udelay(10);
  1129. }
  1130. /* Ensure the correct MAC is selected before statistics
  1131. * are re-enabled by the caller */
  1132. efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
  1133. falcon_setup_xaui(efx);
  1134. }
  1135. static void falcon_drain_tx_fifo(struct efx_nic *efx)
  1136. {
  1137. efx_oword_t reg;
  1138. if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
  1139. (efx->loopback_mode != LOOPBACK_NONE))
  1140. return;
  1141. efx_reado(efx, &reg, FR_AB_MAC_CTRL);
  1142. /* There is no point in draining more than once */
  1143. if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
  1144. return;
  1145. falcon_reset_macs(efx);
  1146. }
  1147. static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
  1148. {
  1149. efx_oword_t reg;
  1150. if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
  1151. return;
  1152. /* Isolate the MAC -> RX */
  1153. efx_reado(efx, &reg, FR_AZ_RX_CFG);
  1154. EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
  1155. efx_writeo(efx, &reg, FR_AZ_RX_CFG);
  1156. /* Isolate TX -> MAC */
  1157. falcon_drain_tx_fifo(efx);
  1158. }
  1159. static void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
  1160. {
  1161. struct efx_link_state *link_state = &efx->link_state;
  1162. efx_oword_t reg;
  1163. int link_speed, isolate;
  1164. isolate = !!ACCESS_ONCE(efx->reset_pending);
  1165. switch (link_state->speed) {
  1166. case 10000: link_speed = 3; break;
  1167. case 1000: link_speed = 2; break;
  1168. case 100: link_speed = 1; break;
  1169. default: link_speed = 0; break;
  1170. }
  1171. /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
  1172. * as advertised. Disable to ensure packets are not
  1173. * indefinitely held and TX queue can be flushed at any point
  1174. * while the link is down. */
  1175. EFX_POPULATE_OWORD_5(reg,
  1176. FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
  1177. FRF_AB_MAC_BCAD_ACPT, 1,
  1178. FRF_AB_MAC_UC_PROM, !efx->unicast_filter,
  1179. FRF_AB_MAC_LINK_STATUS, 1, /* always set */
  1180. FRF_AB_MAC_SPEED, link_speed);
  1181. /* On B0, MAC backpressure can be disabled and packets get
  1182. * discarded. */
  1183. if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
  1184. EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
  1185. !link_state->up || isolate);
  1186. }
  1187. efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
  1188. /* Restore the multicast hash registers. */
  1189. falcon_push_multicast_hash(efx);
  1190. efx_reado(efx, &reg, FR_AZ_RX_CFG);
  1191. /* Enable XOFF signal from RX FIFO (we enabled it during NIC
  1192. * initialisation but it may read back as 0) */
  1193. EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
  1194. /* Unisolate the MAC -> RX */
  1195. if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
  1196. EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate);
  1197. efx_writeo(efx, &reg, FR_AZ_RX_CFG);
  1198. }
  1199. static void falcon_stats_request(struct efx_nic *efx)
  1200. {
  1201. struct falcon_nic_data *nic_data = efx->nic_data;
  1202. efx_oword_t reg;
  1203. WARN_ON(nic_data->stats_pending);
  1204. WARN_ON(nic_data->stats_disable_count);
  1205. FALCON_XMAC_STATS_DMA_FLAG(efx) = 0;
  1206. nic_data->stats_pending = true;
  1207. wmb(); /* ensure done flag is clear */
  1208. /* Initiate DMA transfer of stats */
  1209. EFX_POPULATE_OWORD_2(reg,
  1210. FRF_AB_MAC_STAT_DMA_CMD, 1,
  1211. FRF_AB_MAC_STAT_DMA_ADR,
  1212. efx->stats_buffer.dma_addr);
  1213. efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
  1214. mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2));
  1215. }
  1216. static void falcon_stats_complete(struct efx_nic *efx)
  1217. {
  1218. struct falcon_nic_data *nic_data = efx->nic_data;
  1219. if (!nic_data->stats_pending)
  1220. return;
  1221. nic_data->stats_pending = false;
  1222. if (FALCON_XMAC_STATS_DMA_FLAG(efx)) {
  1223. rmb(); /* read the done flag before the stats */
  1224. falcon_update_stats_xmac(efx);
  1225. } else {
  1226. netif_err(efx, hw, efx->net_dev,
  1227. "timed out waiting for statistics\n");
  1228. }
  1229. }
  1230. static void falcon_stats_timer_func(unsigned long context)
  1231. {
  1232. struct efx_nic *efx = (struct efx_nic *)context;
  1233. struct falcon_nic_data *nic_data = efx->nic_data;
  1234. spin_lock(&efx->stats_lock);
  1235. falcon_stats_complete(efx);
  1236. if (nic_data->stats_disable_count == 0)
  1237. falcon_stats_request(efx);
  1238. spin_unlock(&efx->stats_lock);
  1239. }
  1240. static bool falcon_loopback_link_poll(struct efx_nic *efx)
  1241. {
  1242. struct efx_link_state old_state = efx->link_state;
  1243. WARN_ON(!mutex_is_locked(&efx->mac_lock));
  1244. WARN_ON(!LOOPBACK_INTERNAL(efx));
  1245. efx->link_state.fd = true;
  1246. efx->link_state.fc = efx->wanted_fc;
  1247. efx->link_state.up = true;
  1248. efx->link_state.speed = 10000;
  1249. return !efx_link_state_equal(&efx->link_state, &old_state);
  1250. }
  1251. static int falcon_reconfigure_port(struct efx_nic *efx)
  1252. {
  1253. int rc;
  1254. WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0);
  1255. /* Poll the PHY link state *before* reconfiguring it. This means we
  1256. * will pick up the correct speed (in loopback) to select the correct
  1257. * MAC.
  1258. */
  1259. if (LOOPBACK_INTERNAL(efx))
  1260. falcon_loopback_link_poll(efx);
  1261. else
  1262. efx->phy_op->poll(efx);
  1263. falcon_stop_nic_stats(efx);
  1264. falcon_deconfigure_mac_wrapper(efx);
  1265. falcon_reset_macs(efx);
  1266. efx->phy_op->reconfigure(efx);
  1267. rc = falcon_reconfigure_xmac(efx);
  1268. BUG_ON(rc);
  1269. falcon_start_nic_stats(efx);
  1270. /* Synchronise efx->link_state with the kernel */
  1271. efx_link_status_changed(efx);
  1272. return 0;
  1273. }
  1274. /* TX flow control may automatically turn itself off if the link
  1275. * partner (intermittently) stops responding to pause frames. There
  1276. * isn't any indication that this has happened, so the best we do is
  1277. * leave it up to the user to spot this and fix it by cycling transmit
  1278. * flow control on this end.
  1279. */
  1280. static void falcon_a1_prepare_enable_fc_tx(struct efx_nic *efx)
  1281. {
  1282. /* Schedule a reset to recover */
  1283. efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
  1284. }
  1285. static void falcon_b0_prepare_enable_fc_tx(struct efx_nic *efx)
  1286. {
  1287. /* Recover by resetting the EM block */
  1288. falcon_stop_nic_stats(efx);
  1289. falcon_drain_tx_fifo(efx);
  1290. falcon_reconfigure_xmac(efx);
  1291. falcon_start_nic_stats(efx);
  1292. }
  1293. /**************************************************************************
  1294. *
  1295. * PHY access via GMII
  1296. *
  1297. **************************************************************************
  1298. */
  1299. /* Wait for GMII access to complete */
  1300. static int falcon_gmii_wait(struct efx_nic *efx)
  1301. {
  1302. efx_oword_t md_stat;
  1303. int count;
  1304. /* wait up to 50ms - taken max from datasheet */
  1305. for (count = 0; count < 5000; count++) {
  1306. efx_reado(efx, &md_stat, FR_AB_MD_STAT);
  1307. if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
  1308. if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
  1309. EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
  1310. netif_err(efx, hw, efx->net_dev,
  1311. "error from GMII access "
  1312. EFX_OWORD_FMT"\n",
  1313. EFX_OWORD_VAL(md_stat));
  1314. return -EIO;
  1315. }
  1316. return 0;
  1317. }
  1318. udelay(10);
  1319. }
  1320. netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n");
  1321. return -ETIMEDOUT;
  1322. }
  1323. /* Write an MDIO register of a PHY connected to Falcon. */
  1324. static int falcon_mdio_write(struct net_device *net_dev,
  1325. int prtad, int devad, u16 addr, u16 value)
  1326. {
  1327. struct efx_nic *efx = netdev_priv(net_dev);
  1328. struct falcon_nic_data *nic_data = efx->nic_data;
  1329. efx_oword_t reg;
  1330. int rc;
  1331. netif_vdbg(efx, hw, efx->net_dev,
  1332. "writing MDIO %d register %d.%d with 0x%04x\n",
  1333. prtad, devad, addr, value);
  1334. mutex_lock(&nic_data->mdio_lock);
  1335. /* Check MDIO not currently being accessed */
  1336. rc = falcon_gmii_wait(efx);
  1337. if (rc)
  1338. goto out;
  1339. /* Write the address/ID register */
  1340. EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
  1341. efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
  1342. EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
  1343. FRF_AB_MD_DEV_ADR, devad);
  1344. efx_writeo(efx, &reg, FR_AB_MD_ID);
  1345. /* Write data */
  1346. EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
  1347. efx_writeo(efx, &reg, FR_AB_MD_TXD);
  1348. EFX_POPULATE_OWORD_2(reg,
  1349. FRF_AB_MD_WRC, 1,
  1350. FRF_AB_MD_GC, 0);
  1351. efx_writeo(efx, &reg, FR_AB_MD_CS);
  1352. /* Wait for data to be written */
  1353. rc = falcon_gmii_wait(efx);
  1354. if (rc) {
  1355. /* Abort the write operation */
  1356. EFX_POPULATE_OWORD_2(reg,
  1357. FRF_AB_MD_WRC, 0,
  1358. FRF_AB_MD_GC, 1);
  1359. efx_writeo(efx, &reg, FR_AB_MD_CS);
  1360. udelay(10);
  1361. }
  1362. out:
  1363. mutex_unlock(&nic_data->mdio_lock);
  1364. return rc;
  1365. }
  1366. /* Read an MDIO register of a PHY connected to Falcon. */
  1367. static int falcon_mdio_read(struct net_device *net_dev,
  1368. int prtad, int devad, u16 addr)
  1369. {
  1370. struct efx_nic *efx = netdev_priv(net_dev);
  1371. struct falcon_nic_data *nic_data = efx->nic_data;
  1372. efx_oword_t reg;
  1373. int rc;
  1374. mutex_lock(&nic_data->mdio_lock);
  1375. /* Check MDIO not currently being accessed */
  1376. rc = falcon_gmii_wait(efx);
  1377. if (rc)
  1378. goto out;
  1379. EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
  1380. efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
  1381. EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
  1382. FRF_AB_MD_DEV_ADR, devad);
  1383. efx_writeo(efx, &reg, FR_AB_MD_ID);
  1384. /* Request data to be read */
  1385. EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
  1386. efx_writeo(efx, &reg, FR_AB_MD_CS);
  1387. /* Wait for data to become available */
  1388. rc = falcon_gmii_wait(efx);
  1389. if (rc == 0) {
  1390. efx_reado(efx, &reg, FR_AB_MD_RXD);
  1391. rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
  1392. netif_vdbg(efx, hw, efx->net_dev,
  1393. "read from MDIO %d register %d.%d, got %04x\n",
  1394. prtad, devad, addr, rc);
  1395. } else {
  1396. /* Abort the read operation */
  1397. EFX_POPULATE_OWORD_2(reg,
  1398. FRF_AB_MD_RIC, 0,
  1399. FRF_AB_MD_GC, 1);
  1400. efx_writeo(efx, &reg, FR_AB_MD_CS);
  1401. netif_dbg(efx, hw, efx->net_dev,
  1402. "read from MDIO %d register %d.%d, got error %d\n",
  1403. prtad, devad, addr, rc);
  1404. }
  1405. out:
  1406. mutex_unlock(&nic_data->mdio_lock);
  1407. return rc;
  1408. }
  1409. /* This call is responsible for hooking in the MAC and PHY operations */
  1410. static int falcon_probe_port(struct efx_nic *efx)
  1411. {
  1412. struct falcon_nic_data *nic_data = efx->nic_data;
  1413. int rc;
  1414. switch (efx->phy_type) {
  1415. case PHY_TYPE_SFX7101:
  1416. efx->phy_op = &falcon_sfx7101_phy_ops;
  1417. break;
  1418. case PHY_TYPE_QT2022C2:
  1419. case PHY_TYPE_QT2025C:
  1420. efx->phy_op = &falcon_qt202x_phy_ops;
  1421. break;
  1422. case PHY_TYPE_TXC43128:
  1423. efx->phy_op = &falcon_txc_phy_ops;
  1424. break;
  1425. default:
  1426. netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n",
  1427. efx->phy_type);
  1428. return -ENODEV;
  1429. }
  1430. /* Fill out MDIO structure and loopback modes */
  1431. mutex_init(&nic_data->mdio_lock);
  1432. efx->mdio.mdio_read = falcon_mdio_read;
  1433. efx->mdio.mdio_write = falcon_mdio_write;
  1434. rc = efx->phy_op->probe(efx);
  1435. if (rc != 0)
  1436. return rc;
  1437. /* Initial assumption */
  1438. efx->link_state.speed = 10000;
  1439. efx->link_state.fd = true;
  1440. /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
  1441. if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
  1442. efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
  1443. else
  1444. efx->wanted_fc = EFX_FC_RX;
  1445. if (efx->mdio.mmds & MDIO_DEVS_AN)
  1446. efx->wanted_fc |= EFX_FC_AUTO;
  1447. /* Allocate buffer for stats */
  1448. rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
  1449. FALCON_MAC_STATS_SIZE, GFP_KERNEL);
  1450. if (rc)
  1451. return rc;
  1452. netif_dbg(efx, probe, efx->net_dev,
  1453. "stats buffer at %llx (virt %p phys %llx)\n",
  1454. (u64)efx->stats_buffer.dma_addr,
  1455. efx->stats_buffer.addr,
  1456. (u64)virt_to_phys(efx->stats_buffer.addr));
  1457. return 0;
  1458. }
  1459. static void falcon_remove_port(struct efx_nic *efx)
  1460. {
  1461. efx->phy_op->remove(efx);
  1462. efx_nic_free_buffer(efx, &efx->stats_buffer);
  1463. }
  1464. /* Global events are basically PHY events */
  1465. static bool
  1466. falcon_handle_global_event(struct efx_channel *channel, efx_qword_t *event)
  1467. {
  1468. struct efx_nic *efx = channel->efx;
  1469. struct falcon_nic_data *nic_data = efx->nic_data;
  1470. if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
  1471. EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
  1472. EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR))
  1473. /* Ignored */
  1474. return true;
  1475. if ((efx_nic_rev(efx) == EFX_REV_FALCON_B0) &&
  1476. EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
  1477. nic_data->xmac_poll_required = true;
  1478. return true;
  1479. }
  1480. if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ?
  1481. EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
  1482. EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
  1483. netif_err(efx, rx_err, efx->net_dev,
  1484. "channel %d seen global RX_RESET event. Resetting.\n",
  1485. channel->channel);
  1486. atomic_inc(&efx->rx_reset);
  1487. efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
  1488. RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
  1489. return true;
  1490. }
  1491. return false;
  1492. }
  1493. /**************************************************************************
  1494. *
  1495. * Falcon test code
  1496. *
  1497. **************************************************************************/
  1498. static int
  1499. falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
  1500. {
  1501. struct falcon_nic_data *nic_data = efx->nic_data;
  1502. struct falcon_nvconfig *nvconfig;
  1503. struct falcon_spi_device *spi;
  1504. void *region;
  1505. int rc, magic_num, struct_ver;
  1506. __le16 *word, *limit;
  1507. u32 csum;
  1508. if (falcon_spi_present(&nic_data->spi_flash))
  1509. spi = &nic_data->spi_flash;
  1510. else if (falcon_spi_present(&nic_data->spi_eeprom))
  1511. spi = &nic_data->spi_eeprom;
  1512. else
  1513. return -EINVAL;
  1514. region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
  1515. if (!region)
  1516. return -ENOMEM;
  1517. nvconfig = region + FALCON_NVCONFIG_OFFSET;
  1518. mutex_lock(&nic_data->spi_lock);
  1519. rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
  1520. mutex_unlock(&nic_data->spi_lock);
  1521. if (rc) {
  1522. netif_err(efx, hw, efx->net_dev, "Failed to read %s\n",
  1523. falcon_spi_present(&nic_data->spi_flash) ?
  1524. "flash" : "EEPROM");
  1525. rc = -EIO;
  1526. goto out;
  1527. }
  1528. magic_num = le16_to_cpu(nvconfig->board_magic_num);
  1529. struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
  1530. rc = -EINVAL;
  1531. if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
  1532. netif_err(efx, hw, efx->net_dev,
  1533. "NVRAM bad magic 0x%x\n", magic_num);
  1534. goto out;
  1535. }
  1536. if (struct_ver < 2) {
  1537. netif_err(efx, hw, efx->net_dev,
  1538. "NVRAM has ancient version 0x%x\n", struct_ver);
  1539. goto out;
  1540. } else if (struct_ver < 4) {
  1541. word = &nvconfig->board_magic_num;
  1542. limit = (__le16 *) (nvconfig + 1);
  1543. } else {
  1544. word = region;
  1545. limit = region + FALCON_NVCONFIG_END;
  1546. }
  1547. for (csum = 0; word < limit; ++word)
  1548. csum += le16_to_cpu(*word);
  1549. if (~csum & 0xffff) {
  1550. netif_err(efx, hw, efx->net_dev,
  1551. "NVRAM has incorrect checksum\n");
  1552. goto out;
  1553. }
  1554. rc = 0;
  1555. if (nvconfig_out)
  1556. memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
  1557. out:
  1558. kfree(region);
  1559. return rc;
  1560. }
  1561. static int falcon_test_nvram(struct efx_nic *efx)
  1562. {
  1563. return falcon_read_nvram(efx, NULL);
  1564. }
  1565. static const struct efx_farch_register_test falcon_b0_register_tests[] = {
  1566. { FR_AZ_ADR_REGION,
  1567. EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
  1568. { FR_AZ_RX_CFG,
  1569. EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
  1570. { FR_AZ_TX_CFG,
  1571. EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
  1572. { FR_AZ_TX_RESERVED,
  1573. EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
  1574. { FR_AB_MAC_CTRL,
  1575. EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
  1576. { FR_AZ_SRM_TX_DC_CFG,
  1577. EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
  1578. { FR_AZ_RX_DC_CFG,
  1579. EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
  1580. { FR_AZ_RX_DC_PF_WM,
  1581. EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
  1582. { FR_BZ_DP_CTRL,
  1583. EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
  1584. { FR_AB_GM_CFG2,
  1585. EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
  1586. { FR_AB_GMF_CFG0,
  1587. EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
  1588. { FR_AB_XM_GLB_CFG,
  1589. EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
  1590. { FR_AB_XM_TX_CFG,
  1591. EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
  1592. { FR_AB_XM_RX_CFG,
  1593. EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
  1594. { FR_AB_XM_RX_PARAM,
  1595. EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
  1596. { FR_AB_XM_FC,
  1597. EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
  1598. { FR_AB_XM_ADR_LO,
  1599. EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
  1600. { FR_AB_XX_SD_CTL,
  1601. EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
  1602. };
  1603. static int
  1604. falcon_b0_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
  1605. {
  1606. enum reset_type reset_method = RESET_TYPE_INVISIBLE;
  1607. int rc, rc2;
  1608. mutex_lock(&efx->mac_lock);
  1609. if (efx->loopback_modes) {
  1610. /* We need the 312 clock from the PHY to test the XMAC
  1611. * registers, so move into XGMII loopback if available */
  1612. if (efx->loopback_modes & (1 << LOOPBACK_XGMII))
  1613. efx->loopback_mode = LOOPBACK_XGMII;
  1614. else
  1615. efx->loopback_mode = __ffs(efx->loopback_modes);
  1616. }
  1617. __efx_reconfigure_port(efx);
  1618. mutex_unlock(&efx->mac_lock);
  1619. efx_reset_down(efx, reset_method);
  1620. tests->registers =
  1621. efx_farch_test_registers(efx, falcon_b0_register_tests,
  1622. ARRAY_SIZE(falcon_b0_register_tests))
  1623. ? -1 : 1;
  1624. rc = falcon_reset_hw(efx, reset_method);
  1625. rc2 = efx_reset_up(efx, reset_method, rc == 0);
  1626. return rc ? rc : rc2;
  1627. }
  1628. /**************************************************************************
  1629. *
  1630. * Device reset
  1631. *
  1632. **************************************************************************
  1633. */
  1634. static enum reset_type falcon_map_reset_reason(enum reset_type reason)
  1635. {
  1636. switch (reason) {
  1637. case RESET_TYPE_RX_RECOVERY:
  1638. case RESET_TYPE_RX_DESC_FETCH:
  1639. case RESET_TYPE_TX_DESC_FETCH:
  1640. case RESET_TYPE_TX_SKIP:
  1641. /* These can occasionally occur due to hardware bugs.
  1642. * We try to reset without disrupting the link.
  1643. */
  1644. return RESET_TYPE_INVISIBLE;
  1645. default:
  1646. return RESET_TYPE_ALL;
  1647. }
  1648. }
  1649. static int falcon_map_reset_flags(u32 *flags)
  1650. {
  1651. enum {
  1652. FALCON_RESET_INVISIBLE = (ETH_RESET_DMA | ETH_RESET_FILTER |
  1653. ETH_RESET_OFFLOAD | ETH_RESET_MAC),
  1654. FALCON_RESET_ALL = FALCON_RESET_INVISIBLE | ETH_RESET_PHY,
  1655. FALCON_RESET_WORLD = FALCON_RESET_ALL | ETH_RESET_IRQ,
  1656. };
  1657. if ((*flags & FALCON_RESET_WORLD) == FALCON_RESET_WORLD) {
  1658. *flags &= ~FALCON_RESET_WORLD;
  1659. return RESET_TYPE_WORLD;
  1660. }
  1661. if ((*flags & FALCON_RESET_ALL) == FALCON_RESET_ALL) {
  1662. *flags &= ~FALCON_RESET_ALL;
  1663. return RESET_TYPE_ALL;
  1664. }
  1665. if ((*flags & FALCON_RESET_INVISIBLE) == FALCON_RESET_INVISIBLE) {
  1666. *flags &= ~FALCON_RESET_INVISIBLE;
  1667. return RESET_TYPE_INVISIBLE;
  1668. }
  1669. return -EINVAL;
  1670. }
  1671. /* Resets NIC to known state. This routine must be called in process
  1672. * context and is allowed to sleep. */
  1673. static int __falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
  1674. {
  1675. struct falcon_nic_data *nic_data = efx->nic_data;
  1676. efx_oword_t glb_ctl_reg_ker;
  1677. int rc;
  1678. netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n",
  1679. RESET_TYPE(method));
  1680. /* Initiate device reset */
  1681. if (method == RESET_TYPE_WORLD) {
  1682. rc = pci_save_state(efx->pci_dev);
  1683. if (rc) {
  1684. netif_err(efx, drv, efx->net_dev,
  1685. "failed to backup PCI state of primary "
  1686. "function prior to hardware reset\n");
  1687. goto fail1;
  1688. }
  1689. if (efx_nic_is_dual_func(efx)) {
  1690. rc = pci_save_state(nic_data->pci_dev2);
  1691. if (rc) {
  1692. netif_err(efx, drv, efx->net_dev,
  1693. "failed to backup PCI state of "
  1694. "secondary function prior to "
  1695. "hardware reset\n");
  1696. goto fail2;
  1697. }
  1698. }
  1699. EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
  1700. FRF_AB_EXT_PHY_RST_DUR,
  1701. FFE_AB_EXT_PHY_RST_DUR_10240US,
  1702. FRF_AB_SWRST, 1);
  1703. } else {
  1704. EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
  1705. /* exclude PHY from "invisible" reset */
  1706. FRF_AB_EXT_PHY_RST_CTL,
  1707. method == RESET_TYPE_INVISIBLE,
  1708. /* exclude EEPROM/flash and PCIe */
  1709. FRF_AB_PCIE_CORE_RST_CTL, 1,
  1710. FRF_AB_PCIE_NSTKY_RST_CTL, 1,
  1711. FRF_AB_PCIE_SD_RST_CTL, 1,
  1712. FRF_AB_EE_RST_CTL, 1,
  1713. FRF_AB_EXT_PHY_RST_DUR,
  1714. FFE_AB_EXT_PHY_RST_DUR_10240US,
  1715. FRF_AB_SWRST, 1);
  1716. }
  1717. efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
  1718. netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n");
  1719. schedule_timeout_uninterruptible(HZ / 20);
  1720. /* Restore PCI configuration if needed */
  1721. if (method == RESET_TYPE_WORLD) {
  1722. if (efx_nic_is_dual_func(efx))
  1723. pci_restore_state(nic_data->pci_dev2);
  1724. pci_restore_state(efx->pci_dev);
  1725. netif_dbg(efx, drv, efx->net_dev,
  1726. "successfully restored PCI config\n");
  1727. }
  1728. /* Assert that reset complete */
  1729. efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
  1730. if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
  1731. rc = -ETIMEDOUT;
  1732. netif_err(efx, hw, efx->net_dev,
  1733. "timed out waiting for hardware reset\n");
  1734. goto fail3;
  1735. }
  1736. netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n");
  1737. return 0;
  1738. /* pci_save_state() and pci_restore_state() MUST be called in pairs */
  1739. fail2:
  1740. pci_restore_state(efx->pci_dev);
  1741. fail1:
  1742. fail3:
  1743. return rc;
  1744. }
  1745. static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
  1746. {
  1747. struct falcon_nic_data *nic_data = efx->nic_data;
  1748. int rc;
  1749. mutex_lock(&nic_data->spi_lock);
  1750. rc = __falcon_reset_hw(efx, method);
  1751. mutex_unlock(&nic_data->spi_lock);
  1752. return rc;
  1753. }
  1754. static void falcon_monitor(struct efx_nic *efx)
  1755. {
  1756. bool link_changed;
  1757. int rc;
  1758. BUG_ON(!mutex_is_locked(&efx->mac_lock));
  1759. rc = falcon_board(efx)->type->monitor(efx);
  1760. if (rc) {
  1761. netif_err(efx, hw, efx->net_dev,
  1762. "Board sensor %s; shutting down PHY\n",
  1763. (rc == -ERANGE) ? "reported fault" : "failed");
  1764. efx->phy_mode |= PHY_MODE_LOW_POWER;
  1765. rc = __efx_reconfigure_port(efx);
  1766. WARN_ON(rc);
  1767. }
  1768. if (LOOPBACK_INTERNAL(efx))
  1769. link_changed = falcon_loopback_link_poll(efx);
  1770. else
  1771. link_changed = efx->phy_op->poll(efx);
  1772. if (link_changed) {
  1773. falcon_stop_nic_stats(efx);
  1774. falcon_deconfigure_mac_wrapper(efx);
  1775. falcon_reset_macs(efx);
  1776. rc = falcon_reconfigure_xmac(efx);
  1777. BUG_ON(rc);
  1778. falcon_start_nic_stats(efx);
  1779. efx_link_status_changed(efx);
  1780. }
  1781. falcon_poll_xmac(efx);
  1782. }
  1783. /* Zeroes out the SRAM contents. This routine must be called in
  1784. * process context and is allowed to sleep.
  1785. */
  1786. static int falcon_reset_sram(struct efx_nic *efx)
  1787. {
  1788. efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
  1789. int count;
  1790. /* Set the SRAM wake/sleep GPIO appropriately. */
  1791. efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
  1792. EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
  1793. EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
  1794. efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
  1795. /* Initiate SRAM reset */
  1796. EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
  1797. FRF_AZ_SRM_INIT_EN, 1,
  1798. FRF_AZ_SRM_NB_SZ, 0);
  1799. efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
  1800. /* Wait for SRAM reset to complete */
  1801. count = 0;
  1802. do {
  1803. netif_dbg(efx, hw, efx->net_dev,
  1804. "waiting for SRAM reset (attempt %d)...\n", count);
  1805. /* SRAM reset is slow; expect around 16ms */
  1806. schedule_timeout_uninterruptible(HZ / 50);
  1807. /* Check for reset complete */
  1808. efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
  1809. if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
  1810. netif_dbg(efx, hw, efx->net_dev,
  1811. "SRAM reset complete\n");
  1812. return 0;
  1813. }
  1814. } while (++count < 20); /* wait up to 0.4 sec */
  1815. netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n");
  1816. return -ETIMEDOUT;
  1817. }
  1818. static void falcon_spi_device_init(struct efx_nic *efx,
  1819. struct falcon_spi_device *spi_device,
  1820. unsigned int device_id, u32 device_type)
  1821. {
  1822. if (device_type != 0) {
  1823. spi_device->device_id = device_id;
  1824. spi_device->size =
  1825. 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
  1826. spi_device->addr_len =
  1827. SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
  1828. spi_device->munge_address = (spi_device->size == 1 << 9 &&
  1829. spi_device->addr_len == 1);
  1830. spi_device->erase_command =
  1831. SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
  1832. spi_device->erase_size =
  1833. 1 << SPI_DEV_TYPE_FIELD(device_type,
  1834. SPI_DEV_TYPE_ERASE_SIZE);
  1835. spi_device->block_size =
  1836. 1 << SPI_DEV_TYPE_FIELD(device_type,
  1837. SPI_DEV_TYPE_BLOCK_SIZE);
  1838. } else {
  1839. spi_device->size = 0;
  1840. }
  1841. }
  1842. /* Extract non-volatile configuration */
  1843. static int falcon_probe_nvconfig(struct efx_nic *efx)
  1844. {
  1845. struct falcon_nic_data *nic_data = efx->nic_data;
  1846. struct falcon_nvconfig *nvconfig;
  1847. int rc;
  1848. nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
  1849. if (!nvconfig)
  1850. return -ENOMEM;
  1851. rc = falcon_read_nvram(efx, nvconfig);
  1852. if (rc)
  1853. goto out;
  1854. efx->phy_type = nvconfig->board_v2.port0_phy_type;
  1855. efx->mdio.prtad = nvconfig->board_v2.port0_phy_addr;
  1856. if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
  1857. falcon_spi_device_init(
  1858. efx, &nic_data->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
  1859. le32_to_cpu(nvconfig->board_v3
  1860. .spi_device_type[FFE_AB_SPI_DEVICE_FLASH]));
  1861. falcon_spi_device_init(
  1862. efx, &nic_data->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
  1863. le32_to_cpu(nvconfig->board_v3
  1864. .spi_device_type[FFE_AB_SPI_DEVICE_EEPROM]));
  1865. }
  1866. /* Read the MAC addresses */
  1867. memcpy(efx->net_dev->perm_addr, nvconfig->mac_address[0], ETH_ALEN);
  1868. netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n",
  1869. efx->phy_type, efx->mdio.prtad);
  1870. rc = falcon_probe_board(efx,
  1871. le16_to_cpu(nvconfig->board_v2.board_revision));
  1872. out:
  1873. kfree(nvconfig);
  1874. return rc;
  1875. }
  1876. static void falcon_dimension_resources(struct efx_nic *efx)
  1877. {
  1878. efx->rx_dc_base = 0x20000;
  1879. efx->tx_dc_base = 0x26000;
  1880. }
  1881. /* Probe all SPI devices on the NIC */
  1882. static void falcon_probe_spi_devices(struct efx_nic *efx)
  1883. {
  1884. struct falcon_nic_data *nic_data = efx->nic_data;
  1885. efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
  1886. int boot_dev;
  1887. efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
  1888. efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
  1889. efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
  1890. if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
  1891. boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
  1892. FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
  1893. netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n",
  1894. boot_dev == FFE_AB_SPI_DEVICE_FLASH ?
  1895. "flash" : "EEPROM");
  1896. } else {
  1897. /* Disable VPD and set clock dividers to safe
  1898. * values for initial programming. */
  1899. boot_dev = -1;
  1900. netif_dbg(efx, probe, efx->net_dev,
  1901. "Booted from internal ASIC settings;"
  1902. " setting SPI config\n");
  1903. EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
  1904. /* 125 MHz / 7 ~= 20 MHz */
  1905. FRF_AB_EE_SF_CLOCK_DIV, 7,
  1906. /* 125 MHz / 63 ~= 2 MHz */
  1907. FRF_AB_EE_EE_CLOCK_DIV, 63);
  1908. efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
  1909. }
  1910. mutex_init(&nic_data->spi_lock);
  1911. if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
  1912. falcon_spi_device_init(efx, &nic_data->spi_flash,
  1913. FFE_AB_SPI_DEVICE_FLASH,
  1914. default_flash_type);
  1915. if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
  1916. falcon_spi_device_init(efx, &nic_data->spi_eeprom,
  1917. FFE_AB_SPI_DEVICE_EEPROM,
  1918. large_eeprom_type);
  1919. }
  1920. static unsigned int falcon_a1_mem_map_size(struct efx_nic *efx)
  1921. {
  1922. return 0x20000;
  1923. }
  1924. static unsigned int falcon_b0_mem_map_size(struct efx_nic *efx)
  1925. {
  1926. /* Map everything up to and including the RSS indirection table.
  1927. * The PCI core takes care of mapping the MSI-X tables.
  1928. */
  1929. return FR_BZ_RX_INDIRECTION_TBL +
  1930. FR_BZ_RX_INDIRECTION_TBL_STEP * FR_BZ_RX_INDIRECTION_TBL_ROWS;
  1931. }
  1932. static int falcon_probe_nic(struct efx_nic *efx)
  1933. {
  1934. struct falcon_nic_data *nic_data;
  1935. struct falcon_board *board;
  1936. int rc;
  1937. /* Allocate storage for hardware specific data */
  1938. nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
  1939. if (!nic_data)
  1940. return -ENOMEM;
  1941. efx->nic_data = nic_data;
  1942. rc = -ENODEV;
  1943. if (efx_farch_fpga_ver(efx) != 0) {
  1944. netif_err(efx, probe, efx->net_dev,
  1945. "Falcon FPGA not supported\n");
  1946. goto fail1;
  1947. }
  1948. if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
  1949. efx_oword_t nic_stat;
  1950. struct pci_dev *dev;
  1951. u8 pci_rev = efx->pci_dev->revision;
  1952. if ((pci_rev == 0xff) || (pci_rev == 0)) {
  1953. netif_err(efx, probe, efx->net_dev,
  1954. "Falcon rev A0 not supported\n");
  1955. goto fail1;
  1956. }
  1957. efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
  1958. if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
  1959. netif_err(efx, probe, efx->net_dev,
  1960. "Falcon rev A1 1G not supported\n");
  1961. goto fail1;
  1962. }
  1963. if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
  1964. netif_err(efx, probe, efx->net_dev,
  1965. "Falcon rev A1 PCI-X not supported\n");
  1966. goto fail1;
  1967. }
  1968. dev = pci_dev_get(efx->pci_dev);
  1969. while ((dev = pci_get_device(PCI_VENDOR_ID_SOLARFLARE,
  1970. PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1,
  1971. dev))) {
  1972. if (dev->bus == efx->pci_dev->bus &&
  1973. dev->devfn == efx->pci_dev->devfn + 1) {
  1974. nic_data->pci_dev2 = dev;
  1975. break;
  1976. }
  1977. }
  1978. if (!nic_data->pci_dev2) {
  1979. netif_err(efx, probe, efx->net_dev,
  1980. "failed to find secondary function\n");
  1981. rc = -ENODEV;
  1982. goto fail2;
  1983. }
  1984. }
  1985. /* Now we can reset the NIC */
  1986. rc = __falcon_reset_hw(efx, RESET_TYPE_ALL);
  1987. if (rc) {
  1988. netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
  1989. goto fail3;
  1990. }
  1991. /* Allocate memory for INT_KER */
  1992. rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
  1993. GFP_KERNEL);
  1994. if (rc)
  1995. goto fail4;
  1996. BUG_ON(efx->irq_status.dma_addr & 0x0f);
  1997. netif_dbg(efx, probe, efx->net_dev,
  1998. "INT_KER at %llx (virt %p phys %llx)\n",
  1999. (u64)efx->irq_status.dma_addr,
  2000. efx->irq_status.addr,
  2001. (u64)virt_to_phys(efx->irq_status.addr));
  2002. falcon_probe_spi_devices(efx);
  2003. /* Read in the non-volatile configuration */
  2004. rc = falcon_probe_nvconfig(efx);
  2005. if (rc) {
  2006. if (rc == -EINVAL)
  2007. netif_err(efx, probe, efx->net_dev, "NVRAM is invalid\n");
  2008. goto fail5;
  2009. }
  2010. efx->max_channels = (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ? 4 :
  2011. EFX_MAX_CHANNELS);
  2012. efx->timer_quantum_ns = 4968; /* 621 cycles */
  2013. /* Initialise I2C adapter */
  2014. board = falcon_board(efx);
  2015. board->i2c_adap.owner = THIS_MODULE;
  2016. board->i2c_data = falcon_i2c_bit_operations;
  2017. board->i2c_data.data = efx;
  2018. board->i2c_adap.algo_data = &board->i2c_data;
  2019. board->i2c_adap.dev.parent = &efx->pci_dev->dev;
  2020. strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
  2021. sizeof(board->i2c_adap.name));
  2022. rc = i2c_bit_add_bus(&board->i2c_adap);
  2023. if (rc)
  2024. goto fail5;
  2025. rc = falcon_board(efx)->type->init(efx);
  2026. if (rc) {
  2027. netif_err(efx, probe, efx->net_dev,
  2028. "failed to initialise board\n");
  2029. goto fail6;
  2030. }
  2031. nic_data->stats_disable_count = 1;
  2032. setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func,
  2033. (unsigned long)efx);
  2034. return 0;
  2035. fail6:
  2036. i2c_del_adapter(&board->i2c_adap);
  2037. memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
  2038. fail5:
  2039. efx_nic_free_buffer(efx, &efx->irq_status);
  2040. fail4:
  2041. fail3:
  2042. if (nic_data->pci_dev2) {
  2043. pci_dev_put(nic_data->pci_dev2);
  2044. nic_data->pci_dev2 = NULL;
  2045. }
  2046. fail2:
  2047. fail1:
  2048. kfree(efx->nic_data);
  2049. return rc;
  2050. }
  2051. static void falcon_init_rx_cfg(struct efx_nic *efx)
  2052. {
  2053. /* RX control FIFO thresholds (32 entries) */
  2054. const unsigned ctrl_xon_thr = 20;
  2055. const unsigned ctrl_xoff_thr = 25;
  2056. efx_oword_t reg;
  2057. efx_reado(efx, &reg, FR_AZ_RX_CFG);
  2058. if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
  2059. /* Data FIFO size is 5.5K. The RX DMA engine only
  2060. * supports scattering for user-mode queues, but will
  2061. * split DMA writes at intervals of RX_USR_BUF_SIZE
  2062. * (32-byte units) even for kernel-mode queues. We
  2063. * set it to be so large that that never happens.
  2064. */
  2065. EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
  2066. EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
  2067. (3 * 4096) >> 5);
  2068. EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, 512 >> 8);
  2069. EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, 2048 >> 8);
  2070. EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
  2071. EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
  2072. } else {
  2073. /* Data FIFO size is 80K; register fields moved */
  2074. EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
  2075. EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
  2076. EFX_RX_USR_BUF_SIZE >> 5);
  2077. /* Send XON and XOFF at ~3 * max MTU away from empty/full */
  2078. EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, 27648 >> 8);
  2079. EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, 54272 >> 8);
  2080. EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
  2081. EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
  2082. EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
  2083. /* Enable hash insertion. This is broken for the
  2084. * 'Falcon' hash so also select Toeplitz TCP/IPv4 and
  2085. * IPv4 hashes. */
  2086. EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1);
  2087. EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1);
  2088. EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1);
  2089. }
  2090. /* Always enable XOFF signal from RX FIFO. We enable
  2091. * or disable transmission of pause frames at the MAC. */
  2092. EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
  2093. efx_writeo(efx, &reg, FR_AZ_RX_CFG);
  2094. }
  2095. /* This call performs hardware-specific global initialisation, such as
  2096. * defining the descriptor cache sizes and number of RSS channels.
  2097. * It does not set up any buffers, descriptor rings or event queues.
  2098. */
  2099. static int falcon_init_nic(struct efx_nic *efx)
  2100. {
  2101. efx_oword_t temp;
  2102. int rc;
  2103. /* Use on-chip SRAM */
  2104. efx_reado(efx, &temp, FR_AB_NIC_STAT);
  2105. EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
  2106. efx_writeo(efx, &temp, FR_AB_NIC_STAT);
  2107. rc = falcon_reset_sram(efx);
  2108. if (rc)
  2109. return rc;
  2110. /* Clear the parity enables on the TX data fifos as
  2111. * they produce false parity errors because of timing issues
  2112. */
  2113. if (EFX_WORKAROUND_5129(efx)) {
  2114. efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
  2115. EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
  2116. efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
  2117. }
  2118. if (EFX_WORKAROUND_7244(efx)) {
  2119. efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
  2120. EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
  2121. EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
  2122. EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
  2123. EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
  2124. efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
  2125. }
  2126. /* XXX This is documented only for Falcon A0/A1 */
  2127. /* Setup RX. Wait for descriptor is broken and must
  2128. * be disabled. RXDP recovery shouldn't be needed, but is.
  2129. */
  2130. efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
  2131. EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
  2132. EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
  2133. if (EFX_WORKAROUND_5583(efx))
  2134. EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
  2135. efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
  2136. /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
  2137. * descriptors (which is bad).
  2138. */
  2139. efx_reado(efx, &temp, FR_AZ_TX_CFG);
  2140. EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
  2141. efx_writeo(efx, &temp, FR_AZ_TX_CFG);
  2142. falcon_init_rx_cfg(efx);
  2143. if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
  2144. /* Set hash key for IPv4 */
  2145. memcpy(&temp, efx->rx_hash_key, sizeof(temp));
  2146. efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
  2147. /* Set destination of both TX and RX Flush events */
  2148. EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
  2149. efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
  2150. }
  2151. efx_farch_init_common(efx);
  2152. return 0;
  2153. }
  2154. static void falcon_remove_nic(struct efx_nic *efx)
  2155. {
  2156. struct falcon_nic_data *nic_data = efx->nic_data;
  2157. struct falcon_board *board = falcon_board(efx);
  2158. board->type->fini(efx);
  2159. /* Remove I2C adapter and clear it in preparation for a retry */
  2160. i2c_del_adapter(&board->i2c_adap);
  2161. memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
  2162. efx_nic_free_buffer(efx, &efx->irq_status);
  2163. __falcon_reset_hw(efx, RESET_TYPE_ALL);
  2164. /* Release the second function after the reset */
  2165. if (nic_data->pci_dev2) {
  2166. pci_dev_put(nic_data->pci_dev2);
  2167. nic_data->pci_dev2 = NULL;
  2168. }
  2169. /* Tear down the private nic state */
  2170. kfree(efx->nic_data);
  2171. efx->nic_data = NULL;
  2172. }
  2173. static void falcon_update_nic_stats(struct efx_nic *efx)
  2174. {
  2175. struct falcon_nic_data *nic_data = efx->nic_data;
  2176. efx_oword_t cnt;
  2177. if (nic_data->stats_disable_count)
  2178. return;
  2179. efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
  2180. efx->n_rx_nodesc_drop_cnt +=
  2181. EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
  2182. if (nic_data->stats_pending && FALCON_XMAC_STATS_DMA_FLAG(efx)) {
  2183. nic_data->stats_pending = false;
  2184. rmb(); /* read the done flag before the stats */
  2185. falcon_update_stats_xmac(efx);
  2186. }
  2187. }
  2188. void falcon_start_nic_stats(struct efx_nic *efx)
  2189. {
  2190. struct falcon_nic_data *nic_data = efx->nic_data;
  2191. spin_lock_bh(&efx->stats_lock);
  2192. if (--nic_data->stats_disable_count == 0)
  2193. falcon_stats_request(efx);
  2194. spin_unlock_bh(&efx->stats_lock);
  2195. }
  2196. void falcon_stop_nic_stats(struct efx_nic *efx)
  2197. {
  2198. struct falcon_nic_data *nic_data = efx->nic_data;
  2199. int i;
  2200. might_sleep();
  2201. spin_lock_bh(&efx->stats_lock);
  2202. ++nic_data->stats_disable_count;
  2203. spin_unlock_bh(&efx->stats_lock);
  2204. del_timer_sync(&nic_data->stats_timer);
  2205. /* Wait enough time for the most recent transfer to
  2206. * complete. */
  2207. for (i = 0; i < 4 && nic_data->stats_pending; i++) {
  2208. if (FALCON_XMAC_STATS_DMA_FLAG(efx))
  2209. break;
  2210. msleep(1);
  2211. }
  2212. spin_lock_bh(&efx->stats_lock);
  2213. falcon_stats_complete(efx);
  2214. spin_unlock_bh(&efx->stats_lock);
  2215. }
  2216. static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
  2217. {
  2218. falcon_board(efx)->type->set_id_led(efx, mode);
  2219. }
  2220. /**************************************************************************
  2221. *
  2222. * Wake on LAN
  2223. *
  2224. **************************************************************************
  2225. */
  2226. static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
  2227. {
  2228. wol->supported = 0;
  2229. wol->wolopts = 0;
  2230. memset(&wol->sopass, 0, sizeof(wol->sopass));
  2231. }
  2232. static int falcon_set_wol(struct efx_nic *efx, u32 type)
  2233. {
  2234. if (type != 0)
  2235. return -EINVAL;
  2236. return 0;
  2237. }
  2238. /**************************************************************************
  2239. *
  2240. * Revision-dependent attributes used by efx.c and nic.c
  2241. *
  2242. **************************************************************************
  2243. */
  2244. const struct efx_nic_type falcon_a1_nic_type = {
  2245. .mem_map_size = falcon_a1_mem_map_size,
  2246. .probe = falcon_probe_nic,
  2247. .remove = falcon_remove_nic,
  2248. .init = falcon_init_nic,
  2249. .dimension_resources = falcon_dimension_resources,
  2250. .fini = falcon_irq_ack_a1,
  2251. .monitor = falcon_monitor,
  2252. .map_reset_reason = falcon_map_reset_reason,
  2253. .map_reset_flags = falcon_map_reset_flags,
  2254. .reset = falcon_reset_hw,
  2255. .probe_port = falcon_probe_port,
  2256. .remove_port = falcon_remove_port,
  2257. .handle_global_event = falcon_handle_global_event,
  2258. .fini_dmaq = efx_farch_fini_dmaq,
  2259. .prepare_flush = falcon_prepare_flush,
  2260. .finish_flush = efx_port_dummy_op_void,
  2261. .update_stats = falcon_update_nic_stats,
  2262. .start_stats = falcon_start_nic_stats,
  2263. .stop_stats = falcon_stop_nic_stats,
  2264. .set_id_led = falcon_set_id_led,
  2265. .push_irq_moderation = falcon_push_irq_moderation,
  2266. .reconfigure_port = falcon_reconfigure_port,
  2267. .prepare_enable_fc_tx = falcon_a1_prepare_enable_fc_tx,
  2268. .reconfigure_mac = falcon_reconfigure_xmac,
  2269. .check_mac_fault = falcon_xmac_check_fault,
  2270. .get_wol = falcon_get_wol,
  2271. .set_wol = falcon_set_wol,
  2272. .resume_wol = efx_port_dummy_op_void,
  2273. .test_nvram = falcon_test_nvram,
  2274. .irq_enable_master = efx_farch_irq_enable_master,
  2275. .irq_test_generate = efx_farch_irq_test_generate,
  2276. .irq_disable_non_ev = efx_farch_irq_disable_master,
  2277. .irq_handle_msi = efx_farch_msi_interrupt,
  2278. .irq_handle_legacy = falcon_legacy_interrupt_a1,
  2279. .tx_probe = efx_farch_tx_probe,
  2280. .tx_init = efx_farch_tx_init,
  2281. .tx_remove = efx_farch_tx_remove,
  2282. .tx_write = efx_farch_tx_write,
  2283. .rx_push_indir_table = efx_farch_rx_push_indir_table,
  2284. .rx_probe = efx_farch_rx_probe,
  2285. .rx_init = efx_farch_rx_init,
  2286. .rx_remove = efx_farch_rx_remove,
  2287. .rx_write = efx_farch_rx_write,
  2288. .rx_defer_refill = efx_farch_rx_defer_refill,
  2289. .ev_probe = efx_farch_ev_probe,
  2290. .ev_init = efx_farch_ev_init,
  2291. .ev_fini = efx_farch_ev_fini,
  2292. .ev_remove = efx_farch_ev_remove,
  2293. .ev_process = efx_farch_ev_process,
  2294. .ev_read_ack = efx_farch_ev_read_ack,
  2295. .ev_test_generate = efx_farch_ev_test_generate,
  2296. /* We don't expose the filter table on Falcon A1 as it is not
  2297. * mapped into function 0, but these implementations still
  2298. * work with a degenerate case of all tables set to size 0.
  2299. */
  2300. .filter_table_probe = efx_farch_filter_table_probe,
  2301. .filter_table_restore = efx_farch_filter_table_restore,
  2302. .filter_table_remove = efx_farch_filter_table_remove,
  2303. .filter_insert = efx_farch_filter_insert,
  2304. .filter_remove_safe = efx_farch_filter_remove_safe,
  2305. .filter_get_safe = efx_farch_filter_get_safe,
  2306. .filter_clear_rx = efx_farch_filter_clear_rx,
  2307. .filter_count_rx_used = efx_farch_filter_count_rx_used,
  2308. .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
  2309. .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
  2310. #ifdef CONFIG_SFC_MTD
  2311. .mtd_probe = falcon_mtd_probe,
  2312. .mtd_rename = falcon_mtd_rename,
  2313. .mtd_read = falcon_mtd_read,
  2314. .mtd_erase = falcon_mtd_erase,
  2315. .mtd_write = falcon_mtd_write,
  2316. .mtd_sync = falcon_mtd_sync,
  2317. #endif
  2318. .revision = EFX_REV_FALCON_A1,
  2319. .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
  2320. .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
  2321. .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
  2322. .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
  2323. .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
  2324. .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
  2325. .rx_buffer_padding = 0x24,
  2326. .can_rx_scatter = false,
  2327. .max_interrupt_mode = EFX_INT_MODE_MSI,
  2328. .timer_period_max = 1 << FRF_AB_TC_TIMER_VAL_WIDTH,
  2329. .offload_features = NETIF_F_IP_CSUM,
  2330. .mcdi_max_ver = -1,
  2331. };
  2332. const struct efx_nic_type falcon_b0_nic_type = {
  2333. .mem_map_size = falcon_b0_mem_map_size,
  2334. .probe = falcon_probe_nic,
  2335. .remove = falcon_remove_nic,
  2336. .init = falcon_init_nic,
  2337. .dimension_resources = falcon_dimension_resources,
  2338. .fini = efx_port_dummy_op_void,
  2339. .monitor = falcon_monitor,
  2340. .map_reset_reason = falcon_map_reset_reason,
  2341. .map_reset_flags = falcon_map_reset_flags,
  2342. .reset = falcon_reset_hw,
  2343. .probe_port = falcon_probe_port,
  2344. .remove_port = falcon_remove_port,
  2345. .handle_global_event = falcon_handle_global_event,
  2346. .fini_dmaq = efx_farch_fini_dmaq,
  2347. .prepare_flush = falcon_prepare_flush,
  2348. .finish_flush = efx_port_dummy_op_void,
  2349. .update_stats = falcon_update_nic_stats,
  2350. .start_stats = falcon_start_nic_stats,
  2351. .stop_stats = falcon_stop_nic_stats,
  2352. .set_id_led = falcon_set_id_led,
  2353. .push_irq_moderation = falcon_push_irq_moderation,
  2354. .reconfigure_port = falcon_reconfigure_port,
  2355. .prepare_enable_fc_tx = falcon_b0_prepare_enable_fc_tx,
  2356. .reconfigure_mac = falcon_reconfigure_xmac,
  2357. .check_mac_fault = falcon_xmac_check_fault,
  2358. .get_wol = falcon_get_wol,
  2359. .set_wol = falcon_set_wol,
  2360. .resume_wol = efx_port_dummy_op_void,
  2361. .test_chip = falcon_b0_test_chip,
  2362. .test_nvram = falcon_test_nvram,
  2363. .irq_enable_master = efx_farch_irq_enable_master,
  2364. .irq_test_generate = efx_farch_irq_test_generate,
  2365. .irq_disable_non_ev = efx_farch_irq_disable_master,
  2366. .irq_handle_msi = efx_farch_msi_interrupt,
  2367. .irq_handle_legacy = efx_farch_legacy_interrupt,
  2368. .tx_probe = efx_farch_tx_probe,
  2369. .tx_init = efx_farch_tx_init,
  2370. .tx_remove = efx_farch_tx_remove,
  2371. .tx_write = efx_farch_tx_write,
  2372. .rx_push_indir_table = efx_farch_rx_push_indir_table,
  2373. .rx_probe = efx_farch_rx_probe,
  2374. .rx_init = efx_farch_rx_init,
  2375. .rx_remove = efx_farch_rx_remove,
  2376. .rx_write = efx_farch_rx_write,
  2377. .rx_defer_refill = efx_farch_rx_defer_refill,
  2378. .ev_probe = efx_farch_ev_probe,
  2379. .ev_init = efx_farch_ev_init,
  2380. .ev_fini = efx_farch_ev_fini,
  2381. .ev_remove = efx_farch_ev_remove,
  2382. .ev_process = efx_farch_ev_process,
  2383. .ev_read_ack = efx_farch_ev_read_ack,
  2384. .ev_test_generate = efx_farch_ev_test_generate,
  2385. .filter_table_probe = efx_farch_filter_table_probe,
  2386. .filter_table_restore = efx_farch_filter_table_restore,
  2387. .filter_table_remove = efx_farch_filter_table_remove,
  2388. .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter,
  2389. .filter_insert = efx_farch_filter_insert,
  2390. .filter_remove_safe = efx_farch_filter_remove_safe,
  2391. .filter_get_safe = efx_farch_filter_get_safe,
  2392. .filter_clear_rx = efx_farch_filter_clear_rx,
  2393. .filter_count_rx_used = efx_farch_filter_count_rx_used,
  2394. .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit,
  2395. .filter_get_rx_ids = efx_farch_filter_get_rx_ids,
  2396. #ifdef CONFIG_RFS_ACCEL
  2397. .filter_rfs_insert = efx_farch_filter_rfs_insert,
  2398. .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one,
  2399. #endif
  2400. #ifdef CONFIG_SFC_MTD
  2401. .mtd_probe = falcon_mtd_probe,
  2402. .mtd_rename = falcon_mtd_rename,
  2403. .mtd_read = falcon_mtd_read,
  2404. .mtd_erase = falcon_mtd_erase,
  2405. .mtd_write = falcon_mtd_write,
  2406. .mtd_sync = falcon_mtd_sync,
  2407. #endif
  2408. .revision = EFX_REV_FALCON_B0,
  2409. .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
  2410. .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
  2411. .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
  2412. .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
  2413. .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
  2414. .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
  2415. .rx_buffer_hash_size = 0x10,
  2416. .rx_buffer_padding = 0,
  2417. .can_rx_scatter = true,
  2418. .max_interrupt_mode = EFX_INT_MODE_MSIX,
  2419. .timer_period_max = 1 << FRF_AB_TC_TIMER_VAL_WIDTH,
  2420. .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE,
  2421. .mcdi_max_ver = -1,
  2422. .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS,
  2423. };