ehci-sched.c 60 KB

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  1. /*
  2. * Copyright (c) 2001-2004 by David Brownell
  3. * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2 of the License, or (at your
  8. * option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  13. * for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software Foundation,
  17. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. /* this file is part of ehci-hcd.c */
  20. /*-------------------------------------------------------------------------*/
  21. /*
  22. * EHCI scheduled transaction support: interrupt, iso, split iso
  23. * These are called "periodic" transactions in the EHCI spec.
  24. *
  25. * Note that for interrupt transfers, the QH/QTD manipulation is shared
  26. * with the "asynchronous" transaction support (control/bulk transfers).
  27. * The only real difference is in how interrupt transfers are scheduled.
  28. *
  29. * For ISO, we make an "iso_stream" head to serve the same role as a QH.
  30. * It keeps track of every ITD (or SITD) that's linked, and holds enough
  31. * pre-calculated schedule data to make appending to the queue be quick.
  32. */
  33. static int ehci_get_frame (struct usb_hcd *hcd);
  34. /*
  35. * periodic_next_shadow - return "next" pointer on shadow list
  36. * @periodic: host pointer to qh/itd/sitd
  37. * @tag: hardware tag for type of this record
  38. */
  39. static union ehci_shadow *
  40. periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic,
  41. __hc32 tag)
  42. {
  43. switch (hc32_to_cpu(ehci, tag)) {
  44. case Q_TYPE_QH:
  45. return &periodic->qh->qh_next;
  46. case Q_TYPE_FSTN:
  47. return &periodic->fstn->fstn_next;
  48. case Q_TYPE_ITD:
  49. return &periodic->itd->itd_next;
  50. // case Q_TYPE_SITD:
  51. default:
  52. return &periodic->sitd->sitd_next;
  53. }
  54. }
  55. static __hc32 *
  56. shadow_next_periodic(struct ehci_hcd *ehci, union ehci_shadow *periodic,
  57. __hc32 tag)
  58. {
  59. switch (hc32_to_cpu(ehci, tag)) {
  60. /* our ehci_shadow.qh is actually software part */
  61. case Q_TYPE_QH:
  62. return &periodic->qh->hw->hw_next;
  63. /* others are hw parts */
  64. default:
  65. return periodic->hw_next;
  66. }
  67. }
  68. /* caller must hold ehci->lock */
  69. static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
  70. {
  71. union ehci_shadow *prev_p = &ehci->pshadow[frame];
  72. __hc32 *hw_p = &ehci->periodic[frame];
  73. union ehci_shadow here = *prev_p;
  74. /* find predecessor of "ptr"; hw and shadow lists are in sync */
  75. while (here.ptr && here.ptr != ptr) {
  76. prev_p = periodic_next_shadow(ehci, prev_p,
  77. Q_NEXT_TYPE(ehci, *hw_p));
  78. hw_p = shadow_next_periodic(ehci, &here,
  79. Q_NEXT_TYPE(ehci, *hw_p));
  80. here = *prev_p;
  81. }
  82. /* an interrupt entry (at list end) could have been shared */
  83. if (!here.ptr)
  84. return;
  85. /* update shadow and hardware lists ... the old "next" pointers
  86. * from ptr may still be in use, the caller updates them.
  87. */
  88. *prev_p = *periodic_next_shadow(ehci, &here,
  89. Q_NEXT_TYPE(ehci, *hw_p));
  90. if (!ehci->use_dummy_qh ||
  91. *shadow_next_periodic(ehci, &here, Q_NEXT_TYPE(ehci, *hw_p))
  92. != EHCI_LIST_END(ehci))
  93. *hw_p = *shadow_next_periodic(ehci, &here,
  94. Q_NEXT_TYPE(ehci, *hw_p));
  95. else
  96. *hw_p = ehci->dummy->qh_dma;
  97. }
  98. /* how many of the uframe's 125 usecs are allocated? */
  99. static unsigned short
  100. periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
  101. {
  102. __hc32 *hw_p = &ehci->periodic [frame];
  103. union ehci_shadow *q = &ehci->pshadow [frame];
  104. unsigned usecs = 0;
  105. struct ehci_qh_hw *hw;
  106. while (q->ptr) {
  107. switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
  108. case Q_TYPE_QH:
  109. hw = q->qh->hw;
  110. /* is it in the S-mask? */
  111. if (hw->hw_info2 & cpu_to_hc32(ehci, 1 << uframe))
  112. usecs += q->qh->usecs;
  113. /* ... or C-mask? */
  114. if (hw->hw_info2 & cpu_to_hc32(ehci,
  115. 1 << (8 + uframe)))
  116. usecs += q->qh->c_usecs;
  117. hw_p = &hw->hw_next;
  118. q = &q->qh->qh_next;
  119. break;
  120. // case Q_TYPE_FSTN:
  121. default:
  122. /* for "save place" FSTNs, count the relevant INTR
  123. * bandwidth from the previous frame
  124. */
  125. if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) {
  126. ehci_dbg (ehci, "ignoring FSTN cost ...\n");
  127. }
  128. hw_p = &q->fstn->hw_next;
  129. q = &q->fstn->fstn_next;
  130. break;
  131. case Q_TYPE_ITD:
  132. if (q->itd->hw_transaction[uframe])
  133. usecs += q->itd->stream->usecs;
  134. hw_p = &q->itd->hw_next;
  135. q = &q->itd->itd_next;
  136. break;
  137. case Q_TYPE_SITD:
  138. /* is it in the S-mask? (count SPLIT, DATA) */
  139. if (q->sitd->hw_uframe & cpu_to_hc32(ehci,
  140. 1 << uframe)) {
  141. if (q->sitd->hw_fullspeed_ep &
  142. cpu_to_hc32(ehci, 1<<31))
  143. usecs += q->sitd->stream->usecs;
  144. else /* worst case for OUT start-split */
  145. usecs += HS_USECS_ISO (188);
  146. }
  147. /* ... C-mask? (count CSPLIT, DATA) */
  148. if (q->sitd->hw_uframe &
  149. cpu_to_hc32(ehci, 1 << (8 + uframe))) {
  150. /* worst case for IN complete-split */
  151. usecs += q->sitd->stream->c_usecs;
  152. }
  153. hw_p = &q->sitd->hw_next;
  154. q = &q->sitd->sitd_next;
  155. break;
  156. }
  157. }
  158. #if defined(DEBUG) || defined(CONFIG_DYNAMIC_DEBUG)
  159. if (usecs > ehci->uframe_periodic_max)
  160. ehci_err (ehci, "uframe %d sched overrun: %d usecs\n",
  161. frame * 8 + uframe, usecs);
  162. #endif
  163. return usecs;
  164. }
  165. /*-------------------------------------------------------------------------*/
  166. static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
  167. {
  168. if (!dev1->tt || !dev2->tt)
  169. return 0;
  170. if (dev1->tt != dev2->tt)
  171. return 0;
  172. if (dev1->tt->multi)
  173. return dev1->ttport == dev2->ttport;
  174. else
  175. return 1;
  176. }
  177. #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
  178. /* Which uframe does the low/fullspeed transfer start in?
  179. *
  180. * The parameter is the mask of ssplits in "H-frame" terms
  181. * and this returns the transfer start uframe in "B-frame" terms,
  182. * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
  183. * will cause a transfer in "B-frame" uframe 0. "B-frames" lag
  184. * "H-frames" by 1 uframe. See the EHCI spec sec 4.5 and figure 4.7.
  185. */
  186. static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
  187. {
  188. unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask);
  189. if (!smask) {
  190. ehci_err(ehci, "invalid empty smask!\n");
  191. /* uframe 7 can't have bw so this will indicate failure */
  192. return 7;
  193. }
  194. return ffs(smask) - 1;
  195. }
  196. static const unsigned char
  197. max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 };
  198. /* carryover low/fullspeed bandwidth that crosses uframe boundries */
  199. static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8])
  200. {
  201. int i;
  202. for (i=0; i<7; i++) {
  203. if (max_tt_usecs[i] < tt_usecs[i]) {
  204. tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i];
  205. tt_usecs[i] = max_tt_usecs[i];
  206. }
  207. }
  208. }
  209. /* How many of the tt's periodic downstream 1000 usecs are allocated?
  210. *
  211. * While this measures the bandwidth in terms of usecs/uframe,
  212. * the low/fullspeed bus has no notion of uframes, so any particular
  213. * low/fullspeed transfer can "carry over" from one uframe to the next,
  214. * since the TT just performs downstream transfers in sequence.
  215. *
  216. * For example two separate 100 usec transfers can start in the same uframe,
  217. * and the second one would "carry over" 75 usecs into the next uframe.
  218. */
  219. static void
  220. periodic_tt_usecs (
  221. struct ehci_hcd *ehci,
  222. struct usb_device *dev,
  223. unsigned frame,
  224. unsigned short tt_usecs[8]
  225. )
  226. {
  227. __hc32 *hw_p = &ehci->periodic [frame];
  228. union ehci_shadow *q = &ehci->pshadow [frame];
  229. unsigned char uf;
  230. memset(tt_usecs, 0, 16);
  231. while (q->ptr) {
  232. switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
  233. case Q_TYPE_ITD:
  234. hw_p = &q->itd->hw_next;
  235. q = &q->itd->itd_next;
  236. continue;
  237. case Q_TYPE_QH:
  238. if (same_tt(dev, q->qh->dev)) {
  239. uf = tt_start_uframe(ehci, q->qh->hw->hw_info2);
  240. tt_usecs[uf] += q->qh->tt_usecs;
  241. }
  242. hw_p = &q->qh->hw->hw_next;
  243. q = &q->qh->qh_next;
  244. continue;
  245. case Q_TYPE_SITD:
  246. if (same_tt(dev, q->sitd->urb->dev)) {
  247. uf = tt_start_uframe(ehci, q->sitd->hw_uframe);
  248. tt_usecs[uf] += q->sitd->stream->tt_usecs;
  249. }
  250. hw_p = &q->sitd->hw_next;
  251. q = &q->sitd->sitd_next;
  252. continue;
  253. // case Q_TYPE_FSTN:
  254. default:
  255. ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n",
  256. frame);
  257. hw_p = &q->fstn->hw_next;
  258. q = &q->fstn->fstn_next;
  259. }
  260. }
  261. carryover_tt_bandwidth(tt_usecs);
  262. if (max_tt_usecs[7] < tt_usecs[7])
  263. ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n",
  264. frame, tt_usecs[7] - max_tt_usecs[7]);
  265. }
  266. /*
  267. * Return true if the device's tt's downstream bus is available for a
  268. * periodic transfer of the specified length (usecs), starting at the
  269. * specified frame/uframe. Note that (as summarized in section 11.19
  270. * of the usb 2.0 spec) TTs can buffer multiple transactions for each
  271. * uframe.
  272. *
  273. * The uframe parameter is when the fullspeed/lowspeed transfer
  274. * should be executed in "B-frame" terms, which is the same as the
  275. * highspeed ssplit's uframe (which is in "H-frame" terms). For example
  276. * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0.
  277. * See the EHCI spec sec 4.5 and fig 4.7.
  278. *
  279. * This checks if the full/lowspeed bus, at the specified starting uframe,
  280. * has the specified bandwidth available, according to rules listed
  281. * in USB 2.0 spec section 11.18.1 fig 11-60.
  282. *
  283. * This does not check if the transfer would exceed the max ssplit
  284. * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4,
  285. * since proper scheduling limits ssplits to less than 16 per uframe.
  286. */
  287. static int tt_available (
  288. struct ehci_hcd *ehci,
  289. unsigned period,
  290. struct usb_device *dev,
  291. unsigned frame,
  292. unsigned uframe,
  293. u16 usecs
  294. )
  295. {
  296. if ((period == 0) || (uframe >= 7)) /* error */
  297. return 0;
  298. for (; frame < ehci->periodic_size; frame += period) {
  299. unsigned short tt_usecs[8];
  300. periodic_tt_usecs (ehci, dev, frame, tt_usecs);
  301. if (max_tt_usecs[uframe] <= tt_usecs[uframe])
  302. return 0;
  303. /* special case for isoc transfers larger than 125us:
  304. * the first and each subsequent fully used uframe
  305. * must be empty, so as to not illegally delay
  306. * already scheduled transactions
  307. */
  308. if (125 < usecs) {
  309. int ufs = (usecs / 125);
  310. int i;
  311. for (i = uframe; i < (uframe + ufs) && i < 8; i++)
  312. if (0 < tt_usecs[i])
  313. return 0;
  314. }
  315. tt_usecs[uframe] += usecs;
  316. carryover_tt_bandwidth(tt_usecs);
  317. /* fail if the carryover pushed bw past the last uframe's limit */
  318. if (max_tt_usecs[7] < tt_usecs[7])
  319. return 0;
  320. }
  321. return 1;
  322. }
  323. #else
  324. /* return true iff the device's transaction translator is available
  325. * for a periodic transfer starting at the specified frame, using
  326. * all the uframes in the mask.
  327. */
  328. static int tt_no_collision (
  329. struct ehci_hcd *ehci,
  330. unsigned period,
  331. struct usb_device *dev,
  332. unsigned frame,
  333. u32 uf_mask
  334. )
  335. {
  336. if (period == 0) /* error */
  337. return 0;
  338. /* note bandwidth wastage: split never follows csplit
  339. * (different dev or endpoint) until the next uframe.
  340. * calling convention doesn't make that distinction.
  341. */
  342. for (; frame < ehci->periodic_size; frame += period) {
  343. union ehci_shadow here;
  344. __hc32 type;
  345. struct ehci_qh_hw *hw;
  346. here = ehci->pshadow [frame];
  347. type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]);
  348. while (here.ptr) {
  349. switch (hc32_to_cpu(ehci, type)) {
  350. case Q_TYPE_ITD:
  351. type = Q_NEXT_TYPE(ehci, here.itd->hw_next);
  352. here = here.itd->itd_next;
  353. continue;
  354. case Q_TYPE_QH:
  355. hw = here.qh->hw;
  356. if (same_tt (dev, here.qh->dev)) {
  357. u32 mask;
  358. mask = hc32_to_cpu(ehci,
  359. hw->hw_info2);
  360. /* "knows" no gap is needed */
  361. mask |= mask >> 8;
  362. if (mask & uf_mask)
  363. break;
  364. }
  365. type = Q_NEXT_TYPE(ehci, hw->hw_next);
  366. here = here.qh->qh_next;
  367. continue;
  368. case Q_TYPE_SITD:
  369. if (same_tt (dev, here.sitd->urb->dev)) {
  370. u16 mask;
  371. mask = hc32_to_cpu(ehci, here.sitd
  372. ->hw_uframe);
  373. /* FIXME assumes no gap for IN! */
  374. mask |= mask >> 8;
  375. if (mask & uf_mask)
  376. break;
  377. }
  378. type = Q_NEXT_TYPE(ehci, here.sitd->hw_next);
  379. here = here.sitd->sitd_next;
  380. continue;
  381. // case Q_TYPE_FSTN:
  382. default:
  383. ehci_dbg (ehci,
  384. "periodic frame %d bogus type %d\n",
  385. frame, type);
  386. }
  387. /* collision or error */
  388. return 0;
  389. }
  390. }
  391. /* no collision */
  392. return 1;
  393. }
  394. #endif /* CONFIG_USB_EHCI_TT_NEWSCHED */
  395. /*-------------------------------------------------------------------------*/
  396. static void enable_periodic(struct ehci_hcd *ehci)
  397. {
  398. if (ehci->periodic_count++)
  399. return;
  400. /* Stop waiting to turn off the periodic schedule */
  401. ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_DISABLE_PERIODIC);
  402. /* Don't start the schedule until PSS is 0 */
  403. ehci_poll_PSS(ehci);
  404. turn_on_io_watchdog(ehci);
  405. }
  406. static void disable_periodic(struct ehci_hcd *ehci)
  407. {
  408. if (--ehci->periodic_count)
  409. return;
  410. /* Don't turn off the schedule until PSS is 1 */
  411. ehci_poll_PSS(ehci);
  412. }
  413. /*-------------------------------------------------------------------------*/
  414. /* periodic schedule slots have iso tds (normal or split) first, then a
  415. * sparse tree for active interrupt transfers.
  416. *
  417. * this just links in a qh; caller guarantees uframe masks are set right.
  418. * no FSTN support (yet; ehci 0.96+)
  419. */
  420. static void qh_link_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh)
  421. {
  422. unsigned i;
  423. unsigned period = qh->period;
  424. dev_dbg (&qh->dev->dev,
  425. "link qh%d-%04x/%p start %d [%d/%d us]\n",
  426. period, hc32_to_cpup(ehci, &qh->hw->hw_info2)
  427. & (QH_CMASK | QH_SMASK),
  428. qh, qh->start, qh->usecs, qh->c_usecs);
  429. /* high bandwidth, or otherwise every microframe */
  430. if (period == 0)
  431. period = 1;
  432. for (i = qh->start; i < ehci->periodic_size; i += period) {
  433. union ehci_shadow *prev = &ehci->pshadow[i];
  434. __hc32 *hw_p = &ehci->periodic[i];
  435. union ehci_shadow here = *prev;
  436. __hc32 type = 0;
  437. /* skip the iso nodes at list head */
  438. while (here.ptr) {
  439. type = Q_NEXT_TYPE(ehci, *hw_p);
  440. if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
  441. break;
  442. prev = periodic_next_shadow(ehci, prev, type);
  443. hw_p = shadow_next_periodic(ehci, &here, type);
  444. here = *prev;
  445. }
  446. /* sorting each branch by period (slow-->fast)
  447. * enables sharing interior tree nodes
  448. */
  449. while (here.ptr && qh != here.qh) {
  450. if (qh->period > here.qh->period)
  451. break;
  452. prev = &here.qh->qh_next;
  453. hw_p = &here.qh->hw->hw_next;
  454. here = *prev;
  455. }
  456. /* link in this qh, unless some earlier pass did that */
  457. if (qh != here.qh) {
  458. qh->qh_next = here;
  459. if (here.qh)
  460. qh->hw->hw_next = *hw_p;
  461. wmb ();
  462. prev->qh = qh;
  463. *hw_p = QH_NEXT (ehci, qh->qh_dma);
  464. }
  465. }
  466. qh->qh_state = QH_STATE_LINKED;
  467. qh->xacterrs = 0;
  468. qh->exception = 0;
  469. /* update per-qh bandwidth for usbfs */
  470. ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
  471. ? ((qh->usecs + qh->c_usecs) / qh->period)
  472. : (qh->usecs * 8);
  473. list_add(&qh->intr_node, &ehci->intr_qh_list);
  474. /* maybe enable periodic schedule processing */
  475. ++ehci->intr_count;
  476. enable_periodic(ehci);
  477. }
  478. static void qh_unlink_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh)
  479. {
  480. unsigned i;
  481. unsigned period;
  482. /*
  483. * If qh is for a low/full-speed device, simply unlinking it
  484. * could interfere with an ongoing split transaction. To unlink
  485. * it safely would require setting the QH_INACTIVATE bit and
  486. * waiting at least one frame, as described in EHCI 4.12.2.5.
  487. *
  488. * We won't bother with any of this. Instead, we assume that the
  489. * only reason for unlinking an interrupt QH while the current URB
  490. * is still active is to dequeue all the URBs (flush the whole
  491. * endpoint queue).
  492. *
  493. * If rebalancing the periodic schedule is ever implemented, this
  494. * approach will no longer be valid.
  495. */
  496. /* high bandwidth, or otherwise part of every microframe */
  497. if ((period = qh->period) == 0)
  498. period = 1;
  499. for (i = qh->start; i < ehci->periodic_size; i += period)
  500. periodic_unlink (ehci, i, qh);
  501. /* update per-qh bandwidth for usbfs */
  502. ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
  503. ? ((qh->usecs + qh->c_usecs) / qh->period)
  504. : (qh->usecs * 8);
  505. dev_dbg (&qh->dev->dev,
  506. "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
  507. qh->period,
  508. hc32_to_cpup(ehci, &qh->hw->hw_info2) & (QH_CMASK | QH_SMASK),
  509. qh, qh->start, qh->usecs, qh->c_usecs);
  510. /* qh->qh_next still "live" to HC */
  511. qh->qh_state = QH_STATE_UNLINK;
  512. qh->qh_next.ptr = NULL;
  513. if (ehci->qh_scan_next == qh)
  514. ehci->qh_scan_next = list_entry(qh->intr_node.next,
  515. struct ehci_qh, intr_node);
  516. list_del(&qh->intr_node);
  517. }
  518. static void cancel_unlink_wait_intr(struct ehci_hcd *ehci, struct ehci_qh *qh)
  519. {
  520. if (qh->qh_state != QH_STATE_LINKED ||
  521. list_empty(&qh->unlink_node))
  522. return;
  523. list_del_init(&qh->unlink_node);
  524. /*
  525. * TODO: disable the event of EHCI_HRTIMER_START_UNLINK_INTR for
  526. * avoiding unnecessary CPU wakeup
  527. */
  528. }
  529. static void start_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh)
  530. {
  531. /* If the QH isn't linked then there's nothing we can do. */
  532. if (qh->qh_state != QH_STATE_LINKED)
  533. return;
  534. /* if the qh is waiting for unlink, cancel it now */
  535. cancel_unlink_wait_intr(ehci, qh);
  536. qh_unlink_periodic (ehci, qh);
  537. /* Make sure the unlinks are visible before starting the timer */
  538. wmb();
  539. /*
  540. * The EHCI spec doesn't say how long it takes the controller to
  541. * stop accessing an unlinked interrupt QH. The timer delay is
  542. * 9 uframes; presumably that will be long enough.
  543. */
  544. qh->unlink_cycle = ehci->intr_unlink_cycle;
  545. /* New entries go at the end of the intr_unlink list */
  546. list_add_tail(&qh->unlink_node, &ehci->intr_unlink);
  547. if (ehci->intr_unlinking)
  548. ; /* Avoid recursive calls */
  549. else if (ehci->rh_state < EHCI_RH_RUNNING)
  550. ehci_handle_intr_unlinks(ehci);
  551. else if (ehci->intr_unlink.next == &qh->unlink_node) {
  552. ehci_enable_event(ehci, EHCI_HRTIMER_UNLINK_INTR, true);
  553. ++ehci->intr_unlink_cycle;
  554. }
  555. }
  556. /*
  557. * It is common only one intr URB is scheduled on one qh, and
  558. * given complete() is run in tasklet context, introduce a bit
  559. * delay to avoid unlink qh too early.
  560. */
  561. static void start_unlink_intr_wait(struct ehci_hcd *ehci,
  562. struct ehci_qh *qh)
  563. {
  564. qh->unlink_cycle = ehci->intr_unlink_wait_cycle;
  565. /* New entries go at the end of the intr_unlink_wait list */
  566. list_add_tail(&qh->unlink_node, &ehci->intr_unlink_wait);
  567. if (ehci->rh_state < EHCI_RH_RUNNING)
  568. ehci_handle_start_intr_unlinks(ehci);
  569. else if (ehci->intr_unlink_wait.next == &qh->unlink_node) {
  570. ehci_enable_event(ehci, EHCI_HRTIMER_START_UNLINK_INTR, true);
  571. ++ehci->intr_unlink_wait_cycle;
  572. }
  573. }
  574. static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh)
  575. {
  576. struct ehci_qh_hw *hw = qh->hw;
  577. int rc;
  578. qh->qh_state = QH_STATE_IDLE;
  579. hw->hw_next = EHCI_LIST_END(ehci);
  580. if (!list_empty(&qh->qtd_list))
  581. qh_completions(ehci, qh);
  582. /* reschedule QH iff another request is queued */
  583. if (!list_empty(&qh->qtd_list) && ehci->rh_state == EHCI_RH_RUNNING) {
  584. rc = qh_schedule(ehci, qh);
  585. if (rc == 0) {
  586. qh_refresh(ehci, qh);
  587. qh_link_periodic(ehci, qh);
  588. }
  589. /* An error here likely indicates handshake failure
  590. * or no space left in the schedule. Neither fault
  591. * should happen often ...
  592. *
  593. * FIXME kill the now-dysfunctional queued urbs
  594. */
  595. else {
  596. ehci_err(ehci, "can't reschedule qh %p, err %d\n",
  597. qh, rc);
  598. }
  599. }
  600. /* maybe turn off periodic schedule */
  601. --ehci->intr_count;
  602. disable_periodic(ehci);
  603. }
  604. /*-------------------------------------------------------------------------*/
  605. static int check_period (
  606. struct ehci_hcd *ehci,
  607. unsigned frame,
  608. unsigned uframe,
  609. unsigned period,
  610. unsigned usecs
  611. ) {
  612. int claimed;
  613. /* complete split running into next frame?
  614. * given FSTN support, we could sometimes check...
  615. */
  616. if (uframe >= 8)
  617. return 0;
  618. /* convert "usecs we need" to "max already claimed" */
  619. usecs = ehci->uframe_periodic_max - usecs;
  620. /* we "know" 2 and 4 uframe intervals were rejected; so
  621. * for period 0, check _every_ microframe in the schedule.
  622. */
  623. if (unlikely (period == 0)) {
  624. do {
  625. for (uframe = 0; uframe < 7; uframe++) {
  626. claimed = periodic_usecs (ehci, frame, uframe);
  627. if (claimed > usecs)
  628. return 0;
  629. }
  630. } while ((frame += 1) < ehci->periodic_size);
  631. /* just check the specified uframe, at that period */
  632. } else {
  633. do {
  634. claimed = periodic_usecs (ehci, frame, uframe);
  635. if (claimed > usecs)
  636. return 0;
  637. } while ((frame += period) < ehci->periodic_size);
  638. }
  639. // success!
  640. return 1;
  641. }
  642. static int check_intr_schedule (
  643. struct ehci_hcd *ehci,
  644. unsigned frame,
  645. unsigned uframe,
  646. const struct ehci_qh *qh,
  647. __hc32 *c_maskp
  648. )
  649. {
  650. int retval = -ENOSPC;
  651. u8 mask = 0;
  652. if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
  653. goto done;
  654. if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
  655. goto done;
  656. if (!qh->c_usecs) {
  657. retval = 0;
  658. *c_maskp = 0;
  659. goto done;
  660. }
  661. #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
  662. if (tt_available (ehci, qh->period, qh->dev, frame, uframe,
  663. qh->tt_usecs)) {
  664. unsigned i;
  665. /* TODO : this may need FSTN for SSPLIT in uframe 5. */
  666. for (i=uframe+1; i<8 && i<uframe+4; i++)
  667. if (!check_period (ehci, frame, i,
  668. qh->period, qh->c_usecs))
  669. goto done;
  670. else
  671. mask |= 1 << i;
  672. retval = 0;
  673. *c_maskp = cpu_to_hc32(ehci, mask << 8);
  674. }
  675. #else
  676. /* Make sure this tt's buffer is also available for CSPLITs.
  677. * We pessimize a bit; probably the typical full speed case
  678. * doesn't need the second CSPLIT.
  679. *
  680. * NOTE: both SPLIT and CSPLIT could be checked in just
  681. * one smart pass...
  682. */
  683. mask = 0x03 << (uframe + qh->gap_uf);
  684. *c_maskp = cpu_to_hc32(ehci, mask << 8);
  685. mask |= 1 << uframe;
  686. if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
  687. if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
  688. qh->period, qh->c_usecs))
  689. goto done;
  690. if (!check_period (ehci, frame, uframe + qh->gap_uf,
  691. qh->period, qh->c_usecs))
  692. goto done;
  693. retval = 0;
  694. }
  695. #endif
  696. done:
  697. return retval;
  698. }
  699. /* "first fit" scheduling policy used the first time through,
  700. * or when the previous schedule slot can't be re-used.
  701. */
  702. static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
  703. {
  704. int status;
  705. unsigned uframe;
  706. __hc32 c_mask;
  707. unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
  708. struct ehci_qh_hw *hw = qh->hw;
  709. hw->hw_next = EHCI_LIST_END(ehci);
  710. frame = qh->start;
  711. /* reuse the previous schedule slots, if we can */
  712. if (frame < qh->period) {
  713. uframe = ffs(hc32_to_cpup(ehci, &hw->hw_info2) & QH_SMASK);
  714. status = check_intr_schedule (ehci, frame, --uframe,
  715. qh, &c_mask);
  716. } else {
  717. uframe = 0;
  718. c_mask = 0;
  719. status = -ENOSPC;
  720. }
  721. /* else scan the schedule to find a group of slots such that all
  722. * uframes have enough periodic bandwidth available.
  723. */
  724. if (status) {
  725. /* "normal" case, uframing flexible except with splits */
  726. if (qh->period) {
  727. int i;
  728. for (i = qh->period; status && i > 0; --i) {
  729. frame = ++ehci->random_frame % qh->period;
  730. for (uframe = 0; uframe < 8; uframe++) {
  731. status = check_intr_schedule (ehci,
  732. frame, uframe, qh,
  733. &c_mask);
  734. if (status == 0)
  735. break;
  736. }
  737. }
  738. /* qh->period == 0 means every uframe */
  739. } else {
  740. frame = 0;
  741. status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
  742. }
  743. if (status)
  744. goto done;
  745. qh->start = frame;
  746. /* reset S-frame and (maybe) C-frame masks */
  747. hw->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK));
  748. hw->hw_info2 |= qh->period
  749. ? cpu_to_hc32(ehci, 1 << uframe)
  750. : cpu_to_hc32(ehci, QH_SMASK);
  751. hw->hw_info2 |= c_mask;
  752. } else
  753. ehci_dbg (ehci, "reused qh %p schedule\n", qh);
  754. done:
  755. return status;
  756. }
  757. static int intr_submit (
  758. struct ehci_hcd *ehci,
  759. struct urb *urb,
  760. struct list_head *qtd_list,
  761. gfp_t mem_flags
  762. ) {
  763. unsigned epnum;
  764. unsigned long flags;
  765. struct ehci_qh *qh;
  766. int status;
  767. struct list_head empty;
  768. /* get endpoint and transfer/schedule data */
  769. epnum = urb->ep->desc.bEndpointAddress;
  770. spin_lock_irqsave (&ehci->lock, flags);
  771. if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
  772. status = -ESHUTDOWN;
  773. goto done_not_linked;
  774. }
  775. status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
  776. if (unlikely(status))
  777. goto done_not_linked;
  778. /* get qh and force any scheduling errors */
  779. INIT_LIST_HEAD (&empty);
  780. qh = qh_append_tds(ehci, urb, &empty, epnum, &urb->ep->hcpriv);
  781. if (qh == NULL) {
  782. status = -ENOMEM;
  783. goto done;
  784. }
  785. if (qh->qh_state == QH_STATE_IDLE) {
  786. if ((status = qh_schedule (ehci, qh)) != 0)
  787. goto done;
  788. }
  789. /* then queue the urb's tds to the qh */
  790. qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv);
  791. BUG_ON (qh == NULL);
  792. /* stuff into the periodic schedule */
  793. if (qh->qh_state == QH_STATE_IDLE) {
  794. qh_refresh(ehci, qh);
  795. qh_link_periodic(ehci, qh);
  796. } else {
  797. /* cancel unlink wait for the qh */
  798. cancel_unlink_wait_intr(ehci, qh);
  799. }
  800. /* ... update usbfs periodic stats */
  801. ehci_to_hcd(ehci)->self.bandwidth_int_reqs++;
  802. done:
  803. if (unlikely(status))
  804. usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
  805. done_not_linked:
  806. spin_unlock_irqrestore (&ehci->lock, flags);
  807. if (status)
  808. qtd_list_free (ehci, urb, qtd_list);
  809. return status;
  810. }
  811. static void scan_intr(struct ehci_hcd *ehci)
  812. {
  813. struct ehci_qh *qh;
  814. list_for_each_entry_safe(qh, ehci->qh_scan_next, &ehci->intr_qh_list,
  815. intr_node) {
  816. /* clean any finished work for this qh */
  817. if (!list_empty(&qh->qtd_list)) {
  818. int temp;
  819. /*
  820. * Unlinks could happen here; completion reporting
  821. * drops the lock. That's why ehci->qh_scan_next
  822. * always holds the next qh to scan; if the next qh
  823. * gets unlinked then ehci->qh_scan_next is adjusted
  824. * in qh_unlink_periodic().
  825. */
  826. temp = qh_completions(ehci, qh);
  827. if (unlikely(temp))
  828. start_unlink_intr(ehci, qh);
  829. else if (unlikely(list_empty(&qh->qtd_list) &&
  830. qh->qh_state == QH_STATE_LINKED))
  831. start_unlink_intr_wait(ehci, qh);
  832. }
  833. }
  834. }
  835. /*-------------------------------------------------------------------------*/
  836. /* ehci_iso_stream ops work with both ITD and SITD */
  837. static struct ehci_iso_stream *
  838. iso_stream_alloc (gfp_t mem_flags)
  839. {
  840. struct ehci_iso_stream *stream;
  841. stream = kzalloc(sizeof *stream, mem_flags);
  842. if (likely (stream != NULL)) {
  843. INIT_LIST_HEAD(&stream->td_list);
  844. INIT_LIST_HEAD(&stream->free_list);
  845. stream->next_uframe = -1;
  846. }
  847. return stream;
  848. }
  849. static void
  850. iso_stream_init (
  851. struct ehci_hcd *ehci,
  852. struct ehci_iso_stream *stream,
  853. struct usb_device *dev,
  854. int pipe,
  855. unsigned interval
  856. )
  857. {
  858. static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
  859. u32 buf1;
  860. unsigned epnum, maxp;
  861. int is_input;
  862. long bandwidth;
  863. /*
  864. * this might be a "high bandwidth" highspeed endpoint,
  865. * as encoded in the ep descriptor's wMaxPacket field
  866. */
  867. epnum = usb_pipeendpoint (pipe);
  868. is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
  869. maxp = usb_maxpacket(dev, pipe, !is_input);
  870. if (is_input) {
  871. buf1 = (1 << 11);
  872. } else {
  873. buf1 = 0;
  874. }
  875. /* knows about ITD vs SITD */
  876. if (dev->speed == USB_SPEED_HIGH) {
  877. unsigned multi = hb_mult(maxp);
  878. stream->highspeed = 1;
  879. maxp = max_packet(maxp);
  880. buf1 |= maxp;
  881. maxp *= multi;
  882. stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum);
  883. stream->buf1 = cpu_to_hc32(ehci, buf1);
  884. stream->buf2 = cpu_to_hc32(ehci, multi);
  885. /* usbfs wants to report the average usecs per frame tied up
  886. * when transfers on this endpoint are scheduled ...
  887. */
  888. stream->usecs = HS_USECS_ISO (maxp);
  889. bandwidth = stream->usecs * 8;
  890. bandwidth /= interval;
  891. } else {
  892. u32 addr;
  893. int think_time;
  894. int hs_transfers;
  895. addr = dev->ttport << 24;
  896. if (!ehci_is_TDI(ehci)
  897. || (dev->tt->hub !=
  898. ehci_to_hcd(ehci)->self.root_hub))
  899. addr |= dev->tt->hub->devnum << 16;
  900. addr |= epnum << 8;
  901. addr |= dev->devnum;
  902. stream->usecs = HS_USECS_ISO (maxp);
  903. think_time = dev->tt ? dev->tt->think_time : 0;
  904. stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (
  905. dev->speed, is_input, 1, maxp));
  906. hs_transfers = max (1u, (maxp + 187) / 188);
  907. if (is_input) {
  908. u32 tmp;
  909. addr |= 1 << 31;
  910. stream->c_usecs = stream->usecs;
  911. stream->usecs = HS_USECS_ISO (1);
  912. stream->raw_mask = 1;
  913. /* c-mask as specified in USB 2.0 11.18.4 3.c */
  914. tmp = (1 << (hs_transfers + 2)) - 1;
  915. stream->raw_mask |= tmp << (8 + 2);
  916. } else
  917. stream->raw_mask = smask_out [hs_transfers - 1];
  918. bandwidth = stream->usecs + stream->c_usecs;
  919. bandwidth /= interval << 3;
  920. /* stream->splits gets created from raw_mask later */
  921. stream->address = cpu_to_hc32(ehci, addr);
  922. }
  923. stream->bandwidth = bandwidth;
  924. stream->udev = dev;
  925. stream->bEndpointAddress = is_input | epnum;
  926. stream->interval = interval;
  927. stream->maxp = maxp;
  928. }
  929. static struct ehci_iso_stream *
  930. iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
  931. {
  932. unsigned epnum;
  933. struct ehci_iso_stream *stream;
  934. struct usb_host_endpoint *ep;
  935. unsigned long flags;
  936. epnum = usb_pipeendpoint (urb->pipe);
  937. if (usb_pipein(urb->pipe))
  938. ep = urb->dev->ep_in[epnum];
  939. else
  940. ep = urb->dev->ep_out[epnum];
  941. spin_lock_irqsave (&ehci->lock, flags);
  942. stream = ep->hcpriv;
  943. if (unlikely (stream == NULL)) {
  944. stream = iso_stream_alloc(GFP_ATOMIC);
  945. if (likely (stream != NULL)) {
  946. ep->hcpriv = stream;
  947. stream->ep = ep;
  948. iso_stream_init(ehci, stream, urb->dev, urb->pipe,
  949. urb->interval);
  950. }
  951. /* if dev->ep [epnum] is a QH, hw is set */
  952. } else if (unlikely (stream->hw != NULL)) {
  953. ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
  954. urb->dev->devpath, epnum,
  955. usb_pipein(urb->pipe) ? "in" : "out");
  956. stream = NULL;
  957. }
  958. spin_unlock_irqrestore (&ehci->lock, flags);
  959. return stream;
  960. }
  961. /*-------------------------------------------------------------------------*/
  962. /* ehci_iso_sched ops can be ITD-only or SITD-only */
  963. static struct ehci_iso_sched *
  964. iso_sched_alloc (unsigned packets, gfp_t mem_flags)
  965. {
  966. struct ehci_iso_sched *iso_sched;
  967. int size = sizeof *iso_sched;
  968. size += packets * sizeof (struct ehci_iso_packet);
  969. iso_sched = kzalloc(size, mem_flags);
  970. if (likely (iso_sched != NULL)) {
  971. INIT_LIST_HEAD (&iso_sched->td_list);
  972. }
  973. return iso_sched;
  974. }
  975. static inline void
  976. itd_sched_init(
  977. struct ehci_hcd *ehci,
  978. struct ehci_iso_sched *iso_sched,
  979. struct ehci_iso_stream *stream,
  980. struct urb *urb
  981. )
  982. {
  983. unsigned i;
  984. dma_addr_t dma = urb->transfer_dma;
  985. /* how many uframes are needed for these transfers */
  986. iso_sched->span = urb->number_of_packets * stream->interval;
  987. /* figure out per-uframe itd fields that we'll need later
  988. * when we fit new itds into the schedule.
  989. */
  990. for (i = 0; i < urb->number_of_packets; i++) {
  991. struct ehci_iso_packet *uframe = &iso_sched->packet [i];
  992. unsigned length;
  993. dma_addr_t buf;
  994. u32 trans;
  995. length = urb->iso_frame_desc [i].length;
  996. buf = dma + urb->iso_frame_desc [i].offset;
  997. trans = EHCI_ISOC_ACTIVE;
  998. trans |= buf & 0x0fff;
  999. if (unlikely (((i + 1) == urb->number_of_packets))
  1000. && !(urb->transfer_flags & URB_NO_INTERRUPT))
  1001. trans |= EHCI_ITD_IOC;
  1002. trans |= length << 16;
  1003. uframe->transaction = cpu_to_hc32(ehci, trans);
  1004. /* might need to cross a buffer page within a uframe */
  1005. uframe->bufp = (buf & ~(u64)0x0fff);
  1006. buf += length;
  1007. if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
  1008. uframe->cross = 1;
  1009. }
  1010. }
  1011. static void
  1012. iso_sched_free (
  1013. struct ehci_iso_stream *stream,
  1014. struct ehci_iso_sched *iso_sched
  1015. )
  1016. {
  1017. if (!iso_sched)
  1018. return;
  1019. // caller must hold ehci->lock!
  1020. list_splice (&iso_sched->td_list, &stream->free_list);
  1021. kfree (iso_sched);
  1022. }
  1023. static int
  1024. itd_urb_transaction (
  1025. struct ehci_iso_stream *stream,
  1026. struct ehci_hcd *ehci,
  1027. struct urb *urb,
  1028. gfp_t mem_flags
  1029. )
  1030. {
  1031. struct ehci_itd *itd;
  1032. dma_addr_t itd_dma;
  1033. int i;
  1034. unsigned num_itds;
  1035. struct ehci_iso_sched *sched;
  1036. unsigned long flags;
  1037. sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
  1038. if (unlikely (sched == NULL))
  1039. return -ENOMEM;
  1040. itd_sched_init(ehci, sched, stream, urb);
  1041. if (urb->interval < 8)
  1042. num_itds = 1 + (sched->span + 7) / 8;
  1043. else
  1044. num_itds = urb->number_of_packets;
  1045. /* allocate/init ITDs */
  1046. spin_lock_irqsave (&ehci->lock, flags);
  1047. for (i = 0; i < num_itds; i++) {
  1048. /*
  1049. * Use iTDs from the free list, but not iTDs that may
  1050. * still be in use by the hardware.
  1051. */
  1052. if (likely(!list_empty(&stream->free_list))) {
  1053. itd = list_first_entry(&stream->free_list,
  1054. struct ehci_itd, itd_list);
  1055. if (itd->frame == ehci->now_frame)
  1056. goto alloc_itd;
  1057. list_del (&itd->itd_list);
  1058. itd_dma = itd->itd_dma;
  1059. } else {
  1060. alloc_itd:
  1061. spin_unlock_irqrestore (&ehci->lock, flags);
  1062. itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
  1063. &itd_dma);
  1064. spin_lock_irqsave (&ehci->lock, flags);
  1065. if (!itd) {
  1066. iso_sched_free(stream, sched);
  1067. spin_unlock_irqrestore(&ehci->lock, flags);
  1068. return -ENOMEM;
  1069. }
  1070. }
  1071. memset (itd, 0, sizeof *itd);
  1072. itd->itd_dma = itd_dma;
  1073. itd->frame = 9999; /* an invalid value */
  1074. list_add (&itd->itd_list, &sched->td_list);
  1075. }
  1076. spin_unlock_irqrestore (&ehci->lock, flags);
  1077. /* temporarily store schedule info in hcpriv */
  1078. urb->hcpriv = sched;
  1079. urb->error_count = 0;
  1080. return 0;
  1081. }
  1082. /*-------------------------------------------------------------------------*/
  1083. static inline int
  1084. itd_slot_ok (
  1085. struct ehci_hcd *ehci,
  1086. u32 mod,
  1087. u32 uframe,
  1088. u8 usecs,
  1089. u32 period
  1090. )
  1091. {
  1092. uframe %= period;
  1093. do {
  1094. /* can't commit more than uframe_periodic_max usec */
  1095. if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
  1096. > (ehci->uframe_periodic_max - usecs))
  1097. return 0;
  1098. /* we know urb->interval is 2^N uframes */
  1099. uframe += period;
  1100. } while (uframe < mod);
  1101. return 1;
  1102. }
  1103. static inline int
  1104. sitd_slot_ok (
  1105. struct ehci_hcd *ehci,
  1106. u32 mod,
  1107. struct ehci_iso_stream *stream,
  1108. u32 uframe,
  1109. struct ehci_iso_sched *sched,
  1110. u32 period_uframes
  1111. )
  1112. {
  1113. u32 mask, tmp;
  1114. u32 frame, uf;
  1115. mask = stream->raw_mask << (uframe & 7);
  1116. /* for IN, don't wrap CSPLIT into the next frame */
  1117. if (mask & ~0xffff)
  1118. return 0;
  1119. /* check bandwidth */
  1120. uframe %= period_uframes;
  1121. frame = uframe >> 3;
  1122. #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
  1123. /* The tt's fullspeed bus bandwidth must be available.
  1124. * tt_available scheduling guarantees 10+% for control/bulk.
  1125. */
  1126. uf = uframe & 7;
  1127. if (!tt_available(ehci, period_uframes >> 3,
  1128. stream->udev, frame, uf, stream->tt_usecs))
  1129. return 0;
  1130. #else
  1131. /* tt must be idle for start(s), any gap, and csplit.
  1132. * assume scheduling slop leaves 10+% for control/bulk.
  1133. */
  1134. if (!tt_no_collision(ehci, period_uframes >> 3,
  1135. stream->udev, frame, mask))
  1136. return 0;
  1137. #endif
  1138. /* this multi-pass logic is simple, but performance may
  1139. * suffer when the schedule data isn't cached.
  1140. */
  1141. do {
  1142. u32 max_used;
  1143. frame = uframe >> 3;
  1144. uf = uframe & 7;
  1145. /* check starts (OUT uses more than one) */
  1146. max_used = ehci->uframe_periodic_max - stream->usecs;
  1147. for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
  1148. if (periodic_usecs (ehci, frame, uf) > max_used)
  1149. return 0;
  1150. }
  1151. /* for IN, check CSPLIT */
  1152. if (stream->c_usecs) {
  1153. uf = uframe & 7;
  1154. max_used = ehci->uframe_periodic_max - stream->c_usecs;
  1155. do {
  1156. tmp = 1 << uf;
  1157. tmp <<= 8;
  1158. if ((stream->raw_mask & tmp) == 0)
  1159. continue;
  1160. if (periodic_usecs (ehci, frame, uf)
  1161. > max_used)
  1162. return 0;
  1163. } while (++uf < 8);
  1164. }
  1165. /* we know urb->interval is 2^N uframes */
  1166. uframe += period_uframes;
  1167. } while (uframe < mod);
  1168. stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7));
  1169. return 1;
  1170. }
  1171. /*
  1172. * This scheduler plans almost as far into the future as it has actual
  1173. * periodic schedule slots. (Affected by TUNE_FLS, which defaults to
  1174. * "as small as possible" to be cache-friendlier.) That limits the size
  1175. * transfers you can stream reliably; avoid more than 64 msec per urb.
  1176. * Also avoid queue depths of less than ehci's worst irq latency (affected
  1177. * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
  1178. * and other factors); or more than about 230 msec total (for portability,
  1179. * given EHCI_TUNE_FLS and the slop). Or, write a smarter scheduler!
  1180. */
  1181. #define SCHEDULING_DELAY 40 /* microframes */
  1182. static int
  1183. iso_stream_schedule (
  1184. struct ehci_hcd *ehci,
  1185. struct urb *urb,
  1186. struct ehci_iso_stream *stream
  1187. )
  1188. {
  1189. u32 now, base, next, start, period, span;
  1190. int status;
  1191. unsigned mod = ehci->periodic_size << 3;
  1192. struct ehci_iso_sched *sched = urb->hcpriv;
  1193. period = urb->interval;
  1194. span = sched->span;
  1195. if (!stream->highspeed) {
  1196. period <<= 3;
  1197. span <<= 3;
  1198. }
  1199. now = ehci_read_frame_index(ehci) & (mod - 1);
  1200. /*
  1201. * Need to schedule; when's the next (u)frame we could start?
  1202. * This is bigger than ehci->i_thresh allows; scheduling itself
  1203. * isn't free, the delay should handle reasonably slow cpus. It
  1204. * can also help high bandwidth if the dma and irq loads don't
  1205. * jump until after the queue is primed.
  1206. */
  1207. if (unlikely(list_empty(&stream->td_list))) {
  1208. int done = 0;
  1209. base = now & ~0x07;
  1210. start = base + SCHEDULING_DELAY;
  1211. /* find a uframe slot with enough bandwidth.
  1212. * Early uframes are more precious because full-speed
  1213. * iso IN transfers can't use late uframes,
  1214. * and therefore they should be allocated last.
  1215. */
  1216. next = start;
  1217. start += period;
  1218. do {
  1219. start--;
  1220. /* check schedule: enough space? */
  1221. if (stream->highspeed) {
  1222. if (itd_slot_ok(ehci, mod, start,
  1223. stream->usecs, period))
  1224. done = 1;
  1225. } else {
  1226. if ((start % 8) >= 6)
  1227. continue;
  1228. if (sitd_slot_ok(ehci, mod, stream,
  1229. start, sched, period))
  1230. done = 1;
  1231. }
  1232. } while (start > next && !done);
  1233. /* no room in the schedule */
  1234. if (!done) {
  1235. ehci_dbg(ehci, "iso sched full %p", urb);
  1236. status = -ENOSPC;
  1237. goto fail;
  1238. }
  1239. }
  1240. /*
  1241. * Typical case: reuse current schedule, stream is still active.
  1242. * Hopefully there are no gaps from the host falling behind
  1243. * (irq delays etc). If there are, the behavior depends on
  1244. * whether URB_ISO_ASAP is set.
  1245. */
  1246. else {
  1247. /* Take the isochronous scheduling threshold into account */
  1248. if (ehci->i_thresh)
  1249. next = now + ehci->i_thresh; /* uframe cache */
  1250. else
  1251. next = (now + 2 + 7) & ~0x07; /* full frame cache */
  1252. /*
  1253. * Use ehci->last_iso_frame as the base. There can't be any
  1254. * TDs scheduled for earlier than that.
  1255. */
  1256. base = ehci->last_iso_frame << 3;
  1257. next = (next - base) & (mod - 1);
  1258. start = (stream->next_uframe - base) & (mod - 1);
  1259. /* Is the schedule already full? */
  1260. if (unlikely(start < period)) {
  1261. ehci_dbg(ehci, "iso sched full %p (%u-%u < %u mod %u)\n",
  1262. urb, stream->next_uframe, base,
  1263. period, mod);
  1264. status = -ENOSPC;
  1265. goto fail;
  1266. }
  1267. /* Behind the scheduling threshold? */
  1268. if (unlikely(start < next)) {
  1269. unsigned now2 = (now - base) & (mod - 1);
  1270. /* USB_ISO_ASAP: Round up to the first available slot */
  1271. if (urb->transfer_flags & URB_ISO_ASAP)
  1272. start += (next - start + period - 1) & -period;
  1273. /*
  1274. * Not ASAP: Use the next slot in the stream,
  1275. * no matter what.
  1276. */
  1277. else if (start + span - period < now2) {
  1278. ehci_dbg(ehci, "iso underrun %p (%u+%u < %u)\n",
  1279. urb, start + base,
  1280. span - period, now2 + base);
  1281. }
  1282. }
  1283. start += base;
  1284. }
  1285. /* Tried to schedule too far into the future? */
  1286. if (unlikely(start - base + span - period >= mod)) {
  1287. ehci_dbg(ehci, "request %p would overflow (%u+%u >= %u)\n",
  1288. urb, start - base, span - period, mod);
  1289. status = -EFBIG;
  1290. goto fail;
  1291. }
  1292. stream->next_uframe = start & (mod - 1);
  1293. /* report high speed start in uframes; full speed, in frames */
  1294. urb->start_frame = stream->next_uframe;
  1295. if (!stream->highspeed)
  1296. urb->start_frame >>= 3;
  1297. /* Make sure scan_isoc() sees these */
  1298. if (ehci->isoc_count == 0)
  1299. ehci->last_iso_frame = now >> 3;
  1300. return 0;
  1301. fail:
  1302. iso_sched_free(stream, sched);
  1303. urb->hcpriv = NULL;
  1304. return status;
  1305. }
  1306. /*-------------------------------------------------------------------------*/
  1307. static inline void
  1308. itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream,
  1309. struct ehci_itd *itd)
  1310. {
  1311. int i;
  1312. /* it's been recently zeroed */
  1313. itd->hw_next = EHCI_LIST_END(ehci);
  1314. itd->hw_bufp [0] = stream->buf0;
  1315. itd->hw_bufp [1] = stream->buf1;
  1316. itd->hw_bufp [2] = stream->buf2;
  1317. for (i = 0; i < 8; i++)
  1318. itd->index[i] = -1;
  1319. /* All other fields are filled when scheduling */
  1320. }
  1321. static inline void
  1322. itd_patch(
  1323. struct ehci_hcd *ehci,
  1324. struct ehci_itd *itd,
  1325. struct ehci_iso_sched *iso_sched,
  1326. unsigned index,
  1327. u16 uframe
  1328. )
  1329. {
  1330. struct ehci_iso_packet *uf = &iso_sched->packet [index];
  1331. unsigned pg = itd->pg;
  1332. // BUG_ON (pg == 6 && uf->cross);
  1333. uframe &= 0x07;
  1334. itd->index [uframe] = index;
  1335. itd->hw_transaction[uframe] = uf->transaction;
  1336. itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12);
  1337. itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0);
  1338. itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32));
  1339. /* iso_frame_desc[].offset must be strictly increasing */
  1340. if (unlikely (uf->cross)) {
  1341. u64 bufp = uf->bufp + 4096;
  1342. itd->pg = ++pg;
  1343. itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0);
  1344. itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32));
  1345. }
  1346. }
  1347. static inline void
  1348. itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
  1349. {
  1350. union ehci_shadow *prev = &ehci->pshadow[frame];
  1351. __hc32 *hw_p = &ehci->periodic[frame];
  1352. union ehci_shadow here = *prev;
  1353. __hc32 type = 0;
  1354. /* skip any iso nodes which might belong to previous microframes */
  1355. while (here.ptr) {
  1356. type = Q_NEXT_TYPE(ehci, *hw_p);
  1357. if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
  1358. break;
  1359. prev = periodic_next_shadow(ehci, prev, type);
  1360. hw_p = shadow_next_periodic(ehci, &here, type);
  1361. here = *prev;
  1362. }
  1363. itd->itd_next = here;
  1364. itd->hw_next = *hw_p;
  1365. prev->itd = itd;
  1366. itd->frame = frame;
  1367. wmb ();
  1368. *hw_p = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
  1369. }
  1370. /* fit urb's itds into the selected schedule slot; activate as needed */
  1371. static void itd_link_urb(
  1372. struct ehci_hcd *ehci,
  1373. struct urb *urb,
  1374. unsigned mod,
  1375. struct ehci_iso_stream *stream
  1376. )
  1377. {
  1378. int packet;
  1379. unsigned next_uframe, uframe, frame;
  1380. struct ehci_iso_sched *iso_sched = urb->hcpriv;
  1381. struct ehci_itd *itd;
  1382. next_uframe = stream->next_uframe & (mod - 1);
  1383. if (unlikely (list_empty(&stream->td_list)))
  1384. ehci_to_hcd(ehci)->self.bandwidth_allocated
  1385. += stream->bandwidth;
  1386. if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
  1387. if (ehci->amd_pll_fix == 1)
  1388. usb_amd_quirk_pll_disable();
  1389. }
  1390. ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
  1391. /* fill iTDs uframe by uframe */
  1392. for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
  1393. if (itd == NULL) {
  1394. /* ASSERT: we have all necessary itds */
  1395. // BUG_ON (list_empty (&iso_sched->td_list));
  1396. /* ASSERT: no itds for this endpoint in this uframe */
  1397. itd = list_entry (iso_sched->td_list.next,
  1398. struct ehci_itd, itd_list);
  1399. list_move_tail (&itd->itd_list, &stream->td_list);
  1400. itd->stream = stream;
  1401. itd->urb = urb;
  1402. itd_init (ehci, stream, itd);
  1403. }
  1404. uframe = next_uframe & 0x07;
  1405. frame = next_uframe >> 3;
  1406. itd_patch(ehci, itd, iso_sched, packet, uframe);
  1407. next_uframe += stream->interval;
  1408. next_uframe &= mod - 1;
  1409. packet++;
  1410. /* link completed itds into the schedule */
  1411. if (((next_uframe >> 3) != frame)
  1412. || packet == urb->number_of_packets) {
  1413. itd_link(ehci, frame & (ehci->periodic_size - 1), itd);
  1414. itd = NULL;
  1415. }
  1416. }
  1417. stream->next_uframe = next_uframe;
  1418. /* don't need that schedule data any more */
  1419. iso_sched_free (stream, iso_sched);
  1420. urb->hcpriv = stream;
  1421. ++ehci->isoc_count;
  1422. enable_periodic(ehci);
  1423. }
  1424. #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
  1425. /* Process and recycle a completed ITD. Return true iff its urb completed,
  1426. * and hence its completion callback probably added things to the hardware
  1427. * schedule.
  1428. *
  1429. * Note that we carefully avoid recycling this descriptor until after any
  1430. * completion callback runs, so that it won't be reused quickly. That is,
  1431. * assuming (a) no more than two urbs per frame on this endpoint, and also
  1432. * (b) only this endpoint's completions submit URBs. It seems some silicon
  1433. * corrupts things if you reuse completed descriptors very quickly...
  1434. */
  1435. static bool itd_complete(struct ehci_hcd *ehci, struct ehci_itd *itd)
  1436. {
  1437. struct urb *urb = itd->urb;
  1438. struct usb_iso_packet_descriptor *desc;
  1439. u32 t;
  1440. unsigned uframe;
  1441. int urb_index = -1;
  1442. struct ehci_iso_stream *stream = itd->stream;
  1443. struct usb_device *dev;
  1444. bool retval = false;
  1445. /* for each uframe with a packet */
  1446. for (uframe = 0; uframe < 8; uframe++) {
  1447. if (likely (itd->index[uframe] == -1))
  1448. continue;
  1449. urb_index = itd->index[uframe];
  1450. desc = &urb->iso_frame_desc [urb_index];
  1451. t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]);
  1452. itd->hw_transaction [uframe] = 0;
  1453. /* report transfer status */
  1454. if (unlikely (t & ISO_ERRS)) {
  1455. urb->error_count++;
  1456. if (t & EHCI_ISOC_BUF_ERR)
  1457. desc->status = usb_pipein (urb->pipe)
  1458. ? -ENOSR /* hc couldn't read */
  1459. : -ECOMM; /* hc couldn't write */
  1460. else if (t & EHCI_ISOC_BABBLE)
  1461. desc->status = -EOVERFLOW;
  1462. else /* (t & EHCI_ISOC_XACTERR) */
  1463. desc->status = -EPROTO;
  1464. /* HC need not update length with this error */
  1465. if (!(t & EHCI_ISOC_BABBLE)) {
  1466. desc->actual_length = EHCI_ITD_LENGTH(t);
  1467. urb->actual_length += desc->actual_length;
  1468. }
  1469. } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
  1470. desc->status = 0;
  1471. desc->actual_length = EHCI_ITD_LENGTH(t);
  1472. urb->actual_length += desc->actual_length;
  1473. } else {
  1474. /* URB was too late */
  1475. urb->error_count++;
  1476. }
  1477. }
  1478. /* handle completion now? */
  1479. if (likely ((urb_index + 1) != urb->number_of_packets))
  1480. goto done;
  1481. /* ASSERT: it's really the last itd for this urb
  1482. list_for_each_entry (itd, &stream->td_list, itd_list)
  1483. BUG_ON (itd->urb == urb);
  1484. */
  1485. /* give urb back to the driver; completion often (re)submits */
  1486. dev = urb->dev;
  1487. ehci_urb_done(ehci, urb, 0);
  1488. retval = true;
  1489. urb = NULL;
  1490. --ehci->isoc_count;
  1491. disable_periodic(ehci);
  1492. ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
  1493. if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
  1494. if (ehci->amd_pll_fix == 1)
  1495. usb_amd_quirk_pll_enable();
  1496. }
  1497. if (unlikely(list_is_singular(&stream->td_list)))
  1498. ehci_to_hcd(ehci)->self.bandwidth_allocated
  1499. -= stream->bandwidth;
  1500. done:
  1501. itd->urb = NULL;
  1502. /* Add to the end of the free list for later reuse */
  1503. list_move_tail(&itd->itd_list, &stream->free_list);
  1504. /* Recycle the iTDs when the pipeline is empty (ep no longer in use) */
  1505. if (list_empty(&stream->td_list)) {
  1506. list_splice_tail_init(&stream->free_list,
  1507. &ehci->cached_itd_list);
  1508. start_free_itds(ehci);
  1509. }
  1510. return retval;
  1511. }
  1512. /*-------------------------------------------------------------------------*/
  1513. static int itd_submit (struct ehci_hcd *ehci, struct urb *urb,
  1514. gfp_t mem_flags)
  1515. {
  1516. int status = -EINVAL;
  1517. unsigned long flags;
  1518. struct ehci_iso_stream *stream;
  1519. /* Get iso_stream head */
  1520. stream = iso_stream_find (ehci, urb);
  1521. if (unlikely (stream == NULL)) {
  1522. ehci_dbg (ehci, "can't get iso stream\n");
  1523. return -ENOMEM;
  1524. }
  1525. if (unlikely (urb->interval != stream->interval)) {
  1526. ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
  1527. stream->interval, urb->interval);
  1528. goto done;
  1529. }
  1530. #ifdef EHCI_URB_TRACE
  1531. ehci_dbg (ehci,
  1532. "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
  1533. __func__, urb->dev->devpath, urb,
  1534. usb_pipeendpoint (urb->pipe),
  1535. usb_pipein (urb->pipe) ? "in" : "out",
  1536. urb->transfer_buffer_length,
  1537. urb->number_of_packets, urb->interval,
  1538. stream);
  1539. #endif
  1540. /* allocate ITDs w/o locking anything */
  1541. status = itd_urb_transaction (stream, ehci, urb, mem_flags);
  1542. if (unlikely (status < 0)) {
  1543. ehci_dbg (ehci, "can't init itds\n");
  1544. goto done;
  1545. }
  1546. /* schedule ... need to lock */
  1547. spin_lock_irqsave (&ehci->lock, flags);
  1548. if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
  1549. status = -ESHUTDOWN;
  1550. goto done_not_linked;
  1551. }
  1552. status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
  1553. if (unlikely(status))
  1554. goto done_not_linked;
  1555. status = iso_stream_schedule(ehci, urb, stream);
  1556. if (likely (status == 0))
  1557. itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
  1558. else
  1559. usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
  1560. done_not_linked:
  1561. spin_unlock_irqrestore (&ehci->lock, flags);
  1562. done:
  1563. return status;
  1564. }
  1565. /*-------------------------------------------------------------------------*/
  1566. /*
  1567. * "Split ISO TDs" ... used for USB 1.1 devices going through the
  1568. * TTs in USB 2.0 hubs. These need microframe scheduling.
  1569. */
  1570. static inline void
  1571. sitd_sched_init(
  1572. struct ehci_hcd *ehci,
  1573. struct ehci_iso_sched *iso_sched,
  1574. struct ehci_iso_stream *stream,
  1575. struct urb *urb
  1576. )
  1577. {
  1578. unsigned i;
  1579. dma_addr_t dma = urb->transfer_dma;
  1580. /* how many frames are needed for these transfers */
  1581. iso_sched->span = urb->number_of_packets * stream->interval;
  1582. /* figure out per-frame sitd fields that we'll need later
  1583. * when we fit new sitds into the schedule.
  1584. */
  1585. for (i = 0; i < urb->number_of_packets; i++) {
  1586. struct ehci_iso_packet *packet = &iso_sched->packet [i];
  1587. unsigned length;
  1588. dma_addr_t buf;
  1589. u32 trans;
  1590. length = urb->iso_frame_desc [i].length & 0x03ff;
  1591. buf = dma + urb->iso_frame_desc [i].offset;
  1592. trans = SITD_STS_ACTIVE;
  1593. if (((i + 1) == urb->number_of_packets)
  1594. && !(urb->transfer_flags & URB_NO_INTERRUPT))
  1595. trans |= SITD_IOC;
  1596. trans |= length << 16;
  1597. packet->transaction = cpu_to_hc32(ehci, trans);
  1598. /* might need to cross a buffer page within a td */
  1599. packet->bufp = buf;
  1600. packet->buf1 = (buf + length) & ~0x0fff;
  1601. if (packet->buf1 != (buf & ~(u64)0x0fff))
  1602. packet->cross = 1;
  1603. /* OUT uses multiple start-splits */
  1604. if (stream->bEndpointAddress & USB_DIR_IN)
  1605. continue;
  1606. length = (length + 187) / 188;
  1607. if (length > 1) /* BEGIN vs ALL */
  1608. length |= 1 << 3;
  1609. packet->buf1 |= length;
  1610. }
  1611. }
  1612. static int
  1613. sitd_urb_transaction (
  1614. struct ehci_iso_stream *stream,
  1615. struct ehci_hcd *ehci,
  1616. struct urb *urb,
  1617. gfp_t mem_flags
  1618. )
  1619. {
  1620. struct ehci_sitd *sitd;
  1621. dma_addr_t sitd_dma;
  1622. int i;
  1623. struct ehci_iso_sched *iso_sched;
  1624. unsigned long flags;
  1625. iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
  1626. if (iso_sched == NULL)
  1627. return -ENOMEM;
  1628. sitd_sched_init(ehci, iso_sched, stream, urb);
  1629. /* allocate/init sITDs */
  1630. spin_lock_irqsave (&ehci->lock, flags);
  1631. for (i = 0; i < urb->number_of_packets; i++) {
  1632. /* NOTE: for now, we don't try to handle wraparound cases
  1633. * for IN (using sitd->hw_backpointer, like a FSTN), which
  1634. * means we never need two sitds for full speed packets.
  1635. */
  1636. /*
  1637. * Use siTDs from the free list, but not siTDs that may
  1638. * still be in use by the hardware.
  1639. */
  1640. if (likely(!list_empty(&stream->free_list))) {
  1641. sitd = list_first_entry(&stream->free_list,
  1642. struct ehci_sitd, sitd_list);
  1643. if (sitd->frame == ehci->now_frame)
  1644. goto alloc_sitd;
  1645. list_del (&sitd->sitd_list);
  1646. sitd_dma = sitd->sitd_dma;
  1647. } else {
  1648. alloc_sitd:
  1649. spin_unlock_irqrestore (&ehci->lock, flags);
  1650. sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
  1651. &sitd_dma);
  1652. spin_lock_irqsave (&ehci->lock, flags);
  1653. if (!sitd) {
  1654. iso_sched_free(stream, iso_sched);
  1655. spin_unlock_irqrestore(&ehci->lock, flags);
  1656. return -ENOMEM;
  1657. }
  1658. }
  1659. memset (sitd, 0, sizeof *sitd);
  1660. sitd->sitd_dma = sitd_dma;
  1661. sitd->frame = 9999; /* an invalid value */
  1662. list_add (&sitd->sitd_list, &iso_sched->td_list);
  1663. }
  1664. /* temporarily store schedule info in hcpriv */
  1665. urb->hcpriv = iso_sched;
  1666. urb->error_count = 0;
  1667. spin_unlock_irqrestore (&ehci->lock, flags);
  1668. return 0;
  1669. }
  1670. /*-------------------------------------------------------------------------*/
  1671. static inline void
  1672. sitd_patch(
  1673. struct ehci_hcd *ehci,
  1674. struct ehci_iso_stream *stream,
  1675. struct ehci_sitd *sitd,
  1676. struct ehci_iso_sched *iso_sched,
  1677. unsigned index
  1678. )
  1679. {
  1680. struct ehci_iso_packet *uf = &iso_sched->packet [index];
  1681. u64 bufp = uf->bufp;
  1682. sitd->hw_next = EHCI_LIST_END(ehci);
  1683. sitd->hw_fullspeed_ep = stream->address;
  1684. sitd->hw_uframe = stream->splits;
  1685. sitd->hw_results = uf->transaction;
  1686. sitd->hw_backpointer = EHCI_LIST_END(ehci);
  1687. bufp = uf->bufp;
  1688. sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp);
  1689. sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32);
  1690. sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1);
  1691. if (uf->cross)
  1692. bufp += 4096;
  1693. sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32);
  1694. sitd->index = index;
  1695. }
  1696. static inline void
  1697. sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
  1698. {
  1699. /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
  1700. sitd->sitd_next = ehci->pshadow [frame];
  1701. sitd->hw_next = ehci->periodic [frame];
  1702. ehci->pshadow [frame].sitd = sitd;
  1703. sitd->frame = frame;
  1704. wmb ();
  1705. ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD);
  1706. }
  1707. /* fit urb's sitds into the selected schedule slot; activate as needed */
  1708. static void sitd_link_urb(
  1709. struct ehci_hcd *ehci,
  1710. struct urb *urb,
  1711. unsigned mod,
  1712. struct ehci_iso_stream *stream
  1713. )
  1714. {
  1715. int packet;
  1716. unsigned next_uframe;
  1717. struct ehci_iso_sched *sched = urb->hcpriv;
  1718. struct ehci_sitd *sitd;
  1719. next_uframe = stream->next_uframe;
  1720. if (list_empty(&stream->td_list))
  1721. /* usbfs ignores TT bandwidth */
  1722. ehci_to_hcd(ehci)->self.bandwidth_allocated
  1723. += stream->bandwidth;
  1724. if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
  1725. if (ehci->amd_pll_fix == 1)
  1726. usb_amd_quirk_pll_disable();
  1727. }
  1728. ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
  1729. /* fill sITDs frame by frame */
  1730. for (packet = 0, sitd = NULL;
  1731. packet < urb->number_of_packets;
  1732. packet++) {
  1733. /* ASSERT: we have all necessary sitds */
  1734. BUG_ON (list_empty (&sched->td_list));
  1735. /* ASSERT: no itds for this endpoint in this frame */
  1736. sitd = list_entry (sched->td_list.next,
  1737. struct ehci_sitd, sitd_list);
  1738. list_move_tail (&sitd->sitd_list, &stream->td_list);
  1739. sitd->stream = stream;
  1740. sitd->urb = urb;
  1741. sitd_patch(ehci, stream, sitd, sched, packet);
  1742. sitd_link(ehci, (next_uframe >> 3) & (ehci->periodic_size - 1),
  1743. sitd);
  1744. next_uframe += stream->interval << 3;
  1745. }
  1746. stream->next_uframe = next_uframe & (mod - 1);
  1747. /* don't need that schedule data any more */
  1748. iso_sched_free (stream, sched);
  1749. urb->hcpriv = stream;
  1750. ++ehci->isoc_count;
  1751. enable_periodic(ehci);
  1752. }
  1753. /*-------------------------------------------------------------------------*/
  1754. #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
  1755. | SITD_STS_XACT | SITD_STS_MMF)
  1756. /* Process and recycle a completed SITD. Return true iff its urb completed,
  1757. * and hence its completion callback probably added things to the hardware
  1758. * schedule.
  1759. *
  1760. * Note that we carefully avoid recycling this descriptor until after any
  1761. * completion callback runs, so that it won't be reused quickly. That is,
  1762. * assuming (a) no more than two urbs per frame on this endpoint, and also
  1763. * (b) only this endpoint's completions submit URBs. It seems some silicon
  1764. * corrupts things if you reuse completed descriptors very quickly...
  1765. */
  1766. static bool sitd_complete(struct ehci_hcd *ehci, struct ehci_sitd *sitd)
  1767. {
  1768. struct urb *urb = sitd->urb;
  1769. struct usb_iso_packet_descriptor *desc;
  1770. u32 t;
  1771. int urb_index = -1;
  1772. struct ehci_iso_stream *stream = sitd->stream;
  1773. struct usb_device *dev;
  1774. bool retval = false;
  1775. urb_index = sitd->index;
  1776. desc = &urb->iso_frame_desc [urb_index];
  1777. t = hc32_to_cpup(ehci, &sitd->hw_results);
  1778. /* report transfer status */
  1779. if (unlikely(t & SITD_ERRS)) {
  1780. urb->error_count++;
  1781. if (t & SITD_STS_DBE)
  1782. desc->status = usb_pipein (urb->pipe)
  1783. ? -ENOSR /* hc couldn't read */
  1784. : -ECOMM; /* hc couldn't write */
  1785. else if (t & SITD_STS_BABBLE)
  1786. desc->status = -EOVERFLOW;
  1787. else /* XACT, MMF, etc */
  1788. desc->status = -EPROTO;
  1789. } else if (unlikely(t & SITD_STS_ACTIVE)) {
  1790. /* URB was too late */
  1791. urb->error_count++;
  1792. } else {
  1793. desc->status = 0;
  1794. desc->actual_length = desc->length - SITD_LENGTH(t);
  1795. urb->actual_length += desc->actual_length;
  1796. }
  1797. /* handle completion now? */
  1798. if ((urb_index + 1) != urb->number_of_packets)
  1799. goto done;
  1800. /* ASSERT: it's really the last sitd for this urb
  1801. list_for_each_entry (sitd, &stream->td_list, sitd_list)
  1802. BUG_ON (sitd->urb == urb);
  1803. */
  1804. /* give urb back to the driver; completion often (re)submits */
  1805. dev = urb->dev;
  1806. ehci_urb_done(ehci, urb, 0);
  1807. retval = true;
  1808. urb = NULL;
  1809. --ehci->isoc_count;
  1810. disable_periodic(ehci);
  1811. ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
  1812. if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
  1813. if (ehci->amd_pll_fix == 1)
  1814. usb_amd_quirk_pll_enable();
  1815. }
  1816. if (list_is_singular(&stream->td_list))
  1817. ehci_to_hcd(ehci)->self.bandwidth_allocated
  1818. -= stream->bandwidth;
  1819. done:
  1820. sitd->urb = NULL;
  1821. /* Add to the end of the free list for later reuse */
  1822. list_move_tail(&sitd->sitd_list, &stream->free_list);
  1823. /* Recycle the siTDs when the pipeline is empty (ep no longer in use) */
  1824. if (list_empty(&stream->td_list)) {
  1825. list_splice_tail_init(&stream->free_list,
  1826. &ehci->cached_sitd_list);
  1827. start_free_itds(ehci);
  1828. }
  1829. return retval;
  1830. }
  1831. static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb,
  1832. gfp_t mem_flags)
  1833. {
  1834. int status = -EINVAL;
  1835. unsigned long flags;
  1836. struct ehci_iso_stream *stream;
  1837. /* Get iso_stream head */
  1838. stream = iso_stream_find (ehci, urb);
  1839. if (stream == NULL) {
  1840. ehci_dbg (ehci, "can't get iso stream\n");
  1841. return -ENOMEM;
  1842. }
  1843. if (urb->interval != stream->interval) {
  1844. ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
  1845. stream->interval, urb->interval);
  1846. goto done;
  1847. }
  1848. #ifdef EHCI_URB_TRACE
  1849. ehci_dbg (ehci,
  1850. "submit %p dev%s ep%d%s-iso len %d\n",
  1851. urb, urb->dev->devpath,
  1852. usb_pipeendpoint (urb->pipe),
  1853. usb_pipein (urb->pipe) ? "in" : "out",
  1854. urb->transfer_buffer_length);
  1855. #endif
  1856. /* allocate SITDs */
  1857. status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
  1858. if (status < 0) {
  1859. ehci_dbg (ehci, "can't init sitds\n");
  1860. goto done;
  1861. }
  1862. /* schedule ... need to lock */
  1863. spin_lock_irqsave (&ehci->lock, flags);
  1864. if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
  1865. status = -ESHUTDOWN;
  1866. goto done_not_linked;
  1867. }
  1868. status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
  1869. if (unlikely(status))
  1870. goto done_not_linked;
  1871. status = iso_stream_schedule(ehci, urb, stream);
  1872. if (status == 0)
  1873. sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
  1874. else
  1875. usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
  1876. done_not_linked:
  1877. spin_unlock_irqrestore (&ehci->lock, flags);
  1878. done:
  1879. return status;
  1880. }
  1881. /*-------------------------------------------------------------------------*/
  1882. static void scan_isoc(struct ehci_hcd *ehci)
  1883. {
  1884. unsigned uf, now_frame, frame;
  1885. unsigned fmask = ehci->periodic_size - 1;
  1886. bool modified, live;
  1887. /*
  1888. * When running, scan from last scan point up to "now"
  1889. * else clean up by scanning everything that's left.
  1890. * Touches as few pages as possible: cache-friendly.
  1891. */
  1892. if (ehci->rh_state >= EHCI_RH_RUNNING) {
  1893. uf = ehci_read_frame_index(ehci);
  1894. now_frame = (uf >> 3) & fmask;
  1895. live = true;
  1896. } else {
  1897. now_frame = (ehci->last_iso_frame - 1) & fmask;
  1898. live = false;
  1899. }
  1900. ehci->now_frame = now_frame;
  1901. frame = ehci->last_iso_frame;
  1902. for (;;) {
  1903. union ehci_shadow q, *q_p;
  1904. __hc32 type, *hw_p;
  1905. restart:
  1906. /* scan each element in frame's queue for completions */
  1907. q_p = &ehci->pshadow [frame];
  1908. hw_p = &ehci->periodic [frame];
  1909. q.ptr = q_p->ptr;
  1910. type = Q_NEXT_TYPE(ehci, *hw_p);
  1911. modified = false;
  1912. while (q.ptr != NULL) {
  1913. switch (hc32_to_cpu(ehci, type)) {
  1914. case Q_TYPE_ITD:
  1915. /* If this ITD is still active, leave it for
  1916. * later processing ... check the next entry.
  1917. * No need to check for activity unless the
  1918. * frame is current.
  1919. */
  1920. if (frame == now_frame && live) {
  1921. rmb();
  1922. for (uf = 0; uf < 8; uf++) {
  1923. if (q.itd->hw_transaction[uf] &
  1924. ITD_ACTIVE(ehci))
  1925. break;
  1926. }
  1927. if (uf < 8) {
  1928. q_p = &q.itd->itd_next;
  1929. hw_p = &q.itd->hw_next;
  1930. type = Q_NEXT_TYPE(ehci,
  1931. q.itd->hw_next);
  1932. q = *q_p;
  1933. break;
  1934. }
  1935. }
  1936. /* Take finished ITDs out of the schedule
  1937. * and process them: recycle, maybe report
  1938. * URB completion. HC won't cache the
  1939. * pointer for much longer, if at all.
  1940. */
  1941. *q_p = q.itd->itd_next;
  1942. if (!ehci->use_dummy_qh ||
  1943. q.itd->hw_next != EHCI_LIST_END(ehci))
  1944. *hw_p = q.itd->hw_next;
  1945. else
  1946. *hw_p = ehci->dummy->qh_dma;
  1947. type = Q_NEXT_TYPE(ehci, q.itd->hw_next);
  1948. wmb();
  1949. modified = itd_complete (ehci, q.itd);
  1950. q = *q_p;
  1951. break;
  1952. case Q_TYPE_SITD:
  1953. /* If this SITD is still active, leave it for
  1954. * later processing ... check the next entry.
  1955. * No need to check for activity unless the
  1956. * frame is current.
  1957. */
  1958. if (((frame == now_frame) ||
  1959. (((frame + 1) & fmask) == now_frame))
  1960. && live
  1961. && (q.sitd->hw_results &
  1962. SITD_ACTIVE(ehci))) {
  1963. q_p = &q.sitd->sitd_next;
  1964. hw_p = &q.sitd->hw_next;
  1965. type = Q_NEXT_TYPE(ehci,
  1966. q.sitd->hw_next);
  1967. q = *q_p;
  1968. break;
  1969. }
  1970. /* Take finished SITDs out of the schedule
  1971. * and process them: recycle, maybe report
  1972. * URB completion.
  1973. */
  1974. *q_p = q.sitd->sitd_next;
  1975. if (!ehci->use_dummy_qh ||
  1976. q.sitd->hw_next != EHCI_LIST_END(ehci))
  1977. *hw_p = q.sitd->hw_next;
  1978. else
  1979. *hw_p = ehci->dummy->qh_dma;
  1980. type = Q_NEXT_TYPE(ehci, q.sitd->hw_next);
  1981. wmb();
  1982. modified = sitd_complete (ehci, q.sitd);
  1983. q = *q_p;
  1984. break;
  1985. default:
  1986. ehci_dbg(ehci, "corrupt type %d frame %d shadow %p\n",
  1987. type, frame, q.ptr);
  1988. // BUG ();
  1989. /* FALL THROUGH */
  1990. case Q_TYPE_QH:
  1991. case Q_TYPE_FSTN:
  1992. /* End of the iTDs and siTDs */
  1993. q.ptr = NULL;
  1994. break;
  1995. }
  1996. /* assume completion callbacks modify the queue */
  1997. if (unlikely(modified && ehci->isoc_count > 0))
  1998. goto restart;
  1999. }
  2000. /* Stop when we have reached the current frame */
  2001. if (frame == now_frame)
  2002. break;
  2003. /* The last frame may still have active siTDs */
  2004. ehci->last_iso_frame = frame;
  2005. frame = (frame + 1) & fmask;
  2006. }
  2007. }