video1394.c 42 KB

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  1. /*
  2. * video1394.c - video driver for OHCI 1394 boards
  3. * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
  4. * Peter Schlaile <udbz@rz.uni-karlsruhe.de>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software Foundation,
  18. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. *
  20. * NOTES:
  21. *
  22. * ioctl return codes:
  23. * EFAULT is only for invalid address for the argp
  24. * EINVAL for out of range values
  25. * EBUSY when trying to use an already used resource
  26. * ESRCH when trying to free/stop a not used resource
  27. * EAGAIN for resource allocation failure that could perhaps succeed later
  28. * ENOTTY for unsupported ioctl request
  29. *
  30. */
  31. #include <linux/config.h>
  32. #include <linux/kernel.h>
  33. #include <linux/list.h>
  34. #include <linux/slab.h>
  35. #include <linux/interrupt.h>
  36. #include <linux/wait.h>
  37. #include <linux/errno.h>
  38. #include <linux/module.h>
  39. #include <linux/init.h>
  40. #include <linux/pci.h>
  41. #include <linux/fs.h>
  42. #include <linux/poll.h>
  43. #include <linux/smp_lock.h>
  44. #include <linux/delay.h>
  45. #include <linux/devfs_fs_kernel.h>
  46. #include <linux/bitops.h>
  47. #include <linux/types.h>
  48. #include <linux/vmalloc.h>
  49. #include <linux/timex.h>
  50. #include <linux/mm.h>
  51. #include <linux/ioctl32.h>
  52. #include <linux/compat.h>
  53. #include <linux/cdev.h>
  54. #include "ieee1394.h"
  55. #include "ieee1394_types.h"
  56. #include "hosts.h"
  57. #include "ieee1394_core.h"
  58. #include "highlevel.h"
  59. #include "video1394.h"
  60. #include "nodemgr.h"
  61. #include "dma.h"
  62. #include "ohci1394.h"
  63. #define ISO_CHANNELS 64
  64. struct it_dma_prg {
  65. struct dma_cmd begin;
  66. quadlet_t data[4];
  67. struct dma_cmd end;
  68. quadlet_t pad[4]; /* FIXME: quick hack for memory alignment */
  69. };
  70. struct dma_iso_ctx {
  71. struct ti_ohci *ohci;
  72. int type; /* OHCI_ISO_TRANSMIT or OHCI_ISO_RECEIVE */
  73. struct ohci1394_iso_tasklet iso_tasklet;
  74. int channel;
  75. int ctx;
  76. int last_buffer;
  77. int * next_buffer; /* For ISO Transmit of video packets
  78. to write the correct SYT field
  79. into the next block */
  80. unsigned int num_desc;
  81. unsigned int buf_size;
  82. unsigned int frame_size;
  83. unsigned int packet_size;
  84. unsigned int left_size;
  85. unsigned int nb_cmd;
  86. struct dma_region dma;
  87. struct dma_prog_region *prg_reg;
  88. struct dma_cmd **ir_prg;
  89. struct it_dma_prg **it_prg;
  90. unsigned int *buffer_status;
  91. unsigned int *buffer_prg_assignment;
  92. struct timeval *buffer_time; /* time when the buffer was received */
  93. unsigned int *last_used_cmd; /* For ISO Transmit with
  94. variable sized packets only ! */
  95. int ctrlClear;
  96. int ctrlSet;
  97. int cmdPtr;
  98. int ctxMatch;
  99. wait_queue_head_t waitq;
  100. spinlock_t lock;
  101. unsigned int syt_offset;
  102. int flags;
  103. struct list_head link;
  104. };
  105. struct file_ctx {
  106. struct ti_ohci *ohci;
  107. struct list_head context_list;
  108. struct dma_iso_ctx *current_ctx;
  109. };
  110. #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
  111. #define VIDEO1394_DEBUG
  112. #endif
  113. #ifdef DBGMSG
  114. #undef DBGMSG
  115. #endif
  116. #ifdef VIDEO1394_DEBUG
  117. #define DBGMSG(card, fmt, args...) \
  118. printk(KERN_INFO "video1394_%d: " fmt "\n" , card , ## args)
  119. #else
  120. #define DBGMSG(card, fmt, args...)
  121. #endif
  122. /* print general (card independent) information */
  123. #define PRINT_G(level, fmt, args...) \
  124. printk(level "video1394: " fmt "\n" , ## args)
  125. /* print card specific information */
  126. #define PRINT(level, card, fmt, args...) \
  127. printk(level "video1394_%d: " fmt "\n" , card , ## args)
  128. static void wakeup_dma_ir_ctx(unsigned long l);
  129. static void wakeup_dma_it_ctx(unsigned long l);
  130. static struct hpsb_highlevel video1394_highlevel;
  131. static int free_dma_iso_ctx(struct dma_iso_ctx *d)
  132. {
  133. int i;
  134. DBGMSG(d->ohci->host->id, "Freeing dma_iso_ctx %d", d->ctx);
  135. ohci1394_stop_context(d->ohci, d->ctrlClear, NULL);
  136. if (d->iso_tasklet.link.next != NULL)
  137. ohci1394_unregister_iso_tasklet(d->ohci, &d->iso_tasklet);
  138. dma_region_free(&d->dma);
  139. if (d->prg_reg) {
  140. for (i = 0; i < d->num_desc; i++)
  141. dma_prog_region_free(&d->prg_reg[i]);
  142. kfree(d->prg_reg);
  143. }
  144. kfree(d->ir_prg);
  145. kfree(d->it_prg);
  146. kfree(d->buffer_status);
  147. kfree(d->buffer_prg_assignment);
  148. kfree(d->buffer_time);
  149. kfree(d->last_used_cmd);
  150. kfree(d->next_buffer);
  151. list_del(&d->link);
  152. kfree(d);
  153. return 0;
  154. }
  155. static struct dma_iso_ctx *
  156. alloc_dma_iso_ctx(struct ti_ohci *ohci, int type, int num_desc,
  157. int buf_size, int channel, unsigned int packet_size)
  158. {
  159. struct dma_iso_ctx *d;
  160. int i;
  161. d = kzalloc(sizeof(*d), GFP_KERNEL);
  162. if (!d) {
  163. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma_iso_ctx");
  164. return NULL;
  165. }
  166. d->ohci = ohci;
  167. d->type = type;
  168. d->channel = channel;
  169. d->num_desc = num_desc;
  170. d->frame_size = buf_size;
  171. d->buf_size = PAGE_ALIGN(buf_size);
  172. d->last_buffer = -1;
  173. INIT_LIST_HEAD(&d->link);
  174. init_waitqueue_head(&d->waitq);
  175. /* Init the regions for easy cleanup */
  176. dma_region_init(&d->dma);
  177. if (dma_region_alloc(&d->dma, (d->num_desc - 1) * d->buf_size, ohci->dev,
  178. PCI_DMA_BIDIRECTIONAL)) {
  179. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma buffer");
  180. free_dma_iso_ctx(d);
  181. return NULL;
  182. }
  183. if (type == OHCI_ISO_RECEIVE)
  184. ohci1394_init_iso_tasklet(&d->iso_tasklet, type,
  185. wakeup_dma_ir_ctx,
  186. (unsigned long) d);
  187. else
  188. ohci1394_init_iso_tasklet(&d->iso_tasklet, type,
  189. wakeup_dma_it_ctx,
  190. (unsigned long) d);
  191. if (ohci1394_register_iso_tasklet(ohci, &d->iso_tasklet) < 0) {
  192. PRINT(KERN_ERR, ohci->host->id, "no free iso %s contexts",
  193. type == OHCI_ISO_RECEIVE ? "receive" : "transmit");
  194. free_dma_iso_ctx(d);
  195. return NULL;
  196. }
  197. d->ctx = d->iso_tasklet.context;
  198. d->prg_reg = kmalloc(d->num_desc * sizeof(*d->prg_reg), GFP_KERNEL);
  199. if (!d->prg_reg) {
  200. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate ir prg regs");
  201. free_dma_iso_ctx(d);
  202. return NULL;
  203. }
  204. /* Makes for easier cleanup */
  205. for (i = 0; i < d->num_desc; i++)
  206. dma_prog_region_init(&d->prg_reg[i]);
  207. if (type == OHCI_ISO_RECEIVE) {
  208. d->ctrlSet = OHCI1394_IsoRcvContextControlSet+32*d->ctx;
  209. d->ctrlClear = OHCI1394_IsoRcvContextControlClear+32*d->ctx;
  210. d->cmdPtr = OHCI1394_IsoRcvCommandPtr+32*d->ctx;
  211. d->ctxMatch = OHCI1394_IsoRcvContextMatch+32*d->ctx;
  212. d->ir_prg = kzalloc(d->num_desc * sizeof(*d->ir_prg),
  213. GFP_KERNEL);
  214. if (!d->ir_prg) {
  215. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg");
  216. free_dma_iso_ctx(d);
  217. return NULL;
  218. }
  219. d->nb_cmd = d->buf_size / PAGE_SIZE + 1;
  220. d->left_size = (d->frame_size % PAGE_SIZE) ?
  221. d->frame_size % PAGE_SIZE : PAGE_SIZE;
  222. for (i = 0;i < d->num_desc; i++) {
  223. if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd *
  224. sizeof(struct dma_cmd), ohci->dev)) {
  225. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg");
  226. free_dma_iso_ctx(d);
  227. return NULL;
  228. }
  229. d->ir_prg[i] = (struct dma_cmd *)d->prg_reg[i].kvirt;
  230. }
  231. } else { /* OHCI_ISO_TRANSMIT */
  232. d->ctrlSet = OHCI1394_IsoXmitContextControlSet+16*d->ctx;
  233. d->ctrlClear = OHCI1394_IsoXmitContextControlClear+16*d->ctx;
  234. d->cmdPtr = OHCI1394_IsoXmitCommandPtr+16*d->ctx;
  235. d->it_prg = kzalloc(d->num_desc * sizeof(*d->it_prg),
  236. GFP_KERNEL);
  237. if (!d->it_prg) {
  238. PRINT(KERN_ERR, ohci->host->id,
  239. "Failed to allocate dma it prg");
  240. free_dma_iso_ctx(d);
  241. return NULL;
  242. }
  243. d->packet_size = packet_size;
  244. if (PAGE_SIZE % packet_size || packet_size>4096) {
  245. PRINT(KERN_ERR, ohci->host->id,
  246. "Packet size %d (page_size: %ld) "
  247. "not yet supported\n",
  248. packet_size, PAGE_SIZE);
  249. free_dma_iso_ctx(d);
  250. return NULL;
  251. }
  252. d->nb_cmd = d->frame_size / d->packet_size;
  253. if (d->frame_size % d->packet_size) {
  254. d->nb_cmd++;
  255. d->left_size = d->frame_size % d->packet_size;
  256. } else
  257. d->left_size = d->packet_size;
  258. for (i = 0; i < d->num_desc; i++) {
  259. if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd *
  260. sizeof(struct it_dma_prg), ohci->dev)) {
  261. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma it prg");
  262. free_dma_iso_ctx(d);
  263. return NULL;
  264. }
  265. d->it_prg[i] = (struct it_dma_prg *)d->prg_reg[i].kvirt;
  266. }
  267. }
  268. d->buffer_status =
  269. kzalloc(d->num_desc * sizeof(*d->buffer_status), GFP_KERNEL);
  270. d->buffer_prg_assignment =
  271. kzalloc(d->num_desc * sizeof(*d->buffer_prg_assignment), GFP_KERNEL);
  272. d->buffer_time =
  273. kzalloc(d->num_desc * sizeof(*d->buffer_time), GFP_KERNEL);
  274. d->last_used_cmd =
  275. kzalloc(d->num_desc * sizeof(*d->last_used_cmd), GFP_KERNEL);
  276. d->next_buffer =
  277. kzalloc(d->num_desc * sizeof(*d->next_buffer), GFP_KERNEL);
  278. if (!d->buffer_status || !d->buffer_prg_assignment || !d->buffer_time ||
  279. !d->last_used_cmd || !d->next_buffer) {
  280. PRINT(KERN_ERR, ohci->host->id,
  281. "Failed to allocate dma_iso_ctx member");
  282. free_dma_iso_ctx(d);
  283. return NULL;
  284. }
  285. spin_lock_init(&d->lock);
  286. PRINT(KERN_INFO, ohci->host->id, "Iso %s DMA: %d buffers "
  287. "of size %d allocated for a frame size %d, each with %d prgs",
  288. (type == OHCI_ISO_RECEIVE) ? "receive" : "transmit",
  289. d->num_desc - 1, d->buf_size, d->frame_size, d->nb_cmd);
  290. return d;
  291. }
  292. static void reset_ir_status(struct dma_iso_ctx *d, int n)
  293. {
  294. int i;
  295. d->ir_prg[n][0].status = cpu_to_le32(4);
  296. d->ir_prg[n][1].status = cpu_to_le32(PAGE_SIZE-4);
  297. for (i = 2; i < d->nb_cmd - 1; i++)
  298. d->ir_prg[n][i].status = cpu_to_le32(PAGE_SIZE);
  299. d->ir_prg[n][i].status = cpu_to_le32(d->left_size);
  300. }
  301. static void reprogram_dma_ir_prg(struct dma_iso_ctx *d, int n, int buffer, int flags)
  302. {
  303. struct dma_cmd *ir_prg = d->ir_prg[n];
  304. unsigned long buf = (unsigned long)d->dma.kvirt + buffer * d->buf_size;
  305. int i;
  306. d->buffer_prg_assignment[n] = buffer;
  307. ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf -
  308. (unsigned long)d->dma.kvirt));
  309. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  310. (buf + 4) - (unsigned long)d->dma.kvirt));
  311. for (i=2;i<d->nb_cmd-1;i++) {
  312. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  313. (buf+(i-1)*PAGE_SIZE) -
  314. (unsigned long)d->dma.kvirt));
  315. }
  316. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  317. DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size);
  318. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  319. (buf+(i-1)*PAGE_SIZE) - (unsigned long)d->dma.kvirt));
  320. }
  321. static void initialize_dma_ir_prg(struct dma_iso_ctx *d, int n, int flags)
  322. {
  323. struct dma_cmd *ir_prg = d->ir_prg[n];
  324. struct dma_prog_region *ir_reg = &d->prg_reg[n];
  325. unsigned long buf = (unsigned long)d->dma.kvirt;
  326. int i;
  327. /* the first descriptor will read only 4 bytes */
  328. ir_prg[0].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  329. DMA_CTL_BRANCH | 4);
  330. /* set the sync flag */
  331. if (flags & VIDEO1394_SYNC_FRAMES)
  332. ir_prg[0].control |= cpu_to_le32(DMA_CTL_WAIT);
  333. ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf -
  334. (unsigned long)d->dma.kvirt));
  335. ir_prg[0].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  336. 1 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  337. /* If there is *not* only one DMA page per frame (hence, d->nb_cmd==2) */
  338. if (d->nb_cmd > 2) {
  339. /* The second descriptor will read PAGE_SIZE-4 bytes */
  340. ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  341. DMA_CTL_BRANCH | (PAGE_SIZE-4));
  342. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf + 4) -
  343. (unsigned long)d->dma.kvirt));
  344. ir_prg[1].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  345. 2 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  346. for (i = 2; i < d->nb_cmd - 1; i++) {
  347. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  348. DMA_CTL_BRANCH | PAGE_SIZE);
  349. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  350. (buf+(i-1)*PAGE_SIZE) -
  351. (unsigned long)d->dma.kvirt));
  352. ir_prg[i].branchAddress =
  353. cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  354. (i + 1) * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  355. }
  356. /* The last descriptor will generate an interrupt */
  357. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  358. DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size);
  359. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  360. (buf+(i-1)*PAGE_SIZE) -
  361. (unsigned long)d->dma.kvirt));
  362. } else {
  363. /* Only one DMA page is used. Read d->left_size immediately and */
  364. /* generate an interrupt as this is also the last page. */
  365. ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  366. DMA_CTL_IRQ | DMA_CTL_BRANCH | (d->left_size-4));
  367. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  368. (buf + 4) - (unsigned long)d->dma.kvirt));
  369. }
  370. }
  371. static void initialize_dma_ir_ctx(struct dma_iso_ctx *d, int tag, int flags)
  372. {
  373. struct ti_ohci *ohci = (struct ti_ohci *)d->ohci;
  374. int i;
  375. d->flags = flags;
  376. ohci1394_stop_context(ohci, d->ctrlClear, NULL);
  377. for (i=0;i<d->num_desc;i++) {
  378. initialize_dma_ir_prg(d, i, flags);
  379. reset_ir_status(d, i);
  380. }
  381. /* reset the ctrl register */
  382. reg_write(ohci, d->ctrlClear, 0xf0000000);
  383. /* Set bufferFill */
  384. reg_write(ohci, d->ctrlSet, 0x80000000);
  385. /* Set isoch header */
  386. if (flags & VIDEO1394_INCLUDE_ISO_HEADERS)
  387. reg_write(ohci, d->ctrlSet, 0x40000000);
  388. /* Set the context match register to match on all tags,
  389. sync for sync tag, and listen to d->channel */
  390. reg_write(ohci, d->ctxMatch, 0xf0000000|((tag&0xf)<<8)|d->channel);
  391. /* Set up isoRecvIntMask to generate interrupts */
  392. reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1<<d->ctx);
  393. }
  394. /* find which context is listening to this channel */
  395. static struct dma_iso_ctx *
  396. find_ctx(struct list_head *list, int type, int channel)
  397. {
  398. struct dma_iso_ctx *ctx;
  399. list_for_each_entry(ctx, list, link) {
  400. if (ctx->type == type && ctx->channel == channel)
  401. return ctx;
  402. }
  403. return NULL;
  404. }
  405. static void wakeup_dma_ir_ctx(unsigned long l)
  406. {
  407. struct dma_iso_ctx *d = (struct dma_iso_ctx *) l;
  408. int i;
  409. spin_lock(&d->lock);
  410. for (i = 0; i < d->num_desc; i++) {
  411. if (d->ir_prg[i][d->nb_cmd-1].status & cpu_to_le32(0xFFFF0000)) {
  412. reset_ir_status(d, i);
  413. d->buffer_status[d->buffer_prg_assignment[i]] = VIDEO1394_BUFFER_READY;
  414. do_gettimeofday(&d->buffer_time[d->buffer_prg_assignment[i]]);
  415. }
  416. }
  417. spin_unlock(&d->lock);
  418. if (waitqueue_active(&d->waitq))
  419. wake_up_interruptible(&d->waitq);
  420. }
  421. static inline void put_timestamp(struct ti_ohci *ohci, struct dma_iso_ctx * d,
  422. int n)
  423. {
  424. unsigned char* buf = d->dma.kvirt + n * d->buf_size;
  425. u32 cycleTimer;
  426. u32 timeStamp;
  427. if (n == -1) {
  428. return;
  429. }
  430. cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
  431. timeStamp = ((cycleTimer & 0x0fff) + d->syt_offset); /* 11059 = 450 us */
  432. timeStamp = (timeStamp % 3072 + ((timeStamp / 3072) << 12)
  433. + (cycleTimer & 0xf000)) & 0xffff;
  434. buf[6] = timeStamp >> 8;
  435. buf[7] = timeStamp & 0xff;
  436. /* if first packet is empty packet, then put timestamp into the next full one too */
  437. if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) {
  438. buf += d->packet_size;
  439. buf[6] = timeStamp >> 8;
  440. buf[7] = timeStamp & 0xff;
  441. }
  442. /* do the next buffer frame too in case of irq latency */
  443. n = d->next_buffer[n];
  444. if (n == -1) {
  445. return;
  446. }
  447. buf = d->dma.kvirt + n * d->buf_size;
  448. timeStamp += (d->last_used_cmd[n] << 12) & 0xffff;
  449. buf[6] = timeStamp >> 8;
  450. buf[7] = timeStamp & 0xff;
  451. /* if first packet is empty packet, then put timestamp into the next full one too */
  452. if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) {
  453. buf += d->packet_size;
  454. buf[6] = timeStamp >> 8;
  455. buf[7] = timeStamp & 0xff;
  456. }
  457. #if 0
  458. printk("curr: %d, next: %d, cycleTimer: %08x timeStamp: %08x\n",
  459. curr, n, cycleTimer, timeStamp);
  460. #endif
  461. }
  462. static void wakeup_dma_it_ctx(unsigned long l)
  463. {
  464. struct dma_iso_ctx *d = (struct dma_iso_ctx *) l;
  465. struct ti_ohci *ohci = d->ohci;
  466. int i;
  467. spin_lock(&d->lock);
  468. for (i = 0; i < d->num_desc; i++) {
  469. if (d->it_prg[i][d->last_used_cmd[i]].end.status &
  470. cpu_to_le32(0xFFFF0000)) {
  471. int next = d->next_buffer[i];
  472. put_timestamp(ohci, d, next);
  473. d->it_prg[i][d->last_used_cmd[i]].end.status = 0;
  474. d->buffer_status[d->buffer_prg_assignment[i]] = VIDEO1394_BUFFER_READY;
  475. }
  476. }
  477. spin_unlock(&d->lock);
  478. if (waitqueue_active(&d->waitq))
  479. wake_up_interruptible(&d->waitq);
  480. }
  481. static void reprogram_dma_it_prg(struct dma_iso_ctx *d, int n, int buffer)
  482. {
  483. struct it_dma_prg *it_prg = d->it_prg[n];
  484. unsigned long buf = (unsigned long)d->dma.kvirt + buffer * d->buf_size;
  485. int i;
  486. d->buffer_prg_assignment[n] = buffer;
  487. for (i=0;i<d->nb_cmd;i++) {
  488. it_prg[i].end.address =
  489. cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  490. (buf+i*d->packet_size) - (unsigned long)d->dma.kvirt));
  491. }
  492. }
  493. static void initialize_dma_it_prg(struct dma_iso_ctx *d, int n, int sync_tag)
  494. {
  495. struct it_dma_prg *it_prg = d->it_prg[n];
  496. struct dma_prog_region *it_reg = &d->prg_reg[n];
  497. unsigned long buf = (unsigned long)d->dma.kvirt;
  498. int i;
  499. d->last_used_cmd[n] = d->nb_cmd - 1;
  500. for (i=0;i<d->nb_cmd;i++) {
  501. it_prg[i].begin.control = cpu_to_le32(DMA_CTL_OUTPUT_MORE |
  502. DMA_CTL_IMMEDIATE | 8) ;
  503. it_prg[i].begin.address = 0;
  504. it_prg[i].begin.status = 0;
  505. it_prg[i].data[0] = cpu_to_le32(
  506. (IEEE1394_SPEED_100 << 16)
  507. | (/* tag */ 1 << 14)
  508. | (d->channel << 8)
  509. | (TCODE_ISO_DATA << 4));
  510. if (i==0) it_prg[i].data[0] |= cpu_to_le32(sync_tag);
  511. it_prg[i].data[1] = cpu_to_le32(d->packet_size << 16);
  512. it_prg[i].data[2] = 0;
  513. it_prg[i].data[3] = 0;
  514. it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST |
  515. DMA_CTL_BRANCH);
  516. it_prg[i].end.address =
  517. cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf+i*d->packet_size) -
  518. (unsigned long)d->dma.kvirt));
  519. if (i<d->nb_cmd-1) {
  520. it_prg[i].end.control |= cpu_to_le32(d->packet_size);
  521. it_prg[i].begin.branchAddress =
  522. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  523. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  524. it_prg[i].end.branchAddress =
  525. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  526. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  527. } else {
  528. /* the last prg generates an interrupt */
  529. it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE |
  530. DMA_CTL_IRQ | d->left_size);
  531. /* the last prg doesn't branch */
  532. it_prg[i].begin.branchAddress = 0;
  533. it_prg[i].end.branchAddress = 0;
  534. }
  535. it_prg[i].end.status = 0;
  536. }
  537. }
  538. static void initialize_dma_it_prg_var_packet_queue(
  539. struct dma_iso_ctx *d, int n, unsigned int * packet_sizes,
  540. struct ti_ohci *ohci)
  541. {
  542. struct it_dma_prg *it_prg = d->it_prg[n];
  543. struct dma_prog_region *it_reg = &d->prg_reg[n];
  544. int i;
  545. #if 0
  546. if (n != -1) {
  547. put_timestamp(ohci, d, n);
  548. }
  549. #endif
  550. d->last_used_cmd[n] = d->nb_cmd - 1;
  551. for (i = 0; i < d->nb_cmd; i++) {
  552. unsigned int size;
  553. if (packet_sizes[i] > d->packet_size) {
  554. size = d->packet_size;
  555. } else {
  556. size = packet_sizes[i];
  557. }
  558. it_prg[i].data[1] = cpu_to_le32(size << 16);
  559. it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST | DMA_CTL_BRANCH);
  560. if (i < d->nb_cmd-1 && packet_sizes[i+1] != 0) {
  561. it_prg[i].end.control |= cpu_to_le32(size);
  562. it_prg[i].begin.branchAddress =
  563. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  564. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  565. it_prg[i].end.branchAddress =
  566. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  567. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  568. } else {
  569. /* the last prg generates an interrupt */
  570. it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE |
  571. DMA_CTL_IRQ | size);
  572. /* the last prg doesn't branch */
  573. it_prg[i].begin.branchAddress = 0;
  574. it_prg[i].end.branchAddress = 0;
  575. d->last_used_cmd[n] = i;
  576. break;
  577. }
  578. }
  579. }
  580. static void initialize_dma_it_ctx(struct dma_iso_ctx *d, int sync_tag,
  581. unsigned int syt_offset, int flags)
  582. {
  583. struct ti_ohci *ohci = (struct ti_ohci *)d->ohci;
  584. int i;
  585. d->flags = flags;
  586. d->syt_offset = (syt_offset == 0 ? 11000 : syt_offset);
  587. ohci1394_stop_context(ohci, d->ctrlClear, NULL);
  588. for (i=0;i<d->num_desc;i++)
  589. initialize_dma_it_prg(d, i, sync_tag);
  590. /* Set up isoRecvIntMask to generate interrupts */
  591. reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1<<d->ctx);
  592. }
  593. static inline unsigned video1394_buffer_state(struct dma_iso_ctx *d,
  594. unsigned int buffer)
  595. {
  596. unsigned long flags;
  597. unsigned int ret;
  598. spin_lock_irqsave(&d->lock, flags);
  599. ret = d->buffer_status[buffer];
  600. spin_unlock_irqrestore(&d->lock, flags);
  601. return ret;
  602. }
  603. static int __video1394_ioctl(struct file *file,
  604. unsigned int cmd, unsigned long arg)
  605. {
  606. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  607. struct ti_ohci *ohci = ctx->ohci;
  608. unsigned long flags;
  609. void __user *argp = (void __user *)arg;
  610. switch(cmd)
  611. {
  612. case VIDEO1394_IOC_LISTEN_CHANNEL:
  613. case VIDEO1394_IOC_TALK_CHANNEL:
  614. {
  615. struct video1394_mmap v;
  616. u64 mask;
  617. struct dma_iso_ctx *d;
  618. int i;
  619. if (copy_from_user(&v, argp, sizeof(v)))
  620. return -EFAULT;
  621. /* if channel < 0, find lowest available one */
  622. if (v.channel < 0) {
  623. mask = (u64)0x1;
  624. for (i=0; ; i++) {
  625. if (i == ISO_CHANNELS) {
  626. PRINT(KERN_ERR, ohci->host->id,
  627. "No free channel found");
  628. return EAGAIN;
  629. }
  630. if (!(ohci->ISO_channel_usage & mask)) {
  631. v.channel = i;
  632. PRINT(KERN_INFO, ohci->host->id, "Found free channel %d", i);
  633. break;
  634. }
  635. mask = mask << 1;
  636. }
  637. } else if (v.channel >= ISO_CHANNELS) {
  638. PRINT(KERN_ERR, ohci->host->id,
  639. "Iso channel %d out of bounds", v.channel);
  640. return -EINVAL;
  641. } else {
  642. mask = (u64)0x1<<v.channel;
  643. }
  644. PRINT(KERN_INFO, ohci->host->id, "mask: %08X%08X usage: %08X%08X\n",
  645. (u32)(mask>>32),(u32)(mask&0xffffffff),
  646. (u32)(ohci->ISO_channel_usage>>32),
  647. (u32)(ohci->ISO_channel_usage&0xffffffff));
  648. if (ohci->ISO_channel_usage & mask) {
  649. PRINT(KERN_ERR, ohci->host->id,
  650. "Channel %d is already taken", v.channel);
  651. return -EBUSY;
  652. }
  653. if (v.buf_size == 0 || v.buf_size > VIDEO1394_MAX_SIZE) {
  654. PRINT(KERN_ERR, ohci->host->id,
  655. "Invalid %d length buffer requested",v.buf_size);
  656. return -EINVAL;
  657. }
  658. if (v.nb_buffers == 0 || v.nb_buffers > VIDEO1394_MAX_SIZE) {
  659. PRINT(KERN_ERR, ohci->host->id,
  660. "Invalid %d buffers requested",v.nb_buffers);
  661. return -EINVAL;
  662. }
  663. if (v.nb_buffers * v.buf_size > VIDEO1394_MAX_SIZE) {
  664. PRINT(KERN_ERR, ohci->host->id,
  665. "%d buffers of size %d bytes is too big",
  666. v.nb_buffers, v.buf_size);
  667. return -EINVAL;
  668. }
  669. if (cmd == VIDEO1394_IOC_LISTEN_CHANNEL) {
  670. d = alloc_dma_iso_ctx(ohci, OHCI_ISO_RECEIVE,
  671. v.nb_buffers + 1, v.buf_size,
  672. v.channel, 0);
  673. if (d == NULL) {
  674. PRINT(KERN_ERR, ohci->host->id,
  675. "Couldn't allocate ir context");
  676. return -EAGAIN;
  677. }
  678. initialize_dma_ir_ctx(d, v.sync_tag, v.flags);
  679. ctx->current_ctx = d;
  680. v.buf_size = d->buf_size;
  681. list_add_tail(&d->link, &ctx->context_list);
  682. PRINT(KERN_INFO, ohci->host->id,
  683. "iso context %d listen on channel %d",
  684. d->ctx, v.channel);
  685. }
  686. else {
  687. d = alloc_dma_iso_ctx(ohci, OHCI_ISO_TRANSMIT,
  688. v.nb_buffers + 1, v.buf_size,
  689. v.channel, v.packet_size);
  690. if (d == NULL) {
  691. PRINT(KERN_ERR, ohci->host->id,
  692. "Couldn't allocate it context");
  693. return -EAGAIN;
  694. }
  695. initialize_dma_it_ctx(d, v.sync_tag,
  696. v.syt_offset, v.flags);
  697. ctx->current_ctx = d;
  698. v.buf_size = d->buf_size;
  699. list_add_tail(&d->link, &ctx->context_list);
  700. PRINT(KERN_INFO, ohci->host->id,
  701. "Iso context %d talk on channel %d", d->ctx,
  702. v.channel);
  703. }
  704. if (copy_to_user(argp, &v, sizeof(v))) {
  705. /* FIXME : free allocated dma resources */
  706. return -EFAULT;
  707. }
  708. ohci->ISO_channel_usage |= mask;
  709. return 0;
  710. }
  711. case VIDEO1394_IOC_UNLISTEN_CHANNEL:
  712. case VIDEO1394_IOC_UNTALK_CHANNEL:
  713. {
  714. int channel;
  715. u64 mask;
  716. struct dma_iso_ctx *d;
  717. if (copy_from_user(&channel, argp, sizeof(int)))
  718. return -EFAULT;
  719. if (channel < 0 || channel >= ISO_CHANNELS) {
  720. PRINT(KERN_ERR, ohci->host->id,
  721. "Iso channel %d out of bound", channel);
  722. return -EINVAL;
  723. }
  724. mask = (u64)0x1<<channel;
  725. if (!(ohci->ISO_channel_usage & mask)) {
  726. PRINT(KERN_ERR, ohci->host->id,
  727. "Channel %d is not being used", channel);
  728. return -ESRCH;
  729. }
  730. /* Mark this channel as unused */
  731. ohci->ISO_channel_usage &= ~mask;
  732. if (cmd == VIDEO1394_IOC_UNLISTEN_CHANNEL)
  733. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, channel);
  734. else
  735. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, channel);
  736. if (d == NULL) return -ESRCH;
  737. PRINT(KERN_INFO, ohci->host->id, "Iso context %d "
  738. "stop talking on channel %d", d->ctx, channel);
  739. free_dma_iso_ctx(d);
  740. return 0;
  741. }
  742. case VIDEO1394_IOC_LISTEN_QUEUE_BUFFER:
  743. {
  744. struct video1394_wait v;
  745. struct dma_iso_ctx *d;
  746. int next_prg;
  747. if (copy_from_user(&v, argp, sizeof(v)))
  748. return -EFAULT;
  749. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel);
  750. if (d == NULL) return -EFAULT;
  751. if ((v.buffer<0) || (v.buffer>=d->num_desc - 1)) {
  752. PRINT(KERN_ERR, ohci->host->id,
  753. "Buffer %d out of range",v.buffer);
  754. return -EINVAL;
  755. }
  756. spin_lock_irqsave(&d->lock,flags);
  757. if (d->buffer_status[v.buffer]==VIDEO1394_BUFFER_QUEUED) {
  758. PRINT(KERN_ERR, ohci->host->id,
  759. "Buffer %d is already used",v.buffer);
  760. spin_unlock_irqrestore(&d->lock,flags);
  761. return -EBUSY;
  762. }
  763. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED;
  764. next_prg = (d->last_buffer + 1) % d->num_desc;
  765. if (d->last_buffer>=0)
  766. d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress =
  767. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 0)
  768. & 0xfffffff0) | 0x1);
  769. d->last_buffer = next_prg;
  770. reprogram_dma_ir_prg(d, d->last_buffer, v.buffer, d->flags);
  771. d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress = 0;
  772. spin_unlock_irqrestore(&d->lock,flags);
  773. if (!(reg_read(ohci, d->ctrlSet) & 0x8000))
  774. {
  775. DBGMSG(ohci->host->id, "Starting iso DMA ctx=%d",d->ctx);
  776. /* Tell the controller where the first program is */
  777. reg_write(ohci, d->cmdPtr,
  778. dma_prog_region_offset_to_bus(&d->prg_reg[d->last_buffer], 0) | 0x1);
  779. /* Run IR context */
  780. reg_write(ohci, d->ctrlSet, 0x8000);
  781. }
  782. else {
  783. /* Wake up dma context if necessary */
  784. if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
  785. PRINT(KERN_INFO, ohci->host->id,
  786. "Waking up iso dma ctx=%d", d->ctx);
  787. reg_write(ohci, d->ctrlSet, 0x1000);
  788. }
  789. }
  790. return 0;
  791. }
  792. case VIDEO1394_IOC_LISTEN_WAIT_BUFFER:
  793. case VIDEO1394_IOC_LISTEN_POLL_BUFFER:
  794. {
  795. struct video1394_wait v;
  796. struct dma_iso_ctx *d;
  797. int i = 0;
  798. if (copy_from_user(&v, argp, sizeof(v)))
  799. return -EFAULT;
  800. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel);
  801. if (d == NULL) return -EFAULT;
  802. if ((v.buffer<0) || (v.buffer>d->num_desc - 1)) {
  803. PRINT(KERN_ERR, ohci->host->id,
  804. "Buffer %d out of range",v.buffer);
  805. return -EINVAL;
  806. }
  807. /*
  808. * I change the way it works so that it returns
  809. * the last received frame.
  810. */
  811. spin_lock_irqsave(&d->lock, flags);
  812. switch(d->buffer_status[v.buffer]) {
  813. case VIDEO1394_BUFFER_READY:
  814. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  815. break;
  816. case VIDEO1394_BUFFER_QUEUED:
  817. if (cmd == VIDEO1394_IOC_LISTEN_POLL_BUFFER) {
  818. /* for polling, return error code EINTR */
  819. spin_unlock_irqrestore(&d->lock, flags);
  820. return -EINTR;
  821. }
  822. spin_unlock_irqrestore(&d->lock, flags);
  823. wait_event_interruptible(d->waitq,
  824. video1394_buffer_state(d, v.buffer) ==
  825. VIDEO1394_BUFFER_READY);
  826. if (signal_pending(current))
  827. return -EINTR;
  828. spin_lock_irqsave(&d->lock, flags);
  829. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  830. break;
  831. default:
  832. PRINT(KERN_ERR, ohci->host->id,
  833. "Buffer %d is not queued",v.buffer);
  834. spin_unlock_irqrestore(&d->lock, flags);
  835. return -ESRCH;
  836. }
  837. /* set time of buffer */
  838. v.filltime = d->buffer_time[v.buffer];
  839. /*
  840. * Look ahead to see how many more buffers have been received
  841. */
  842. i=0;
  843. while (d->buffer_status[(v.buffer+1)%(d->num_desc - 1)]==
  844. VIDEO1394_BUFFER_READY) {
  845. v.buffer=(v.buffer+1)%(d->num_desc - 1);
  846. i++;
  847. }
  848. spin_unlock_irqrestore(&d->lock, flags);
  849. v.buffer=i;
  850. if (copy_to_user(argp, &v, sizeof(v)))
  851. return -EFAULT;
  852. return 0;
  853. }
  854. case VIDEO1394_IOC_TALK_QUEUE_BUFFER:
  855. {
  856. struct video1394_wait v;
  857. unsigned int *psizes = NULL;
  858. struct dma_iso_ctx *d;
  859. int next_prg;
  860. if (copy_from_user(&v, argp, sizeof(v)))
  861. return -EFAULT;
  862. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel);
  863. if (d == NULL) return -EFAULT;
  864. if ((v.buffer<0) || (v.buffer>=d->num_desc - 1)) {
  865. PRINT(KERN_ERR, ohci->host->id,
  866. "Buffer %d out of range",v.buffer);
  867. return -EINVAL;
  868. }
  869. if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) {
  870. int buf_size = d->nb_cmd * sizeof(*psizes);
  871. struct video1394_queue_variable __user *p = argp;
  872. unsigned int __user *qv;
  873. if (get_user(qv, &p->packet_sizes))
  874. return -EFAULT;
  875. psizes = kmalloc(buf_size, GFP_KERNEL);
  876. if (!psizes)
  877. return -ENOMEM;
  878. if (copy_from_user(psizes, qv, buf_size)) {
  879. kfree(psizes);
  880. return -EFAULT;
  881. }
  882. }
  883. spin_lock_irqsave(&d->lock,flags);
  884. /* last_buffer is last_prg */
  885. next_prg = (d->last_buffer + 1) % d->num_desc;
  886. if (d->buffer_status[v.buffer]!=VIDEO1394_BUFFER_FREE) {
  887. PRINT(KERN_ERR, ohci->host->id,
  888. "Buffer %d is already used",v.buffer);
  889. spin_unlock_irqrestore(&d->lock,flags);
  890. kfree(psizes);
  891. return -EBUSY;
  892. }
  893. if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) {
  894. initialize_dma_it_prg_var_packet_queue(
  895. d, next_prg, psizes, ohci);
  896. }
  897. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED;
  898. if (d->last_buffer >= 0) {
  899. d->it_prg[d->last_buffer]
  900. [ d->last_used_cmd[d->last_buffer] ].end.branchAddress =
  901. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg],
  902. 0) & 0xfffffff0) | 0x3);
  903. d->it_prg[d->last_buffer]
  904. [ d->last_used_cmd[d->last_buffer] ].begin.branchAddress =
  905. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg],
  906. 0) & 0xfffffff0) | 0x3);
  907. d->next_buffer[d->last_buffer] = (v.buffer + 1) % (d->num_desc - 1);
  908. }
  909. d->last_buffer = next_prg;
  910. reprogram_dma_it_prg(d, d->last_buffer, v.buffer);
  911. d->next_buffer[d->last_buffer] = -1;
  912. d->it_prg[d->last_buffer][d->last_used_cmd[d->last_buffer]].end.branchAddress = 0;
  913. spin_unlock_irqrestore(&d->lock,flags);
  914. if (!(reg_read(ohci, d->ctrlSet) & 0x8000))
  915. {
  916. DBGMSG(ohci->host->id, "Starting iso transmit DMA ctx=%d",
  917. d->ctx);
  918. put_timestamp(ohci, d, d->last_buffer);
  919. /* Tell the controller where the first program is */
  920. reg_write(ohci, d->cmdPtr,
  921. dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 0) | 0x3);
  922. /* Run IT context */
  923. reg_write(ohci, d->ctrlSet, 0x8000);
  924. }
  925. else {
  926. /* Wake up dma context if necessary */
  927. if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
  928. PRINT(KERN_INFO, ohci->host->id,
  929. "Waking up iso transmit dma ctx=%d",
  930. d->ctx);
  931. put_timestamp(ohci, d, d->last_buffer);
  932. reg_write(ohci, d->ctrlSet, 0x1000);
  933. }
  934. }
  935. kfree(psizes);
  936. return 0;
  937. }
  938. case VIDEO1394_IOC_TALK_WAIT_BUFFER:
  939. {
  940. struct video1394_wait v;
  941. struct dma_iso_ctx *d;
  942. if (copy_from_user(&v, argp, sizeof(v)))
  943. return -EFAULT;
  944. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel);
  945. if (d == NULL) return -EFAULT;
  946. if ((v.buffer<0) || (v.buffer>=d->num_desc-1)) {
  947. PRINT(KERN_ERR, ohci->host->id,
  948. "Buffer %d out of range",v.buffer);
  949. return -EINVAL;
  950. }
  951. switch(d->buffer_status[v.buffer]) {
  952. case VIDEO1394_BUFFER_READY:
  953. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  954. return 0;
  955. case VIDEO1394_BUFFER_QUEUED:
  956. wait_event_interruptible(d->waitq,
  957. (d->buffer_status[v.buffer] == VIDEO1394_BUFFER_READY));
  958. if (signal_pending(current))
  959. return -EINTR;
  960. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  961. return 0;
  962. default:
  963. PRINT(KERN_ERR, ohci->host->id,
  964. "Buffer %d is not queued",v.buffer);
  965. return -ESRCH;
  966. }
  967. }
  968. default:
  969. return -ENOTTY;
  970. }
  971. }
  972. static long video1394_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  973. {
  974. int err;
  975. lock_kernel();
  976. err = __video1394_ioctl(file, cmd, arg);
  977. unlock_kernel();
  978. return err;
  979. }
  980. /*
  981. * This maps the vmalloced and reserved buffer to user space.
  982. *
  983. * FIXME:
  984. * - PAGE_READONLY should suffice!?
  985. * - remap_pfn_range is kind of inefficient for page by page remapping.
  986. * But e.g. pte_alloc() does not work in modules ... :-(
  987. */
  988. static int video1394_mmap(struct file *file, struct vm_area_struct *vma)
  989. {
  990. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  991. int res = -EINVAL;
  992. lock_kernel();
  993. if (ctx->current_ctx == NULL) {
  994. PRINT(KERN_ERR, ctx->ohci->host->id, "Current iso context not set");
  995. } else
  996. res = dma_region_mmap(&ctx->current_ctx->dma, file, vma);
  997. unlock_kernel();
  998. return res;
  999. }
  1000. static int video1394_open(struct inode *inode, struct file *file)
  1001. {
  1002. int i = ieee1394_file_to_instance(file);
  1003. struct ti_ohci *ohci;
  1004. struct file_ctx *ctx;
  1005. ohci = hpsb_get_hostinfo_bykey(&video1394_highlevel, i);
  1006. if (ohci == NULL)
  1007. return -EIO;
  1008. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  1009. if (!ctx) {
  1010. PRINT(KERN_ERR, ohci->host->id, "Cannot malloc file_ctx");
  1011. return -ENOMEM;
  1012. }
  1013. ctx->ohci = ohci;
  1014. INIT_LIST_HEAD(&ctx->context_list);
  1015. ctx->current_ctx = NULL;
  1016. file->private_data = ctx;
  1017. return 0;
  1018. }
  1019. static int video1394_release(struct inode *inode, struct file *file)
  1020. {
  1021. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  1022. struct ti_ohci *ohci = ctx->ohci;
  1023. struct list_head *lh, *next;
  1024. u64 mask;
  1025. lock_kernel();
  1026. list_for_each_safe(lh, next, &ctx->context_list) {
  1027. struct dma_iso_ctx *d;
  1028. d = list_entry(lh, struct dma_iso_ctx, link);
  1029. mask = (u64) 1 << d->channel;
  1030. if (!(ohci->ISO_channel_usage & mask))
  1031. PRINT(KERN_ERR, ohci->host->id, "On release: Channel %d "
  1032. "is not being used", d->channel);
  1033. else
  1034. ohci->ISO_channel_usage &= ~mask;
  1035. PRINT(KERN_INFO, ohci->host->id, "On release: Iso %s context "
  1036. "%d stop listening on channel %d",
  1037. d->type == OHCI_ISO_RECEIVE ? "receive" : "transmit",
  1038. d->ctx, d->channel);
  1039. free_dma_iso_ctx(d);
  1040. }
  1041. kfree(ctx);
  1042. file->private_data = NULL;
  1043. unlock_kernel();
  1044. return 0;
  1045. }
  1046. #ifdef CONFIG_COMPAT
  1047. static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg);
  1048. #endif
  1049. static struct cdev video1394_cdev;
  1050. static struct file_operations video1394_fops=
  1051. {
  1052. .owner = THIS_MODULE,
  1053. .unlocked_ioctl = video1394_ioctl,
  1054. #ifdef CONFIG_COMPAT
  1055. .compat_ioctl = video1394_compat_ioctl,
  1056. #endif
  1057. .mmap = video1394_mmap,
  1058. .open = video1394_open,
  1059. .release = video1394_release
  1060. };
  1061. /*** HOTPLUG STUFF **********************************************************/
  1062. /*
  1063. * Export information about protocols/devices supported by this driver.
  1064. */
  1065. static struct ieee1394_device_id video1394_id_table[] = {
  1066. {
  1067. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1068. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1069. .version = CAMERA_SW_VERSION_ENTRY & 0xffffff
  1070. },
  1071. {
  1072. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1073. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1074. .version = (CAMERA_SW_VERSION_ENTRY + 1) & 0xffffff
  1075. },
  1076. {
  1077. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1078. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1079. .version = (CAMERA_SW_VERSION_ENTRY + 2) & 0xffffff
  1080. },
  1081. { }
  1082. };
  1083. MODULE_DEVICE_TABLE(ieee1394, video1394_id_table);
  1084. static struct hpsb_protocol_driver video1394_driver = {
  1085. .name = "1394 Digital Camera Driver",
  1086. .id_table = video1394_id_table,
  1087. .driver = {
  1088. .name = VIDEO1394_DRIVER_NAME,
  1089. .bus = &ieee1394_bus_type,
  1090. },
  1091. };
  1092. static void video1394_add_host (struct hpsb_host *host)
  1093. {
  1094. struct ti_ohci *ohci;
  1095. int minor;
  1096. /* We only work with the OHCI-1394 driver */
  1097. if (strcmp(host->driver->name, OHCI1394_DRIVER_NAME))
  1098. return;
  1099. ohci = (struct ti_ohci *)host->hostdata;
  1100. if (!hpsb_create_hostinfo(&video1394_highlevel, host, 0)) {
  1101. PRINT(KERN_ERR, ohci->host->id, "Cannot allocate hostinfo");
  1102. return;
  1103. }
  1104. hpsb_set_hostinfo(&video1394_highlevel, host, ohci);
  1105. hpsb_set_hostinfo_key(&video1394_highlevel, host, ohci->host->id);
  1106. minor = IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id;
  1107. class_device_create(hpsb_protocol_class, NULL, MKDEV(
  1108. IEEE1394_MAJOR, minor),
  1109. NULL, "%s-%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
  1110. devfs_mk_cdev(MKDEV(IEEE1394_MAJOR, minor),
  1111. S_IFCHR | S_IRUSR | S_IWUSR,
  1112. "%s/%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
  1113. }
  1114. static void video1394_remove_host (struct hpsb_host *host)
  1115. {
  1116. struct ti_ohci *ohci = hpsb_get_hostinfo(&video1394_highlevel, host);
  1117. if (ohci) {
  1118. class_device_destroy(hpsb_protocol_class, MKDEV(IEEE1394_MAJOR,
  1119. IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id));
  1120. devfs_remove("%s/%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
  1121. }
  1122. return;
  1123. }
  1124. static struct hpsb_highlevel video1394_highlevel = {
  1125. .name = VIDEO1394_DRIVER_NAME,
  1126. .add_host = video1394_add_host,
  1127. .remove_host = video1394_remove_host,
  1128. };
  1129. MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>");
  1130. MODULE_DESCRIPTION("driver for digital video on OHCI board");
  1131. MODULE_SUPPORTED_DEVICE(VIDEO1394_DRIVER_NAME);
  1132. MODULE_LICENSE("GPL");
  1133. #ifdef CONFIG_COMPAT
  1134. #define VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER \
  1135. _IOW ('#', 0x12, struct video1394_wait32)
  1136. #define VIDEO1394_IOC32_LISTEN_WAIT_BUFFER \
  1137. _IOWR('#', 0x13, struct video1394_wait32)
  1138. #define VIDEO1394_IOC32_TALK_WAIT_BUFFER \
  1139. _IOW ('#', 0x17, struct video1394_wait32)
  1140. #define VIDEO1394_IOC32_LISTEN_POLL_BUFFER \
  1141. _IOWR('#', 0x18, struct video1394_wait32)
  1142. struct video1394_wait32 {
  1143. u32 channel;
  1144. u32 buffer;
  1145. struct compat_timeval filltime;
  1146. };
  1147. static int video1394_wr_wait32(struct file *file, unsigned int cmd, unsigned long arg)
  1148. {
  1149. struct video1394_wait32 __user *argp = (void __user *)arg;
  1150. struct video1394_wait32 wait32;
  1151. struct video1394_wait wait;
  1152. mm_segment_t old_fs;
  1153. int ret;
  1154. if (copy_from_user(&wait32, argp, sizeof(wait32)))
  1155. return -EFAULT;
  1156. wait.channel = wait32.channel;
  1157. wait.buffer = wait32.buffer;
  1158. wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec;
  1159. wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec;
  1160. old_fs = get_fs();
  1161. set_fs(KERNEL_DS);
  1162. if (cmd == VIDEO1394_IOC32_LISTEN_WAIT_BUFFER)
  1163. ret = video1394_ioctl(file,
  1164. VIDEO1394_IOC_LISTEN_WAIT_BUFFER,
  1165. (unsigned long) &wait);
  1166. else
  1167. ret = video1394_ioctl(file,
  1168. VIDEO1394_IOC_LISTEN_POLL_BUFFER,
  1169. (unsigned long) &wait);
  1170. set_fs(old_fs);
  1171. if (!ret) {
  1172. wait32.channel = wait.channel;
  1173. wait32.buffer = wait.buffer;
  1174. wait32.filltime.tv_sec = (int)wait.filltime.tv_sec;
  1175. wait32.filltime.tv_usec = (int)wait.filltime.tv_usec;
  1176. if (copy_to_user(argp, &wait32, sizeof(wait32)))
  1177. ret = -EFAULT;
  1178. }
  1179. return ret;
  1180. }
  1181. static int video1394_w_wait32(struct file *file, unsigned int cmd, unsigned long arg)
  1182. {
  1183. struct video1394_wait32 wait32;
  1184. struct video1394_wait wait;
  1185. mm_segment_t old_fs;
  1186. int ret;
  1187. if (copy_from_user(&wait32, (void __user *)arg, sizeof(wait32)))
  1188. return -EFAULT;
  1189. wait.channel = wait32.channel;
  1190. wait.buffer = wait32.buffer;
  1191. wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec;
  1192. wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec;
  1193. old_fs = get_fs();
  1194. set_fs(KERNEL_DS);
  1195. if (cmd == VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER)
  1196. ret = video1394_ioctl(file,
  1197. VIDEO1394_IOC_LISTEN_QUEUE_BUFFER,
  1198. (unsigned long) &wait);
  1199. else
  1200. ret = video1394_ioctl(file,
  1201. VIDEO1394_IOC_TALK_WAIT_BUFFER,
  1202. (unsigned long) &wait);
  1203. set_fs(old_fs);
  1204. return ret;
  1205. }
  1206. static int video1394_queue_buf32(struct file *file, unsigned int cmd, unsigned long arg)
  1207. {
  1208. return -EFAULT; /* ??? was there before. */
  1209. return video1394_ioctl(file,
  1210. VIDEO1394_IOC_TALK_QUEUE_BUFFER, arg);
  1211. }
  1212. static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg)
  1213. {
  1214. switch (cmd) {
  1215. case VIDEO1394_IOC_LISTEN_CHANNEL:
  1216. case VIDEO1394_IOC_UNLISTEN_CHANNEL:
  1217. case VIDEO1394_IOC_TALK_CHANNEL:
  1218. case VIDEO1394_IOC_UNTALK_CHANNEL:
  1219. return video1394_ioctl(f, cmd, arg);
  1220. case VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER:
  1221. return video1394_w_wait32(f, cmd, arg);
  1222. case VIDEO1394_IOC32_LISTEN_WAIT_BUFFER:
  1223. return video1394_wr_wait32(f, cmd, arg);
  1224. case VIDEO1394_IOC_TALK_QUEUE_BUFFER:
  1225. return video1394_queue_buf32(f, cmd, arg);
  1226. case VIDEO1394_IOC32_TALK_WAIT_BUFFER:
  1227. return video1394_w_wait32(f, cmd, arg);
  1228. case VIDEO1394_IOC32_LISTEN_POLL_BUFFER:
  1229. return video1394_wr_wait32(f, cmd, arg);
  1230. default:
  1231. return -ENOIOCTLCMD;
  1232. }
  1233. }
  1234. #endif /* CONFIG_COMPAT */
  1235. static void __exit video1394_exit_module (void)
  1236. {
  1237. hpsb_unregister_protocol(&video1394_driver);
  1238. hpsb_unregister_highlevel(&video1394_highlevel);
  1239. devfs_remove(VIDEO1394_DRIVER_NAME);
  1240. cdev_del(&video1394_cdev);
  1241. PRINT_G(KERN_INFO, "Removed " VIDEO1394_DRIVER_NAME " module");
  1242. }
  1243. static int __init video1394_init_module (void)
  1244. {
  1245. int ret;
  1246. cdev_init(&video1394_cdev, &video1394_fops);
  1247. video1394_cdev.owner = THIS_MODULE;
  1248. kobject_set_name(&video1394_cdev.kobj, VIDEO1394_DRIVER_NAME);
  1249. ret = cdev_add(&video1394_cdev, IEEE1394_VIDEO1394_DEV, 16);
  1250. if (ret) {
  1251. PRINT_G(KERN_ERR, "video1394: unable to get minor device block");
  1252. return ret;
  1253. }
  1254. devfs_mk_dir(VIDEO1394_DRIVER_NAME);
  1255. hpsb_register_highlevel(&video1394_highlevel);
  1256. ret = hpsb_register_protocol(&video1394_driver);
  1257. if (ret) {
  1258. PRINT_G(KERN_ERR, "video1394: failed to register protocol");
  1259. hpsb_unregister_highlevel(&video1394_highlevel);
  1260. devfs_remove(VIDEO1394_DRIVER_NAME);
  1261. cdev_del(&video1394_cdev);
  1262. return ret;
  1263. }
  1264. PRINT_G(KERN_INFO, "Installed " VIDEO1394_DRIVER_NAME " module");
  1265. return 0;
  1266. }
  1267. module_init(video1394_init_module);
  1268. module_exit(video1394_exit_module);