io.h 10 KB

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  1. #ifndef _ASM_X86_IO_H
  2. #define _ASM_X86_IO_H
  3. /*
  4. * This file contains the definitions for the x86 IO instructions
  5. * inb/inw/inl/outb/outw/outl and the "string versions" of the same
  6. * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
  7. * versions of the single-IO instructions (inb_p/inw_p/..).
  8. *
  9. * This file is not meant to be obfuscating: it's just complicated
  10. * to (a) handle it all in a way that makes gcc able to optimize it
  11. * as well as possible and (b) trying to avoid writing the same thing
  12. * over and over again with slight variations and possibly making a
  13. * mistake somewhere.
  14. */
  15. /*
  16. * Thanks to James van Artsdalen for a better timing-fix than
  17. * the two short jumps: using outb's to a nonexistent port seems
  18. * to guarantee better timings even on fast machines.
  19. *
  20. * On the other hand, I'd like to be sure of a non-existent port:
  21. * I feel a bit unsafe about using 0x80 (should be safe, though)
  22. *
  23. * Linus
  24. */
  25. /*
  26. * Bit simplified and optimized by Jan Hubicka
  27. * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
  28. *
  29. * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
  30. * isa_read[wl] and isa_write[wl] fixed
  31. * - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
  32. */
  33. #define ARCH_HAS_IOREMAP_WC
  34. #include <linux/string.h>
  35. #include <linux/compiler.h>
  36. #include <asm/page.h>
  37. #include <xen/xen.h>
  38. #define build_mmio_read(name, size, type, reg, barrier) \
  39. static inline type name(const volatile void __iomem *addr) \
  40. { type ret; asm volatile("mov" size " %1,%0":reg (ret) \
  41. :"m" (*(volatile type __force *)addr) barrier); return ret; }
  42. #define build_mmio_write(name, size, type, reg, barrier) \
  43. static inline void name(type val, volatile void __iomem *addr) \
  44. { asm volatile("mov" size " %0,%1": :reg (val), \
  45. "m" (*(volatile type __force *)addr) barrier); }
  46. build_mmio_read(readb, "b", unsigned char, "=q", :"memory")
  47. build_mmio_read(readw, "w", unsigned short, "=r", :"memory")
  48. build_mmio_read(readl, "l", unsigned int, "=r", :"memory")
  49. build_mmio_read(__readb, "b", unsigned char, "=q", )
  50. build_mmio_read(__readw, "w", unsigned short, "=r", )
  51. build_mmio_read(__readl, "l", unsigned int, "=r", )
  52. build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
  53. build_mmio_write(writew, "w", unsigned short, "r", :"memory")
  54. build_mmio_write(writel, "l", unsigned int, "r", :"memory")
  55. build_mmio_write(__writeb, "b", unsigned char, "q", )
  56. build_mmio_write(__writew, "w", unsigned short, "r", )
  57. build_mmio_write(__writel, "l", unsigned int, "r", )
  58. #define readb_relaxed(a) __readb(a)
  59. #define readw_relaxed(a) __readw(a)
  60. #define readl_relaxed(a) __readl(a)
  61. #define __raw_readb __readb
  62. #define __raw_readw __readw
  63. #define __raw_readl __readl
  64. #define __raw_writeb __writeb
  65. #define __raw_writew __writew
  66. #define __raw_writel __writel
  67. #define mmiowb() barrier()
  68. #ifdef CONFIG_X86_64
  69. build_mmio_read(readq, "q", unsigned long, "=r", :"memory")
  70. build_mmio_write(writeq, "q", unsigned long, "r", :"memory")
  71. #define readq_relaxed(a) readq(a)
  72. #define __raw_readq(a) readq(a)
  73. #define __raw_writeq(val, addr) writeq(val, addr)
  74. /* Let people know that we have them */
  75. #define readq readq
  76. #define writeq writeq
  77. #endif
  78. /**
  79. * virt_to_phys - map virtual addresses to physical
  80. * @address: address to remap
  81. *
  82. * The returned physical address is the physical (CPU) mapping for
  83. * the memory address given. It is only valid to use this function on
  84. * addresses directly mapped or allocated via kmalloc.
  85. *
  86. * This function does not give bus mappings for DMA transfers. In
  87. * almost all conceivable cases a device driver should not be using
  88. * this function
  89. */
  90. static inline phys_addr_t virt_to_phys(volatile void *address)
  91. {
  92. return __pa(address);
  93. }
  94. /**
  95. * phys_to_virt - map physical address to virtual
  96. * @address: address to remap
  97. *
  98. * The returned virtual address is a current CPU mapping for
  99. * the memory address given. It is only valid to use this function on
  100. * addresses that have a kernel mapping
  101. *
  102. * This function does not handle bus mappings for DMA transfers. In
  103. * almost all conceivable cases a device driver should not be using
  104. * this function
  105. */
  106. static inline void *phys_to_virt(phys_addr_t address)
  107. {
  108. return __va(address);
  109. }
  110. /*
  111. * Change "struct page" to physical address.
  112. */
  113. #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
  114. /*
  115. * ISA I/O bus memory addresses are 1:1 with the physical address.
  116. * However, we truncate the address to unsigned int to avoid undesirable
  117. * promitions in legacy drivers.
  118. */
  119. static inline unsigned int isa_virt_to_bus(volatile void *address)
  120. {
  121. return (unsigned int)virt_to_phys(address);
  122. }
  123. #define isa_page_to_bus(page) ((unsigned int)page_to_phys(page))
  124. #define isa_bus_to_virt phys_to_virt
  125. /*
  126. * However PCI ones are not necessarily 1:1 and therefore these interfaces
  127. * are forbidden in portable PCI drivers.
  128. *
  129. * Allow them on x86 for legacy drivers, though.
  130. */
  131. #define virt_to_bus virt_to_phys
  132. #define bus_to_virt phys_to_virt
  133. /**
  134. * ioremap - map bus memory into CPU space
  135. * @offset: bus address of the memory
  136. * @size: size of the resource to map
  137. *
  138. * ioremap performs a platform specific sequence of operations to
  139. * make bus memory CPU accessible via the readb/readw/readl/writeb/
  140. * writew/writel functions and the other mmio helpers. The returned
  141. * address is not guaranteed to be usable directly as a virtual
  142. * address.
  143. *
  144. * If the area you are trying to map is a PCI BAR you should have a
  145. * look at pci_iomap().
  146. */
  147. extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size);
  148. extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size);
  149. extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size,
  150. unsigned long prot_val);
  151. /*
  152. * The default ioremap() behavior is non-cached:
  153. */
  154. static inline void __iomem *ioremap(resource_size_t offset, unsigned long size)
  155. {
  156. return ioremap_nocache(offset, size);
  157. }
  158. extern void iounmap(volatile void __iomem *addr);
  159. extern void set_iounmap_nonlazy(void);
  160. #ifdef __KERNEL__
  161. #include <asm-generic/iomap.h>
  162. #include <linux/vmalloc.h>
  163. /*
  164. * Convert a virtual cached pointer to an uncached pointer
  165. */
  166. #define xlate_dev_kmem_ptr(p) p
  167. static inline void
  168. memset_io(volatile void __iomem *addr, unsigned char val, size_t count)
  169. {
  170. memset((void __force *)addr, val, count);
  171. }
  172. static inline void
  173. memcpy_fromio(void *dst, const volatile void __iomem *src, size_t count)
  174. {
  175. memcpy(dst, (const void __force *)src, count);
  176. }
  177. static inline void
  178. memcpy_toio(volatile void __iomem *dst, const void *src, size_t count)
  179. {
  180. memcpy((void __force *)dst, src, count);
  181. }
  182. /*
  183. * ISA space is 'always mapped' on a typical x86 system, no need to
  184. * explicitly ioremap() it. The fact that the ISA IO space is mapped
  185. * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
  186. * are physical addresses. The following constant pointer can be
  187. * used as the IO-area pointer (it can be iounmapped as well, so the
  188. * analogy with PCI is quite large):
  189. */
  190. #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
  191. /*
  192. * Cache management
  193. *
  194. * This needed for two cases
  195. * 1. Out of order aware processors
  196. * 2. Accidentally out of order processors (PPro errata #51)
  197. */
  198. static inline void flush_write_buffers(void)
  199. {
  200. #if defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE)
  201. asm volatile("lock; addl $0,0(%%esp)": : :"memory");
  202. #endif
  203. }
  204. #endif /* __KERNEL__ */
  205. extern void native_io_delay(void);
  206. extern int io_delay_type;
  207. extern void io_delay_init(void);
  208. #if defined(CONFIG_PARAVIRT)
  209. #include <asm/paravirt.h>
  210. #else
  211. static inline void slow_down_io(void)
  212. {
  213. native_io_delay();
  214. #ifdef REALLY_SLOW_IO
  215. native_io_delay();
  216. native_io_delay();
  217. native_io_delay();
  218. #endif
  219. }
  220. #endif
  221. #define BUILDIO(bwl, bw, type) \
  222. static inline void out##bwl(unsigned type value, int port) \
  223. { \
  224. asm volatile("out" #bwl " %" #bw "0, %w1" \
  225. : : "a"(value), "Nd"(port)); \
  226. } \
  227. \
  228. static inline unsigned type in##bwl(int port) \
  229. { \
  230. unsigned type value; \
  231. asm volatile("in" #bwl " %w1, %" #bw "0" \
  232. : "=a"(value) : "Nd"(port)); \
  233. return value; \
  234. } \
  235. \
  236. static inline void out##bwl##_p(unsigned type value, int port) \
  237. { \
  238. out##bwl(value, port); \
  239. slow_down_io(); \
  240. } \
  241. \
  242. static inline unsigned type in##bwl##_p(int port) \
  243. { \
  244. unsigned type value = in##bwl(port); \
  245. slow_down_io(); \
  246. return value; \
  247. } \
  248. \
  249. static inline void outs##bwl(int port, const void *addr, unsigned long count) \
  250. { \
  251. asm volatile("rep; outs" #bwl \
  252. : "+S"(addr), "+c"(count) : "d"(port)); \
  253. } \
  254. \
  255. static inline void ins##bwl(int port, void *addr, unsigned long count) \
  256. { \
  257. asm volatile("rep; ins" #bwl \
  258. : "+D"(addr), "+c"(count) : "d"(port)); \
  259. }
  260. BUILDIO(b, b, char)
  261. BUILDIO(w, w, short)
  262. BUILDIO(l, , int)
  263. extern void *xlate_dev_mem_ptr(unsigned long phys);
  264. extern void unxlate_dev_mem_ptr(unsigned long phys, void *addr);
  265. extern int ioremap_change_attr(unsigned long vaddr, unsigned long size,
  266. unsigned long prot_val);
  267. extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size);
  268. /*
  269. * early_ioremap() and early_iounmap() are for temporary early boot-time
  270. * mappings, before the real ioremap() is functional.
  271. * A boot-time mapping is currently limited to at most 16 pages.
  272. */
  273. extern void early_ioremap_init(void);
  274. extern void early_ioremap_reset(void);
  275. extern void __iomem *early_ioremap(resource_size_t phys_addr,
  276. unsigned long size);
  277. extern void __iomem *early_memremap(resource_size_t phys_addr,
  278. unsigned long size);
  279. extern void early_iounmap(void __iomem *addr, unsigned long size);
  280. extern void fixup_early_ioremap(void);
  281. extern bool is_early_ioremap_ptep(pte_t *ptep);
  282. #ifdef CONFIG_XEN
  283. struct bio_vec;
  284. extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
  285. const struct bio_vec *vec2);
  286. #define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \
  287. (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \
  288. (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
  289. #endif /* CONFIG_XEN */
  290. #define IO_SPACE_LIMIT 0xffff
  291. #endif /* _ASM_X86_IO_H */