rtc-s3c.c 15 KB

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  1. /* drivers/rtc/rtc-s3c.c
  2. *
  3. * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com/
  5. *
  6. * Copyright (c) 2004,2006 Simtec Electronics
  7. * Ben Dooks, <ben@simtec.co.uk>
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. *
  14. * S3C2410/S3C2440/S3C24XX Internal RTC Driver
  15. */
  16. #include <linux/module.h>
  17. #include <linux/fs.h>
  18. #include <linux/string.h>
  19. #include <linux/init.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/rtc.h>
  23. #include <linux/bcd.h>
  24. #include <linux/clk.h>
  25. #include <linux/log2.h>
  26. #include <linux/slab.h>
  27. #include <mach/hardware.h>
  28. #include <asm/uaccess.h>
  29. #include <asm/io.h>
  30. #include <asm/irq.h>
  31. #include <plat/regs-rtc.h>
  32. enum s3c_cpu_type {
  33. TYPE_S3C2410,
  34. TYPE_S3C64XX,
  35. };
  36. /* I have yet to find an S3C implementation with more than one
  37. * of these rtc blocks in */
  38. static struct resource *s3c_rtc_mem;
  39. static struct clk *rtc_clk;
  40. static void __iomem *s3c_rtc_base;
  41. static int s3c_rtc_alarmno = NO_IRQ;
  42. static int s3c_rtc_tickno = NO_IRQ;
  43. static enum s3c_cpu_type s3c_rtc_cpu_type;
  44. static DEFINE_SPINLOCK(s3c_rtc_pie_lock);
  45. /* IRQ Handlers */
  46. static irqreturn_t s3c_rtc_alarmirq(int irq, void *id)
  47. {
  48. struct rtc_device *rdev = id;
  49. rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF);
  50. return IRQ_HANDLED;
  51. }
  52. static irqreturn_t s3c_rtc_tickirq(int irq, void *id)
  53. {
  54. struct rtc_device *rdev = id;
  55. rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF);
  56. return IRQ_HANDLED;
  57. }
  58. /* Update control registers */
  59. static void s3c_rtc_setaie(int to)
  60. {
  61. unsigned int tmp;
  62. pr_debug("%s: aie=%d\n", __func__, to);
  63. tmp = readb(s3c_rtc_base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN;
  64. if (to)
  65. tmp |= S3C2410_RTCALM_ALMEN;
  66. writeb(tmp, s3c_rtc_base + S3C2410_RTCALM);
  67. }
  68. static int s3c_rtc_setpie(struct device *dev, int enabled)
  69. {
  70. unsigned int tmp;
  71. pr_debug("%s: pie=%d\n", __func__, enabled);
  72. spin_lock_irq(&s3c_rtc_pie_lock);
  73. if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
  74. tmp = readb(s3c_rtc_base + S3C2410_RTCCON);
  75. tmp &= ~S3C64XX_RTCCON_TICEN;
  76. if (enabled)
  77. tmp |= S3C64XX_RTCCON_TICEN;
  78. writeb(tmp, s3c_rtc_base + S3C2410_RTCCON);
  79. } else {
  80. tmp = readb(s3c_rtc_base + S3C2410_TICNT);
  81. tmp &= ~S3C2410_TICNT_ENABLE;
  82. if (enabled)
  83. tmp |= S3C2410_TICNT_ENABLE;
  84. writeb(tmp, s3c_rtc_base + S3C2410_TICNT);
  85. }
  86. spin_unlock_irq(&s3c_rtc_pie_lock);
  87. return 0;
  88. }
  89. static int s3c_rtc_setfreq(struct device *dev, int freq)
  90. {
  91. struct platform_device *pdev = to_platform_device(dev);
  92. struct rtc_device *rtc_dev = platform_get_drvdata(pdev);
  93. unsigned int tmp = 0;
  94. if (!is_power_of_2(freq))
  95. return -EINVAL;
  96. spin_lock_irq(&s3c_rtc_pie_lock);
  97. if (s3c_rtc_cpu_type == TYPE_S3C2410) {
  98. tmp = readb(s3c_rtc_base + S3C2410_TICNT);
  99. tmp &= S3C2410_TICNT_ENABLE;
  100. }
  101. tmp |= (rtc_dev->max_user_freq / freq)-1;
  102. writeb(tmp, s3c_rtc_base + S3C2410_TICNT);
  103. spin_unlock_irq(&s3c_rtc_pie_lock);
  104. return 0;
  105. }
  106. /* Time read/write */
  107. static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
  108. {
  109. unsigned int have_retried = 0;
  110. void __iomem *base = s3c_rtc_base;
  111. retry_get_time:
  112. rtc_tm->tm_min = readb(base + S3C2410_RTCMIN);
  113. rtc_tm->tm_hour = readb(base + S3C2410_RTCHOUR);
  114. rtc_tm->tm_mday = readb(base + S3C2410_RTCDATE);
  115. rtc_tm->tm_mon = readb(base + S3C2410_RTCMON);
  116. rtc_tm->tm_year = readb(base + S3C2410_RTCYEAR);
  117. rtc_tm->tm_sec = readb(base + S3C2410_RTCSEC);
  118. /* the only way to work out wether the system was mid-update
  119. * when we read it is to check the second counter, and if it
  120. * is zero, then we re-try the entire read
  121. */
  122. if (rtc_tm->tm_sec == 0 && !have_retried) {
  123. have_retried = 1;
  124. goto retry_get_time;
  125. }
  126. pr_debug("read time %02x.%02x.%02x %02x/%02x/%02x\n",
  127. rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday,
  128. rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec);
  129. rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
  130. rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
  131. rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
  132. rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
  133. rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
  134. rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
  135. rtc_tm->tm_year += 100;
  136. rtc_tm->tm_mon -= 1;
  137. return 0;
  138. }
  139. static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
  140. {
  141. void __iomem *base = s3c_rtc_base;
  142. int year = tm->tm_year - 100;
  143. pr_debug("set time %02d.%02d.%02d %02d/%02d/%02d\n",
  144. tm->tm_year, tm->tm_mon, tm->tm_mday,
  145. tm->tm_hour, tm->tm_min, tm->tm_sec);
  146. /* we get around y2k by simply not supporting it */
  147. if (year < 0 || year >= 100) {
  148. dev_err(dev, "rtc only supports 100 years\n");
  149. return -EINVAL;
  150. }
  151. writeb(bin2bcd(tm->tm_sec), base + S3C2410_RTCSEC);
  152. writeb(bin2bcd(tm->tm_min), base + S3C2410_RTCMIN);
  153. writeb(bin2bcd(tm->tm_hour), base + S3C2410_RTCHOUR);
  154. writeb(bin2bcd(tm->tm_mday), base + S3C2410_RTCDATE);
  155. writeb(bin2bcd(tm->tm_mon + 1), base + S3C2410_RTCMON);
  156. writeb(bin2bcd(year), base + S3C2410_RTCYEAR);
  157. return 0;
  158. }
  159. static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
  160. {
  161. struct rtc_time *alm_tm = &alrm->time;
  162. void __iomem *base = s3c_rtc_base;
  163. unsigned int alm_en;
  164. alm_tm->tm_sec = readb(base + S3C2410_ALMSEC);
  165. alm_tm->tm_min = readb(base + S3C2410_ALMMIN);
  166. alm_tm->tm_hour = readb(base + S3C2410_ALMHOUR);
  167. alm_tm->tm_mon = readb(base + S3C2410_ALMMON);
  168. alm_tm->tm_mday = readb(base + S3C2410_ALMDATE);
  169. alm_tm->tm_year = readb(base + S3C2410_ALMYEAR);
  170. alm_en = readb(base + S3C2410_RTCALM);
  171. alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0;
  172. pr_debug("read alarm %02x %02x.%02x.%02x %02x/%02x/%02x\n",
  173. alm_en,
  174. alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday,
  175. alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec);
  176. /* decode the alarm enable field */
  177. if (alm_en & S3C2410_RTCALM_SECEN)
  178. alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec);
  179. else
  180. alm_tm->tm_sec = 0xff;
  181. if (alm_en & S3C2410_RTCALM_MINEN)
  182. alm_tm->tm_min = bcd2bin(alm_tm->tm_min);
  183. else
  184. alm_tm->tm_min = 0xff;
  185. if (alm_en & S3C2410_RTCALM_HOUREN)
  186. alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour);
  187. else
  188. alm_tm->tm_hour = 0xff;
  189. if (alm_en & S3C2410_RTCALM_DAYEN)
  190. alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday);
  191. else
  192. alm_tm->tm_mday = 0xff;
  193. if (alm_en & S3C2410_RTCALM_MONEN) {
  194. alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon);
  195. alm_tm->tm_mon -= 1;
  196. } else {
  197. alm_tm->tm_mon = 0xff;
  198. }
  199. if (alm_en & S3C2410_RTCALM_YEAREN)
  200. alm_tm->tm_year = bcd2bin(alm_tm->tm_year);
  201. else
  202. alm_tm->tm_year = 0xffff;
  203. return 0;
  204. }
  205. static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
  206. {
  207. struct rtc_time *tm = &alrm->time;
  208. void __iomem *base = s3c_rtc_base;
  209. unsigned int alrm_en;
  210. pr_debug("s3c_rtc_setalarm: %d, %02x/%02x/%02x %02x.%02x.%02x\n",
  211. alrm->enabled,
  212. tm->tm_mday & 0xff, tm->tm_mon & 0xff, tm->tm_year & 0xff,
  213. tm->tm_hour & 0xff, tm->tm_min & 0xff, tm->tm_sec);
  214. alrm_en = readb(base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN;
  215. writeb(0x00, base + S3C2410_RTCALM);
  216. if (tm->tm_sec < 60 && tm->tm_sec >= 0) {
  217. alrm_en |= S3C2410_RTCALM_SECEN;
  218. writeb(bin2bcd(tm->tm_sec), base + S3C2410_ALMSEC);
  219. }
  220. if (tm->tm_min < 60 && tm->tm_min >= 0) {
  221. alrm_en |= S3C2410_RTCALM_MINEN;
  222. writeb(bin2bcd(tm->tm_min), base + S3C2410_ALMMIN);
  223. }
  224. if (tm->tm_hour < 24 && tm->tm_hour >= 0) {
  225. alrm_en |= S3C2410_RTCALM_HOUREN;
  226. writeb(bin2bcd(tm->tm_hour), base + S3C2410_ALMHOUR);
  227. }
  228. pr_debug("setting S3C2410_RTCALM to %08x\n", alrm_en);
  229. writeb(alrm_en, base + S3C2410_RTCALM);
  230. s3c_rtc_setaie(alrm->enabled);
  231. if (alrm->enabled)
  232. enable_irq_wake(s3c_rtc_alarmno);
  233. else
  234. disable_irq_wake(s3c_rtc_alarmno);
  235. return 0;
  236. }
  237. static int s3c_rtc_proc(struct device *dev, struct seq_file *seq)
  238. {
  239. unsigned int ticnt;
  240. if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
  241. ticnt = readb(s3c_rtc_base + S3C2410_RTCCON);
  242. ticnt &= S3C64XX_RTCCON_TICEN;
  243. } else {
  244. ticnt = readb(s3c_rtc_base + S3C2410_TICNT);
  245. ticnt &= S3C2410_TICNT_ENABLE;
  246. }
  247. seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no");
  248. return 0;
  249. }
  250. static int s3c_rtc_open(struct device *dev)
  251. {
  252. struct platform_device *pdev = to_platform_device(dev);
  253. struct rtc_device *rtc_dev = platform_get_drvdata(pdev);
  254. int ret;
  255. ret = request_irq(s3c_rtc_alarmno, s3c_rtc_alarmirq,
  256. IRQF_DISABLED, "s3c2410-rtc alarm", rtc_dev);
  257. if (ret) {
  258. dev_err(dev, "IRQ%d error %d\n", s3c_rtc_alarmno, ret);
  259. return ret;
  260. }
  261. ret = request_irq(s3c_rtc_tickno, s3c_rtc_tickirq,
  262. IRQF_DISABLED, "s3c2410-rtc tick", rtc_dev);
  263. if (ret) {
  264. dev_err(dev, "IRQ%d error %d\n", s3c_rtc_tickno, ret);
  265. goto tick_err;
  266. }
  267. return ret;
  268. tick_err:
  269. free_irq(s3c_rtc_alarmno, rtc_dev);
  270. return ret;
  271. }
  272. static void s3c_rtc_release(struct device *dev)
  273. {
  274. struct platform_device *pdev = to_platform_device(dev);
  275. struct rtc_device *rtc_dev = platform_get_drvdata(pdev);
  276. /* do not clear AIE here, it may be needed for wake */
  277. s3c_rtc_setpie(dev, 0);
  278. free_irq(s3c_rtc_alarmno, rtc_dev);
  279. free_irq(s3c_rtc_tickno, rtc_dev);
  280. }
  281. static const struct rtc_class_ops s3c_rtcops = {
  282. .open = s3c_rtc_open,
  283. .release = s3c_rtc_release,
  284. .read_time = s3c_rtc_gettime,
  285. .set_time = s3c_rtc_settime,
  286. .read_alarm = s3c_rtc_getalarm,
  287. .set_alarm = s3c_rtc_setalarm,
  288. .irq_set_freq = s3c_rtc_setfreq,
  289. .irq_set_state = s3c_rtc_setpie,
  290. .proc = s3c_rtc_proc,
  291. };
  292. static void s3c_rtc_enable(struct platform_device *pdev, int en)
  293. {
  294. void __iomem *base = s3c_rtc_base;
  295. unsigned int tmp;
  296. if (s3c_rtc_base == NULL)
  297. return;
  298. if (!en) {
  299. tmp = readb(base + S3C2410_RTCCON);
  300. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  301. tmp &= ~S3C64XX_RTCCON_TICEN;
  302. tmp &= ~S3C2410_RTCCON_RTCEN;
  303. writeb(tmp, base + S3C2410_RTCCON);
  304. if (s3c_rtc_cpu_type == TYPE_S3C2410) {
  305. tmp = readb(base + S3C2410_TICNT);
  306. tmp &= ~S3C2410_TICNT_ENABLE;
  307. writeb(tmp, base + S3C2410_TICNT);
  308. }
  309. } else {
  310. /* re-enable the device, and check it is ok */
  311. if ((readb(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0){
  312. dev_info(&pdev->dev, "rtc disabled, re-enabling\n");
  313. tmp = readb(base + S3C2410_RTCCON);
  314. writeb(tmp|S3C2410_RTCCON_RTCEN, base+S3C2410_RTCCON);
  315. }
  316. if ((readb(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)){
  317. dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n");
  318. tmp = readb(base + S3C2410_RTCCON);
  319. writeb(tmp& ~S3C2410_RTCCON_CNTSEL, base+S3C2410_RTCCON);
  320. }
  321. if ((readb(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)){
  322. dev_info(&pdev->dev, "removing RTCCON_CLKRST\n");
  323. tmp = readb(base + S3C2410_RTCCON);
  324. writeb(tmp & ~S3C2410_RTCCON_CLKRST, base+S3C2410_RTCCON);
  325. }
  326. }
  327. }
  328. static int __devexit s3c_rtc_remove(struct platform_device *dev)
  329. {
  330. struct rtc_device *rtc = platform_get_drvdata(dev);
  331. platform_set_drvdata(dev, NULL);
  332. rtc_device_unregister(rtc);
  333. s3c_rtc_setpie(&dev->dev, 0);
  334. s3c_rtc_setaie(0);
  335. clk_disable(rtc_clk);
  336. clk_put(rtc_clk);
  337. rtc_clk = NULL;
  338. iounmap(s3c_rtc_base);
  339. release_resource(s3c_rtc_mem);
  340. kfree(s3c_rtc_mem);
  341. return 0;
  342. }
  343. static int __devinit s3c_rtc_probe(struct platform_device *pdev)
  344. {
  345. struct rtc_device *rtc;
  346. struct resource *res;
  347. int ret;
  348. pr_debug("%s: probe=%p\n", __func__, pdev);
  349. /* find the IRQs */
  350. s3c_rtc_tickno = platform_get_irq(pdev, 1);
  351. if (s3c_rtc_tickno < 0) {
  352. dev_err(&pdev->dev, "no irq for rtc tick\n");
  353. return -ENOENT;
  354. }
  355. s3c_rtc_alarmno = platform_get_irq(pdev, 0);
  356. if (s3c_rtc_alarmno < 0) {
  357. dev_err(&pdev->dev, "no irq for alarm\n");
  358. return -ENOENT;
  359. }
  360. pr_debug("s3c2410_rtc: tick irq %d, alarm irq %d\n",
  361. s3c_rtc_tickno, s3c_rtc_alarmno);
  362. /* get the memory region */
  363. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  364. if (res == NULL) {
  365. dev_err(&pdev->dev, "failed to get memory region resource\n");
  366. return -ENOENT;
  367. }
  368. s3c_rtc_mem = request_mem_region(res->start,
  369. res->end-res->start+1,
  370. pdev->name);
  371. if (s3c_rtc_mem == NULL) {
  372. dev_err(&pdev->dev, "failed to reserve memory region\n");
  373. ret = -ENOENT;
  374. goto err_nores;
  375. }
  376. s3c_rtc_base = ioremap(res->start, res->end - res->start + 1);
  377. if (s3c_rtc_base == NULL) {
  378. dev_err(&pdev->dev, "failed ioremap()\n");
  379. ret = -EINVAL;
  380. goto err_nomap;
  381. }
  382. rtc_clk = clk_get(&pdev->dev, "rtc");
  383. if (IS_ERR(rtc_clk)) {
  384. dev_err(&pdev->dev, "failed to find rtc clock source\n");
  385. ret = PTR_ERR(rtc_clk);
  386. rtc_clk = NULL;
  387. goto err_clk;
  388. }
  389. clk_enable(rtc_clk);
  390. /* check to see if everything is setup correctly */
  391. s3c_rtc_enable(pdev, 1);
  392. pr_debug("s3c2410_rtc: RTCCON=%02x\n",
  393. readb(s3c_rtc_base + S3C2410_RTCCON));
  394. device_init_wakeup(&pdev->dev, 1);
  395. /* register RTC and exit */
  396. rtc = rtc_device_register("s3c", &pdev->dev, &s3c_rtcops,
  397. THIS_MODULE);
  398. if (IS_ERR(rtc)) {
  399. dev_err(&pdev->dev, "cannot attach rtc\n");
  400. ret = PTR_ERR(rtc);
  401. goto err_nortc;
  402. }
  403. s3c_rtc_cpu_type = platform_get_device_id(pdev)->driver_data;
  404. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  405. rtc->max_user_freq = 32768;
  406. else
  407. rtc->max_user_freq = 128;
  408. platform_set_drvdata(pdev, rtc);
  409. s3c_rtc_setfreq(&pdev->dev, 1);
  410. return 0;
  411. err_nortc:
  412. s3c_rtc_enable(pdev, 0);
  413. clk_disable(rtc_clk);
  414. clk_put(rtc_clk);
  415. err_clk:
  416. iounmap(s3c_rtc_base);
  417. err_nomap:
  418. release_resource(s3c_rtc_mem);
  419. err_nores:
  420. return ret;
  421. }
  422. #ifdef CONFIG_PM
  423. /* RTC Power management control */
  424. static int ticnt_save, ticnt_en_save;
  425. static int s3c_rtc_suspend(struct platform_device *pdev, pm_message_t state)
  426. {
  427. /* save TICNT for anyone using periodic interrupts */
  428. ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT);
  429. if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
  430. ticnt_en_save = readb(s3c_rtc_base + S3C2410_RTCCON);
  431. ticnt_en_save &= S3C64XX_RTCCON_TICEN;
  432. }
  433. s3c_rtc_enable(pdev, 0);
  434. return 0;
  435. }
  436. static int s3c_rtc_resume(struct platform_device *pdev)
  437. {
  438. unsigned int tmp;
  439. s3c_rtc_enable(pdev, 1);
  440. writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT);
  441. if (s3c_rtc_cpu_type == TYPE_S3C64XX && ticnt_en_save) {
  442. tmp = readb(s3c_rtc_base + S3C2410_RTCCON);
  443. writeb(tmp | ticnt_en_save, s3c_rtc_base + S3C2410_RTCCON);
  444. }
  445. return 0;
  446. }
  447. #else
  448. #define s3c_rtc_suspend NULL
  449. #define s3c_rtc_resume NULL
  450. #endif
  451. static struct platform_device_id s3c_rtc_driver_ids[] = {
  452. {
  453. .name = "s3c2410-rtc",
  454. .driver_data = TYPE_S3C2410,
  455. }, {
  456. .name = "s3c64xx-rtc",
  457. .driver_data = TYPE_S3C64XX,
  458. },
  459. { }
  460. };
  461. MODULE_DEVICE_TABLE(platform, s3c_rtc_driver_ids);
  462. static struct platform_driver s3c_rtc_driver = {
  463. .probe = s3c_rtc_probe,
  464. .remove = __devexit_p(s3c_rtc_remove),
  465. .suspend = s3c_rtc_suspend,
  466. .resume = s3c_rtc_resume,
  467. .id_table = s3c_rtc_driver_ids,
  468. .driver = {
  469. .name = "s3c-rtc",
  470. .owner = THIS_MODULE,
  471. },
  472. };
  473. static char __initdata banner[] = "S3C24XX RTC, (c) 2004,2006 Simtec Electronics\n";
  474. static int __init s3c_rtc_init(void)
  475. {
  476. printk(banner);
  477. return platform_driver_register(&s3c_rtc_driver);
  478. }
  479. static void __exit s3c_rtc_exit(void)
  480. {
  481. platform_driver_unregister(&s3c_rtc_driver);
  482. }
  483. module_init(s3c_rtc_init);
  484. module_exit(s3c_rtc_exit);
  485. MODULE_DESCRIPTION("Samsung S3C RTC Driver");
  486. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
  487. MODULE_LICENSE("GPL");
  488. MODULE_ALIAS("platform:s3c2410-rtc");