setup-r8a73a4.c 2.9 KB

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  1. /*
  2. * r8a73a4 processor support
  3. *
  4. * Copyright (C) 2013 Renesas Solutions Corp.
  5. * Copyright (C) 2013 Magnus Damm
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. */
  20. #include <linux/irq.h>
  21. #include <linux/irqchip.h>
  22. #include <linux/kernel.h>
  23. #include <linux/of_platform.h>
  24. #include <linux/serial_sci.h>
  25. #include <mach/common.h>
  26. #include <mach/irqs.h>
  27. #include <mach/r8a73a4.h>
  28. #include <asm/mach/arch.h>
  29. #define SCIF_COMMON(scif_type, baseaddr, irq) \
  30. .type = scif_type, \
  31. .mapbase = baseaddr, \
  32. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
  33. .scbrr_algo_id = SCBRR_ALGO_4, \
  34. .irqs = SCIx_IRQ_MUXED(irq)
  35. #define SCIFA_DATA(index, baseaddr, irq) \
  36. [index] = { \
  37. SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
  38. .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
  39. }
  40. #define SCIFB_DATA(index, baseaddr, irq) \
  41. [index] = { \
  42. SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
  43. .scscr = SCSCR_RE | SCSCR_TE, \
  44. }
  45. enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 };
  46. static const struct plat_sci_port scif[] = {
  47. SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
  48. SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
  49. SCIFB_DATA(SCIFB0, 0xe6c50000, gic_spi(145)), /* SCIFB0 */
  50. SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
  51. SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
  52. SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
  53. };
  54. static inline void r8a73a4_register_scif(int idx)
  55. {
  56. platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
  57. sizeof(struct plat_sci_port));
  58. }
  59. void __init r8a73a4_add_standard_devices(void)
  60. {
  61. r8a73a4_register_scif(SCIFA0);
  62. r8a73a4_register_scif(SCIFA1);
  63. r8a73a4_register_scif(SCIFB0);
  64. r8a73a4_register_scif(SCIFB1);
  65. r8a73a4_register_scif(SCIFB2);
  66. r8a73a4_register_scif(SCIFB3);
  67. }
  68. #ifdef CONFIG_USE_OF
  69. void __init r8a73a4_add_standard_devices_dt(void)
  70. {
  71. of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
  72. }
  73. static const char *r8a73a4_boards_compat_dt[] __initdata = {
  74. "renesas,r8a73a4",
  75. NULL,
  76. };
  77. DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
  78. .init_irq = irqchip_init,
  79. .init_machine = r8a73a4_add_standard_devices_dt,
  80. .init_time = shmobile_timer_init,
  81. .dt_compat = r8a73a4_boards_compat_dt,
  82. MACHINE_END
  83. #endif /* CONFIG_USE_OF */