netxen_nic_init.c 40 KB

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  1. /*
  2. * Copyright (C) 2003 - 2006 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. *
  30. * Source file for NIC routines to initialize the Phantom Hardware
  31. *
  32. */
  33. #include <linux/netdevice.h>
  34. #include <linux/delay.h>
  35. #include "netxen_nic.h"
  36. #include "netxen_nic_hw.h"
  37. #include "netxen_nic_phan_reg.h"
  38. struct crb_addr_pair {
  39. long addr;
  40. long data;
  41. };
  42. #define NETXEN_MAX_CRB_XFORM 60
  43. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  44. #define NETXEN_ADDR_ERROR ((unsigned long ) 0xffffffff )
  45. #define crb_addr_transform(name) \
  46. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  47. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  48. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  49. static inline void
  50. netxen_nic_locked_write_reg(struct netxen_adapter *adapter,
  51. unsigned long off, int *data)
  52. {
  53. void __iomem *addr = pci_base_offset(adapter, off);
  54. writel(*data, addr);
  55. }
  56. static void crb_addr_transform_setup(void)
  57. {
  58. crb_addr_transform(XDMA);
  59. crb_addr_transform(TIMR);
  60. crb_addr_transform(SRE);
  61. crb_addr_transform(SQN3);
  62. crb_addr_transform(SQN2);
  63. crb_addr_transform(SQN1);
  64. crb_addr_transform(SQN0);
  65. crb_addr_transform(SQS3);
  66. crb_addr_transform(SQS2);
  67. crb_addr_transform(SQS1);
  68. crb_addr_transform(SQS0);
  69. crb_addr_transform(RPMX7);
  70. crb_addr_transform(RPMX6);
  71. crb_addr_transform(RPMX5);
  72. crb_addr_transform(RPMX4);
  73. crb_addr_transform(RPMX3);
  74. crb_addr_transform(RPMX2);
  75. crb_addr_transform(RPMX1);
  76. crb_addr_transform(RPMX0);
  77. crb_addr_transform(ROMUSB);
  78. crb_addr_transform(SN);
  79. crb_addr_transform(QMN);
  80. crb_addr_transform(QMS);
  81. crb_addr_transform(PGNI);
  82. crb_addr_transform(PGND);
  83. crb_addr_transform(PGN3);
  84. crb_addr_transform(PGN2);
  85. crb_addr_transform(PGN1);
  86. crb_addr_transform(PGN0);
  87. crb_addr_transform(PGSI);
  88. crb_addr_transform(PGSD);
  89. crb_addr_transform(PGS3);
  90. crb_addr_transform(PGS2);
  91. crb_addr_transform(PGS1);
  92. crb_addr_transform(PGS0);
  93. crb_addr_transform(PS);
  94. crb_addr_transform(PH);
  95. crb_addr_transform(NIU);
  96. crb_addr_transform(I2Q);
  97. crb_addr_transform(EG);
  98. crb_addr_transform(MN);
  99. crb_addr_transform(MS);
  100. crb_addr_transform(CAS2);
  101. crb_addr_transform(CAS1);
  102. crb_addr_transform(CAS0);
  103. crb_addr_transform(CAM);
  104. crb_addr_transform(C2C1);
  105. crb_addr_transform(C2C0);
  106. crb_addr_transform(SMB);
  107. }
  108. int netxen_init_firmware(struct netxen_adapter *adapter)
  109. {
  110. u32 state = 0, loops = 0, err = 0;
  111. /* Window 1 call */
  112. state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  113. if (state == PHAN_INITIALIZE_ACK)
  114. return 0;
  115. while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
  116. udelay(100);
  117. /* Window 1 call */
  118. state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  119. loops++;
  120. }
  121. if (loops >= 2000) {
  122. printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
  123. state);
  124. err = -EIO;
  125. return err;
  126. }
  127. /* Window 1 call */
  128. writel(MPORT_SINGLE_FUNCTION_MODE,
  129. NETXEN_CRB_NORMALIZE(adapter, CRB_MPORT_MODE));
  130. writel(PHAN_INITIALIZE_ACK,
  131. NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  132. return err;
  133. }
  134. #define NETXEN_ADDR_LIMIT 0xffffffffULL
  135. void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr,
  136. struct pci_dev **used_dev)
  137. {
  138. void *addr;
  139. addr = pci_alloc_consistent(pdev, sz, ptr);
  140. if ((unsigned long long)(*ptr) < NETXEN_ADDR_LIMIT) {
  141. *used_dev = pdev;
  142. return addr;
  143. }
  144. pci_free_consistent(pdev, sz, addr, *ptr);
  145. addr = pci_alloc_consistent(NULL, sz, ptr);
  146. *used_dev = NULL;
  147. return addr;
  148. }
  149. void netxen_initialize_adapter_sw(struct netxen_adapter *adapter)
  150. {
  151. int ctxid, ring;
  152. u32 i;
  153. u32 num_rx_bufs = 0;
  154. struct netxen_rcv_desc_ctx *rcv_desc;
  155. DPRINTK(INFO, "initializing some queues: %p\n", adapter);
  156. for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
  157. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  158. struct netxen_rx_buffer *rx_buf;
  159. rcv_desc = &adapter->recv_ctx[ctxid].rcv_desc[ring];
  160. rcv_desc->rcv_free = rcv_desc->max_rx_desc_count;
  161. rcv_desc->begin_alloc = 0;
  162. rx_buf = rcv_desc->rx_buf_arr;
  163. num_rx_bufs = rcv_desc->max_rx_desc_count;
  164. /*
  165. * Now go through all of them, set reference handles
  166. * and put them in the queues.
  167. */
  168. for (i = 0; i < num_rx_bufs; i++) {
  169. rx_buf->ref_handle = i;
  170. rx_buf->state = NETXEN_BUFFER_FREE;
  171. DPRINTK(INFO, "Rx buf:ctx%d i(%d) rx_buf:"
  172. "%p\n", ctxid, i, rx_buf);
  173. rx_buf++;
  174. }
  175. }
  176. }
  177. }
  178. void netxen_initialize_adapter_hw(struct netxen_adapter *adapter)
  179. {
  180. int ports = 0;
  181. struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
  182. if (netxen_nic_get_board_info(adapter) != 0)
  183. printk("%s: Error getting board config info.\n",
  184. netxen_nic_driver_name);
  185. get_brd_port_by_type(board_info->board_type, &ports);
  186. if (ports == 0)
  187. printk(KERN_ERR "%s: Unknown board type\n",
  188. netxen_nic_driver_name);
  189. adapter->ahw.max_ports = ports;
  190. }
  191. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  192. {
  193. switch (adapter->ahw.board_type) {
  194. case NETXEN_NIC_GBE:
  195. adapter->enable_phy_interrupts =
  196. netxen_niu_gbe_enable_phy_interrupts;
  197. adapter->disable_phy_interrupts =
  198. netxen_niu_gbe_disable_phy_interrupts;
  199. adapter->handle_phy_intr = netxen_nic_gbe_handle_phy_intr;
  200. adapter->macaddr_set = netxen_niu_macaddr_set;
  201. adapter->set_mtu = netxen_nic_set_mtu_gb;
  202. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  203. adapter->unset_promisc = netxen_niu_set_promiscuous_mode;
  204. adapter->phy_read = netxen_niu_gbe_phy_read;
  205. adapter->phy_write = netxen_niu_gbe_phy_write;
  206. adapter->init_port = netxen_niu_gbe_init_port;
  207. adapter->init_niu = netxen_nic_init_niu_gb;
  208. adapter->stop_port = netxen_niu_disable_gbe_port;
  209. break;
  210. case NETXEN_NIC_XGBE:
  211. adapter->enable_phy_interrupts =
  212. netxen_niu_xgbe_enable_phy_interrupts;
  213. adapter->disable_phy_interrupts =
  214. netxen_niu_xgbe_disable_phy_interrupts;
  215. adapter->handle_phy_intr = netxen_nic_xgbe_handle_phy_intr;
  216. adapter->macaddr_set = netxen_niu_xg_macaddr_set;
  217. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  218. adapter->init_port = netxen_niu_xg_init_port;
  219. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  220. adapter->unset_promisc = netxen_niu_xg_set_promiscuous_mode;
  221. adapter->stop_port = netxen_niu_disable_xg_port;
  222. break;
  223. default:
  224. break;
  225. }
  226. }
  227. /*
  228. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  229. * address to external PCI CRB address.
  230. */
  231. unsigned long netxen_decode_crb_addr(unsigned long addr)
  232. {
  233. int i;
  234. unsigned long base_addr, offset, pci_base;
  235. crb_addr_transform_setup();
  236. pci_base = NETXEN_ADDR_ERROR;
  237. base_addr = addr & 0xfff00000;
  238. offset = addr & 0x000fffff;
  239. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  240. if (crb_addr_xform[i] == base_addr) {
  241. pci_base = i << 20;
  242. break;
  243. }
  244. }
  245. if (pci_base == NETXEN_ADDR_ERROR)
  246. return pci_base;
  247. else
  248. return (pci_base + offset);
  249. }
  250. static long rom_max_timeout = 10000;
  251. static long rom_lock_timeout = 1000000;
  252. static long rom_write_timeout = 700;
  253. static inline int rom_lock(struct netxen_adapter *adapter)
  254. {
  255. int iter;
  256. u32 done = 0;
  257. int timeout = 0;
  258. while (!done) {
  259. /* acquire semaphore2 from PCI HW block */
  260. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
  261. &done);
  262. if (done == 1)
  263. break;
  264. if (timeout >= rom_lock_timeout)
  265. return -EIO;
  266. timeout++;
  267. /*
  268. * Yield CPU
  269. */
  270. if (!in_atomic())
  271. schedule();
  272. else {
  273. for (iter = 0; iter < 20; iter++)
  274. cpu_relax(); /*This a nop instr on i386 */
  275. }
  276. }
  277. netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  278. return 0;
  279. }
  280. int netxen_wait_rom_done(struct netxen_adapter *adapter)
  281. {
  282. long timeout = 0;
  283. long done = 0;
  284. while (done == 0) {
  285. done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
  286. done &= 2;
  287. timeout++;
  288. if (timeout >= rom_max_timeout) {
  289. printk("Timeout reached waiting for rom done");
  290. return -EIO;
  291. }
  292. }
  293. return 0;
  294. }
  295. static inline int netxen_rom_wren(struct netxen_adapter *adapter)
  296. {
  297. /* Set write enable latch in ROM status register */
  298. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  299. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  300. M25P_INSTR_WREN);
  301. if (netxen_wait_rom_done(adapter)) {
  302. return -1;
  303. }
  304. return 0;
  305. }
  306. static inline unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter,
  307. unsigned int addr)
  308. {
  309. unsigned int data = 0xdeaddead;
  310. data = netxen_nic_reg_read(adapter, addr);
  311. return data;
  312. }
  313. static inline int netxen_do_rom_rdsr(struct netxen_adapter *adapter)
  314. {
  315. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  316. M25P_INSTR_RDSR);
  317. if (netxen_wait_rom_done(adapter)) {
  318. return -1;
  319. }
  320. return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA);
  321. }
  322. static inline void netxen_rom_unlock(struct netxen_adapter *adapter)
  323. {
  324. u32 val;
  325. /* release semaphore2 */
  326. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
  327. }
  328. int netxen_rom_wip_poll(struct netxen_adapter *adapter)
  329. {
  330. long timeout = 0;
  331. long wip = 1;
  332. int val;
  333. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  334. while (wip != 0) {
  335. val = netxen_do_rom_rdsr(adapter);
  336. wip = val & 1;
  337. timeout++;
  338. if (timeout > rom_max_timeout) {
  339. return -1;
  340. }
  341. }
  342. return 0;
  343. }
  344. static inline int do_rom_fast_write(struct netxen_adapter *adapter, int addr,
  345. int data)
  346. {
  347. if (netxen_rom_wren(adapter)) {
  348. return -1;
  349. }
  350. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  351. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  352. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  353. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  354. M25P_INSTR_PP);
  355. if (netxen_wait_rom_done(adapter)) {
  356. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  357. return -1;
  358. }
  359. return netxen_rom_wip_poll(adapter);
  360. }
  361. static inline int
  362. do_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  363. {
  364. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  365. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  366. udelay(70); /* prevent bursting on CRB */
  367. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  368. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  369. if (netxen_wait_rom_done(adapter)) {
  370. printk("Error waiting for rom done\n");
  371. return -EIO;
  372. }
  373. /* reset abyte_cnt and dummy_byte_cnt */
  374. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  375. udelay(70); /* prevent bursting on CRB */
  376. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  377. *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
  378. return 0;
  379. }
  380. static inline int
  381. do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  382. u8 *bytes, size_t size)
  383. {
  384. int addridx;
  385. int ret = 0;
  386. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  387. ret = do_rom_fast_read(adapter, addridx, (int *)bytes);
  388. if (ret != 0)
  389. break;
  390. bytes += 4;
  391. }
  392. return ret;
  393. }
  394. int
  395. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  396. u8 *bytes, size_t size)
  397. {
  398. int ret;
  399. ret = rom_lock(adapter);
  400. if (ret < 0)
  401. return ret;
  402. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  403. netxen_rom_unlock(adapter);
  404. return ret;
  405. }
  406. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  407. {
  408. int ret;
  409. if (rom_lock(adapter) != 0)
  410. return -EIO;
  411. ret = do_rom_fast_read(adapter, addr, valp);
  412. netxen_rom_unlock(adapter);
  413. return ret;
  414. }
  415. int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data)
  416. {
  417. int ret = 0;
  418. if (rom_lock(adapter) != 0) {
  419. return -1;
  420. }
  421. ret = do_rom_fast_write(adapter, addr, data);
  422. netxen_rom_unlock(adapter);
  423. return ret;
  424. }
  425. static inline int do_rom_fast_write_words(struct netxen_adapter *adapter,
  426. int addr, u8 *bytes, size_t size)
  427. {
  428. int addridx = addr;
  429. int ret = 0;
  430. while (addridx < (addr + size)) {
  431. int last_attempt = 0;
  432. int timeout = 0;
  433. int data;
  434. data = *(u32*)bytes;
  435. ret = do_rom_fast_write(adapter, addridx, data);
  436. if (ret < 0)
  437. return ret;
  438. while(1) {
  439. int data1;
  440. do_rom_fast_read(adapter, addridx, &data1);
  441. if (data1 == data)
  442. break;
  443. if (timeout++ >= rom_write_timeout) {
  444. if (last_attempt++ < 4) {
  445. ret = do_rom_fast_write(adapter,
  446. addridx, data);
  447. if (ret < 0)
  448. return ret;
  449. }
  450. else {
  451. printk(KERN_INFO "Data write did not "
  452. "succeed at address 0x%x\n", addridx);
  453. break;
  454. }
  455. }
  456. }
  457. bytes += 4;
  458. addridx += 4;
  459. }
  460. return ret;
  461. }
  462. int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
  463. u8 *bytes, size_t size)
  464. {
  465. int ret = 0;
  466. ret = rom_lock(adapter);
  467. if (ret < 0)
  468. return ret;
  469. ret = do_rom_fast_write_words(adapter, addr, bytes, size);
  470. netxen_rom_unlock(adapter);
  471. return ret;
  472. }
  473. int netxen_rom_wrsr(struct netxen_adapter *adapter, int data)
  474. {
  475. int ret;
  476. ret = netxen_rom_wren(adapter);
  477. if (ret < 0)
  478. return ret;
  479. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  480. netxen_crb_writelit_adapter(adapter,
  481. NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0x1);
  482. ret = netxen_wait_rom_done(adapter);
  483. if (ret < 0)
  484. return ret;
  485. return netxen_rom_wip_poll(adapter);
  486. }
  487. int netxen_rom_rdsr(struct netxen_adapter *adapter)
  488. {
  489. int ret;
  490. ret = rom_lock(adapter);
  491. if (ret < 0)
  492. return ret;
  493. ret = netxen_do_rom_rdsr(adapter);
  494. netxen_rom_unlock(adapter);
  495. return ret;
  496. }
  497. int netxen_backup_crbinit(struct netxen_adapter *adapter)
  498. {
  499. int ret = FLASH_SUCCESS;
  500. int val;
  501. char *buffer = kmalloc(FLASH_SECTOR_SIZE, GFP_KERNEL);
  502. if (!buffer)
  503. return -ENOMEM;
  504. /* unlock sector 63 */
  505. val = netxen_rom_rdsr(adapter);
  506. val = val & 0xe3;
  507. ret = netxen_rom_wrsr(adapter, val);
  508. if (ret != FLASH_SUCCESS)
  509. goto out_kfree;
  510. ret = netxen_rom_wip_poll(adapter);
  511. if (ret != FLASH_SUCCESS)
  512. goto out_kfree;
  513. /* copy sector 0 to sector 63 */
  514. ret = netxen_rom_fast_read_words(adapter, CRBINIT_START,
  515. buffer, FLASH_SECTOR_SIZE);
  516. if (ret != FLASH_SUCCESS)
  517. goto out_kfree;
  518. ret = netxen_rom_fast_write_words(adapter, FIXED_START,
  519. buffer, FLASH_SECTOR_SIZE);
  520. if (ret != FLASH_SUCCESS)
  521. goto out_kfree;
  522. /* lock sector 63 */
  523. val = netxen_rom_rdsr(adapter);
  524. if (!(val & 0x8)) {
  525. val |= (0x1 << 2);
  526. /* lock sector 63 */
  527. if (netxen_rom_wrsr(adapter, val) == 0) {
  528. ret = netxen_rom_wip_poll(adapter);
  529. if (ret != FLASH_SUCCESS)
  530. goto out_kfree;
  531. /* lock SR writes */
  532. ret = netxen_rom_wip_poll(adapter);
  533. if (ret != FLASH_SUCCESS)
  534. goto out_kfree;
  535. }
  536. }
  537. out_kfree:
  538. kfree(buffer);
  539. return ret;
  540. }
  541. int netxen_do_rom_se(struct netxen_adapter *adapter, int addr)
  542. {
  543. netxen_rom_wren(adapter);
  544. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  545. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  546. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  547. M25P_INSTR_SE);
  548. if (netxen_wait_rom_done(adapter)) {
  549. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  550. return -1;
  551. }
  552. return netxen_rom_wip_poll(adapter);
  553. }
  554. void check_erased_flash(struct netxen_adapter *adapter, int addr)
  555. {
  556. int i;
  557. int val;
  558. int count = 0, erased_errors = 0;
  559. int range;
  560. range = (addr == USER_START) ? FIXED_START : addr + FLASH_SECTOR_SIZE;
  561. for (i = addr; i < range; i += 4) {
  562. netxen_rom_fast_read(adapter, i, &val);
  563. if (val != 0xffffffff)
  564. erased_errors++;
  565. count++;
  566. }
  567. if (erased_errors)
  568. printk(KERN_INFO "0x%x out of 0x%x words fail to be erased "
  569. "for sector address: %x\n", erased_errors, count, addr);
  570. }
  571. int netxen_rom_se(struct netxen_adapter *adapter, int addr)
  572. {
  573. int ret = 0;
  574. if (rom_lock(adapter) != 0) {
  575. return -1;
  576. }
  577. ret = netxen_do_rom_se(adapter, addr);
  578. netxen_rom_unlock(adapter);
  579. msleep(30);
  580. check_erased_flash(adapter, addr);
  581. return ret;
  582. }
  583. int
  584. netxen_flash_erase_sections(struct netxen_adapter *adapter, int start, int end)
  585. {
  586. int ret = FLASH_SUCCESS;
  587. int i;
  588. for (i = start; i < end; i++) {
  589. ret = netxen_rom_se(adapter, i * FLASH_SECTOR_SIZE);
  590. if (ret)
  591. break;
  592. ret = netxen_rom_wip_poll(adapter);
  593. if (ret < 0)
  594. return ret;
  595. }
  596. return ret;
  597. }
  598. int
  599. netxen_flash_erase_secondary(struct netxen_adapter *adapter)
  600. {
  601. int ret = FLASH_SUCCESS;
  602. int start, end;
  603. start = SECONDARY_START / FLASH_SECTOR_SIZE;
  604. end = USER_START / FLASH_SECTOR_SIZE;
  605. ret = netxen_flash_erase_sections(adapter, start, end);
  606. return ret;
  607. }
  608. int
  609. netxen_flash_erase_primary(struct netxen_adapter *adapter)
  610. {
  611. int ret = FLASH_SUCCESS;
  612. int start, end;
  613. start = PRIMARY_START / FLASH_SECTOR_SIZE;
  614. end = SECONDARY_START / FLASH_SECTOR_SIZE;
  615. ret = netxen_flash_erase_sections(adapter, start, end);
  616. return ret;
  617. }
  618. void netxen_halt_pegs(struct netxen_adapter *adapter)
  619. {
  620. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x3c, 1);
  621. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x3c, 1);
  622. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x3c, 1);
  623. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x3c, 1);
  624. }
  625. int netxen_flash_unlock(struct netxen_adapter *adapter)
  626. {
  627. int ret = 0;
  628. ret = netxen_rom_wrsr(adapter, 0);
  629. if (ret < 0)
  630. return ret;
  631. ret = netxen_rom_wren(adapter);
  632. if (ret < 0)
  633. return ret;
  634. return ret;
  635. }
  636. #define NETXEN_BOARDTYPE 0x4008
  637. #define NETXEN_BOARDNUM 0x400c
  638. #define NETXEN_CHIPNUM 0x4010
  639. #define NETXEN_ROMBUS_RESET 0xFFFFFFFF
  640. #define NETXEN_ROM_FIRST_BARRIER 0x800000000ULL
  641. #define NETXEN_ROM_FOUND_INIT 0x400
  642. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  643. {
  644. int addr, val, status;
  645. int n, i;
  646. int init_delay = 0;
  647. struct crb_addr_pair *buf;
  648. unsigned long off;
  649. /* resetall */
  650. status = netxen_nic_get_board_info(adapter);
  651. if (status)
  652. printk("%s: netxen_pinit_from_rom: Error getting board info\n",
  653. netxen_nic_driver_name);
  654. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  655. NETXEN_ROMBUS_RESET);
  656. if (verbose) {
  657. int val;
  658. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  659. printk("P2 ROM board type: 0x%08x\n", val);
  660. else
  661. printk("Could not read board type\n");
  662. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  663. printk("P2 ROM board num: 0x%08x\n", val);
  664. else
  665. printk("Could not read board number\n");
  666. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  667. printk("P2 ROM chip num: 0x%08x\n", val);
  668. else
  669. printk("Could not read chip number\n");
  670. }
  671. if (netxen_rom_fast_read(adapter, 0, &n) == 0
  672. && (n & NETXEN_ROM_FIRST_BARRIER)) {
  673. n &= ~NETXEN_ROM_ROUNDUP;
  674. if (n < NETXEN_ROM_FOUND_INIT) {
  675. if (verbose)
  676. printk("%s: %d CRB init values found"
  677. " in ROM.\n", netxen_nic_driver_name, n);
  678. } else {
  679. printk("%s:n=0x%x Error! NetXen card flash not"
  680. " initialized.\n", __FUNCTION__, n);
  681. return -EIO;
  682. }
  683. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  684. if (buf == NULL) {
  685. printk("%s: netxen_pinit_from_rom: Unable to calloc "
  686. "memory.\n", netxen_nic_driver_name);
  687. return -ENOMEM;
  688. }
  689. for (i = 0; i < n; i++) {
  690. if (netxen_rom_fast_read(adapter, 8 * i + 4, &val) != 0
  691. || netxen_rom_fast_read(adapter, 8 * i + 8,
  692. &addr) != 0)
  693. return -EIO;
  694. buf[i].addr = addr;
  695. buf[i].data = val;
  696. if (verbose)
  697. printk("%s: PCI: 0x%08x == 0x%08x\n",
  698. netxen_nic_driver_name, (unsigned int)
  699. netxen_decode_crb_addr((unsigned long)
  700. addr), val);
  701. }
  702. for (i = 0; i < n; i++) {
  703. off = netxen_decode_crb_addr((unsigned long)buf[i].addr);
  704. if (off == NETXEN_ADDR_ERROR) {
  705. printk(KERN_ERR"CRB init value out of range %lx\n",
  706. buf[i].addr);
  707. continue;
  708. }
  709. off += NETXEN_PCI_CRBSPACE;
  710. /* skipping cold reboot MAGIC */
  711. if (off == NETXEN_CAM_RAM(0x1fc))
  712. continue;
  713. /* After writing this register, HW needs time for CRB */
  714. /* to quiet down (else crb_window returns 0xffffffff) */
  715. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  716. init_delay = 1;
  717. /* hold xdma in reset also */
  718. buf[i].data = NETXEN_NIC_XDMA_RESET;
  719. }
  720. if (ADDR_IN_WINDOW1(off)) {
  721. writel(buf[i].data,
  722. NETXEN_CRB_NORMALIZE(adapter, off));
  723. } else {
  724. netxen_nic_pci_change_crbwindow(adapter, 0);
  725. writel(buf[i].data,
  726. pci_base_offset(adapter, off));
  727. netxen_nic_pci_change_crbwindow(adapter, 1);
  728. }
  729. if (init_delay == 1) {
  730. ssleep(1);
  731. init_delay = 0;
  732. }
  733. msleep(1);
  734. }
  735. kfree(buf);
  736. /* disable_peg_cache_all */
  737. /* unreset_net_cache */
  738. netxen_nic_hw_read_wx(adapter, NETXEN_ROMUSB_GLB_SW_RESET, &val,
  739. 4);
  740. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  741. (val & 0xffffff0f));
  742. /* p2dn replyCount */
  743. netxen_crb_writelit_adapter(adapter,
  744. NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  745. /* disable_peg_cache 0 */
  746. netxen_crb_writelit_adapter(adapter,
  747. NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  748. /* disable_peg_cache 1 */
  749. netxen_crb_writelit_adapter(adapter,
  750. NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  751. /* peg_clr_all */
  752. /* peg_clr 0 */
  753. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8,
  754. 0);
  755. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc,
  756. 0);
  757. /* peg_clr 1 */
  758. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8,
  759. 0);
  760. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc,
  761. 0);
  762. /* peg_clr 2 */
  763. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8,
  764. 0);
  765. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc,
  766. 0);
  767. /* peg_clr 3 */
  768. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8,
  769. 0);
  770. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc,
  771. 0);
  772. }
  773. return 0;
  774. }
  775. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  776. {
  777. uint64_t addr;
  778. uint32_t hi;
  779. uint32_t lo;
  780. adapter->dummy_dma.addr =
  781. pci_alloc_consistent(adapter->ahw.pdev,
  782. NETXEN_HOST_DUMMY_DMA_SIZE,
  783. &adapter->dummy_dma.phys_addr);
  784. if (adapter->dummy_dma.addr == NULL) {
  785. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  786. __FUNCTION__);
  787. return -ENOMEM;
  788. }
  789. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  790. hi = (addr >> 32) & 0xffffffff;
  791. lo = addr & 0xffffffff;
  792. writel(hi, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI));
  793. writel(lo, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO));
  794. return 0;
  795. }
  796. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  797. {
  798. if (adapter->dummy_dma.addr) {
  799. pci_free_consistent(adapter->ahw.pdev,
  800. NETXEN_HOST_DUMMY_DMA_SIZE,
  801. adapter->dummy_dma.addr,
  802. adapter->dummy_dma.phys_addr);
  803. adapter->dummy_dma.addr = NULL;
  804. }
  805. }
  806. void netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  807. {
  808. u32 val = 0;
  809. int loops = 0;
  810. if (!pegtune_val) {
  811. val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  812. while (val != PHAN_INITIALIZE_COMPLETE && loops < 200000) {
  813. udelay(100);
  814. schedule();
  815. val =
  816. readl(NETXEN_CRB_NORMALIZE
  817. (adapter, CRB_CMDPEG_STATE));
  818. loops++;
  819. }
  820. if (val != PHAN_INITIALIZE_COMPLETE)
  821. printk("WARNING: Initial boot wait loop failed...\n");
  822. }
  823. }
  824. int netxen_nic_rx_has_work(struct netxen_adapter *adapter)
  825. {
  826. int ctx;
  827. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  828. struct netxen_recv_context *recv_ctx =
  829. &(adapter->recv_ctx[ctx]);
  830. u32 consumer;
  831. struct status_desc *desc_head;
  832. struct status_desc *desc;
  833. consumer = recv_ctx->status_rx_consumer;
  834. desc_head = recv_ctx->rcv_status_desc_head;
  835. desc = &desc_head[consumer];
  836. if (netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)
  837. return 1;
  838. }
  839. return 0;
  840. }
  841. static inline int netxen_nic_check_temp(struct netxen_adapter *adapter)
  842. {
  843. int port_num;
  844. struct netxen_port *port;
  845. struct net_device *netdev;
  846. uint32_t temp, temp_state, temp_val;
  847. int rv = 0;
  848. temp = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_TEMP_STATE));
  849. temp_state = nx_get_temp_state(temp);
  850. temp_val = nx_get_temp_val(temp);
  851. if (temp_state == NX_TEMP_PANIC) {
  852. printk(KERN_ALERT
  853. "%s: Device temperature %d degrees C exceeds"
  854. " maximum allowed. Hardware has been shut down.\n",
  855. netxen_nic_driver_name, temp_val);
  856. for (port_num = 0; port_num < adapter->ahw.max_ports;
  857. port_num++) {
  858. port = adapter->port[port_num];
  859. netdev = port->netdev;
  860. netif_carrier_off(netdev);
  861. netif_stop_queue(netdev);
  862. }
  863. rv = 1;
  864. } else if (temp_state == NX_TEMP_WARN) {
  865. if (adapter->temp == NX_TEMP_NORMAL) {
  866. printk(KERN_ALERT
  867. "%s: Device temperature %d degrees C "
  868. "exceeds operating range."
  869. " Immediate action needed.\n",
  870. netxen_nic_driver_name, temp_val);
  871. }
  872. } else {
  873. if (adapter->temp == NX_TEMP_WARN) {
  874. printk(KERN_INFO
  875. "%s: Device temperature is now %d degrees C"
  876. " in normal range.\n", netxen_nic_driver_name,
  877. temp_val);
  878. }
  879. }
  880. adapter->temp = temp_state;
  881. return rv;
  882. }
  883. void netxen_watchdog_task(struct work_struct *work)
  884. {
  885. int port_num;
  886. struct netxen_port *port;
  887. struct net_device *netdev;
  888. struct netxen_adapter *adapter =
  889. container_of(work, struct netxen_adapter, watchdog_task);
  890. if (netxen_nic_check_temp(adapter))
  891. return;
  892. for (port_num = 0; port_num < adapter->ahw.max_ports; port_num++) {
  893. port = adapter->port[port_num];
  894. netdev = port->netdev;
  895. if ((netif_running(netdev)) && !netif_carrier_ok(netdev)) {
  896. printk(KERN_INFO "%s port %d, %s carrier is now ok\n",
  897. netxen_nic_driver_name, port_num, netdev->name);
  898. netif_carrier_on(netdev);
  899. }
  900. if (netif_queue_stopped(netdev))
  901. netif_wake_queue(netdev);
  902. }
  903. if (adapter->handle_phy_intr)
  904. adapter->handle_phy_intr(adapter);
  905. mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
  906. }
  907. /*
  908. * netxen_process_rcv() send the received packet to the protocol stack.
  909. * and if the number of receives exceeds RX_BUFFERS_REFILL, then we
  910. * invoke the routine to send more rx buffers to the Phantom...
  911. */
  912. void
  913. netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
  914. struct status_desc *desc)
  915. {
  916. struct netxen_port *port = adapter->port[netxen_get_sts_port(desc)];
  917. struct pci_dev *pdev = port->pdev;
  918. struct net_device *netdev = port->netdev;
  919. int index = netxen_get_sts_refhandle(desc);
  920. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  921. struct netxen_rx_buffer *buffer;
  922. struct sk_buff *skb;
  923. u32 length = netxen_get_sts_totallength(desc);
  924. u32 desc_ctx;
  925. struct netxen_rcv_desc_ctx *rcv_desc;
  926. int ret;
  927. desc_ctx = netxen_get_sts_type(desc);
  928. if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
  929. printk("%s: %s Bad Rcv descriptor ring\n",
  930. netxen_nic_driver_name, netdev->name);
  931. return;
  932. }
  933. rcv_desc = &recv_ctx->rcv_desc[desc_ctx];
  934. if (unlikely(index > rcv_desc->max_rx_desc_count)) {
  935. DPRINTK(ERR, "Got a buffer index:%x Max is %x\n",
  936. index, rcv_desc->max_rx_desc_count);
  937. return;
  938. }
  939. buffer = &rcv_desc->rx_buf_arr[index];
  940. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  941. buffer->lro_current_frags++;
  942. if (netxen_get_sts_desc_lro_last_frag(desc)) {
  943. buffer->lro_expected_frags =
  944. netxen_get_sts_desc_lro_cnt(desc);
  945. buffer->lro_length = length;
  946. }
  947. if (buffer->lro_current_frags != buffer->lro_expected_frags) {
  948. if (buffer->lro_expected_frags != 0) {
  949. printk("LRO: (refhandle:%x) recv frag."
  950. "wait for last. flags: %x expected:%d"
  951. "have:%d\n", index,
  952. netxen_get_sts_desc_lro_last_frag(desc),
  953. buffer->lro_expected_frags,
  954. buffer->lro_current_frags);
  955. }
  956. return;
  957. }
  958. }
  959. pci_unmap_single(pdev, buffer->dma, rcv_desc->dma_size,
  960. PCI_DMA_FROMDEVICE);
  961. skb = (struct sk_buff *)buffer->skb;
  962. if (likely(netxen_get_sts_status(desc) == STATUS_CKSUM_OK)) {
  963. port->stats.csummed++;
  964. skb->ip_summed = CHECKSUM_UNNECESSARY;
  965. }
  966. skb->dev = netdev;
  967. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  968. /* True length was only available on the last pkt */
  969. skb_put(skb, buffer->lro_length);
  970. } else {
  971. skb_put(skb, length);
  972. }
  973. skb->protocol = eth_type_trans(skb, netdev);
  974. ret = netif_receive_skb(skb);
  975. /*
  976. * RH: Do we need these stats on a regular basis. Can we get it from
  977. * Linux stats.
  978. */
  979. switch (ret) {
  980. case NET_RX_SUCCESS:
  981. port->stats.uphappy++;
  982. break;
  983. case NET_RX_CN_LOW:
  984. port->stats.uplcong++;
  985. break;
  986. case NET_RX_CN_MOD:
  987. port->stats.upmcong++;
  988. break;
  989. case NET_RX_CN_HIGH:
  990. port->stats.uphcong++;
  991. break;
  992. case NET_RX_DROP:
  993. port->stats.updropped++;
  994. break;
  995. default:
  996. port->stats.updunno++;
  997. break;
  998. }
  999. netdev->last_rx = jiffies;
  1000. rcv_desc->rcv_free++;
  1001. rcv_desc->rcv_pending--;
  1002. /*
  1003. * We just consumed one buffer so post a buffer.
  1004. */
  1005. adapter->stats.post_called++;
  1006. buffer->skb = NULL;
  1007. buffer->state = NETXEN_BUFFER_FREE;
  1008. buffer->lro_current_frags = 0;
  1009. buffer->lro_expected_frags = 0;
  1010. port->stats.no_rcv++;
  1011. port->stats.rxbytes += length;
  1012. }
  1013. /* Process Receive status ring */
  1014. u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
  1015. {
  1016. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  1017. struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
  1018. struct status_desc *desc; /* used to read status desc here */
  1019. u32 consumer = recv_ctx->status_rx_consumer;
  1020. u32 producer = 0;
  1021. int count = 0, ring;
  1022. DPRINTK(INFO, "procesing receive\n");
  1023. /*
  1024. * we assume in this case that there is only one port and that is
  1025. * port #1...changes need to be done in firmware to indicate port
  1026. * number as part of the descriptor. This way we will be able to get
  1027. * the netdev which is associated with that device.
  1028. */
  1029. while (count < max) {
  1030. desc = &desc_head[consumer];
  1031. if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) {
  1032. DPRINTK(ERR, "desc %p ownedby %x\n", desc,
  1033. netxen_get_sts_owner(desc));
  1034. break;
  1035. }
  1036. netxen_process_rcv(adapter, ctxid, desc);
  1037. netxen_clear_sts_owner(desc);
  1038. netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM);
  1039. consumer = (consumer + 1) & (adapter->max_rx_desc_count - 1);
  1040. count++;
  1041. }
  1042. if (count) {
  1043. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  1044. netxen_post_rx_buffers_nodb(adapter, ctxid, ring);
  1045. }
  1046. }
  1047. /* update the consumer index in phantom */
  1048. if (count) {
  1049. adapter->stats.process_rcv++;
  1050. recv_ctx->status_rx_consumer = consumer;
  1051. recv_ctx->status_rx_producer = producer;
  1052. /* Window = 1 */
  1053. writel(consumer,
  1054. NETXEN_CRB_NORMALIZE(adapter,
  1055. recv_crb_registers[ctxid].
  1056. crb_rcv_status_consumer));
  1057. }
  1058. return count;
  1059. }
  1060. /* Process Command status ring */
  1061. int netxen_process_cmd_ring(unsigned long data)
  1062. {
  1063. u32 last_consumer;
  1064. u32 consumer;
  1065. struct netxen_adapter *adapter = (struct netxen_adapter *)data;
  1066. int count1 = 0;
  1067. int count2 = 0;
  1068. struct netxen_cmd_buffer *buffer;
  1069. struct netxen_port *port; /* port #1 */
  1070. struct netxen_port *nport;
  1071. struct pci_dev *pdev;
  1072. struct netxen_skb_frag *frag;
  1073. u32 i;
  1074. struct sk_buff *skb = NULL;
  1075. int p;
  1076. int done;
  1077. spin_lock(&adapter->tx_lock);
  1078. last_consumer = adapter->last_cmd_consumer;
  1079. DPRINTK(INFO, "procesing xmit complete\n");
  1080. /* we assume in this case that there is only one port and that is
  1081. * port #1...changes need to be done in firmware to indicate port
  1082. * number as part of the descriptor. This way we will be able to get
  1083. * the netdev which is associated with that device.
  1084. */
  1085. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1086. if (last_consumer == consumer) { /* Ring is empty */
  1087. DPRINTK(INFO, "last_consumer %d == consumer %d\n",
  1088. last_consumer, consumer);
  1089. spin_unlock(&adapter->tx_lock);
  1090. return 1;
  1091. }
  1092. adapter->proc_cmd_buf_counter++;
  1093. adapter->stats.process_xmit++;
  1094. /*
  1095. * Not needed - does not seem to be used anywhere.
  1096. * adapter->cmd_consumer = consumer;
  1097. */
  1098. spin_unlock(&adapter->tx_lock);
  1099. while ((last_consumer != consumer) && (count1 < MAX_STATUS_HANDLE)) {
  1100. buffer = &adapter->cmd_buf_arr[last_consumer];
  1101. port = adapter->port[buffer->port];
  1102. pdev = port->pdev;
  1103. frag = &buffer->frag_array[0];
  1104. skb = buffer->skb;
  1105. if (skb && (cmpxchg(&buffer->skb, skb, 0) == skb)) {
  1106. pci_unmap_single(pdev, frag->dma, frag->length,
  1107. PCI_DMA_TODEVICE);
  1108. for (i = 1; i < buffer->frag_count; i++) {
  1109. DPRINTK(INFO, "getting fragment no %d\n", i);
  1110. frag++; /* Get the next frag */
  1111. pci_unmap_page(pdev, frag->dma, frag->length,
  1112. PCI_DMA_TODEVICE);
  1113. }
  1114. port->stats.skbfreed++;
  1115. dev_kfree_skb_any(skb);
  1116. skb = NULL;
  1117. } else if (adapter->proc_cmd_buf_counter == 1) {
  1118. port->stats.txnullskb++;
  1119. }
  1120. if (unlikely(netif_queue_stopped(port->netdev)
  1121. && netif_carrier_ok(port->netdev))
  1122. && ((jiffies - port->netdev->trans_start) >
  1123. port->netdev->watchdog_timeo)) {
  1124. SCHEDULE_WORK(&port->tx_timeout_task);
  1125. }
  1126. last_consumer = get_next_index(last_consumer,
  1127. adapter->max_tx_desc_count);
  1128. count1++;
  1129. }
  1130. adapter->stats.noxmitdone += count1;
  1131. count2 = 0;
  1132. spin_lock(&adapter->tx_lock);
  1133. if ((--adapter->proc_cmd_buf_counter) == 0) {
  1134. adapter->last_cmd_consumer = last_consumer;
  1135. while ((adapter->last_cmd_consumer != consumer)
  1136. && (count2 < MAX_STATUS_HANDLE)) {
  1137. buffer =
  1138. &adapter->cmd_buf_arr[adapter->last_cmd_consumer];
  1139. count2++;
  1140. if (buffer->skb)
  1141. break;
  1142. else
  1143. adapter->last_cmd_consumer =
  1144. get_next_index(adapter->last_cmd_consumer,
  1145. adapter->max_tx_desc_count);
  1146. }
  1147. }
  1148. if (count1 || count2) {
  1149. for (p = 0; p < adapter->ahw.max_ports; p++) {
  1150. nport = adapter->port[p];
  1151. if (netif_queue_stopped(nport->netdev)
  1152. && (nport->flags & NETXEN_NETDEV_STATUS)) {
  1153. netif_wake_queue(nport->netdev);
  1154. nport->flags &= ~NETXEN_NETDEV_STATUS;
  1155. }
  1156. }
  1157. }
  1158. /*
  1159. * If everything is freed up to consumer then check if the ring is full
  1160. * If the ring is full then check if more needs to be freed and
  1161. * schedule the call back again.
  1162. *
  1163. * This happens when there are 2 CPUs. One could be freeing and the
  1164. * other filling it. If the ring is full when we get out of here and
  1165. * the card has already interrupted the host then the host can miss the
  1166. * interrupt.
  1167. *
  1168. * There is still a possible race condition and the host could miss an
  1169. * interrupt. The card has to take care of this.
  1170. */
  1171. if (adapter->last_cmd_consumer == consumer &&
  1172. (((adapter->cmd_producer + 1) %
  1173. adapter->max_tx_desc_count) == adapter->last_cmd_consumer)) {
  1174. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1175. }
  1176. done = (adapter->last_cmd_consumer == consumer);
  1177. spin_unlock(&adapter->tx_lock);
  1178. DPRINTK(INFO, "last consumer is %d in %s\n", last_consumer,
  1179. __FUNCTION__);
  1180. return (done);
  1181. }
  1182. /*
  1183. * netxen_post_rx_buffers puts buffer in the Phantom memory
  1184. */
  1185. void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
  1186. {
  1187. struct pci_dev *pdev = adapter->ahw.pdev;
  1188. struct sk_buff *skb;
  1189. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1190. struct netxen_rcv_desc_ctx *rcv_desc = NULL;
  1191. uint producer;
  1192. struct rcv_desc *pdesc;
  1193. struct netxen_rx_buffer *buffer;
  1194. int count = 0;
  1195. int index = 0;
  1196. netxen_ctx_msg msg = 0;
  1197. dma_addr_t dma;
  1198. adapter->stats.post_called++;
  1199. rcv_desc = &recv_ctx->rcv_desc[ringid];
  1200. producer = rcv_desc->producer;
  1201. index = rcv_desc->begin_alloc;
  1202. buffer = &rcv_desc->rx_buf_arr[index];
  1203. /* We can start writing rx descriptors into the phantom memory. */
  1204. while (buffer->state == NETXEN_BUFFER_FREE) {
  1205. skb = dev_alloc_skb(rcv_desc->skb_size);
  1206. if (unlikely(!skb)) {
  1207. /*
  1208. * TODO
  1209. * We need to schedule the posting of buffers to the pegs.
  1210. */
  1211. rcv_desc->begin_alloc = index;
  1212. DPRINTK(ERR, "netxen_post_rx_buffers: "
  1213. " allocated only %d buffers\n", count);
  1214. break;
  1215. }
  1216. count++; /* now there should be no failure */
  1217. pdesc = &rcv_desc->desc_head[producer];
  1218. #if defined(XGB_DEBUG)
  1219. *(unsigned long *)(skb->head) = 0xc0debabe;
  1220. if (skb_is_nonlinear(skb)) {
  1221. printk("Allocated SKB @%p is nonlinear\n");
  1222. }
  1223. #endif
  1224. skb_reserve(skb, 2);
  1225. /* This will be setup when we receive the
  1226. * buffer after it has been filled FSL TBD TBD
  1227. * skb->dev = netdev;
  1228. */
  1229. dma = pci_map_single(pdev, skb->data, rcv_desc->dma_size,
  1230. PCI_DMA_FROMDEVICE);
  1231. pdesc->addr_buffer = cpu_to_le64(dma);
  1232. buffer->skb = skb;
  1233. buffer->state = NETXEN_BUFFER_BUSY;
  1234. buffer->dma = dma;
  1235. /* make a rcv descriptor */
  1236. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1237. pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
  1238. DPRINTK(INFO, "done writing descripter\n");
  1239. producer =
  1240. get_next_index(producer, rcv_desc->max_rx_desc_count);
  1241. index = get_next_index(index, rcv_desc->max_rx_desc_count);
  1242. buffer = &rcv_desc->rx_buf_arr[index];
  1243. }
  1244. /* if we did allocate buffers, then write the count to Phantom */
  1245. if (count) {
  1246. rcv_desc->begin_alloc = index;
  1247. rcv_desc->rcv_pending += count;
  1248. adapter->stats.lastposted = count;
  1249. adapter->stats.posted += count;
  1250. rcv_desc->producer = producer;
  1251. if (rcv_desc->rcv_free >= 32) {
  1252. rcv_desc->rcv_free = 0;
  1253. /* Window = 1 */
  1254. writel((producer - 1) &
  1255. (rcv_desc->max_rx_desc_count - 1),
  1256. NETXEN_CRB_NORMALIZE(adapter,
  1257. recv_crb_registers[0].
  1258. rcv_desc_crb[ringid].
  1259. crb_rcv_producer_offset));
  1260. /*
  1261. * Write a doorbell msg to tell phanmon of change in
  1262. * receive ring producer
  1263. */
  1264. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1265. netxen_set_msg_privid(msg);
  1266. netxen_set_msg_count(msg,
  1267. ((producer -
  1268. 1) & (rcv_desc->
  1269. max_rx_desc_count - 1)));
  1270. netxen_set_msg_ctxid(msg, 0);
  1271. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1272. writel(msg,
  1273. DB_NORMALIZE(adapter,
  1274. NETXEN_RCV_PRODUCER_OFFSET));
  1275. }
  1276. }
  1277. }
  1278. void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, uint32_t ctx,
  1279. uint32_t ringid)
  1280. {
  1281. struct pci_dev *pdev = adapter->ahw.pdev;
  1282. struct sk_buff *skb;
  1283. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1284. struct netxen_rcv_desc_ctx *rcv_desc = NULL;
  1285. u32 producer;
  1286. struct rcv_desc *pdesc;
  1287. struct netxen_rx_buffer *buffer;
  1288. int count = 0;
  1289. int index = 0;
  1290. adapter->stats.post_called++;
  1291. rcv_desc = &recv_ctx->rcv_desc[ringid];
  1292. producer = rcv_desc->producer;
  1293. index = rcv_desc->begin_alloc;
  1294. buffer = &rcv_desc->rx_buf_arr[index];
  1295. /* We can start writing rx descriptors into the phantom memory. */
  1296. while (buffer->state == NETXEN_BUFFER_FREE) {
  1297. skb = dev_alloc_skb(rcv_desc->skb_size);
  1298. if (unlikely(!skb)) {
  1299. /*
  1300. * We need to schedule the posting of buffers to the pegs.
  1301. */
  1302. rcv_desc->begin_alloc = index;
  1303. DPRINTK(ERR, "netxen_post_rx_buffers_nodb: "
  1304. " allocated only %d buffers\n", count);
  1305. break;
  1306. }
  1307. count++; /* now there should be no failure */
  1308. pdesc = &rcv_desc->desc_head[producer];
  1309. skb_reserve(skb, 2);
  1310. /*
  1311. * This will be setup when we receive the
  1312. * buffer after it has been filled
  1313. * skb->dev = netdev;
  1314. */
  1315. buffer->skb = skb;
  1316. buffer->state = NETXEN_BUFFER_BUSY;
  1317. buffer->dma = pci_map_single(pdev, skb->data,
  1318. rcv_desc->dma_size,
  1319. PCI_DMA_FROMDEVICE);
  1320. /* make a rcv descriptor */
  1321. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1322. pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
  1323. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1324. DPRINTK(INFO, "done writing descripter\n");
  1325. producer =
  1326. get_next_index(producer, rcv_desc->max_rx_desc_count);
  1327. index = get_next_index(index, rcv_desc->max_rx_desc_count);
  1328. buffer = &rcv_desc->rx_buf_arr[index];
  1329. }
  1330. /* if we did allocate buffers, then write the count to Phantom */
  1331. if (count) {
  1332. rcv_desc->begin_alloc = index;
  1333. rcv_desc->rcv_pending += count;
  1334. adapter->stats.lastposted = count;
  1335. adapter->stats.posted += count;
  1336. rcv_desc->producer = producer;
  1337. if (rcv_desc->rcv_free >= 32) {
  1338. rcv_desc->rcv_free = 0;
  1339. /* Window = 1 */
  1340. writel((producer - 1) &
  1341. (rcv_desc->max_rx_desc_count - 1),
  1342. NETXEN_CRB_NORMALIZE(adapter,
  1343. recv_crb_registers[0].
  1344. rcv_desc_crb[ringid].
  1345. crb_rcv_producer_offset));
  1346. wmb();
  1347. }
  1348. }
  1349. }
  1350. int netxen_nic_tx_has_work(struct netxen_adapter *adapter)
  1351. {
  1352. if (find_diff_among(adapter->last_cmd_consumer,
  1353. adapter->cmd_producer,
  1354. adapter->max_tx_desc_count) > 0)
  1355. return 1;
  1356. return 0;
  1357. }
  1358. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1359. {
  1360. struct netxen_port *port;
  1361. int port_num;
  1362. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1363. for (port_num = 0; port_num < adapter->ahw.max_ports; port_num++) {
  1364. port = adapter->port[port_num];
  1365. memset(&port->stats, 0, sizeof(port->stats));
  1366. }
  1367. }