at91sam9n12.dtsi 5.3 KB

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  1. /*
  2. * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
  3. *
  4. * Copyright (C) 2012 Atmel,
  5. * 2012 Hong Xu <hong.xu@atmel.com>
  6. *
  7. * Licensed under GPLv2 or later.
  8. */
  9. /include/ "skeleton.dtsi"
  10. / {
  11. model = "Atmel AT91SAM9N12 SoC";
  12. compatible = "atmel,at91sam9n12";
  13. interrupt-parent = <&aic>;
  14. aliases {
  15. serial0 = &dbgu;
  16. serial1 = &usart0;
  17. serial2 = &usart1;
  18. serial3 = &usart2;
  19. serial4 = &usart3;
  20. gpio0 = &pioA;
  21. gpio1 = &pioB;
  22. gpio2 = &pioC;
  23. gpio3 = &pioD;
  24. tcb0 = &tcb0;
  25. tcb1 = &tcb1;
  26. i2c0 = &i2c0;
  27. i2c1 = &i2c1;
  28. };
  29. cpus {
  30. cpu@0 {
  31. compatible = "arm,arm926ejs";
  32. };
  33. };
  34. memory {
  35. reg = <0x20000000 0x10000000>;
  36. };
  37. ahb {
  38. compatible = "simple-bus";
  39. #address-cells = <1>;
  40. #size-cells = <1>;
  41. ranges;
  42. apb {
  43. compatible = "simple-bus";
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. ranges;
  47. aic: interrupt-controller@fffff000 {
  48. #interrupt-cells = <3>;
  49. compatible = "atmel,at91rm9200-aic";
  50. interrupt-controller;
  51. reg = <0xfffff000 0x200>;
  52. };
  53. ramc0: ramc@ffffe800 {
  54. compatible = "atmel,at91sam9g45-ddramc";
  55. reg = <0xffffe800 0x200>;
  56. };
  57. pmc: pmc@fffffc00 {
  58. compatible = "atmel,at91rm9200-pmc";
  59. reg = <0xfffffc00 0x100>;
  60. };
  61. rstc@fffffe00 {
  62. compatible = "atmel,at91sam9g45-rstc";
  63. reg = <0xfffffe00 0x10>;
  64. };
  65. pit: timer@fffffe30 {
  66. compatible = "atmel,at91sam9260-pit";
  67. reg = <0xfffffe30 0xf>;
  68. interrupts = <1 4 7>;
  69. };
  70. shdwc@fffffe10 {
  71. compatible = "atmel,at91sam9x5-shdwc";
  72. reg = <0xfffffe10 0x10>;
  73. };
  74. tcb0: timer@f8008000 {
  75. compatible = "atmel,at91sam9x5-tcb";
  76. reg = <0xf8008000 0x100>;
  77. interrupts = <17 4 0>;
  78. };
  79. tcb1: timer@f800c000 {
  80. compatible = "atmel,at91sam9x5-tcb";
  81. reg = <0xf800c000 0x100>;
  82. interrupts = <17 4 0>;
  83. };
  84. dma: dma-controller@ffffec00 {
  85. compatible = "atmel,at91sam9g45-dma";
  86. reg = <0xffffec00 0x200>;
  87. interrupts = <20 4 0>;
  88. };
  89. pinctrl@fffff400 {
  90. #address-cells = <1>;
  91. #size-cells = <1>;
  92. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  93. ranges = <0xfffff400 0xfffff400 0x800>;
  94. pioA: gpio@fffff400 {
  95. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  96. reg = <0xfffff400 0x200>;
  97. interrupts = <2 4 1>;
  98. #gpio-cells = <2>;
  99. gpio-controller;
  100. interrupt-controller;
  101. #interrupt-cells = <2>;
  102. };
  103. pioB: gpio@fffff600 {
  104. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  105. reg = <0xfffff600 0x200>;
  106. interrupts = <2 4 1>;
  107. #gpio-cells = <2>;
  108. gpio-controller;
  109. interrupt-controller;
  110. #interrupt-cells = <2>;
  111. };
  112. pioC: gpio@fffff800 {
  113. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  114. reg = <0xfffff800 0x200>;
  115. interrupts = <3 4 1>;
  116. #gpio-cells = <2>;
  117. gpio-controller;
  118. interrupt-controller;
  119. #interrupt-cells = <2>;
  120. };
  121. pioD: gpio@fffffa00 {
  122. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  123. reg = <0xfffffa00 0x200>;
  124. interrupts = <3 4 1>;
  125. #gpio-cells = <2>;
  126. gpio-controller;
  127. interrupt-controller;
  128. #interrupt-cells = <2>;
  129. };
  130. };
  131. dbgu: serial@fffff200 {
  132. compatible = "atmel,at91sam9260-usart";
  133. reg = <0xfffff200 0x200>;
  134. interrupts = <1 4 7>;
  135. status = "disabled";
  136. };
  137. usart0: serial@f801c000 {
  138. compatible = "atmel,at91sam9260-usart";
  139. reg = <0xf801c000 0x4000>;
  140. interrupts = <5 4 5>;
  141. atmel,use-dma-rx;
  142. atmel,use-dma-tx;
  143. status = "disabled";
  144. };
  145. usart1: serial@f8020000 {
  146. compatible = "atmel,at91sam9260-usart";
  147. reg = <0xf8020000 0x4000>;
  148. interrupts = <6 4 5>;
  149. atmel,use-dma-rx;
  150. atmel,use-dma-tx;
  151. status = "disabled";
  152. };
  153. usart2: serial@f8024000 {
  154. compatible = "atmel,at91sam9260-usart";
  155. reg = <0xf8024000 0x4000>;
  156. interrupts = <7 4 5>;
  157. atmel,use-dma-rx;
  158. atmel,use-dma-tx;
  159. status = "disabled";
  160. };
  161. usart3: serial@f8028000 {
  162. compatible = "atmel,at91sam9260-usart";
  163. reg = <0xf8028000 0x4000>;
  164. interrupts = <8 4 5>;
  165. atmel,use-dma-rx;
  166. atmel,use-dma-tx;
  167. status = "disabled";
  168. };
  169. i2c0: i2c@f8010000 {
  170. compatible = "atmel,at91sam9x5-i2c";
  171. reg = <0xf8010000 0x100>;
  172. interrupts = <9 4 6>;
  173. #address-cells = <1>;
  174. #size-cells = <0>;
  175. status = "disabled";
  176. };
  177. i2c1: i2c@f8014000 {
  178. compatible = "atmel,at91sam9x5-i2c";
  179. reg = <0xf8014000 0x100>;
  180. interrupts = <10 4 6>;
  181. #address-cells = <1>;
  182. #size-cells = <0>;
  183. status = "disabled";
  184. };
  185. };
  186. nand0: nand@40000000 {
  187. compatible = "atmel,at91rm9200-nand";
  188. #address-cells = <1>;
  189. #size-cells = <1>;
  190. reg = < 0x40000000 0x10000000
  191. 0xffffe000 0x00000600
  192. 0xffffe600 0x00000200
  193. 0x00100000 0x00100000
  194. >;
  195. atmel,nand-addr-offset = <21>;
  196. atmel,nand-cmd-offset = <22>;
  197. gpios = <&pioD 5 0
  198. &pioD 4 0
  199. 0
  200. >;
  201. status = "disabled";
  202. };
  203. usb0: ohci@00500000 {
  204. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  205. reg = <0x00500000 0x00100000>;
  206. interrupts = <22 4 2>;
  207. status = "disabled";
  208. };
  209. };
  210. i2c@0 {
  211. compatible = "i2c-gpio";
  212. gpios = <&pioA 30 0 /* sda */
  213. &pioA 31 0 /* scl */
  214. >;
  215. i2c-gpio,sda-open-drain;
  216. i2c-gpio,scl-open-drain;
  217. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  218. #address-cells = <1>;
  219. #size-cells = <0>;
  220. status = "disabled";
  221. };
  222. };