at91sam9g45.dtsi 6.8 KB

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  1. /*
  2. * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
  3. * applies to AT91SAM9G45, AT91SAM9M10,
  4. * AT91SAM9G46, AT91SAM9M11 SoC
  5. *
  6. * Copyright (C) 2011 Atmel,
  7. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9G45 family SoC";
  14. compatible = "atmel,at91sam9g45";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. serial4 = &usart3;
  22. gpio0 = &pioA;
  23. gpio1 = &pioB;
  24. gpio2 = &pioC;
  25. gpio3 = &pioD;
  26. gpio4 = &pioE;
  27. tcb0 = &tcb0;
  28. tcb1 = &tcb1;
  29. i2c0 = &i2c0;
  30. i2c1 = &i2c1;
  31. };
  32. cpus {
  33. cpu@0 {
  34. compatible = "arm,arm926ejs";
  35. };
  36. };
  37. memory {
  38. reg = <0x70000000 0x10000000>;
  39. };
  40. ahb {
  41. compatible = "simple-bus";
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. ranges;
  45. apb {
  46. compatible = "simple-bus";
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. ranges;
  50. aic: interrupt-controller@fffff000 {
  51. #interrupt-cells = <3>;
  52. compatible = "atmel,at91rm9200-aic";
  53. interrupt-controller;
  54. reg = <0xfffff000 0x200>;
  55. atmel,external-irqs = <31>;
  56. };
  57. ramc0: ramc@ffffe400 {
  58. compatible = "atmel,at91sam9g45-ddramc";
  59. reg = <0xffffe400 0x200
  60. 0xffffe600 0x200>;
  61. };
  62. pmc: pmc@fffffc00 {
  63. compatible = "atmel,at91rm9200-pmc";
  64. reg = <0xfffffc00 0x100>;
  65. };
  66. rstc@fffffd00 {
  67. compatible = "atmel,at91sam9g45-rstc";
  68. reg = <0xfffffd00 0x10>;
  69. };
  70. pit: timer@fffffd30 {
  71. compatible = "atmel,at91sam9260-pit";
  72. reg = <0xfffffd30 0xf>;
  73. interrupts = <1 4 7>;
  74. };
  75. shdwc@fffffd10 {
  76. compatible = "atmel,at91sam9rl-shdwc";
  77. reg = <0xfffffd10 0x10>;
  78. };
  79. tcb0: timer@fff7c000 {
  80. compatible = "atmel,at91rm9200-tcb";
  81. reg = <0xfff7c000 0x100>;
  82. interrupts = <18 4 0>;
  83. };
  84. tcb1: timer@fffd4000 {
  85. compatible = "atmel,at91rm9200-tcb";
  86. reg = <0xfffd4000 0x100>;
  87. interrupts = <18 4 0>;
  88. };
  89. dma: dma-controller@ffffec00 {
  90. compatible = "atmel,at91sam9g45-dma";
  91. reg = <0xffffec00 0x200>;
  92. interrupts = <21 4 0>;
  93. };
  94. pinctrl@fffff200 {
  95. #address-cells = <1>;
  96. #size-cells = <1>;
  97. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  98. ranges = <0xfffff200 0xfffff200 0xa00>;
  99. pioA: gpio@fffff200 {
  100. compatible = "atmel,at91rm9200-gpio";
  101. reg = <0xfffff200 0x200>;
  102. interrupts = <2 4 1>;
  103. #gpio-cells = <2>;
  104. gpio-controller;
  105. interrupt-controller;
  106. #interrupt-cells = <2>;
  107. };
  108. pioB: gpio@fffff400 {
  109. compatible = "atmel,at91rm9200-gpio";
  110. reg = <0xfffff400 0x200>;
  111. interrupts = <3 4 1>;
  112. #gpio-cells = <2>;
  113. gpio-controller;
  114. interrupt-controller;
  115. #interrupt-cells = <2>;
  116. };
  117. pioC: gpio@fffff600 {
  118. compatible = "atmel,at91rm9200-gpio";
  119. reg = <0xfffff600 0x200>;
  120. interrupts = <4 4 1>;
  121. #gpio-cells = <2>;
  122. gpio-controller;
  123. interrupt-controller;
  124. #interrupt-cells = <2>;
  125. };
  126. pioD: gpio@fffff800 {
  127. compatible = "atmel,at91rm9200-gpio";
  128. reg = <0xfffff800 0x200>;
  129. interrupts = <5 4 1>;
  130. #gpio-cells = <2>;
  131. gpio-controller;
  132. interrupt-controller;
  133. #interrupt-cells = <2>;
  134. };
  135. pioE: gpio@fffffa00 {
  136. compatible = "atmel,at91rm9200-gpio";
  137. reg = <0xfffffa00 0x200>;
  138. interrupts = <5 4 1>;
  139. #gpio-cells = <2>;
  140. gpio-controller;
  141. interrupt-controller;
  142. #interrupt-cells = <2>;
  143. };
  144. };
  145. dbgu: serial@ffffee00 {
  146. compatible = "atmel,at91sam9260-usart";
  147. reg = <0xffffee00 0x200>;
  148. interrupts = <1 4 7>;
  149. status = "disabled";
  150. };
  151. usart0: serial@fff8c000 {
  152. compatible = "atmel,at91sam9260-usart";
  153. reg = <0xfff8c000 0x200>;
  154. interrupts = <7 4 5>;
  155. atmel,use-dma-rx;
  156. atmel,use-dma-tx;
  157. status = "disabled";
  158. };
  159. usart1: serial@fff90000 {
  160. compatible = "atmel,at91sam9260-usart";
  161. reg = <0xfff90000 0x200>;
  162. interrupts = <8 4 5>;
  163. atmel,use-dma-rx;
  164. atmel,use-dma-tx;
  165. status = "disabled";
  166. };
  167. usart2: serial@fff94000 {
  168. compatible = "atmel,at91sam9260-usart";
  169. reg = <0xfff94000 0x200>;
  170. interrupts = <9 4 5>;
  171. atmel,use-dma-rx;
  172. atmel,use-dma-tx;
  173. status = "disabled";
  174. };
  175. usart3: serial@fff98000 {
  176. compatible = "atmel,at91sam9260-usart";
  177. reg = <0xfff98000 0x200>;
  178. interrupts = <10 4 5>;
  179. atmel,use-dma-rx;
  180. atmel,use-dma-tx;
  181. status = "disabled";
  182. };
  183. macb0: ethernet@fffbc000 {
  184. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  185. reg = <0xfffbc000 0x100>;
  186. interrupts = <25 4 3>;
  187. status = "disabled";
  188. };
  189. i2c0: i2c@fff84000 {
  190. compatible = "atmel,at91sam9g10-i2c";
  191. reg = <0xfff84000 0x100>;
  192. interrupts = <12 4 6>;
  193. #address-cells = <1>;
  194. #size-cells = <0>;
  195. status = "disabled";
  196. };
  197. i2c1: i2c@fff88000 {
  198. compatible = "atmel,at91sam9g10-i2c";
  199. reg = <0xfff88000 0x100>;
  200. interrupts = <13 4 6>;
  201. #address-cells = <1>;
  202. #size-cells = <0>;
  203. status = "disabled";
  204. };
  205. adc0: adc@fffb0000 {
  206. compatible = "atmel,at91sam9260-adc";
  207. reg = <0xfffb0000 0x100>;
  208. interrupts = <20 4 0>;
  209. atmel,adc-use-external-triggers;
  210. atmel,adc-channels-used = <0xff>;
  211. atmel,adc-vref = <3300>;
  212. atmel,adc-num-channels = <8>;
  213. atmel,adc-startup-time = <40>;
  214. atmel,adc-channel-base = <0x30>;
  215. atmel,adc-drdy-mask = <0x10000>;
  216. atmel,adc-status-register = <0x1c>;
  217. atmel,adc-trigger-register = <0x08>;
  218. trigger@0 {
  219. trigger-name = "external-rising";
  220. trigger-value = <0x1>;
  221. trigger-external;
  222. };
  223. trigger@1 {
  224. trigger-name = "external-falling";
  225. trigger-value = <0x2>;
  226. trigger-external;
  227. };
  228. trigger@2 {
  229. trigger-name = "external-any";
  230. trigger-value = <0x3>;
  231. trigger-external;
  232. };
  233. trigger@3 {
  234. trigger-name = "continuous";
  235. trigger-value = <0x6>;
  236. };
  237. };
  238. };
  239. nand0: nand@40000000 {
  240. compatible = "atmel,at91rm9200-nand";
  241. #address-cells = <1>;
  242. #size-cells = <1>;
  243. reg = <0x40000000 0x10000000
  244. 0xffffe200 0x200
  245. >;
  246. atmel,nand-addr-offset = <21>;
  247. atmel,nand-cmd-offset = <22>;
  248. gpios = <&pioC 8 0
  249. &pioC 14 0
  250. 0
  251. >;
  252. status = "disabled";
  253. };
  254. usb0: ohci@00700000 {
  255. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  256. reg = <0x00700000 0x100000>;
  257. interrupts = <22 4 2>;
  258. status = "disabled";
  259. };
  260. usb1: ehci@00800000 {
  261. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  262. reg = <0x00800000 0x100000>;
  263. interrupts = <22 4 2>;
  264. status = "disabled";
  265. };
  266. };
  267. i2c@0 {
  268. compatible = "i2c-gpio";
  269. gpios = <&pioA 20 0 /* sda */
  270. &pioA 21 0 /* scl */
  271. >;
  272. i2c-gpio,sda-open-drain;
  273. i2c-gpio,scl-open-drain;
  274. i2c-gpio,delay-us = <5>; /* ~100 kHz */
  275. #address-cells = <1>;
  276. #size-cells = <0>;
  277. status = "disabled";
  278. };
  279. };