dm.c 43 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2010 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include "../wifi.h"
  30. #include "../base.h"
  31. #include "reg.h"
  32. #include "def.h"
  33. #include "phy.h"
  34. #include "dm.h"
  35. #include "fw.h"
  36. struct dig_t dm_digtable;
  37. static struct ps_t dm_pstable;
  38. static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
  39. 0x7f8001fe,
  40. 0x788001e2,
  41. 0x71c001c7,
  42. 0x6b8001ae,
  43. 0x65400195,
  44. 0x5fc0017f,
  45. 0x5a400169,
  46. 0x55400155,
  47. 0x50800142,
  48. 0x4c000130,
  49. 0x47c0011f,
  50. 0x43c0010f,
  51. 0x40000100,
  52. 0x3c8000f2,
  53. 0x390000e4,
  54. 0x35c000d7,
  55. 0x32c000cb,
  56. 0x300000c0,
  57. 0x2d4000b5,
  58. 0x2ac000ab,
  59. 0x288000a2,
  60. 0x26000098,
  61. 0x24000090,
  62. 0x22000088,
  63. 0x20000080,
  64. 0x1e400079,
  65. 0x1c800072,
  66. 0x1b00006c,
  67. 0x19800066,
  68. 0x18000060,
  69. 0x16c0005b,
  70. 0x15800056,
  71. 0x14400051,
  72. 0x1300004c,
  73. 0x12000048,
  74. 0x11000044,
  75. 0x10000040,
  76. };
  77. static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
  78. {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
  79. {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
  80. {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
  81. {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
  82. {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
  83. {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
  84. {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
  85. {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
  86. {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
  87. {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
  88. {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
  89. {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
  90. {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
  91. {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
  92. {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
  93. {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
  94. {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
  95. {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
  96. {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
  97. {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
  98. {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
  99. {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
  100. {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
  101. {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
  102. {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
  103. {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
  104. {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
  105. {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
  106. {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
  107. {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
  108. {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
  109. {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
  110. {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
  111. };
  112. static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
  113. {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
  114. {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
  115. {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
  116. {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
  117. {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
  118. {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
  119. {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
  120. {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
  121. {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
  122. {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
  123. {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
  124. {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
  125. {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
  126. {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
  127. {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
  128. {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
  129. {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
  130. {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
  131. {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
  132. {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
  133. {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
  134. {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
  135. {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
  136. {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
  137. {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
  138. {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
  139. {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
  140. {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
  141. {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
  142. {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
  143. {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
  144. {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
  145. {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
  146. };
  147. static void rtl92c_dm_diginit(struct ieee80211_hw *hw)
  148. {
  149. dm_digtable.dig_enable_flag = true;
  150. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  151. dm_digtable.cur_igvalue = 0x20;
  152. dm_digtable.pre_igvalue = 0x0;
  153. dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
  154. dm_digtable.presta_connectstate = DIG_STA_DISCONNECT;
  155. dm_digtable.curmultista_connectstate = DIG_MULTISTA_DISCONNECT;
  156. dm_digtable.rssi_lowthresh = DM_DIG_THRESH_LOW;
  157. dm_digtable.rssi_highthresh = DM_DIG_THRESH_HIGH;
  158. dm_digtable.fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
  159. dm_digtable.fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
  160. dm_digtable.rx_gain_range_max = DM_DIG_MAX;
  161. dm_digtable.rx_gain_range_min = DM_DIG_MIN;
  162. dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
  163. dm_digtable.backoff_val_range_max = DM_DIG_BACKOFF_MAX;
  164. dm_digtable.backoff_val_range_min = DM_DIG_BACKOFF_MIN;
  165. dm_digtable.pre_cck_pd_state = CCK_PD_STAGE_MAX;
  166. dm_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
  167. }
  168. static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
  169. {
  170. struct rtl_priv *rtlpriv = rtl_priv(hw);
  171. long rssi_val_min = 0;
  172. if ((dm_digtable.curmultista_connectstate == DIG_MULTISTA_CONNECT) &&
  173. (dm_digtable.cursta_connectctate == DIG_STA_CONNECT)) {
  174. if (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb != 0)
  175. rssi_val_min =
  176. (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb >
  177. rtlpriv->dm.undecorated_smoothed_pwdb) ?
  178. rtlpriv->dm.undecorated_smoothed_pwdb :
  179. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  180. else
  181. rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
  182. } else if (dm_digtable.cursta_connectctate == DIG_STA_CONNECT ||
  183. dm_digtable.cursta_connectctate == DIG_STA_BEFORE_CONNECT) {
  184. rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
  185. } else if (dm_digtable.curmultista_connectstate ==
  186. DIG_MULTISTA_CONNECT) {
  187. rssi_val_min = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  188. }
  189. return (u8) rssi_val_min;
  190. }
  191. static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
  192. {
  193. u32 ret_value;
  194. struct rtl_priv *rtlpriv = rtl_priv(hw);
  195. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  196. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
  197. falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
  198. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
  199. falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
  200. falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
  201. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
  202. falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
  203. falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
  204. falsealm_cnt->cnt_rate_illegal +
  205. falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail;
  206. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
  207. ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
  208. falsealm_cnt->cnt_cck_fail = ret_value;
  209. ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
  210. falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
  211. falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
  212. falsealm_cnt->cnt_rate_illegal +
  213. falsealm_cnt->cnt_crc8_fail +
  214. falsealm_cnt->cnt_mcs_fail +
  215. falsealm_cnt->cnt_cck_fail);
  216. rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
  217. rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
  218. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
  219. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
  220. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  221. ("cnt_parity_fail = %d, cnt_rate_illegal = %d, "
  222. "cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
  223. falsealm_cnt->cnt_parity_fail,
  224. falsealm_cnt->cnt_rate_illegal,
  225. falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail));
  226. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  227. ("cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
  228. falsealm_cnt->cnt_ofdm_fail,
  229. falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all));
  230. }
  231. static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
  232. {
  233. struct rtl_priv *rtlpriv = rtl_priv(hw);
  234. u8 value_igi = dm_digtable.cur_igvalue;
  235. if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
  236. value_igi--;
  237. else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
  238. value_igi += 0;
  239. else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
  240. value_igi++;
  241. else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
  242. value_igi += 2;
  243. if (value_igi > DM_DIG_FA_UPPER)
  244. value_igi = DM_DIG_FA_UPPER;
  245. else if (value_igi < DM_DIG_FA_LOWER)
  246. value_igi = DM_DIG_FA_LOWER;
  247. if (rtlpriv->falsealm_cnt.cnt_all > 10000)
  248. value_igi = 0x32;
  249. dm_digtable.cur_igvalue = value_igi;
  250. rtl92c_dm_write_dig(hw);
  251. }
  252. static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
  253. {
  254. struct rtl_priv *rtlpriv = rtl_priv(hw);
  255. if (rtlpriv->falsealm_cnt.cnt_all > dm_digtable.fa_highthresh) {
  256. if ((dm_digtable.backoff_val - 2) <
  257. dm_digtable.backoff_val_range_min)
  258. dm_digtable.backoff_val =
  259. dm_digtable.backoff_val_range_min;
  260. else
  261. dm_digtable.backoff_val -= 2;
  262. } else if (rtlpriv->falsealm_cnt.cnt_all < dm_digtable.fa_lowthresh) {
  263. if ((dm_digtable.backoff_val + 2) >
  264. dm_digtable.backoff_val_range_max)
  265. dm_digtable.backoff_val =
  266. dm_digtable.backoff_val_range_max;
  267. else
  268. dm_digtable.backoff_val += 2;
  269. }
  270. if ((dm_digtable.rssi_val_min + 10 - dm_digtable.backoff_val) >
  271. dm_digtable.rx_gain_range_max)
  272. dm_digtable.cur_igvalue = dm_digtable.rx_gain_range_max;
  273. else if ((dm_digtable.rssi_val_min + 10 -
  274. dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
  275. dm_digtable.cur_igvalue = dm_digtable.rx_gain_range_min;
  276. else
  277. dm_digtable.cur_igvalue = dm_digtable.rssi_val_min + 10 -
  278. dm_digtable.backoff_val;
  279. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  280. ("rssi_val_min = %x backoff_val %x\n",
  281. dm_digtable.rssi_val_min, dm_digtable.backoff_val));
  282. rtl92c_dm_write_dig(hw);
  283. }
  284. static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
  285. {
  286. static u8 binitialized; /* initialized to false */
  287. struct rtl_priv *rtlpriv = rtl_priv(hw);
  288. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  289. long rssi_strength = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  290. bool b_multi_sta = false;
  291. if (mac->opmode == NL80211_IFTYPE_ADHOC)
  292. b_multi_sta = true;
  293. if ((b_multi_sta == false) || (dm_digtable.cursta_connectctate !=
  294. DIG_STA_DISCONNECT)) {
  295. binitialized = false;
  296. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  297. return;
  298. } else if (binitialized == false) {
  299. binitialized = true;
  300. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
  301. dm_digtable.cur_igvalue = 0x20;
  302. rtl92c_dm_write_dig(hw);
  303. }
  304. if (dm_digtable.curmultista_connectstate == DIG_MULTISTA_CONNECT) {
  305. if ((rssi_strength < dm_digtable.rssi_lowthresh) &&
  306. (dm_digtable.dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
  307. if (dm_digtable.dig_ext_port_stage ==
  308. DIG_EXT_PORT_STAGE_2) {
  309. dm_digtable.cur_igvalue = 0x20;
  310. rtl92c_dm_write_dig(hw);
  311. }
  312. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
  313. } else if (rssi_strength > dm_digtable.rssi_highthresh) {
  314. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
  315. rtl92c_dm_ctrl_initgain_by_fa(hw);
  316. }
  317. } else if (dm_digtable.dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
  318. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
  319. dm_digtable.cur_igvalue = 0x20;
  320. rtl92c_dm_write_dig(hw);
  321. }
  322. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  323. ("curmultista_connectstate = "
  324. "%x dig_ext_port_stage %x\n",
  325. dm_digtable.curmultista_connectstate,
  326. dm_digtable.dig_ext_port_stage));
  327. }
  328. static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw)
  329. {
  330. struct rtl_priv *rtlpriv = rtl_priv(hw);
  331. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  332. ("presta_connectstate = %x,"
  333. " cursta_connectctate = %x\n",
  334. dm_digtable.presta_connectstate,
  335. dm_digtable.cursta_connectctate));
  336. if (dm_digtable.presta_connectstate == dm_digtable.cursta_connectctate
  337. || dm_digtable.cursta_connectctate == DIG_STA_BEFORE_CONNECT
  338. || dm_digtable.cursta_connectctate == DIG_STA_CONNECT) {
  339. if (dm_digtable.cursta_connectctate != DIG_STA_DISCONNECT) {
  340. dm_digtable.rssi_val_min =
  341. rtl92c_dm_initial_gain_min_pwdb(hw);
  342. rtl92c_dm_ctrl_initgain_by_rssi(hw);
  343. }
  344. } else {
  345. dm_digtable.rssi_val_min = 0;
  346. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  347. dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
  348. dm_digtable.cur_igvalue = 0x20;
  349. dm_digtable.pre_igvalue = 0;
  350. rtl92c_dm_write_dig(hw);
  351. }
  352. }
  353. static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
  354. {
  355. struct rtl_priv *rtlpriv = rtl_priv(hw);
  356. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  357. if (dm_digtable.cursta_connectctate == DIG_STA_CONNECT) {
  358. dm_digtable.rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw);
  359. if (dm_digtable.pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
  360. if (dm_digtable.rssi_val_min <= 25)
  361. dm_digtable.cur_cck_pd_state =
  362. CCK_PD_STAGE_LowRssi;
  363. else
  364. dm_digtable.cur_cck_pd_state =
  365. CCK_PD_STAGE_HighRssi;
  366. } else {
  367. if (dm_digtable.rssi_val_min <= 20)
  368. dm_digtable.cur_cck_pd_state =
  369. CCK_PD_STAGE_LowRssi;
  370. else
  371. dm_digtable.cur_cck_pd_state =
  372. CCK_PD_STAGE_HighRssi;
  373. }
  374. } else {
  375. dm_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
  376. }
  377. if (dm_digtable.pre_cck_pd_state != dm_digtable.cur_cck_pd_state) {
  378. if (dm_digtable.cur_cck_pd_state == CCK_PD_STAGE_LowRssi) {
  379. if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
  380. dm_digtable.cur_cck_fa_state =
  381. CCK_FA_STAGE_High;
  382. else
  383. dm_digtable.cur_cck_fa_state = CCK_FA_STAGE_Low;
  384. if (dm_digtable.pre_cck_fa_state !=
  385. dm_digtable.cur_cck_fa_state) {
  386. if (dm_digtable.cur_cck_fa_state ==
  387. CCK_FA_STAGE_Low)
  388. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
  389. 0x83);
  390. else
  391. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
  392. 0xcd);
  393. dm_digtable.pre_cck_fa_state =
  394. dm_digtable.cur_cck_fa_state;
  395. }
  396. rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40);
  397. if (IS_92C_SERIAL(rtlhal->version))
  398. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
  399. MASKBYTE2, 0xd7);
  400. } else {
  401. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
  402. rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47);
  403. if (IS_92C_SERIAL(rtlhal->version))
  404. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
  405. MASKBYTE2, 0xd3);
  406. }
  407. dm_digtable.pre_cck_pd_state = dm_digtable.cur_cck_pd_state;
  408. }
  409. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  410. ("CCKPDStage=%x\n", dm_digtable.cur_cck_pd_state));
  411. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  412. ("is92C=%x\n", IS_92C_SERIAL(rtlhal->version)));
  413. }
  414. static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
  415. {
  416. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  417. if (mac->act_scanning == true)
  418. return;
  419. if ((mac->link_state > MAC80211_NOLINK) &&
  420. (mac->link_state < MAC80211_LINKED))
  421. dm_digtable.cursta_connectctate = DIG_STA_BEFORE_CONNECT;
  422. else if (mac->link_state >= MAC80211_LINKED)
  423. dm_digtable.cursta_connectctate = DIG_STA_CONNECT;
  424. else
  425. dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
  426. rtl92c_dm_initial_gain_sta(hw);
  427. rtl92c_dm_initial_gain_multi_sta(hw);
  428. rtl92c_dm_cck_packet_detection_thresh(hw);
  429. dm_digtable.presta_connectstate = dm_digtable.cursta_connectctate;
  430. }
  431. static void rtl92c_dm_dig(struct ieee80211_hw *hw)
  432. {
  433. struct rtl_priv *rtlpriv = rtl_priv(hw);
  434. if (rtlpriv->dm.b_dm_initialgain_enable == false)
  435. return;
  436. if (dm_digtable.dig_enable_flag == false)
  437. return;
  438. rtl92c_dm_ctrl_initgain_by_twoport(hw);
  439. }
  440. static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
  441. {
  442. struct rtl_priv *rtlpriv = rtl_priv(hw);
  443. rtlpriv->dm.bdynamic_txpower_enable = false;
  444. rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
  445. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  446. }
  447. static void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
  448. {
  449. struct rtl_priv *rtlpriv = rtl_priv(hw);
  450. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  451. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  452. long undecorated_smoothed_pwdb;
  453. if (!rtlpriv->dm.bdynamic_txpower_enable)
  454. return;
  455. if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
  456. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  457. return;
  458. }
  459. if ((mac->link_state < MAC80211_LINKED) &&
  460. (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
  461. RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
  462. ("Not connected to any\n"));
  463. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  464. rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
  465. return;
  466. }
  467. if (mac->link_state >= MAC80211_LINKED) {
  468. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  469. undecorated_smoothed_pwdb =
  470. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  471. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  472. ("AP Client PWDB = 0x%lx\n",
  473. undecorated_smoothed_pwdb));
  474. } else {
  475. undecorated_smoothed_pwdb =
  476. rtlpriv->dm.undecorated_smoothed_pwdb;
  477. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  478. ("STA Default Port PWDB = 0x%lx\n",
  479. undecorated_smoothed_pwdb));
  480. }
  481. } else {
  482. undecorated_smoothed_pwdb =
  483. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  484. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  485. ("AP Ext Port PWDB = 0x%lx\n",
  486. undecorated_smoothed_pwdb));
  487. }
  488. if (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
  489. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
  490. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  491. ("TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n"));
  492. } else if ((undecorated_smoothed_pwdb <
  493. (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
  494. (undecorated_smoothed_pwdb >=
  495. TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
  496. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
  497. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  498. ("TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n"));
  499. } else if (undecorated_smoothed_pwdb <
  500. (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
  501. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  502. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  503. ("TXHIGHPWRLEVEL_NORMAL\n"));
  504. }
  505. if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
  506. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  507. ("PHY_SetTxPowerLevel8192S() Channel = %d\n",
  508. rtlphy->current_channel));
  509. rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
  510. }
  511. rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
  512. }
  513. void rtl92c_dm_write_dig(struct ieee80211_hw *hw)
  514. {
  515. struct rtl_priv *rtlpriv = rtl_priv(hw);
  516. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
  517. ("cur_igvalue = 0x%x, "
  518. "pre_igvalue = 0x%x, backoff_val = %d\n",
  519. dm_digtable.cur_igvalue, dm_digtable.pre_igvalue,
  520. dm_digtable.backoff_val));
  521. if (dm_digtable.pre_igvalue != dm_digtable.cur_igvalue) {
  522. rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
  523. dm_digtable.cur_igvalue);
  524. rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
  525. dm_digtable.cur_igvalue);
  526. dm_digtable.pre_igvalue = dm_digtable.cur_igvalue;
  527. }
  528. }
  529. static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw)
  530. {
  531. struct rtl_priv *rtlpriv = rtl_priv(hw);
  532. long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff;
  533. u8 h2c_parameter[3] = { 0 };
  534. return;
  535. if (tmpentry_max_pwdb != 0) {
  536. rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb =
  537. tmpentry_max_pwdb;
  538. } else {
  539. rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb = 0;
  540. }
  541. if (tmpentry_min_pwdb != 0xff) {
  542. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb =
  543. tmpentry_min_pwdb;
  544. } else {
  545. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb = 0;
  546. }
  547. h2c_parameter[2] = (u8) (rtlpriv->dm.undecorated_smoothed_pwdb & 0xFF);
  548. h2c_parameter[0] = 0;
  549. rtl92c_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, h2c_parameter);
  550. }
  551. void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw)
  552. {
  553. struct rtl_priv *rtlpriv = rtl_priv(hw);
  554. rtlpriv->dm.bcurrent_turbo_edca = false;
  555. rtlpriv->dm.bis_any_nonbepkts = false;
  556. rtlpriv->dm.bis_cur_rdlstate = false;
  557. }
  558. static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw)
  559. {
  560. struct rtl_priv *rtlpriv = rtl_priv(hw);
  561. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  562. static u64 last_txok_cnt;
  563. static u64 last_rxok_cnt;
  564. u64 cur_txok_cnt;
  565. u64 cur_rxok_cnt;
  566. u32 edca_be_ul = 0x5ea42b;
  567. u32 edca_be_dl = 0x5ea42b;
  568. if (mac->opmode == NL80211_IFTYPE_ADHOC)
  569. goto dm_checkedcaturbo_exit;
  570. if (mac->link_state != MAC80211_LINKED) {
  571. rtlpriv->dm.bcurrent_turbo_edca = false;
  572. return;
  573. }
  574. if (!mac->ht_enable) { /*FIX MERGE */
  575. if (!(edca_be_ul & 0xffff0000))
  576. edca_be_ul |= 0x005e0000;
  577. if (!(edca_be_dl & 0xffff0000))
  578. edca_be_dl |= 0x005e0000;
  579. }
  580. if ((!rtlpriv->dm.bis_any_nonbepkts) &&
  581. (!rtlpriv->dm.b_disable_framebursting)) {
  582. cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
  583. cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
  584. if (cur_rxok_cnt > 4 * cur_txok_cnt) {
  585. if (!rtlpriv->dm.bis_cur_rdlstate ||
  586. !rtlpriv->dm.bcurrent_turbo_edca) {
  587. rtl_write_dword(rtlpriv,
  588. REG_EDCA_BE_PARAM,
  589. edca_be_dl);
  590. rtlpriv->dm.bis_cur_rdlstate = true;
  591. }
  592. } else {
  593. if (rtlpriv->dm.bis_cur_rdlstate ||
  594. !rtlpriv->dm.bcurrent_turbo_edca) {
  595. rtl_write_dword(rtlpriv,
  596. REG_EDCA_BE_PARAM,
  597. edca_be_ul);
  598. rtlpriv->dm.bis_cur_rdlstate = false;
  599. }
  600. }
  601. rtlpriv->dm.bcurrent_turbo_edca = true;
  602. } else {
  603. if (rtlpriv->dm.bcurrent_turbo_edca) {
  604. u8 tmp = AC0_BE;
  605. rtlpriv->cfg->ops->set_hw_reg(hw,
  606. HW_VAR_AC_PARAM,
  607. (u8 *) (&tmp));
  608. rtlpriv->dm.bcurrent_turbo_edca = false;
  609. }
  610. }
  611. dm_checkedcaturbo_exit:
  612. rtlpriv->dm.bis_any_nonbepkts = false;
  613. last_txok_cnt = rtlpriv->stats.txbytesunicast;
  614. last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
  615. }
  616. static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
  617. *hw)
  618. {
  619. struct rtl_priv *rtlpriv = rtl_priv(hw);
  620. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  621. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  622. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  623. u8 thermalvalue, delta, delta_lck, delta_iqk;
  624. long ele_a, ele_d, temp_cck, val_x, value32;
  625. long val_y, ele_c;
  626. u8 ofdm_index[2], cck_index, ofdm_index_old[2], cck_index_old;
  627. int i;
  628. bool is2t = IS_92C_SERIAL(rtlhal->version);
  629. u8 txpwr_level[2] = {0, 0};
  630. u8 ofdm_min_index = 6, rf;
  631. rtlpriv->dm.btxpower_trackingInit = true;
  632. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  633. ("rtl92c_dm_txpower_tracking_callback_thermalmeter\n"));
  634. thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
  635. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  636. ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
  637. "eeprom_thermalmeter 0x%x\n",
  638. thermalvalue, rtlpriv->dm.thermalvalue,
  639. rtlefuse->eeprom_thermalmeter));
  640. rtl92c_phy_ap_calibrate(hw, (thermalvalue -
  641. rtlefuse->eeprom_thermalmeter));
  642. if (is2t)
  643. rf = 2;
  644. else
  645. rf = 1;
  646. if (thermalvalue) {
  647. ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  648. MASKDWORD) & MASKOFDM_D;
  649. for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
  650. if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
  651. ofdm_index_old[0] = (u8) i;
  652. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  653. ("Initial pathA ele_d reg0x%x = 0x%lx, "
  654. "ofdm_index=0x%x\n",
  655. ROFDM0_XATXIQIMBALANCE,
  656. ele_d, ofdm_index_old[0]));
  657. break;
  658. }
  659. }
  660. if (is2t) {
  661. ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
  662. MASKDWORD) & MASKOFDM_D;
  663. for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
  664. if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
  665. ofdm_index_old[1] = (u8) i;
  666. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  667. DBG_LOUD,
  668. ("Initial pathB ele_d reg0x%x = "
  669. "0x%lx, ofdm_index=0x%x\n",
  670. ROFDM0_XBTXIQIMBALANCE, ele_d,
  671. ofdm_index_old[1]));
  672. break;
  673. }
  674. }
  675. }
  676. temp_cck =
  677. rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
  678. for (i = 0; i < CCK_TABLE_LENGTH; i++) {
  679. if (rtlpriv->dm.b_cck_inch14) {
  680. if (memcmp((void *)&temp_cck,
  681. (void *)&cckswing_table_ch14[i][2],
  682. 4) == 0) {
  683. cck_index_old = (u8) i;
  684. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  685. DBG_LOUD,
  686. ("Initial reg0x%x = 0x%lx, "
  687. "cck_index=0x%x, ch 14 %d\n",
  688. RCCK0_TXFILTER2, temp_cck,
  689. cck_index_old,
  690. rtlpriv->dm.b_cck_inch14));
  691. break;
  692. }
  693. } else {
  694. if (memcmp((void *)&temp_cck,
  695. (void *)
  696. &cckswing_table_ch1ch13[i][2],
  697. 4) == 0) {
  698. cck_index_old = (u8) i;
  699. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  700. DBG_LOUD,
  701. ("Initial reg0x%x = 0x%lx, "
  702. "cck_index=0x%x, ch14 %d\n",
  703. RCCK0_TXFILTER2, temp_cck,
  704. cck_index_old,
  705. rtlpriv->dm.b_cck_inch14));
  706. break;
  707. }
  708. }
  709. }
  710. if (!rtlpriv->dm.thermalvalue) {
  711. rtlpriv->dm.thermalvalue =
  712. rtlefuse->eeprom_thermalmeter;
  713. rtlpriv->dm.thermalvalue_lck = thermalvalue;
  714. rtlpriv->dm.thermalvalue_iqk = thermalvalue;
  715. for (i = 0; i < rf; i++)
  716. rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
  717. rtlpriv->dm.cck_index = cck_index_old;
  718. }
  719. delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
  720. (thermalvalue - rtlpriv->dm.thermalvalue) :
  721. (rtlpriv->dm.thermalvalue - thermalvalue);
  722. delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
  723. (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
  724. (rtlpriv->dm.thermalvalue_lck - thermalvalue);
  725. delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
  726. (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
  727. (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
  728. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  729. ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
  730. "eeprom_thermalmeter 0x%x delta 0x%x "
  731. "delta_lck 0x%x delta_iqk 0x%x\n",
  732. thermalvalue, rtlpriv->dm.thermalvalue,
  733. rtlefuse->eeprom_thermalmeter, delta, delta_lck,
  734. delta_iqk));
  735. if (delta_lck > 1) {
  736. rtlpriv->dm.thermalvalue_lck = thermalvalue;
  737. rtl92c_phy_lc_calibrate(hw);
  738. }
  739. if (delta > 0 && rtlpriv->dm.txpower_track_control) {
  740. if (thermalvalue > rtlpriv->dm.thermalvalue) {
  741. for (i = 0; i < rf; i++)
  742. rtlpriv->dm.ofdm_index[i] -= delta;
  743. rtlpriv->dm.cck_index -= delta;
  744. } else {
  745. for (i = 0; i < rf; i++)
  746. rtlpriv->dm.ofdm_index[i] += delta;
  747. rtlpriv->dm.cck_index += delta;
  748. }
  749. if (is2t) {
  750. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  751. ("temp OFDM_A_index=0x%x, "
  752. "OFDM_B_index=0x%x,"
  753. "cck_index=0x%x\n",
  754. rtlpriv->dm.ofdm_index[0],
  755. rtlpriv->dm.ofdm_index[1],
  756. rtlpriv->dm.cck_index));
  757. } else {
  758. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  759. ("temp OFDM_A_index=0x%x,"
  760. "cck_index=0x%x\n",
  761. rtlpriv->dm.ofdm_index[0],
  762. rtlpriv->dm.cck_index));
  763. }
  764. if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
  765. for (i = 0; i < rf; i++)
  766. ofdm_index[i] =
  767. rtlpriv->dm.ofdm_index[i]
  768. + 1;
  769. cck_index = rtlpriv->dm.cck_index + 1;
  770. } else {
  771. for (i = 0; i < rf; i++)
  772. ofdm_index[i] =
  773. rtlpriv->dm.ofdm_index[i];
  774. cck_index = rtlpriv->dm.cck_index;
  775. }
  776. for (i = 0; i < rf; i++) {
  777. if (txpwr_level[i] >= 0 &&
  778. txpwr_level[i] <= 26) {
  779. if (thermalvalue >
  780. rtlefuse->eeprom_thermalmeter) {
  781. if (delta < 5)
  782. ofdm_index[i] -= 1;
  783. else
  784. ofdm_index[i] -= 2;
  785. } else if (delta > 5 && thermalvalue <
  786. rtlefuse->
  787. eeprom_thermalmeter) {
  788. ofdm_index[i] += 1;
  789. }
  790. } else if (txpwr_level[i] >= 27 &&
  791. txpwr_level[i] <= 32
  792. && thermalvalue >
  793. rtlefuse->eeprom_thermalmeter) {
  794. if (delta < 5)
  795. ofdm_index[i] -= 1;
  796. else
  797. ofdm_index[i] -= 2;
  798. } else if (txpwr_level[i] >= 32 &&
  799. txpwr_level[i] <= 38 &&
  800. thermalvalue >
  801. rtlefuse->eeprom_thermalmeter
  802. && delta > 5) {
  803. ofdm_index[i] -= 1;
  804. }
  805. }
  806. if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) {
  807. if (thermalvalue >
  808. rtlefuse->eeprom_thermalmeter) {
  809. if (delta < 5)
  810. cck_index -= 1;
  811. else
  812. cck_index -= 2;
  813. } else if (delta > 5 && thermalvalue <
  814. rtlefuse->eeprom_thermalmeter) {
  815. cck_index += 1;
  816. }
  817. } else if (txpwr_level[i] >= 27 &&
  818. txpwr_level[i] <= 32 &&
  819. thermalvalue >
  820. rtlefuse->eeprom_thermalmeter) {
  821. if (delta < 5)
  822. cck_index -= 1;
  823. else
  824. cck_index -= 2;
  825. } else if (txpwr_level[i] >= 32 &&
  826. txpwr_level[i] <= 38 &&
  827. thermalvalue > rtlefuse->eeprom_thermalmeter
  828. && delta > 5) {
  829. cck_index -= 1;
  830. }
  831. for (i = 0; i < rf; i++) {
  832. if (ofdm_index[i] > OFDM_TABLE_SIZE - 1)
  833. ofdm_index[i] = OFDM_TABLE_SIZE - 1;
  834. else if (ofdm_index[i] < ofdm_min_index)
  835. ofdm_index[i] = ofdm_min_index;
  836. }
  837. if (cck_index > CCK_TABLE_SIZE - 1)
  838. cck_index = CCK_TABLE_SIZE - 1;
  839. else if (cck_index < 0)
  840. cck_index = 0;
  841. if (is2t) {
  842. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  843. ("new OFDM_A_index=0x%x, "
  844. "OFDM_B_index=0x%x,"
  845. "cck_index=0x%x\n",
  846. ofdm_index[0], ofdm_index[1],
  847. cck_index));
  848. } else {
  849. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  850. ("new OFDM_A_index=0x%x,"
  851. "cck_index=0x%x\n",
  852. ofdm_index[0], cck_index));
  853. }
  854. }
  855. if (rtlpriv->dm.txpower_track_control && delta != 0) {
  856. ele_d =
  857. (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
  858. val_x = rtlphy->reg_e94;
  859. val_y = rtlphy->reg_e9c;
  860. if (val_x != 0) {
  861. if ((val_x & 0x00000200) != 0)
  862. val_x = val_x | 0xFFFFFC00;
  863. ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
  864. if ((val_y & 0x00000200) != 0)
  865. val_y = val_y | 0xFFFFFC00;
  866. ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
  867. value32 = (ele_d << 22) |
  868. ((ele_c & 0x3F) << 16) | ele_a;
  869. rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  870. MASKDWORD, value32);
  871. value32 = (ele_c & 0x000003C0) >> 6;
  872. rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
  873. value32);
  874. value32 = ((val_x * ele_d) >> 7) & 0x01;
  875. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  876. BIT(31), value32);
  877. value32 = ((val_y * ele_d) >> 7) & 0x01;
  878. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  879. BIT(29), value32);
  880. } else {
  881. rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  882. MASKDWORD,
  883. ofdmswing_table[ofdm_index[0]]);
  884. rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
  885. 0x00);
  886. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  887. BIT(31) | BIT(29), 0x00);
  888. }
  889. if (!rtlpriv->dm.b_cck_inch14) {
  890. rtl_write_byte(rtlpriv, 0xa22,
  891. cckswing_table_ch1ch13[cck_index]
  892. [0]);
  893. rtl_write_byte(rtlpriv, 0xa23,
  894. cckswing_table_ch1ch13[cck_index]
  895. [1]);
  896. rtl_write_byte(rtlpriv, 0xa24,
  897. cckswing_table_ch1ch13[cck_index]
  898. [2]);
  899. rtl_write_byte(rtlpriv, 0xa25,
  900. cckswing_table_ch1ch13[cck_index]
  901. [3]);
  902. rtl_write_byte(rtlpriv, 0xa26,
  903. cckswing_table_ch1ch13[cck_index]
  904. [4]);
  905. rtl_write_byte(rtlpriv, 0xa27,
  906. cckswing_table_ch1ch13[cck_index]
  907. [5]);
  908. rtl_write_byte(rtlpriv, 0xa28,
  909. cckswing_table_ch1ch13[cck_index]
  910. [6]);
  911. rtl_write_byte(rtlpriv, 0xa29,
  912. cckswing_table_ch1ch13[cck_index]
  913. [7]);
  914. } else {
  915. rtl_write_byte(rtlpriv, 0xa22,
  916. cckswing_table_ch14[cck_index]
  917. [0]);
  918. rtl_write_byte(rtlpriv, 0xa23,
  919. cckswing_table_ch14[cck_index]
  920. [1]);
  921. rtl_write_byte(rtlpriv, 0xa24,
  922. cckswing_table_ch14[cck_index]
  923. [2]);
  924. rtl_write_byte(rtlpriv, 0xa25,
  925. cckswing_table_ch14[cck_index]
  926. [3]);
  927. rtl_write_byte(rtlpriv, 0xa26,
  928. cckswing_table_ch14[cck_index]
  929. [4]);
  930. rtl_write_byte(rtlpriv, 0xa27,
  931. cckswing_table_ch14[cck_index]
  932. [5]);
  933. rtl_write_byte(rtlpriv, 0xa28,
  934. cckswing_table_ch14[cck_index]
  935. [6]);
  936. rtl_write_byte(rtlpriv, 0xa29,
  937. cckswing_table_ch14[cck_index]
  938. [7]);
  939. }
  940. if (is2t) {
  941. ele_d = (ofdmswing_table[ofdm_index[1]] &
  942. 0xFFC00000) >> 22;
  943. val_x = rtlphy->reg_eb4;
  944. val_y = rtlphy->reg_ebc;
  945. if (val_x != 0) {
  946. if ((val_x & 0x00000200) != 0)
  947. val_x = val_x | 0xFFFFFC00;
  948. ele_a = ((val_x * ele_d) >> 8) &
  949. 0x000003FF;
  950. if ((val_y & 0x00000200) != 0)
  951. val_y = val_y | 0xFFFFFC00;
  952. ele_c = ((val_y * ele_d) >> 8) &
  953. 0x00003FF;
  954. value32 = (ele_d << 22) |
  955. ((ele_c & 0x3F) << 16) | ele_a;
  956. rtl_set_bbreg(hw,
  957. ROFDM0_XBTXIQIMBALANCE,
  958. MASKDWORD, value32);
  959. value32 = (ele_c & 0x000003C0) >> 6;
  960. rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
  961. MASKH4BITS, value32);
  962. value32 = ((val_x * ele_d) >> 7) & 0x01;
  963. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  964. BIT(27), value32);
  965. value32 = ((val_y * ele_d) >> 7) & 0x01;
  966. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  967. BIT(25), value32);
  968. } else {
  969. rtl_set_bbreg(hw,
  970. ROFDM0_XBTXIQIMBALANCE,
  971. MASKDWORD,
  972. ofdmswing_table[ofdm_index
  973. [1]]);
  974. rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
  975. MASKH4BITS, 0x00);
  976. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  977. BIT(27) | BIT(25), 0x00);
  978. }
  979. }
  980. }
  981. if (delta_iqk > 3) {
  982. rtlpriv->dm.thermalvalue_iqk = thermalvalue;
  983. rtl92c_phy_iq_calibrate(hw, false);
  984. }
  985. if (rtlpriv->dm.txpower_track_control)
  986. rtlpriv->dm.thermalvalue = thermalvalue;
  987. }
  988. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ("<===\n"));
  989. }
  990. static void rtl92c_dm_initialize_txpower_tracking_thermalmeter(
  991. struct ieee80211_hw *hw)
  992. {
  993. struct rtl_priv *rtlpriv = rtl_priv(hw);
  994. rtlpriv->dm.btxpower_tracking = true;
  995. rtlpriv->dm.btxpower_trackingInit = false;
  996. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  997. ("pMgntInfo->btxpower_tracking = %d\n",
  998. rtlpriv->dm.btxpower_tracking));
  999. }
  1000. static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
  1001. {
  1002. rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw);
  1003. }
  1004. static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw)
  1005. {
  1006. rtl92c_dm_txpower_tracking_callback_thermalmeter(hw);
  1007. }
  1008. static void rtl92c_dm_check_txpower_tracking_thermal_meter(
  1009. struct ieee80211_hw *hw)
  1010. {
  1011. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1012. static u8 tm_trigger;
  1013. if (!rtlpriv->dm.btxpower_tracking)
  1014. return;
  1015. if (!tm_trigger) {
  1016. rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK,
  1017. 0x60);
  1018. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  1019. ("Trigger 92S Thermal Meter!!\n"));
  1020. tm_trigger = 1;
  1021. return;
  1022. } else {
  1023. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  1024. ("Schedule TxPowerTracking direct call!!\n"));
  1025. rtl92c_dm_txpower_tracking_directcall(hw);
  1026. tm_trigger = 0;
  1027. }
  1028. }
  1029. void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw)
  1030. {
  1031. rtl92c_dm_check_txpower_tracking_thermal_meter(hw);
  1032. }
  1033. void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
  1034. {
  1035. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1036. struct rate_adaptive *p_ra = &(rtlpriv->ra);
  1037. p_ra->ratr_state = DM_RATR_STA_INIT;
  1038. p_ra->pre_ratr_state = DM_RATR_STA_INIT;
  1039. if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
  1040. rtlpriv->dm.b_useramask = true;
  1041. else
  1042. rtlpriv->dm.b_useramask = false;
  1043. }
  1044. static void rtl92c_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
  1045. {
  1046. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1047. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1048. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1049. struct rate_adaptive *p_ra = &(rtlpriv->ra);
  1050. u32 low_rssithresh_for_ra, high_rssithresh_for_ra;
  1051. if (is_hal_stop(rtlhal)) {
  1052. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1053. ("<---- driver is going to unload\n"));
  1054. return;
  1055. }
  1056. if (!rtlpriv->dm.b_useramask) {
  1057. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1058. ("<---- driver does not control rate adaptive mask\n"));
  1059. return;
  1060. }
  1061. if (mac->link_state == MAC80211_LINKED) {
  1062. switch (p_ra->pre_ratr_state) {
  1063. case DM_RATR_STA_HIGH:
  1064. high_rssithresh_for_ra = 50;
  1065. low_rssithresh_for_ra = 20;
  1066. break;
  1067. case DM_RATR_STA_MIDDLE:
  1068. high_rssithresh_for_ra = 55;
  1069. low_rssithresh_for_ra = 20;
  1070. break;
  1071. case DM_RATR_STA_LOW:
  1072. high_rssithresh_for_ra = 50;
  1073. low_rssithresh_for_ra = 25;
  1074. break;
  1075. default:
  1076. high_rssithresh_for_ra = 50;
  1077. low_rssithresh_for_ra = 20;
  1078. break;
  1079. }
  1080. if (rtlpriv->dm.undecorated_smoothed_pwdb >
  1081. (long)high_rssithresh_for_ra)
  1082. p_ra->ratr_state = DM_RATR_STA_HIGH;
  1083. else if (rtlpriv->dm.undecorated_smoothed_pwdb >
  1084. (long)low_rssithresh_for_ra)
  1085. p_ra->ratr_state = DM_RATR_STA_MIDDLE;
  1086. else
  1087. p_ra->ratr_state = DM_RATR_STA_LOW;
  1088. if (p_ra->pre_ratr_state != p_ra->ratr_state) {
  1089. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1090. ("RSSI = %ld\n",
  1091. rtlpriv->dm.undecorated_smoothed_pwdb));
  1092. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1093. ("RSSI_LEVEL = %d\n", p_ra->ratr_state));
  1094. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1095. ("PreState = %d, CurState = %d\n",
  1096. p_ra->pre_ratr_state, p_ra->ratr_state));
  1097. rtlpriv->cfg->ops->update_rate_mask(hw,
  1098. p_ra->ratr_state);
  1099. p_ra->pre_ratr_state = p_ra->ratr_state;
  1100. }
  1101. }
  1102. }
  1103. static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
  1104. {
  1105. dm_pstable.pre_ccastate = CCA_MAX;
  1106. dm_pstable.cur_ccasate = CCA_MAX;
  1107. dm_pstable.pre_rfstate = RF_MAX;
  1108. dm_pstable.cur_rfstate = RF_MAX;
  1109. dm_pstable.rssi_val_min = 0;
  1110. }
  1111. static void rtl92c_dm_1r_cca(struct ieee80211_hw *hw)
  1112. {
  1113. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1114. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  1115. if (dm_pstable.rssi_val_min != 0) {
  1116. if (dm_pstable.pre_ccastate == CCA_2R) {
  1117. if (dm_pstable.rssi_val_min >= 35)
  1118. dm_pstable.cur_ccasate = CCA_1R;
  1119. else
  1120. dm_pstable.cur_ccasate = CCA_2R;
  1121. } else {
  1122. if (dm_pstable.rssi_val_min <= 30)
  1123. dm_pstable.cur_ccasate = CCA_2R;
  1124. else
  1125. dm_pstable.cur_ccasate = CCA_1R;
  1126. }
  1127. } else {
  1128. dm_pstable.cur_ccasate = CCA_MAX;
  1129. }
  1130. if (dm_pstable.pre_ccastate != dm_pstable.cur_ccasate) {
  1131. if (dm_pstable.cur_ccasate == CCA_1R) {
  1132. if (get_rf_type(rtlphy) == RF_2T2R) {
  1133. rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
  1134. MASKBYTE0, 0x13);
  1135. rtl_set_bbreg(hw, 0xe70, MASKBYTE3, 0x20);
  1136. } else {
  1137. rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
  1138. MASKBYTE0, 0x23);
  1139. rtl_set_bbreg(hw, 0xe70, 0x7fc00000, 0x10c);
  1140. }
  1141. } else {
  1142. rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0,
  1143. 0x33);
  1144. rtl_set_bbreg(hw, 0xe70, MASKBYTE3, 0x63);
  1145. }
  1146. dm_pstable.pre_ccastate = dm_pstable.cur_ccasate;
  1147. }
  1148. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, ("CCAStage = %s\n",
  1149. (dm_pstable.cur_ccasate ==
  1150. 0) ? "1RCCA" : "2RCCA"));
  1151. }
  1152. void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
  1153. {
  1154. static u8 initialize;
  1155. static u32 reg_874, reg_c70, reg_85c, reg_a74;
  1156. if (initialize == 0) {
  1157. reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1158. MASKDWORD) & 0x1CC000) >> 14;
  1159. reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
  1160. MASKDWORD) & BIT(3)) >> 3;
  1161. reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
  1162. MASKDWORD) & 0xFF000000) >> 24;
  1163. reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
  1164. initialize = 1;
  1165. }
  1166. if (!bforce_in_normal) {
  1167. if (dm_pstable.rssi_val_min != 0) {
  1168. if (dm_pstable.pre_rfstate == RF_NORMAL) {
  1169. if (dm_pstable.rssi_val_min >= 30)
  1170. dm_pstable.cur_rfstate = RF_SAVE;
  1171. else
  1172. dm_pstable.cur_rfstate = RF_NORMAL;
  1173. } else {
  1174. if (dm_pstable.rssi_val_min <= 25)
  1175. dm_pstable.cur_rfstate = RF_NORMAL;
  1176. else
  1177. dm_pstable.cur_rfstate = RF_SAVE;
  1178. }
  1179. } else {
  1180. dm_pstable.cur_rfstate = RF_MAX;
  1181. }
  1182. } else {
  1183. dm_pstable.cur_rfstate = RF_NORMAL;
  1184. }
  1185. if (dm_pstable.pre_rfstate != dm_pstable.cur_rfstate) {
  1186. if (dm_pstable.cur_rfstate == RF_SAVE) {
  1187. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1188. 0x1C0000, 0x2);
  1189. rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
  1190. rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
  1191. 0xFF000000, 0x63);
  1192. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1193. 0xC000, 0x2);
  1194. rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
  1195. rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
  1196. rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
  1197. } else {
  1198. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1199. 0x1CC000, reg_874);
  1200. rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
  1201. reg_c70);
  1202. rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
  1203. reg_85c);
  1204. rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
  1205. rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
  1206. }
  1207. dm_pstable.pre_rfstate = dm_pstable.cur_rfstate;
  1208. }
  1209. }
  1210. static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
  1211. {
  1212. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1213. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1214. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1215. if (((mac->link_state == MAC80211_NOLINK)) &&
  1216. (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
  1217. dm_pstable.rssi_val_min = 0;
  1218. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1219. ("Not connected to any\n"));
  1220. }
  1221. if (mac->link_state == MAC80211_LINKED) {
  1222. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  1223. dm_pstable.rssi_val_min =
  1224. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1225. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1226. ("AP Client PWDB = 0x%lx\n",
  1227. dm_pstable.rssi_val_min));
  1228. } else {
  1229. dm_pstable.rssi_val_min =
  1230. rtlpriv->dm.undecorated_smoothed_pwdb;
  1231. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1232. ("STA Default Port PWDB = 0x%lx\n",
  1233. dm_pstable.rssi_val_min));
  1234. }
  1235. } else {
  1236. dm_pstable.rssi_val_min =
  1237. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1238. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1239. ("AP Ext Port PWDB = 0x%lx\n",
  1240. dm_pstable.rssi_val_min));
  1241. }
  1242. if (IS_92C_SERIAL(rtlhal->version))
  1243. rtl92c_dm_1r_cca(hw);
  1244. }
  1245. void rtl92c_dm_init(struct ieee80211_hw *hw)
  1246. {
  1247. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1248. rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
  1249. rtl92c_dm_diginit(hw);
  1250. rtl92c_dm_init_dynamic_txpower(hw);
  1251. rtl92c_dm_init_edca_turbo(hw);
  1252. rtl92c_dm_init_rate_adaptive_mask(hw);
  1253. rtl92c_dm_initialize_txpower_tracking(hw);
  1254. rtl92c_dm_init_dynamic_bb_powersaving(hw);
  1255. }
  1256. void rtl92c_dm_watchdog(struct ieee80211_hw *hw)
  1257. {
  1258. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1259. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  1260. bool b_fw_current_inpsmode = false;
  1261. bool b_fw_ps_awake = true;
  1262. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
  1263. (u8 *) (&b_fw_current_inpsmode));
  1264. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
  1265. (u8 *) (&b_fw_ps_awake));
  1266. if ((ppsc->rfpwr_state == ERFON) && ((!b_fw_current_inpsmode) &&
  1267. b_fw_ps_awake)
  1268. && (!ppsc->rfchange_inprogress)) {
  1269. rtl92c_dm_pwdb_monitor(hw);
  1270. rtl92c_dm_dig(hw);
  1271. rtl92c_dm_false_alarm_counter_statistics(hw);
  1272. rtl92c_dm_dynamic_bb_powersaving(hw);
  1273. rtl92c_dm_dynamic_txpower(hw);
  1274. rtl92c_dm_check_txpower_tracking(hw);
  1275. rtl92c_dm_refresh_rate_adaptive_mask(hw);
  1276. rtl92c_dm_check_edca_turbo(hw);
  1277. }
  1278. }