en_rx.c 26 KB

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  1. /*
  2. * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. *
  32. */
  33. #include <linux/mlx4/cq.h>
  34. #include <linux/slab.h>
  35. #include <linux/mlx4/qp.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/if_ether.h>
  38. #include <linux/if_vlan.h>
  39. #include <linux/vmalloc.h>
  40. #include "mlx4_en.h"
  41. static int mlx4_en_alloc_frag(struct mlx4_en_priv *priv,
  42. struct mlx4_en_rx_desc *rx_desc,
  43. struct page_frag *skb_frags,
  44. struct mlx4_en_rx_alloc *ring_alloc,
  45. int i)
  46. {
  47. struct mlx4_en_dev *mdev = priv->mdev;
  48. struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
  49. struct mlx4_en_rx_alloc *page_alloc = &ring_alloc[i];
  50. struct page *page;
  51. dma_addr_t dma;
  52. if (page_alloc->offset == frag_info->last_offset) {
  53. /* Allocate new page */
  54. page = alloc_pages(GFP_ATOMIC | __GFP_COMP, MLX4_EN_ALLOC_ORDER);
  55. if (!page)
  56. return -ENOMEM;
  57. skb_frags[i].page = page_alloc->page;
  58. skb_frags[i].offset = page_alloc->offset;
  59. page_alloc->page = page;
  60. page_alloc->offset = frag_info->frag_align;
  61. } else {
  62. page = page_alloc->page;
  63. get_page(page);
  64. skb_frags[i].page = page;
  65. skb_frags[i].offset = page_alloc->offset;
  66. page_alloc->offset += frag_info->frag_stride;
  67. }
  68. dma = pci_map_single(mdev->pdev, page_address(skb_frags[i].page) +
  69. skb_frags[i].offset, frag_info->frag_size,
  70. PCI_DMA_FROMDEVICE);
  71. rx_desc->data[i].addr = cpu_to_be64(dma);
  72. return 0;
  73. }
  74. static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
  75. struct mlx4_en_rx_ring *ring)
  76. {
  77. struct mlx4_en_rx_alloc *page_alloc;
  78. int i;
  79. for (i = 0; i < priv->num_frags; i++) {
  80. page_alloc = &ring->page_alloc[i];
  81. page_alloc->page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
  82. MLX4_EN_ALLOC_ORDER);
  83. if (!page_alloc->page)
  84. goto out;
  85. page_alloc->offset = priv->frag_info[i].frag_align;
  86. en_dbg(DRV, priv, "Initialized allocator:%d with page:%p\n",
  87. i, page_alloc->page);
  88. }
  89. return 0;
  90. out:
  91. while (i--) {
  92. page_alloc = &ring->page_alloc[i];
  93. put_page(page_alloc->page);
  94. page_alloc->page = NULL;
  95. }
  96. return -ENOMEM;
  97. }
  98. static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
  99. struct mlx4_en_rx_ring *ring)
  100. {
  101. struct mlx4_en_rx_alloc *page_alloc;
  102. int i;
  103. for (i = 0; i < priv->num_frags; i++) {
  104. page_alloc = &ring->page_alloc[i];
  105. en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
  106. i, page_count(page_alloc->page));
  107. put_page(page_alloc->page);
  108. page_alloc->page = NULL;
  109. }
  110. }
  111. static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
  112. struct mlx4_en_rx_ring *ring, int index)
  113. {
  114. struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
  115. struct skb_frag_struct *skb_frags = ring->rx_info +
  116. (index << priv->log_rx_info);
  117. int possible_frags;
  118. int i;
  119. /* Set size and memtype fields */
  120. for (i = 0; i < priv->num_frags; i++) {
  121. skb_frag_size_set(&skb_frags[i], priv->frag_info[i].frag_size);
  122. rx_desc->data[i].byte_count =
  123. cpu_to_be32(priv->frag_info[i].frag_size);
  124. rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
  125. }
  126. /* If the number of used fragments does not fill up the ring stride,
  127. * remaining (unused) fragments must be padded with null address/size
  128. * and a special memory key */
  129. possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
  130. for (i = priv->num_frags; i < possible_frags; i++) {
  131. rx_desc->data[i].byte_count = 0;
  132. rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
  133. rx_desc->data[i].addr = 0;
  134. }
  135. }
  136. static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
  137. struct mlx4_en_rx_ring *ring, int index)
  138. {
  139. struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
  140. struct page_frag *skb_frags = ring->rx_info +
  141. (index << priv->log_rx_info);
  142. int i;
  143. for (i = 0; i < priv->num_frags; i++)
  144. if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, ring->page_alloc, i))
  145. goto err;
  146. return 0;
  147. err:
  148. while (i--)
  149. put_page(skb_frags[i].page);
  150. return -ENOMEM;
  151. }
  152. static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
  153. {
  154. *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
  155. }
  156. static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
  157. struct mlx4_en_rx_ring *ring,
  158. int index)
  159. {
  160. struct mlx4_en_dev *mdev = priv->mdev;
  161. struct page_frag *skb_frags;
  162. struct mlx4_en_rx_desc *rx_desc = ring->buf + (index << ring->log_stride);
  163. dma_addr_t dma;
  164. int nr;
  165. skb_frags = ring->rx_info + (index << priv->log_rx_info);
  166. for (nr = 0; nr < priv->num_frags; nr++) {
  167. en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
  168. dma = be64_to_cpu(rx_desc->data[nr].addr);
  169. en_dbg(DRV, priv, "Unmapping buffer at dma:0x%llx\n", (u64) dma);
  170. pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size,
  171. PCI_DMA_FROMDEVICE);
  172. put_page(skb_frags[nr].page);
  173. }
  174. }
  175. static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
  176. {
  177. struct mlx4_en_rx_ring *ring;
  178. int ring_ind;
  179. int buf_ind;
  180. int new_size;
  181. for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
  182. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  183. ring = &priv->rx_ring[ring_ind];
  184. if (mlx4_en_prepare_rx_desc(priv, ring,
  185. ring->actual_size)) {
  186. if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
  187. en_err(priv, "Failed to allocate "
  188. "enough rx buffers\n");
  189. return -ENOMEM;
  190. } else {
  191. new_size = rounddown_pow_of_two(ring->actual_size);
  192. en_warn(priv, "Only %d buffers allocated "
  193. "reducing ring size to %d",
  194. ring->actual_size, new_size);
  195. goto reduce_rings;
  196. }
  197. }
  198. ring->actual_size++;
  199. ring->prod++;
  200. }
  201. }
  202. return 0;
  203. reduce_rings:
  204. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  205. ring = &priv->rx_ring[ring_ind];
  206. while (ring->actual_size > new_size) {
  207. ring->actual_size--;
  208. ring->prod--;
  209. mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
  210. }
  211. }
  212. return 0;
  213. }
  214. static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
  215. struct mlx4_en_rx_ring *ring)
  216. {
  217. int index;
  218. en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
  219. ring->cons, ring->prod);
  220. /* Unmap and free Rx buffers */
  221. BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size);
  222. while (ring->cons != ring->prod) {
  223. index = ring->cons & ring->size_mask;
  224. en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
  225. mlx4_en_free_rx_desc(priv, ring, index);
  226. ++ring->cons;
  227. }
  228. }
  229. int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
  230. struct mlx4_en_rx_ring *ring, u32 size, u16 stride)
  231. {
  232. struct mlx4_en_dev *mdev = priv->mdev;
  233. int err;
  234. int tmp;
  235. ring->prod = 0;
  236. ring->cons = 0;
  237. ring->size = size;
  238. ring->size_mask = size - 1;
  239. ring->stride = stride;
  240. ring->log_stride = ffs(ring->stride) - 1;
  241. ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
  242. tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
  243. sizeof(struct skb_frag_struct));
  244. ring->rx_info = vmalloc(tmp);
  245. if (!ring->rx_info)
  246. return -ENOMEM;
  247. en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
  248. ring->rx_info, tmp);
  249. err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
  250. ring->buf_size, 2 * PAGE_SIZE);
  251. if (err)
  252. goto err_ring;
  253. err = mlx4_en_map_buffer(&ring->wqres.buf);
  254. if (err) {
  255. en_err(priv, "Failed to map RX buffer\n");
  256. goto err_hwq;
  257. }
  258. ring->buf = ring->wqres.buf.direct.buf;
  259. return 0;
  260. err_hwq:
  261. mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
  262. err_ring:
  263. vfree(ring->rx_info);
  264. ring->rx_info = NULL;
  265. return err;
  266. }
  267. int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
  268. {
  269. struct mlx4_en_rx_ring *ring;
  270. int i;
  271. int ring_ind;
  272. int err;
  273. int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
  274. DS_SIZE * priv->num_frags);
  275. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  276. ring = &priv->rx_ring[ring_ind];
  277. ring->prod = 0;
  278. ring->cons = 0;
  279. ring->actual_size = 0;
  280. ring->cqn = priv->rx_cq[ring_ind].mcq.cqn;
  281. ring->stride = stride;
  282. if (ring->stride <= TXBB_SIZE)
  283. ring->buf += TXBB_SIZE;
  284. ring->log_stride = ffs(ring->stride) - 1;
  285. ring->buf_size = ring->size * ring->stride;
  286. memset(ring->buf, 0, ring->buf_size);
  287. mlx4_en_update_rx_prod_db(ring);
  288. /* Initailize all descriptors */
  289. for (i = 0; i < ring->size; i++)
  290. mlx4_en_init_rx_desc(priv, ring, i);
  291. /* Initialize page allocators */
  292. err = mlx4_en_init_allocator(priv, ring);
  293. if (err) {
  294. en_err(priv, "Failed initializing ring allocator\n");
  295. if (ring->stride <= TXBB_SIZE)
  296. ring->buf -= TXBB_SIZE;
  297. ring_ind--;
  298. goto err_allocator;
  299. }
  300. }
  301. err = mlx4_en_fill_rx_buffers(priv);
  302. if (err)
  303. goto err_buffers;
  304. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  305. ring = &priv->rx_ring[ring_ind];
  306. ring->size_mask = ring->actual_size - 1;
  307. mlx4_en_update_rx_prod_db(ring);
  308. }
  309. return 0;
  310. err_buffers:
  311. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
  312. mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]);
  313. ring_ind = priv->rx_ring_num - 1;
  314. err_allocator:
  315. while (ring_ind >= 0) {
  316. if (priv->rx_ring[ring_ind].stride <= TXBB_SIZE)
  317. priv->rx_ring[ring_ind].buf -= TXBB_SIZE;
  318. mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]);
  319. ring_ind--;
  320. }
  321. return err;
  322. }
  323. void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
  324. struct mlx4_en_rx_ring *ring)
  325. {
  326. struct mlx4_en_dev *mdev = priv->mdev;
  327. mlx4_en_unmap_buffer(&ring->wqres.buf);
  328. mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size + TXBB_SIZE);
  329. vfree(ring->rx_info);
  330. ring->rx_info = NULL;
  331. }
  332. void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
  333. struct mlx4_en_rx_ring *ring)
  334. {
  335. mlx4_en_free_rx_buf(priv, ring);
  336. if (ring->stride <= TXBB_SIZE)
  337. ring->buf -= TXBB_SIZE;
  338. mlx4_en_destroy_allocator(priv, ring);
  339. }
  340. /* Unmap a completed descriptor and free unused pages */
  341. static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
  342. struct mlx4_en_rx_desc *rx_desc,
  343. struct page_frag *skb_frags,
  344. struct sk_buff *skb,
  345. struct mlx4_en_rx_alloc *page_alloc,
  346. int length)
  347. {
  348. struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
  349. struct mlx4_en_dev *mdev = priv->mdev;
  350. struct mlx4_en_frag_info *frag_info;
  351. int nr;
  352. dma_addr_t dma;
  353. /* Collect used fragments while replacing them in the HW descirptors */
  354. for (nr = 0; nr < priv->num_frags; nr++) {
  355. frag_info = &priv->frag_info[nr];
  356. if (length <= frag_info->frag_prefix_size)
  357. break;
  358. /* Save page reference in skb */
  359. __skb_frag_set_page(&skb_frags_rx[nr], skb_frags[nr].page);
  360. skb_frag_size_set(&skb_frags_rx[nr], skb_frags[nr].size);
  361. skb_frags_rx[nr].page_offset = skb_frags[nr].offset;
  362. skb->truesize += frag_info->frag_stride;
  363. dma = be64_to_cpu(rx_desc->data[nr].addr);
  364. /* Allocate a replacement page */
  365. if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, page_alloc, nr))
  366. goto fail;
  367. /* Unmap buffer */
  368. pci_unmap_single(mdev->pdev, dma, skb_frag_size(&skb_frags_rx[nr]),
  369. PCI_DMA_FROMDEVICE);
  370. }
  371. /* Adjust size of last fragment to match actual length */
  372. if (nr > 0)
  373. skb_frag_size_set(&skb_frags_rx[nr - 1],
  374. length - priv->frag_info[nr - 1].frag_prefix_size);
  375. return nr;
  376. fail:
  377. /* Drop all accumulated fragments (which have already been replaced in
  378. * the descriptor) of this packet; remaining fragments are reused... */
  379. while (nr > 0) {
  380. nr--;
  381. __skb_frag_unref(&skb_frags_rx[nr]);
  382. }
  383. return 0;
  384. }
  385. static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
  386. struct mlx4_en_rx_desc *rx_desc,
  387. struct page_frag *skb_frags,
  388. struct mlx4_en_rx_alloc *page_alloc,
  389. unsigned int length)
  390. {
  391. struct mlx4_en_dev *mdev = priv->mdev;
  392. struct sk_buff *skb;
  393. void *va;
  394. int used_frags;
  395. dma_addr_t dma;
  396. skb = dev_alloc_skb(SMALL_PACKET_SIZE + NET_IP_ALIGN);
  397. if (!skb) {
  398. en_dbg(RX_ERR, priv, "Failed allocating skb\n");
  399. return NULL;
  400. }
  401. skb->dev = priv->dev;
  402. skb_reserve(skb, NET_IP_ALIGN);
  403. skb->len = length;
  404. /* Get pointer to first fragment so we could copy the headers into the
  405. * (linear part of the) skb */
  406. va = page_address(skb_frags[0].page) + skb_frags[0].offset;
  407. if (length <= SMALL_PACKET_SIZE) {
  408. /* We are copying all relevant data to the skb - temporarily
  409. * synch buffers for the copy */
  410. dma = be64_to_cpu(rx_desc->data[0].addr);
  411. dma_sync_single_for_cpu(&mdev->pdev->dev, dma, length,
  412. DMA_FROM_DEVICE);
  413. skb_copy_to_linear_data(skb, va, length);
  414. dma_sync_single_for_device(&mdev->pdev->dev, dma, length,
  415. DMA_FROM_DEVICE);
  416. skb->tail += length;
  417. } else {
  418. /* Move relevant fragments to skb */
  419. used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, skb_frags,
  420. skb, page_alloc, length);
  421. if (unlikely(!used_frags)) {
  422. kfree_skb(skb);
  423. return NULL;
  424. }
  425. skb_shinfo(skb)->nr_frags = used_frags;
  426. /* Copy headers into the skb linear buffer */
  427. memcpy(skb->data, va, HEADER_COPY_SIZE);
  428. skb->tail += HEADER_COPY_SIZE;
  429. /* Skip headers in first fragment */
  430. skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE;
  431. /* Adjust size of first fragment */
  432. skb_frag_size_sub(&skb_shinfo(skb)->frags[0], HEADER_COPY_SIZE);
  433. skb->data_len = length - HEADER_COPY_SIZE;
  434. }
  435. return skb;
  436. }
  437. static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
  438. {
  439. int i;
  440. int offset = ETH_HLEN;
  441. for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
  442. if (*(skb->data + offset) != (unsigned char) (i & 0xff))
  443. goto out_loopback;
  444. }
  445. /* Loopback found */
  446. priv->loopback_ok = 1;
  447. out_loopback:
  448. dev_kfree_skb_any(skb);
  449. }
  450. int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
  451. {
  452. struct mlx4_en_priv *priv = netdev_priv(dev);
  453. struct mlx4_cqe *cqe;
  454. struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring];
  455. struct page_frag *skb_frags;
  456. struct mlx4_en_rx_desc *rx_desc;
  457. struct sk_buff *skb;
  458. int index;
  459. int nr;
  460. unsigned int length;
  461. int polled = 0;
  462. int ip_summed;
  463. struct ethhdr *ethh;
  464. u64 s_mac;
  465. if (!priv->port_up)
  466. return 0;
  467. /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
  468. * descriptor offset can be deduced from the CQE index instead of
  469. * reading 'cqe->index' */
  470. index = cq->mcq.cons_index & ring->size_mask;
  471. cqe = &cq->buf[index];
  472. /* Process all completed CQEs */
  473. while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
  474. cq->mcq.cons_index & cq->size)) {
  475. skb_frags = ring->rx_info + (index << priv->log_rx_info);
  476. rx_desc = ring->buf + (index << ring->log_stride);
  477. /*
  478. * make sure we read the CQE after we read the ownership bit
  479. */
  480. rmb();
  481. /* Drop packet on bad receive or bad checksum */
  482. if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
  483. MLX4_CQE_OPCODE_ERROR)) {
  484. en_err(priv, "CQE completed in error - vendor "
  485. "syndrom:%d syndrom:%d\n",
  486. ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome,
  487. ((struct mlx4_err_cqe *) cqe)->syndrome);
  488. goto next;
  489. }
  490. if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
  491. en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
  492. goto next;
  493. }
  494. /* Get pointer to first fragment since we haven't skb yet and
  495. * cast it to ethhdr struct */
  496. ethh = (struct ethhdr *)(page_address(skb_frags[0].page) +
  497. skb_frags[0].offset);
  498. s_mac = mlx4_en_mac_to_u64(ethh->h_source);
  499. /* If source MAC is equal to our own MAC and not performing
  500. * the selftest or flb disabled - drop the packet */
  501. if (s_mac == priv->mac &&
  502. (!(dev->features & NETIF_F_LOOPBACK) ||
  503. !priv->validate_loopback))
  504. goto next;
  505. /*
  506. * Packet is OK - process it.
  507. */
  508. length = be32_to_cpu(cqe->byte_cnt);
  509. length -= ring->fcs_del;
  510. ring->bytes += length;
  511. ring->packets++;
  512. if (likely(dev->features & NETIF_F_RXCSUM)) {
  513. if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
  514. (cqe->checksum == cpu_to_be16(0xffff))) {
  515. ring->csum_ok++;
  516. /* This packet is eligible for LRO if it is:
  517. * - DIX Ethernet (type interpretation)
  518. * - TCP/IP (v4)
  519. * - without IP options
  520. * - not an IP fragment */
  521. if (dev->features & NETIF_F_GRO) {
  522. struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
  523. if (!gro_skb)
  524. goto next;
  525. nr = mlx4_en_complete_rx_desc(
  526. priv, rx_desc,
  527. skb_frags, gro_skb,
  528. ring->page_alloc, length);
  529. if (!nr)
  530. goto next;
  531. skb_shinfo(gro_skb)->nr_frags = nr;
  532. gro_skb->len = length;
  533. gro_skb->data_len = length;
  534. gro_skb->ip_summed = CHECKSUM_UNNECESSARY;
  535. if (cqe->vlan_my_qpn &
  536. cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) {
  537. u16 vid = be16_to_cpu(cqe->sl_vid);
  538. __vlan_hwaccel_put_tag(gro_skb, vid);
  539. }
  540. if (dev->features & NETIF_F_RXHASH)
  541. gro_skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid);
  542. skb_record_rx_queue(gro_skb, cq->ring);
  543. napi_gro_frags(&cq->napi);
  544. goto next;
  545. }
  546. /* LRO not possible, complete processing here */
  547. ip_summed = CHECKSUM_UNNECESSARY;
  548. } else {
  549. ip_summed = CHECKSUM_NONE;
  550. ring->csum_none++;
  551. }
  552. } else {
  553. ip_summed = CHECKSUM_NONE;
  554. ring->csum_none++;
  555. }
  556. skb = mlx4_en_rx_skb(priv, rx_desc, skb_frags,
  557. ring->page_alloc, length);
  558. if (!skb) {
  559. priv->stats.rx_dropped++;
  560. goto next;
  561. }
  562. if (unlikely(priv->validate_loopback)) {
  563. validate_loopback(priv, skb);
  564. goto next;
  565. }
  566. skb->ip_summed = ip_summed;
  567. skb->protocol = eth_type_trans(skb, dev);
  568. skb_record_rx_queue(skb, cq->ring);
  569. if (dev->features & NETIF_F_RXHASH)
  570. skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid);
  571. if (be32_to_cpu(cqe->vlan_my_qpn) &
  572. MLX4_CQE_VLAN_PRESENT_MASK)
  573. __vlan_hwaccel_put_tag(skb, be16_to_cpu(cqe->sl_vid));
  574. /* Push it up the stack */
  575. netif_receive_skb(skb);
  576. next:
  577. ++cq->mcq.cons_index;
  578. index = (cq->mcq.cons_index) & ring->size_mask;
  579. cqe = &cq->buf[index];
  580. if (++polled == budget) {
  581. /* We are here because we reached the NAPI budget -
  582. * flush only pending LRO sessions */
  583. goto out;
  584. }
  585. }
  586. out:
  587. AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
  588. mlx4_cq_set_ci(&cq->mcq);
  589. wmb(); /* ensure HW sees CQ consumer before we post new buffers */
  590. ring->cons = cq->mcq.cons_index;
  591. ring->prod += polled; /* Polled descriptors were realocated in place */
  592. mlx4_en_update_rx_prod_db(ring);
  593. return polled;
  594. }
  595. void mlx4_en_rx_irq(struct mlx4_cq *mcq)
  596. {
  597. struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
  598. struct mlx4_en_priv *priv = netdev_priv(cq->dev);
  599. if (priv->port_up)
  600. napi_schedule(&cq->napi);
  601. else
  602. mlx4_en_arm_cq(priv, cq);
  603. }
  604. /* Rx CQ polling - called by NAPI */
  605. int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
  606. {
  607. struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
  608. struct net_device *dev = cq->dev;
  609. struct mlx4_en_priv *priv = netdev_priv(dev);
  610. int done;
  611. done = mlx4_en_process_rx_cq(dev, cq, budget);
  612. /* If we used up all the quota - we're probably not done yet... */
  613. if (done == budget)
  614. INC_PERF_COUNTER(priv->pstats.napi_quota);
  615. else {
  616. /* Done for now */
  617. napi_complete(napi);
  618. mlx4_en_arm_cq(priv, cq);
  619. }
  620. return done;
  621. }
  622. /* Calculate the last offset position that accommodates a full fragment
  623. * (assuming fagment size = stride-align) */
  624. static int mlx4_en_last_alloc_offset(struct mlx4_en_priv *priv, u16 stride, u16 align)
  625. {
  626. u16 res = MLX4_EN_ALLOC_SIZE % stride;
  627. u16 offset = MLX4_EN_ALLOC_SIZE - stride - res + align;
  628. en_dbg(DRV, priv, "Calculated last offset for stride:%d align:%d "
  629. "res:%d offset:%d\n", stride, align, res, offset);
  630. return offset;
  631. }
  632. static int frag_sizes[] = {
  633. FRAG_SZ0,
  634. FRAG_SZ1,
  635. FRAG_SZ2,
  636. FRAG_SZ3
  637. };
  638. void mlx4_en_calc_rx_buf(struct net_device *dev)
  639. {
  640. struct mlx4_en_priv *priv = netdev_priv(dev);
  641. int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE;
  642. int buf_size = 0;
  643. int i = 0;
  644. while (buf_size < eff_mtu) {
  645. priv->frag_info[i].frag_size =
  646. (eff_mtu > buf_size + frag_sizes[i]) ?
  647. frag_sizes[i] : eff_mtu - buf_size;
  648. priv->frag_info[i].frag_prefix_size = buf_size;
  649. if (!i) {
  650. priv->frag_info[i].frag_align = NET_IP_ALIGN;
  651. priv->frag_info[i].frag_stride =
  652. ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES);
  653. } else {
  654. priv->frag_info[i].frag_align = 0;
  655. priv->frag_info[i].frag_stride =
  656. ALIGN(frag_sizes[i], SMP_CACHE_BYTES);
  657. }
  658. priv->frag_info[i].last_offset = mlx4_en_last_alloc_offset(
  659. priv, priv->frag_info[i].frag_stride,
  660. priv->frag_info[i].frag_align);
  661. buf_size += priv->frag_info[i].frag_size;
  662. i++;
  663. }
  664. priv->num_frags = i;
  665. priv->rx_skb_size = eff_mtu;
  666. priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct skb_frag_struct));
  667. en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d "
  668. "num_frags:%d):\n", eff_mtu, priv->num_frags);
  669. for (i = 0; i < priv->num_frags; i++) {
  670. en_dbg(DRV, priv, " frag:%d - size:%d prefix:%d align:%d "
  671. "stride:%d last_offset:%d\n", i,
  672. priv->frag_info[i].frag_size,
  673. priv->frag_info[i].frag_prefix_size,
  674. priv->frag_info[i].frag_align,
  675. priv->frag_info[i].frag_stride,
  676. priv->frag_info[i].last_offset);
  677. }
  678. }
  679. /* RSS related functions */
  680. static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
  681. struct mlx4_en_rx_ring *ring,
  682. enum mlx4_qp_state *state,
  683. struct mlx4_qp *qp)
  684. {
  685. struct mlx4_en_dev *mdev = priv->mdev;
  686. struct mlx4_qp_context *context;
  687. int err = 0;
  688. context = kmalloc(sizeof *context , GFP_KERNEL);
  689. if (!context) {
  690. en_err(priv, "Failed to allocate qp context\n");
  691. return -ENOMEM;
  692. }
  693. err = mlx4_qp_alloc(mdev->dev, qpn, qp);
  694. if (err) {
  695. en_err(priv, "Failed to allocate qp #%x\n", qpn);
  696. goto out;
  697. }
  698. qp->event = mlx4_en_sqp_event;
  699. memset(context, 0, sizeof *context);
  700. mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
  701. qpn, ring->cqn, context);
  702. context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
  703. /* Cancel FCS removal if FW allows */
  704. if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
  705. context->param3 |= cpu_to_be32(1 << 29);
  706. ring->fcs_del = ETH_FCS_LEN;
  707. } else
  708. ring->fcs_del = 0;
  709. err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
  710. if (err) {
  711. mlx4_qp_remove(mdev->dev, qp);
  712. mlx4_qp_free(mdev->dev, qp);
  713. }
  714. mlx4_en_update_rx_prod_db(ring);
  715. out:
  716. kfree(context);
  717. return err;
  718. }
  719. /* Allocate rx qp's and configure them according to rss map */
  720. int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
  721. {
  722. struct mlx4_en_dev *mdev = priv->mdev;
  723. struct mlx4_en_rss_map *rss_map = &priv->rss_map;
  724. struct mlx4_qp_context context;
  725. struct mlx4_rss_context *rss_context;
  726. int rss_rings;
  727. void *ptr;
  728. u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
  729. MLX4_RSS_TCP_IPV6);
  730. int i, qpn;
  731. int err = 0;
  732. int good_qps = 0;
  733. static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC,
  734. 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD,
  735. 0x593D56D9, 0xF3253C06, 0x2ADC1FFC};
  736. en_dbg(DRV, priv, "Configuring rss steering\n");
  737. err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
  738. priv->rx_ring_num,
  739. &rss_map->base_qpn);
  740. if (err) {
  741. en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
  742. return err;
  743. }
  744. for (i = 0; i < priv->rx_ring_num; i++) {
  745. qpn = rss_map->base_qpn + i;
  746. err = mlx4_en_config_rss_qp(priv, qpn, &priv->rx_ring[i],
  747. &rss_map->state[i],
  748. &rss_map->qps[i]);
  749. if (err)
  750. goto rss_err;
  751. ++good_qps;
  752. }
  753. /* Configure RSS indirection qp */
  754. err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp);
  755. if (err) {
  756. en_err(priv, "Failed to allocate RSS indirection QP\n");
  757. goto rss_err;
  758. }
  759. rss_map->indir_qp.event = mlx4_en_sqp_event;
  760. mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
  761. priv->rx_ring[0].cqn, &context);
  762. if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
  763. rss_rings = priv->rx_ring_num;
  764. else
  765. rss_rings = priv->prof->rss_rings;
  766. ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
  767. + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
  768. rss_context = ptr;
  769. rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
  770. (rss_map->base_qpn));
  771. rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
  772. if (priv->mdev->profile.udp_rss) {
  773. rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
  774. rss_context->base_qpn_udp = rss_context->default_qpn;
  775. }
  776. rss_context->flags = rss_mask;
  777. rss_context->hash_fn = MLX4_RSS_HASH_TOP;
  778. for (i = 0; i < 10; i++)
  779. rss_context->rss_key[i] = rsskey[i];
  780. err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
  781. &rss_map->indir_qp, &rss_map->indir_state);
  782. if (err)
  783. goto indir_err;
  784. return 0;
  785. indir_err:
  786. mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
  787. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
  788. mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
  789. mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
  790. rss_err:
  791. for (i = 0; i < good_qps; i++) {
  792. mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
  793. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
  794. mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
  795. mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
  796. }
  797. mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
  798. return err;
  799. }
  800. void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
  801. {
  802. struct mlx4_en_dev *mdev = priv->mdev;
  803. struct mlx4_en_rss_map *rss_map = &priv->rss_map;
  804. int i;
  805. mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
  806. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
  807. mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
  808. mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
  809. for (i = 0; i < priv->rx_ring_num; i++) {
  810. mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
  811. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
  812. mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
  813. mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
  814. }
  815. mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
  816. }