omap_hsmmc.c 52 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154
  1. /*
  2. * drivers/mmc/host/omap_hsmmc.c
  3. *
  4. * Driver for OMAP2430/3430 MMC controller.
  5. *
  6. * Copyright (C) 2007 Texas Instruments.
  7. *
  8. * Authors:
  9. * Syed Mohammed Khasim <x0khasim@ti.com>
  10. * Madhusudhan <madhu.cr@ti.com>
  11. * Mohit Jalori <mjalori@ti.com>
  12. *
  13. * This file is licensed under the terms of the GNU General Public License
  14. * version 2. This program is licensed "as is" without any warranty of any
  15. * kind, whether express or implied.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/init.h>
  19. #include <linux/kernel.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/seq_file.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/delay.h>
  24. #include <linux/dma-mapping.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/timer.h>
  27. #include <linux/clk.h>
  28. #include <linux/mmc/host.h>
  29. #include <linux/mmc/core.h>
  30. #include <linux/mmc/mmc.h>
  31. #include <linux/io.h>
  32. #include <linux/semaphore.h>
  33. #include <linux/gpio.h>
  34. #include <linux/regulator/consumer.h>
  35. #include <linux/pm_runtime.h>
  36. #include <plat/dma.h>
  37. #include <mach/hardware.h>
  38. #include <plat/board.h>
  39. #include <plat/mmc.h>
  40. #include <plat/cpu.h>
  41. /* OMAP HSMMC Host Controller Registers */
  42. #define OMAP_HSMMC_SYSCONFIG 0x0010
  43. #define OMAP_HSMMC_SYSSTATUS 0x0014
  44. #define OMAP_HSMMC_CON 0x002C
  45. #define OMAP_HSMMC_BLK 0x0104
  46. #define OMAP_HSMMC_ARG 0x0108
  47. #define OMAP_HSMMC_CMD 0x010C
  48. #define OMAP_HSMMC_RSP10 0x0110
  49. #define OMAP_HSMMC_RSP32 0x0114
  50. #define OMAP_HSMMC_RSP54 0x0118
  51. #define OMAP_HSMMC_RSP76 0x011C
  52. #define OMAP_HSMMC_DATA 0x0120
  53. #define OMAP_HSMMC_HCTL 0x0128
  54. #define OMAP_HSMMC_SYSCTL 0x012C
  55. #define OMAP_HSMMC_STAT 0x0130
  56. #define OMAP_HSMMC_IE 0x0134
  57. #define OMAP_HSMMC_ISE 0x0138
  58. #define OMAP_HSMMC_CAPA 0x0140
  59. #define VS18 (1 << 26)
  60. #define VS30 (1 << 25)
  61. #define SDVS18 (0x5 << 9)
  62. #define SDVS30 (0x6 << 9)
  63. #define SDVS33 (0x7 << 9)
  64. #define SDVS_MASK 0x00000E00
  65. #define SDVSCLR 0xFFFFF1FF
  66. #define SDVSDET 0x00000400
  67. #define AUTOIDLE 0x1
  68. #define SDBP (1 << 8)
  69. #define DTO 0xe
  70. #define ICE 0x1
  71. #define ICS 0x2
  72. #define CEN (1 << 2)
  73. #define CLKD_MASK 0x0000FFC0
  74. #define CLKD_SHIFT 6
  75. #define DTO_MASK 0x000F0000
  76. #define DTO_SHIFT 16
  77. #define INT_EN_MASK 0x307F0033
  78. #define BWR_ENABLE (1 << 4)
  79. #define BRR_ENABLE (1 << 5)
  80. #define DTO_ENABLE (1 << 20)
  81. #define INIT_STREAM (1 << 1)
  82. #define DP_SELECT (1 << 21)
  83. #define DDIR (1 << 4)
  84. #define DMA_EN 0x1
  85. #define MSBS (1 << 5)
  86. #define BCE (1 << 1)
  87. #define FOUR_BIT (1 << 1)
  88. #define DW8 (1 << 5)
  89. #define CC 0x1
  90. #define TC 0x02
  91. #define OD 0x1
  92. #define ERR (1 << 15)
  93. #define CMD_TIMEOUT (1 << 16)
  94. #define DATA_TIMEOUT (1 << 20)
  95. #define CMD_CRC (1 << 17)
  96. #define DATA_CRC (1 << 21)
  97. #define CARD_ERR (1 << 28)
  98. #define STAT_CLEAR 0xFFFFFFFF
  99. #define INIT_STREAM_CMD 0x00000000
  100. #define DUAL_VOLT_OCR_BIT 7
  101. #define SRC (1 << 25)
  102. #define SRD (1 << 26)
  103. #define SOFTRESET (1 << 1)
  104. #define RESETDONE (1 << 0)
  105. #define MMC_AUTOSUSPEND_DELAY 100
  106. #define MMC_TIMEOUT_MS 20
  107. #define OMAP_MMC_MIN_CLOCK 400000
  108. #define OMAP_MMC_MAX_CLOCK 52000000
  109. #define DRIVER_NAME "omap_hsmmc"
  110. /*
  111. * One controller can have multiple slots, like on some omap boards using
  112. * omap.c controller driver. Luckily this is not currently done on any known
  113. * omap_hsmmc.c device.
  114. */
  115. #define mmc_slot(host) (host->pdata->slots[host->slot_id])
  116. /*
  117. * MMC Host controller read/write API's
  118. */
  119. #define OMAP_HSMMC_READ(base, reg) \
  120. __raw_readl((base) + OMAP_HSMMC_##reg)
  121. #define OMAP_HSMMC_WRITE(base, reg, val) \
  122. __raw_writel((val), (base) + OMAP_HSMMC_##reg)
  123. struct omap_hsmmc_next {
  124. unsigned int dma_len;
  125. s32 cookie;
  126. };
  127. struct omap_hsmmc_host {
  128. struct device *dev;
  129. struct mmc_host *mmc;
  130. struct mmc_request *mrq;
  131. struct mmc_command *cmd;
  132. struct mmc_data *data;
  133. struct clk *fclk;
  134. struct clk *dbclk;
  135. /*
  136. * vcc == configured supply
  137. * vcc_aux == optional
  138. * - MMC1, supply for DAT4..DAT7
  139. * - MMC2/MMC2, external level shifter voltage supply, for
  140. * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
  141. */
  142. struct regulator *vcc;
  143. struct regulator *vcc_aux;
  144. void __iomem *base;
  145. resource_size_t mapbase;
  146. spinlock_t irq_lock; /* Prevent races with irq handler */
  147. unsigned int dma_len;
  148. unsigned int dma_sg_idx;
  149. unsigned char bus_mode;
  150. unsigned char power_mode;
  151. u32 *buffer;
  152. u32 bytesleft;
  153. int suspended;
  154. int irq;
  155. int use_dma, dma_ch;
  156. int dma_line_tx, dma_line_rx;
  157. int slot_id;
  158. int got_dbclk;
  159. int response_busy;
  160. int context_loss;
  161. int dpm_state;
  162. int vdd;
  163. int protect_card;
  164. int reqs_blocked;
  165. int use_reg;
  166. int req_in_progress;
  167. struct omap_hsmmc_next next_data;
  168. struct omap_mmc_platform_data *pdata;
  169. };
  170. static int omap_hsmmc_card_detect(struct device *dev, int slot)
  171. {
  172. struct omap_mmc_platform_data *mmc = dev->platform_data;
  173. /* NOTE: assumes card detect signal is active-low */
  174. return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
  175. }
  176. static int omap_hsmmc_get_wp(struct device *dev, int slot)
  177. {
  178. struct omap_mmc_platform_data *mmc = dev->platform_data;
  179. /* NOTE: assumes write protect signal is active-high */
  180. return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
  181. }
  182. static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
  183. {
  184. struct omap_mmc_platform_data *mmc = dev->platform_data;
  185. /* NOTE: assumes card detect signal is active-low */
  186. return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
  187. }
  188. #ifdef CONFIG_PM
  189. static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
  190. {
  191. struct omap_mmc_platform_data *mmc = dev->platform_data;
  192. disable_irq(mmc->slots[0].card_detect_irq);
  193. return 0;
  194. }
  195. static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
  196. {
  197. struct omap_mmc_platform_data *mmc = dev->platform_data;
  198. enable_irq(mmc->slots[0].card_detect_irq);
  199. return 0;
  200. }
  201. #else
  202. #define omap_hsmmc_suspend_cdirq NULL
  203. #define omap_hsmmc_resume_cdirq NULL
  204. #endif
  205. #ifdef CONFIG_REGULATOR
  206. static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
  207. int vdd)
  208. {
  209. struct omap_hsmmc_host *host =
  210. platform_get_drvdata(to_platform_device(dev));
  211. int ret = 0;
  212. /*
  213. * If we don't see a Vcc regulator, assume it's a fixed
  214. * voltage always-on regulator.
  215. */
  216. if (!host->vcc)
  217. return 0;
  218. if (mmc_slot(host).before_set_reg)
  219. mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
  220. /*
  221. * Assume Vcc regulator is used only to power the card ... OMAP
  222. * VDDS is used to power the pins, optionally with a transceiver to
  223. * support cards using voltages other than VDDS (1.8V nominal). When a
  224. * transceiver is used, DAT3..7 are muxed as transceiver control pins.
  225. *
  226. * In some cases this regulator won't support enable/disable;
  227. * e.g. it's a fixed rail for a WLAN chip.
  228. *
  229. * In other cases vcc_aux switches interface power. Example, for
  230. * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
  231. * chips/cards need an interface voltage rail too.
  232. */
  233. if (power_on) {
  234. ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
  235. /* Enable interface voltage rail, if needed */
  236. if (ret == 0 && host->vcc_aux) {
  237. ret = regulator_enable(host->vcc_aux);
  238. if (ret < 0)
  239. ret = mmc_regulator_set_ocr(host->mmc,
  240. host->vcc, 0);
  241. }
  242. } else {
  243. /* Shut down the rail */
  244. if (host->vcc_aux)
  245. ret = regulator_disable(host->vcc_aux);
  246. if (!ret) {
  247. /* Then proceed to shut down the local regulator */
  248. ret = mmc_regulator_set_ocr(host->mmc,
  249. host->vcc, 0);
  250. }
  251. }
  252. if (mmc_slot(host).after_set_reg)
  253. mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
  254. return ret;
  255. }
  256. static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
  257. {
  258. struct regulator *reg;
  259. int ocr_value = 0;
  260. mmc_slot(host).set_power = omap_hsmmc_set_power;
  261. reg = regulator_get(host->dev, "vmmc");
  262. if (IS_ERR(reg)) {
  263. dev_dbg(host->dev, "vmmc regulator missing\n");
  264. } else {
  265. host->vcc = reg;
  266. ocr_value = mmc_regulator_get_ocrmask(reg);
  267. if (!mmc_slot(host).ocr_mask) {
  268. mmc_slot(host).ocr_mask = ocr_value;
  269. } else {
  270. if (!(mmc_slot(host).ocr_mask & ocr_value)) {
  271. pr_err("MMC ocrmask %x is not supported\n",
  272. mmc_slot(host).ocr_mask);
  273. mmc_slot(host).ocr_mask = 0;
  274. return -EINVAL;
  275. }
  276. }
  277. /* Allow an aux regulator */
  278. reg = regulator_get(host->dev, "vmmc_aux");
  279. host->vcc_aux = IS_ERR(reg) ? NULL : reg;
  280. /* For eMMC do not power off when not in sleep state */
  281. if (mmc_slot(host).no_regulator_off_init)
  282. return 0;
  283. /*
  284. * UGLY HACK: workaround regulator framework bugs.
  285. * When the bootloader leaves a supply active, it's
  286. * initialized with zero usecount ... and we can't
  287. * disable it without first enabling it. Until the
  288. * framework is fixed, we need a workaround like this
  289. * (which is safe for MMC, but not in general).
  290. */
  291. if (regulator_is_enabled(host->vcc) > 0 ||
  292. (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
  293. int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
  294. mmc_slot(host).set_power(host->dev, host->slot_id,
  295. 1, vdd);
  296. mmc_slot(host).set_power(host->dev, host->slot_id,
  297. 0, 0);
  298. }
  299. }
  300. return 0;
  301. }
  302. static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
  303. {
  304. regulator_put(host->vcc);
  305. regulator_put(host->vcc_aux);
  306. mmc_slot(host).set_power = NULL;
  307. }
  308. static inline int omap_hsmmc_have_reg(void)
  309. {
  310. return 1;
  311. }
  312. #else
  313. static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
  314. {
  315. return -EINVAL;
  316. }
  317. static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
  318. {
  319. }
  320. static inline int omap_hsmmc_have_reg(void)
  321. {
  322. return 0;
  323. }
  324. #endif
  325. static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
  326. {
  327. int ret;
  328. if (gpio_is_valid(pdata->slots[0].switch_pin)) {
  329. if (pdata->slots[0].cover)
  330. pdata->slots[0].get_cover_state =
  331. omap_hsmmc_get_cover_state;
  332. else
  333. pdata->slots[0].card_detect = omap_hsmmc_card_detect;
  334. pdata->slots[0].card_detect_irq =
  335. gpio_to_irq(pdata->slots[0].switch_pin);
  336. ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
  337. if (ret)
  338. return ret;
  339. ret = gpio_direction_input(pdata->slots[0].switch_pin);
  340. if (ret)
  341. goto err_free_sp;
  342. } else
  343. pdata->slots[0].switch_pin = -EINVAL;
  344. if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
  345. pdata->slots[0].get_ro = omap_hsmmc_get_wp;
  346. ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
  347. if (ret)
  348. goto err_free_cd;
  349. ret = gpio_direction_input(pdata->slots[0].gpio_wp);
  350. if (ret)
  351. goto err_free_wp;
  352. } else
  353. pdata->slots[0].gpio_wp = -EINVAL;
  354. return 0;
  355. err_free_wp:
  356. gpio_free(pdata->slots[0].gpio_wp);
  357. err_free_cd:
  358. if (gpio_is_valid(pdata->slots[0].switch_pin))
  359. err_free_sp:
  360. gpio_free(pdata->slots[0].switch_pin);
  361. return ret;
  362. }
  363. static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
  364. {
  365. if (gpio_is_valid(pdata->slots[0].gpio_wp))
  366. gpio_free(pdata->slots[0].gpio_wp);
  367. if (gpio_is_valid(pdata->slots[0].switch_pin))
  368. gpio_free(pdata->slots[0].switch_pin);
  369. }
  370. /*
  371. * Start clock to the card
  372. */
  373. static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
  374. {
  375. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  376. OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
  377. }
  378. /*
  379. * Stop clock to the card
  380. */
  381. static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
  382. {
  383. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  384. OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
  385. if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
  386. dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
  387. }
  388. static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
  389. struct mmc_command *cmd)
  390. {
  391. unsigned int irq_mask;
  392. if (host->use_dma)
  393. irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
  394. else
  395. irq_mask = INT_EN_MASK;
  396. /* Disable timeout for erases */
  397. if (cmd->opcode == MMC_ERASE)
  398. irq_mask &= ~DTO_ENABLE;
  399. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  400. OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
  401. OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
  402. }
  403. static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
  404. {
  405. OMAP_HSMMC_WRITE(host->base, ISE, 0);
  406. OMAP_HSMMC_WRITE(host->base, IE, 0);
  407. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  408. }
  409. /* Calculate divisor for the given clock frequency */
  410. static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
  411. {
  412. u16 dsor = 0;
  413. if (ios->clock) {
  414. dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
  415. if (dsor > 250)
  416. dsor = 250;
  417. }
  418. return dsor;
  419. }
  420. static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
  421. {
  422. struct mmc_ios *ios = &host->mmc->ios;
  423. unsigned long regval;
  424. unsigned long timeout;
  425. dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
  426. omap_hsmmc_stop_clock(host);
  427. regval = OMAP_HSMMC_READ(host->base, SYSCTL);
  428. regval = regval & ~(CLKD_MASK | DTO_MASK);
  429. regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
  430. OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
  431. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  432. OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
  433. /* Wait till the ICS bit is set */
  434. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  435. while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
  436. && time_before(jiffies, timeout))
  437. cpu_relax();
  438. omap_hsmmc_start_clock(host);
  439. }
  440. static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
  441. {
  442. struct mmc_ios *ios = &host->mmc->ios;
  443. u32 con;
  444. con = OMAP_HSMMC_READ(host->base, CON);
  445. switch (ios->bus_width) {
  446. case MMC_BUS_WIDTH_8:
  447. OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
  448. break;
  449. case MMC_BUS_WIDTH_4:
  450. OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
  451. OMAP_HSMMC_WRITE(host->base, HCTL,
  452. OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
  453. break;
  454. case MMC_BUS_WIDTH_1:
  455. OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
  456. OMAP_HSMMC_WRITE(host->base, HCTL,
  457. OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
  458. break;
  459. }
  460. }
  461. static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
  462. {
  463. struct mmc_ios *ios = &host->mmc->ios;
  464. u32 con;
  465. con = OMAP_HSMMC_READ(host->base, CON);
  466. if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
  467. OMAP_HSMMC_WRITE(host->base, CON, con | OD);
  468. else
  469. OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
  470. }
  471. #ifdef CONFIG_PM
  472. /*
  473. * Restore the MMC host context, if it was lost as result of a
  474. * power state change.
  475. */
  476. static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
  477. {
  478. struct mmc_ios *ios = &host->mmc->ios;
  479. struct omap_mmc_platform_data *pdata = host->pdata;
  480. int context_loss = 0;
  481. u32 hctl, capa;
  482. unsigned long timeout;
  483. if (pdata->get_context_loss_count) {
  484. context_loss = pdata->get_context_loss_count(host->dev);
  485. if (context_loss < 0)
  486. return 1;
  487. }
  488. dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
  489. context_loss == host->context_loss ? "not " : "");
  490. if (host->context_loss == context_loss)
  491. return 1;
  492. /* Wait for hardware reset */
  493. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  494. while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
  495. && time_before(jiffies, timeout))
  496. ;
  497. /* Do software reset */
  498. OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
  499. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  500. while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
  501. && time_before(jiffies, timeout))
  502. ;
  503. OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
  504. OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
  505. if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
  506. if (host->power_mode != MMC_POWER_OFF &&
  507. (1 << ios->vdd) <= MMC_VDD_23_24)
  508. hctl = SDVS18;
  509. else
  510. hctl = SDVS30;
  511. capa = VS30 | VS18;
  512. } else {
  513. hctl = SDVS18;
  514. capa = VS18;
  515. }
  516. OMAP_HSMMC_WRITE(host->base, HCTL,
  517. OMAP_HSMMC_READ(host->base, HCTL) | hctl);
  518. OMAP_HSMMC_WRITE(host->base, CAPA,
  519. OMAP_HSMMC_READ(host->base, CAPA) | capa);
  520. OMAP_HSMMC_WRITE(host->base, HCTL,
  521. OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
  522. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  523. while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
  524. && time_before(jiffies, timeout))
  525. ;
  526. omap_hsmmc_disable_irq(host);
  527. /* Do not initialize card-specific things if the power is off */
  528. if (host->power_mode == MMC_POWER_OFF)
  529. goto out;
  530. omap_hsmmc_set_bus_width(host);
  531. omap_hsmmc_set_clock(host);
  532. omap_hsmmc_set_bus_mode(host);
  533. out:
  534. host->context_loss = context_loss;
  535. dev_dbg(mmc_dev(host->mmc), "context is restored\n");
  536. return 0;
  537. }
  538. /*
  539. * Save the MMC host context (store the number of power state changes so far).
  540. */
  541. static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
  542. {
  543. struct omap_mmc_platform_data *pdata = host->pdata;
  544. int context_loss;
  545. if (pdata->get_context_loss_count) {
  546. context_loss = pdata->get_context_loss_count(host->dev);
  547. if (context_loss < 0)
  548. return;
  549. host->context_loss = context_loss;
  550. }
  551. }
  552. #else
  553. static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
  554. {
  555. return 0;
  556. }
  557. static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
  558. {
  559. }
  560. #endif
  561. /*
  562. * Send init stream sequence to card
  563. * before sending IDLE command
  564. */
  565. static void send_init_stream(struct omap_hsmmc_host *host)
  566. {
  567. int reg = 0;
  568. unsigned long timeout;
  569. if (host->protect_card)
  570. return;
  571. disable_irq(host->irq);
  572. OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
  573. OMAP_HSMMC_WRITE(host->base, CON,
  574. OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
  575. OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
  576. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  577. while ((reg != CC) && time_before(jiffies, timeout))
  578. reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
  579. OMAP_HSMMC_WRITE(host->base, CON,
  580. OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
  581. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  582. OMAP_HSMMC_READ(host->base, STAT);
  583. enable_irq(host->irq);
  584. }
  585. static inline
  586. int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
  587. {
  588. int r = 1;
  589. if (mmc_slot(host).get_cover_state)
  590. r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
  591. return r;
  592. }
  593. static ssize_t
  594. omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
  595. char *buf)
  596. {
  597. struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
  598. struct omap_hsmmc_host *host = mmc_priv(mmc);
  599. return sprintf(buf, "%s\n",
  600. omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
  601. }
  602. static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
  603. static ssize_t
  604. omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
  605. char *buf)
  606. {
  607. struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
  608. struct omap_hsmmc_host *host = mmc_priv(mmc);
  609. return sprintf(buf, "%s\n", mmc_slot(host).name);
  610. }
  611. static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
  612. /*
  613. * Configure the response type and send the cmd.
  614. */
  615. static void
  616. omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
  617. struct mmc_data *data)
  618. {
  619. int cmdreg = 0, resptype = 0, cmdtype = 0;
  620. dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
  621. mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
  622. host->cmd = cmd;
  623. omap_hsmmc_enable_irq(host, cmd);
  624. host->response_busy = 0;
  625. if (cmd->flags & MMC_RSP_PRESENT) {
  626. if (cmd->flags & MMC_RSP_136)
  627. resptype = 1;
  628. else if (cmd->flags & MMC_RSP_BUSY) {
  629. resptype = 3;
  630. host->response_busy = 1;
  631. } else
  632. resptype = 2;
  633. }
  634. /*
  635. * Unlike OMAP1 controller, the cmdtype does not seem to be based on
  636. * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
  637. * a val of 0x3, rest 0x0.
  638. */
  639. if (cmd == host->mrq->stop)
  640. cmdtype = 0x3;
  641. cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
  642. if (data) {
  643. cmdreg |= DP_SELECT | MSBS | BCE;
  644. if (data->flags & MMC_DATA_READ)
  645. cmdreg |= DDIR;
  646. else
  647. cmdreg &= ~(DDIR);
  648. }
  649. if (host->use_dma)
  650. cmdreg |= DMA_EN;
  651. host->req_in_progress = 1;
  652. OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
  653. OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
  654. }
  655. static int
  656. omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
  657. {
  658. if (data->flags & MMC_DATA_WRITE)
  659. return DMA_TO_DEVICE;
  660. else
  661. return DMA_FROM_DEVICE;
  662. }
  663. static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
  664. {
  665. int dma_ch;
  666. spin_lock(&host->irq_lock);
  667. host->req_in_progress = 0;
  668. dma_ch = host->dma_ch;
  669. spin_unlock(&host->irq_lock);
  670. omap_hsmmc_disable_irq(host);
  671. /* Do not complete the request if DMA is still in progress */
  672. if (mrq->data && host->use_dma && dma_ch != -1)
  673. return;
  674. host->mrq = NULL;
  675. mmc_request_done(host->mmc, mrq);
  676. }
  677. /*
  678. * Notify the transfer complete to MMC core
  679. */
  680. static void
  681. omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
  682. {
  683. if (!data) {
  684. struct mmc_request *mrq = host->mrq;
  685. /* TC before CC from CMD6 - don't know why, but it happens */
  686. if (host->cmd && host->cmd->opcode == 6 &&
  687. host->response_busy) {
  688. host->response_busy = 0;
  689. return;
  690. }
  691. omap_hsmmc_request_done(host, mrq);
  692. return;
  693. }
  694. host->data = NULL;
  695. if (!data->error)
  696. data->bytes_xfered += data->blocks * (data->blksz);
  697. else
  698. data->bytes_xfered = 0;
  699. if (!data->stop) {
  700. omap_hsmmc_request_done(host, data->mrq);
  701. return;
  702. }
  703. omap_hsmmc_start_command(host, data->stop, NULL);
  704. }
  705. /*
  706. * Notify the core about command completion
  707. */
  708. static void
  709. omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
  710. {
  711. host->cmd = NULL;
  712. if (cmd->flags & MMC_RSP_PRESENT) {
  713. if (cmd->flags & MMC_RSP_136) {
  714. /* response type 2 */
  715. cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
  716. cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
  717. cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
  718. cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
  719. } else {
  720. /* response types 1, 1b, 3, 4, 5, 6 */
  721. cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
  722. }
  723. }
  724. if ((host->data == NULL && !host->response_busy) || cmd->error)
  725. omap_hsmmc_request_done(host, cmd->mrq);
  726. }
  727. /*
  728. * DMA clean up for command errors
  729. */
  730. static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
  731. {
  732. int dma_ch;
  733. host->data->error = errno;
  734. spin_lock(&host->irq_lock);
  735. dma_ch = host->dma_ch;
  736. host->dma_ch = -1;
  737. spin_unlock(&host->irq_lock);
  738. if (host->use_dma && dma_ch != -1) {
  739. dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
  740. host->data->sg_len,
  741. omap_hsmmc_get_dma_dir(host, host->data));
  742. omap_free_dma(dma_ch);
  743. host->data->host_cookie = 0;
  744. }
  745. host->data = NULL;
  746. }
  747. /*
  748. * Readable error output
  749. */
  750. #ifdef CONFIG_MMC_DEBUG
  751. static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
  752. {
  753. /* --- means reserved bit without definition at documentation */
  754. static const char *omap_hsmmc_status_bits[] = {
  755. "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
  756. "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
  757. "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
  758. "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
  759. };
  760. char res[256];
  761. char *buf = res;
  762. int len, i;
  763. len = sprintf(buf, "MMC IRQ 0x%x :", status);
  764. buf += len;
  765. for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
  766. if (status & (1 << i)) {
  767. len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
  768. buf += len;
  769. }
  770. dev_dbg(mmc_dev(host->mmc), "%s\n", res);
  771. }
  772. #else
  773. static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
  774. u32 status)
  775. {
  776. }
  777. #endif /* CONFIG_MMC_DEBUG */
  778. /*
  779. * MMC controller internal state machines reset
  780. *
  781. * Used to reset command or data internal state machines, using respectively
  782. * SRC or SRD bit of SYSCTL register
  783. * Can be called from interrupt context
  784. */
  785. static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
  786. unsigned long bit)
  787. {
  788. unsigned long i = 0;
  789. unsigned long limit = (loops_per_jiffy *
  790. msecs_to_jiffies(MMC_TIMEOUT_MS));
  791. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  792. OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
  793. /*
  794. * OMAP4 ES2 and greater has an updated reset logic.
  795. * Monitor a 0->1 transition first
  796. */
  797. if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
  798. while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
  799. && (i++ < limit))
  800. cpu_relax();
  801. }
  802. i = 0;
  803. while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
  804. (i++ < limit))
  805. cpu_relax();
  806. if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
  807. dev_err(mmc_dev(host->mmc),
  808. "Timeout waiting on controller reset in %s\n",
  809. __func__);
  810. }
  811. static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
  812. {
  813. struct mmc_data *data;
  814. int end_cmd = 0, end_trans = 0;
  815. if (!host->req_in_progress) {
  816. do {
  817. OMAP_HSMMC_WRITE(host->base, STAT, status);
  818. /* Flush posted write */
  819. status = OMAP_HSMMC_READ(host->base, STAT);
  820. } while (status & INT_EN_MASK);
  821. return;
  822. }
  823. data = host->data;
  824. dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
  825. if (status & ERR) {
  826. omap_hsmmc_dbg_report_irq(host, status);
  827. if ((status & CMD_TIMEOUT) ||
  828. (status & CMD_CRC)) {
  829. if (host->cmd) {
  830. if (status & CMD_TIMEOUT) {
  831. omap_hsmmc_reset_controller_fsm(host,
  832. SRC);
  833. host->cmd->error = -ETIMEDOUT;
  834. } else {
  835. host->cmd->error = -EILSEQ;
  836. }
  837. end_cmd = 1;
  838. }
  839. if (host->data || host->response_busy) {
  840. if (host->data)
  841. omap_hsmmc_dma_cleanup(host,
  842. -ETIMEDOUT);
  843. host->response_busy = 0;
  844. omap_hsmmc_reset_controller_fsm(host, SRD);
  845. }
  846. }
  847. if ((status & DATA_TIMEOUT) ||
  848. (status & DATA_CRC)) {
  849. if (host->data || host->response_busy) {
  850. int err = (status & DATA_TIMEOUT) ?
  851. -ETIMEDOUT : -EILSEQ;
  852. if (host->data)
  853. omap_hsmmc_dma_cleanup(host, err);
  854. else
  855. host->mrq->cmd->error = err;
  856. host->response_busy = 0;
  857. omap_hsmmc_reset_controller_fsm(host, SRD);
  858. end_trans = 1;
  859. }
  860. }
  861. if (status & CARD_ERR) {
  862. dev_dbg(mmc_dev(host->mmc),
  863. "Ignoring card err CMD%d\n", host->cmd->opcode);
  864. if (host->cmd)
  865. end_cmd = 1;
  866. if (host->data)
  867. end_trans = 1;
  868. }
  869. }
  870. OMAP_HSMMC_WRITE(host->base, STAT, status);
  871. if (end_cmd || ((status & CC) && host->cmd))
  872. omap_hsmmc_cmd_done(host, host->cmd);
  873. if ((end_trans || (status & TC)) && host->mrq)
  874. omap_hsmmc_xfer_done(host, data);
  875. }
  876. /*
  877. * MMC controller IRQ handler
  878. */
  879. static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
  880. {
  881. struct omap_hsmmc_host *host = dev_id;
  882. int status;
  883. status = OMAP_HSMMC_READ(host->base, STAT);
  884. do {
  885. omap_hsmmc_do_irq(host, status);
  886. /* Flush posted write */
  887. status = OMAP_HSMMC_READ(host->base, STAT);
  888. } while (status & INT_EN_MASK);
  889. return IRQ_HANDLED;
  890. }
  891. static void set_sd_bus_power(struct omap_hsmmc_host *host)
  892. {
  893. unsigned long i;
  894. OMAP_HSMMC_WRITE(host->base, HCTL,
  895. OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
  896. for (i = 0; i < loops_per_jiffy; i++) {
  897. if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
  898. break;
  899. cpu_relax();
  900. }
  901. }
  902. /*
  903. * Switch MMC interface voltage ... only relevant for MMC1.
  904. *
  905. * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
  906. * The MMC2 transceiver controls are used instead of DAT4..DAT7.
  907. * Some chips, like eMMC ones, use internal transceivers.
  908. */
  909. static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
  910. {
  911. u32 reg_val = 0;
  912. int ret;
  913. /* Disable the clocks */
  914. pm_runtime_put_sync(host->dev);
  915. if (host->got_dbclk)
  916. clk_disable(host->dbclk);
  917. /* Turn the power off */
  918. ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
  919. /* Turn the power ON with given VDD 1.8 or 3.0v */
  920. if (!ret)
  921. ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
  922. vdd);
  923. pm_runtime_get_sync(host->dev);
  924. if (host->got_dbclk)
  925. clk_enable(host->dbclk);
  926. if (ret != 0)
  927. goto err;
  928. OMAP_HSMMC_WRITE(host->base, HCTL,
  929. OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
  930. reg_val = OMAP_HSMMC_READ(host->base, HCTL);
  931. /*
  932. * If a MMC dual voltage card is detected, the set_ios fn calls
  933. * this fn with VDD bit set for 1.8V. Upon card removal from the
  934. * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
  935. *
  936. * Cope with a bit of slop in the range ... per data sheets:
  937. * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
  938. * but recommended values are 1.71V to 1.89V
  939. * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
  940. * but recommended values are 2.7V to 3.3V
  941. *
  942. * Board setup code shouldn't permit anything very out-of-range.
  943. * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
  944. * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
  945. */
  946. if ((1 << vdd) <= MMC_VDD_23_24)
  947. reg_val |= SDVS18;
  948. else
  949. reg_val |= SDVS30;
  950. OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
  951. set_sd_bus_power(host);
  952. return 0;
  953. err:
  954. dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
  955. return ret;
  956. }
  957. /* Protect the card while the cover is open */
  958. static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
  959. {
  960. if (!mmc_slot(host).get_cover_state)
  961. return;
  962. host->reqs_blocked = 0;
  963. if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
  964. if (host->protect_card) {
  965. pr_info("%s: cover is closed, "
  966. "card is now accessible\n",
  967. mmc_hostname(host->mmc));
  968. host->protect_card = 0;
  969. }
  970. } else {
  971. if (!host->protect_card) {
  972. pr_info("%s: cover is open, "
  973. "card is now inaccessible\n",
  974. mmc_hostname(host->mmc));
  975. host->protect_card = 1;
  976. }
  977. }
  978. }
  979. /*
  980. * irq handler to notify the core about card insertion/removal
  981. */
  982. static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
  983. {
  984. struct omap_hsmmc_host *host = dev_id;
  985. struct omap_mmc_slot_data *slot = &mmc_slot(host);
  986. int carddetect;
  987. if (host->suspended)
  988. return IRQ_HANDLED;
  989. sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
  990. if (slot->card_detect)
  991. carddetect = slot->card_detect(host->dev, host->slot_id);
  992. else {
  993. omap_hsmmc_protect_card(host);
  994. carddetect = -ENOSYS;
  995. }
  996. if (carddetect)
  997. mmc_detect_change(host->mmc, (HZ * 200) / 1000);
  998. else
  999. mmc_detect_change(host->mmc, (HZ * 50) / 1000);
  1000. return IRQ_HANDLED;
  1001. }
  1002. static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
  1003. struct mmc_data *data)
  1004. {
  1005. int sync_dev;
  1006. if (data->flags & MMC_DATA_WRITE)
  1007. sync_dev = host->dma_line_tx;
  1008. else
  1009. sync_dev = host->dma_line_rx;
  1010. return sync_dev;
  1011. }
  1012. static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
  1013. struct mmc_data *data,
  1014. struct scatterlist *sgl)
  1015. {
  1016. int blksz, nblk, dma_ch;
  1017. dma_ch = host->dma_ch;
  1018. if (data->flags & MMC_DATA_WRITE) {
  1019. omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
  1020. (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
  1021. omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
  1022. sg_dma_address(sgl), 0, 0);
  1023. } else {
  1024. omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
  1025. (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
  1026. omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
  1027. sg_dma_address(sgl), 0, 0);
  1028. }
  1029. blksz = host->data->blksz;
  1030. nblk = sg_dma_len(sgl) / blksz;
  1031. omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
  1032. blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
  1033. omap_hsmmc_get_dma_sync_dev(host, data),
  1034. !(data->flags & MMC_DATA_WRITE));
  1035. omap_start_dma(dma_ch);
  1036. }
  1037. /*
  1038. * DMA call back function
  1039. */
  1040. static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
  1041. {
  1042. struct omap_hsmmc_host *host = cb_data;
  1043. struct mmc_data *data;
  1044. int dma_ch, req_in_progress;
  1045. if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
  1046. dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
  1047. ch_status);
  1048. return;
  1049. }
  1050. spin_lock(&host->irq_lock);
  1051. if (host->dma_ch < 0) {
  1052. spin_unlock(&host->irq_lock);
  1053. return;
  1054. }
  1055. data = host->mrq->data;
  1056. host->dma_sg_idx++;
  1057. if (host->dma_sg_idx < host->dma_len) {
  1058. /* Fire up the next transfer. */
  1059. omap_hsmmc_config_dma_params(host, data,
  1060. data->sg + host->dma_sg_idx);
  1061. spin_unlock(&host->irq_lock);
  1062. return;
  1063. }
  1064. if (!data->host_cookie)
  1065. dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
  1066. omap_hsmmc_get_dma_dir(host, data));
  1067. req_in_progress = host->req_in_progress;
  1068. dma_ch = host->dma_ch;
  1069. host->dma_ch = -1;
  1070. spin_unlock(&host->irq_lock);
  1071. omap_free_dma(dma_ch);
  1072. /* If DMA has finished after TC, complete the request */
  1073. if (!req_in_progress) {
  1074. struct mmc_request *mrq = host->mrq;
  1075. host->mrq = NULL;
  1076. mmc_request_done(host->mmc, mrq);
  1077. }
  1078. }
  1079. static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
  1080. struct mmc_data *data,
  1081. struct omap_hsmmc_next *next)
  1082. {
  1083. int dma_len;
  1084. if (!next && data->host_cookie &&
  1085. data->host_cookie != host->next_data.cookie) {
  1086. pr_warning("[%s] invalid cookie: data->host_cookie %d"
  1087. " host->next_data.cookie %d\n",
  1088. __func__, data->host_cookie, host->next_data.cookie);
  1089. data->host_cookie = 0;
  1090. }
  1091. /* Check if next job is already prepared */
  1092. if (next ||
  1093. (!next && data->host_cookie != host->next_data.cookie)) {
  1094. dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
  1095. data->sg_len,
  1096. omap_hsmmc_get_dma_dir(host, data));
  1097. } else {
  1098. dma_len = host->next_data.dma_len;
  1099. host->next_data.dma_len = 0;
  1100. }
  1101. if (dma_len == 0)
  1102. return -EINVAL;
  1103. if (next) {
  1104. next->dma_len = dma_len;
  1105. data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
  1106. } else
  1107. host->dma_len = dma_len;
  1108. return 0;
  1109. }
  1110. /*
  1111. * Routine to configure and start DMA for the MMC card
  1112. */
  1113. static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
  1114. struct mmc_request *req)
  1115. {
  1116. int dma_ch = 0, ret = 0, i;
  1117. struct mmc_data *data = req->data;
  1118. /* Sanity check: all the SG entries must be aligned by block size. */
  1119. for (i = 0; i < data->sg_len; i++) {
  1120. struct scatterlist *sgl;
  1121. sgl = data->sg + i;
  1122. if (sgl->length % data->blksz)
  1123. return -EINVAL;
  1124. }
  1125. if ((data->blksz % 4) != 0)
  1126. /* REVISIT: The MMC buffer increments only when MSB is written.
  1127. * Return error for blksz which is non multiple of four.
  1128. */
  1129. return -EINVAL;
  1130. BUG_ON(host->dma_ch != -1);
  1131. ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
  1132. "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
  1133. if (ret != 0) {
  1134. dev_err(mmc_dev(host->mmc),
  1135. "%s: omap_request_dma() failed with %d\n",
  1136. mmc_hostname(host->mmc), ret);
  1137. return ret;
  1138. }
  1139. ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
  1140. if (ret)
  1141. return ret;
  1142. host->dma_ch = dma_ch;
  1143. host->dma_sg_idx = 0;
  1144. omap_hsmmc_config_dma_params(host, data, data->sg);
  1145. return 0;
  1146. }
  1147. static void set_data_timeout(struct omap_hsmmc_host *host,
  1148. unsigned int timeout_ns,
  1149. unsigned int timeout_clks)
  1150. {
  1151. unsigned int timeout, cycle_ns;
  1152. uint32_t reg, clkd, dto = 0;
  1153. reg = OMAP_HSMMC_READ(host->base, SYSCTL);
  1154. clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
  1155. if (clkd == 0)
  1156. clkd = 1;
  1157. cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
  1158. timeout = timeout_ns / cycle_ns;
  1159. timeout += timeout_clks;
  1160. if (timeout) {
  1161. while ((timeout & 0x80000000) == 0) {
  1162. dto += 1;
  1163. timeout <<= 1;
  1164. }
  1165. dto = 31 - dto;
  1166. timeout <<= 1;
  1167. if (timeout && dto)
  1168. dto += 1;
  1169. if (dto >= 13)
  1170. dto -= 13;
  1171. else
  1172. dto = 0;
  1173. if (dto > 14)
  1174. dto = 14;
  1175. }
  1176. reg &= ~DTO_MASK;
  1177. reg |= dto << DTO_SHIFT;
  1178. OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
  1179. }
  1180. /*
  1181. * Configure block length for MMC/SD cards and initiate the transfer.
  1182. */
  1183. static int
  1184. omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
  1185. {
  1186. int ret;
  1187. host->data = req->data;
  1188. if (req->data == NULL) {
  1189. OMAP_HSMMC_WRITE(host->base, BLK, 0);
  1190. /*
  1191. * Set an arbitrary 100ms data timeout for commands with
  1192. * busy signal.
  1193. */
  1194. if (req->cmd->flags & MMC_RSP_BUSY)
  1195. set_data_timeout(host, 100000000U, 0);
  1196. return 0;
  1197. }
  1198. OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
  1199. | (req->data->blocks << 16));
  1200. set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
  1201. if (host->use_dma) {
  1202. ret = omap_hsmmc_start_dma_transfer(host, req);
  1203. if (ret != 0) {
  1204. dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
  1205. return ret;
  1206. }
  1207. }
  1208. return 0;
  1209. }
  1210. static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
  1211. int err)
  1212. {
  1213. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1214. struct mmc_data *data = mrq->data;
  1215. if (host->use_dma) {
  1216. if (data->host_cookie)
  1217. dma_unmap_sg(mmc_dev(host->mmc), data->sg,
  1218. data->sg_len,
  1219. omap_hsmmc_get_dma_dir(host, data));
  1220. data->host_cookie = 0;
  1221. }
  1222. }
  1223. static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
  1224. bool is_first_req)
  1225. {
  1226. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1227. if (mrq->data->host_cookie) {
  1228. mrq->data->host_cookie = 0;
  1229. return ;
  1230. }
  1231. if (host->use_dma)
  1232. if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
  1233. &host->next_data))
  1234. mrq->data->host_cookie = 0;
  1235. }
  1236. /*
  1237. * Request function. for read/write operation
  1238. */
  1239. static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
  1240. {
  1241. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1242. int err;
  1243. BUG_ON(host->req_in_progress);
  1244. BUG_ON(host->dma_ch != -1);
  1245. if (host->protect_card) {
  1246. if (host->reqs_blocked < 3) {
  1247. /*
  1248. * Ensure the controller is left in a consistent
  1249. * state by resetting the command and data state
  1250. * machines.
  1251. */
  1252. omap_hsmmc_reset_controller_fsm(host, SRD);
  1253. omap_hsmmc_reset_controller_fsm(host, SRC);
  1254. host->reqs_blocked += 1;
  1255. }
  1256. req->cmd->error = -EBADF;
  1257. if (req->data)
  1258. req->data->error = -EBADF;
  1259. req->cmd->retries = 0;
  1260. mmc_request_done(mmc, req);
  1261. return;
  1262. } else if (host->reqs_blocked)
  1263. host->reqs_blocked = 0;
  1264. WARN_ON(host->mrq != NULL);
  1265. host->mrq = req;
  1266. err = omap_hsmmc_prepare_data(host, req);
  1267. if (err) {
  1268. req->cmd->error = err;
  1269. if (req->data)
  1270. req->data->error = err;
  1271. host->mrq = NULL;
  1272. mmc_request_done(mmc, req);
  1273. return;
  1274. }
  1275. omap_hsmmc_start_command(host, req->cmd, req->data);
  1276. }
  1277. /* Routine to configure clock values. Exposed API to core */
  1278. static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  1279. {
  1280. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1281. int do_send_init_stream = 0;
  1282. pm_runtime_get_sync(host->dev);
  1283. if (ios->power_mode != host->power_mode) {
  1284. switch (ios->power_mode) {
  1285. case MMC_POWER_OFF:
  1286. mmc_slot(host).set_power(host->dev, host->slot_id,
  1287. 0, 0);
  1288. host->vdd = 0;
  1289. break;
  1290. case MMC_POWER_UP:
  1291. mmc_slot(host).set_power(host->dev, host->slot_id,
  1292. 1, ios->vdd);
  1293. host->vdd = ios->vdd;
  1294. break;
  1295. case MMC_POWER_ON:
  1296. do_send_init_stream = 1;
  1297. break;
  1298. }
  1299. host->power_mode = ios->power_mode;
  1300. }
  1301. /* FIXME: set registers based only on changes to ios */
  1302. omap_hsmmc_set_bus_width(host);
  1303. if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
  1304. /* Only MMC1 can interface at 3V without some flavor
  1305. * of external transceiver; but they all handle 1.8V.
  1306. */
  1307. if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
  1308. (ios->vdd == DUAL_VOLT_OCR_BIT)) {
  1309. /*
  1310. * The mmc_select_voltage fn of the core does
  1311. * not seem to set the power_mode to
  1312. * MMC_POWER_UP upon recalculating the voltage.
  1313. * vdd 1.8v.
  1314. */
  1315. if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
  1316. dev_dbg(mmc_dev(host->mmc),
  1317. "Switch operation failed\n");
  1318. }
  1319. }
  1320. omap_hsmmc_set_clock(host);
  1321. if (do_send_init_stream)
  1322. send_init_stream(host);
  1323. omap_hsmmc_set_bus_mode(host);
  1324. pm_runtime_put_autosuspend(host->dev);
  1325. }
  1326. static int omap_hsmmc_get_cd(struct mmc_host *mmc)
  1327. {
  1328. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1329. if (!mmc_slot(host).card_detect)
  1330. return -ENOSYS;
  1331. return mmc_slot(host).card_detect(host->dev, host->slot_id);
  1332. }
  1333. static int omap_hsmmc_get_ro(struct mmc_host *mmc)
  1334. {
  1335. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1336. if (!mmc_slot(host).get_ro)
  1337. return -ENOSYS;
  1338. return mmc_slot(host).get_ro(host->dev, 0);
  1339. }
  1340. static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
  1341. {
  1342. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1343. if (mmc_slot(host).init_card)
  1344. mmc_slot(host).init_card(card);
  1345. }
  1346. static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
  1347. {
  1348. u32 hctl, capa, value;
  1349. /* Only MMC1 supports 3.0V */
  1350. if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
  1351. hctl = SDVS30;
  1352. capa = VS30 | VS18;
  1353. } else {
  1354. hctl = SDVS18;
  1355. capa = VS18;
  1356. }
  1357. value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
  1358. OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
  1359. value = OMAP_HSMMC_READ(host->base, CAPA);
  1360. OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
  1361. /* Set the controller to AUTO IDLE mode */
  1362. value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
  1363. OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
  1364. /* Set SD bus power bit */
  1365. set_sd_bus_power(host);
  1366. }
  1367. static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
  1368. {
  1369. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1370. pm_runtime_get_sync(host->dev);
  1371. return 0;
  1372. }
  1373. static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
  1374. {
  1375. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1376. pm_runtime_mark_last_busy(host->dev);
  1377. pm_runtime_put_autosuspend(host->dev);
  1378. return 0;
  1379. }
  1380. static const struct mmc_host_ops omap_hsmmc_ops = {
  1381. .enable = omap_hsmmc_enable_fclk,
  1382. .disable = omap_hsmmc_disable_fclk,
  1383. .post_req = omap_hsmmc_post_req,
  1384. .pre_req = omap_hsmmc_pre_req,
  1385. .request = omap_hsmmc_request,
  1386. .set_ios = omap_hsmmc_set_ios,
  1387. .get_cd = omap_hsmmc_get_cd,
  1388. .get_ro = omap_hsmmc_get_ro,
  1389. .init_card = omap_hsmmc_init_card,
  1390. /* NYET -- enable_sdio_irq */
  1391. };
  1392. #ifdef CONFIG_DEBUG_FS
  1393. static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
  1394. {
  1395. struct mmc_host *mmc = s->private;
  1396. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1397. int context_loss = 0;
  1398. if (host->pdata->get_context_loss_count)
  1399. context_loss = host->pdata->get_context_loss_count(host->dev);
  1400. seq_printf(s, "mmc%d:\n"
  1401. " enabled:\t%d\n"
  1402. " dpm_state:\t%d\n"
  1403. " nesting_cnt:\t%d\n"
  1404. " ctx_loss:\t%d:%d\n"
  1405. "\nregs:\n",
  1406. mmc->index, mmc->enabled ? 1 : 0,
  1407. host->dpm_state, mmc->nesting_cnt,
  1408. host->context_loss, context_loss);
  1409. if (host->suspended) {
  1410. seq_printf(s, "host suspended, can't read registers\n");
  1411. return 0;
  1412. }
  1413. pm_runtime_get_sync(host->dev);
  1414. seq_printf(s, "SYSCONFIG:\t0x%08x\n",
  1415. OMAP_HSMMC_READ(host->base, SYSCONFIG));
  1416. seq_printf(s, "CON:\t\t0x%08x\n",
  1417. OMAP_HSMMC_READ(host->base, CON));
  1418. seq_printf(s, "HCTL:\t\t0x%08x\n",
  1419. OMAP_HSMMC_READ(host->base, HCTL));
  1420. seq_printf(s, "SYSCTL:\t\t0x%08x\n",
  1421. OMAP_HSMMC_READ(host->base, SYSCTL));
  1422. seq_printf(s, "IE:\t\t0x%08x\n",
  1423. OMAP_HSMMC_READ(host->base, IE));
  1424. seq_printf(s, "ISE:\t\t0x%08x\n",
  1425. OMAP_HSMMC_READ(host->base, ISE));
  1426. seq_printf(s, "CAPA:\t\t0x%08x\n",
  1427. OMAP_HSMMC_READ(host->base, CAPA));
  1428. pm_runtime_mark_last_busy(host->dev);
  1429. pm_runtime_put_autosuspend(host->dev);
  1430. return 0;
  1431. }
  1432. static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
  1433. {
  1434. return single_open(file, omap_hsmmc_regs_show, inode->i_private);
  1435. }
  1436. static const struct file_operations mmc_regs_fops = {
  1437. .open = omap_hsmmc_regs_open,
  1438. .read = seq_read,
  1439. .llseek = seq_lseek,
  1440. .release = single_release,
  1441. };
  1442. static void omap_hsmmc_debugfs(struct mmc_host *mmc)
  1443. {
  1444. if (mmc->debugfs_root)
  1445. debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
  1446. mmc, &mmc_regs_fops);
  1447. }
  1448. #else
  1449. static void omap_hsmmc_debugfs(struct mmc_host *mmc)
  1450. {
  1451. }
  1452. #endif
  1453. static int __init omap_hsmmc_probe(struct platform_device *pdev)
  1454. {
  1455. struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
  1456. struct mmc_host *mmc;
  1457. struct omap_hsmmc_host *host = NULL;
  1458. struct resource *res;
  1459. int ret, irq;
  1460. if (pdata == NULL) {
  1461. dev_err(&pdev->dev, "Platform Data is missing\n");
  1462. return -ENXIO;
  1463. }
  1464. if (pdata->nr_slots == 0) {
  1465. dev_err(&pdev->dev, "No Slots\n");
  1466. return -ENXIO;
  1467. }
  1468. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1469. irq = platform_get_irq(pdev, 0);
  1470. if (res == NULL || irq < 0)
  1471. return -ENXIO;
  1472. res->start += pdata->reg_offset;
  1473. res->end += pdata->reg_offset;
  1474. res = request_mem_region(res->start, resource_size(res), pdev->name);
  1475. if (res == NULL)
  1476. return -EBUSY;
  1477. ret = omap_hsmmc_gpio_init(pdata);
  1478. if (ret)
  1479. goto err;
  1480. mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
  1481. if (!mmc) {
  1482. ret = -ENOMEM;
  1483. goto err_alloc;
  1484. }
  1485. host = mmc_priv(mmc);
  1486. host->mmc = mmc;
  1487. host->pdata = pdata;
  1488. host->dev = &pdev->dev;
  1489. host->use_dma = 1;
  1490. host->dev->dma_mask = &pdata->dma_mask;
  1491. host->dma_ch = -1;
  1492. host->irq = irq;
  1493. host->slot_id = 0;
  1494. host->mapbase = res->start;
  1495. host->base = ioremap(host->mapbase, SZ_4K);
  1496. host->power_mode = MMC_POWER_OFF;
  1497. host->next_data.cookie = 1;
  1498. platform_set_drvdata(pdev, host);
  1499. mmc->ops = &omap_hsmmc_ops;
  1500. /*
  1501. * If regulator_disable can only put vcc_aux to sleep then there is
  1502. * no off state.
  1503. */
  1504. if (mmc_slot(host).vcc_aux_disable_is_sleep)
  1505. mmc_slot(host).no_off = 1;
  1506. mmc->f_min = OMAP_MMC_MIN_CLOCK;
  1507. if (pdata->max_freq > 0)
  1508. mmc->f_max = pdata->max_freq;
  1509. else
  1510. mmc->f_max = OMAP_MMC_MAX_CLOCK;
  1511. spin_lock_init(&host->irq_lock);
  1512. host->fclk = clk_get(&pdev->dev, "fck");
  1513. if (IS_ERR(host->fclk)) {
  1514. ret = PTR_ERR(host->fclk);
  1515. host->fclk = NULL;
  1516. goto err1;
  1517. }
  1518. omap_hsmmc_context_save(host);
  1519. mmc->caps |= MMC_CAP_DISABLE;
  1520. if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
  1521. dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
  1522. mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
  1523. }
  1524. pm_runtime_enable(host->dev);
  1525. pm_runtime_get_sync(host->dev);
  1526. pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
  1527. pm_runtime_use_autosuspend(host->dev);
  1528. if (cpu_is_omap2430()) {
  1529. host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
  1530. /*
  1531. * MMC can still work without debounce clock.
  1532. */
  1533. if (IS_ERR(host->dbclk))
  1534. dev_warn(mmc_dev(host->mmc),
  1535. "Failed to get debounce clock\n");
  1536. else
  1537. host->got_dbclk = 1;
  1538. if (host->got_dbclk)
  1539. if (clk_enable(host->dbclk) != 0)
  1540. dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
  1541. " clk failed\n");
  1542. }
  1543. /* Since we do only SG emulation, we can have as many segs
  1544. * as we want. */
  1545. mmc->max_segs = 1024;
  1546. mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
  1547. mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
  1548. mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
  1549. mmc->max_seg_size = mmc->max_req_size;
  1550. mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
  1551. MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
  1552. mmc->caps |= mmc_slot(host).caps;
  1553. if (mmc->caps & MMC_CAP_8_BIT_DATA)
  1554. mmc->caps |= MMC_CAP_4_BIT_DATA;
  1555. if (mmc_slot(host).nonremovable)
  1556. mmc->caps |= MMC_CAP_NONREMOVABLE;
  1557. mmc->pm_caps = mmc_slot(host).pm_caps;
  1558. omap_hsmmc_conf_bus_power(host);
  1559. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
  1560. if (!res) {
  1561. dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
  1562. goto err_irq;
  1563. }
  1564. host->dma_line_tx = res->start;
  1565. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
  1566. if (!res) {
  1567. dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
  1568. goto err_irq;
  1569. }
  1570. host->dma_line_rx = res->start;
  1571. /* Request IRQ for MMC operations */
  1572. ret = request_irq(host->irq, omap_hsmmc_irq, 0,
  1573. mmc_hostname(mmc), host);
  1574. if (ret) {
  1575. dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
  1576. goto err_irq;
  1577. }
  1578. if (pdata->init != NULL) {
  1579. if (pdata->init(&pdev->dev) != 0) {
  1580. dev_dbg(mmc_dev(host->mmc),
  1581. "Unable to configure MMC IRQs\n");
  1582. goto err_irq_cd_init;
  1583. }
  1584. }
  1585. if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
  1586. ret = omap_hsmmc_reg_get(host);
  1587. if (ret)
  1588. goto err_reg;
  1589. host->use_reg = 1;
  1590. }
  1591. mmc->ocr_avail = mmc_slot(host).ocr_mask;
  1592. /* Request IRQ for card detect */
  1593. if ((mmc_slot(host).card_detect_irq)) {
  1594. ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
  1595. NULL,
  1596. omap_hsmmc_detect,
  1597. IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
  1598. mmc_hostname(mmc), host);
  1599. if (ret) {
  1600. dev_dbg(mmc_dev(host->mmc),
  1601. "Unable to grab MMC CD IRQ\n");
  1602. goto err_irq_cd;
  1603. }
  1604. pdata->suspend = omap_hsmmc_suspend_cdirq;
  1605. pdata->resume = omap_hsmmc_resume_cdirq;
  1606. }
  1607. omap_hsmmc_disable_irq(host);
  1608. omap_hsmmc_protect_card(host);
  1609. mmc_add_host(mmc);
  1610. if (mmc_slot(host).name != NULL) {
  1611. ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
  1612. if (ret < 0)
  1613. goto err_slot_name;
  1614. }
  1615. if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
  1616. ret = device_create_file(&mmc->class_dev,
  1617. &dev_attr_cover_switch);
  1618. if (ret < 0)
  1619. goto err_slot_name;
  1620. }
  1621. omap_hsmmc_debugfs(mmc);
  1622. pm_runtime_mark_last_busy(host->dev);
  1623. pm_runtime_put_autosuspend(host->dev);
  1624. return 0;
  1625. err_slot_name:
  1626. mmc_remove_host(mmc);
  1627. free_irq(mmc_slot(host).card_detect_irq, host);
  1628. err_irq_cd:
  1629. if (host->use_reg)
  1630. omap_hsmmc_reg_put(host);
  1631. err_reg:
  1632. if (host->pdata->cleanup)
  1633. host->pdata->cleanup(&pdev->dev);
  1634. err_irq_cd_init:
  1635. free_irq(host->irq, host);
  1636. err_irq:
  1637. pm_runtime_mark_last_busy(host->dev);
  1638. pm_runtime_put_autosuspend(host->dev);
  1639. clk_put(host->fclk);
  1640. if (host->got_dbclk) {
  1641. clk_disable(host->dbclk);
  1642. clk_put(host->dbclk);
  1643. }
  1644. err1:
  1645. iounmap(host->base);
  1646. platform_set_drvdata(pdev, NULL);
  1647. mmc_free_host(mmc);
  1648. err_alloc:
  1649. omap_hsmmc_gpio_free(pdata);
  1650. err:
  1651. release_mem_region(res->start, resource_size(res));
  1652. return ret;
  1653. }
  1654. static int omap_hsmmc_remove(struct platform_device *pdev)
  1655. {
  1656. struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
  1657. struct resource *res;
  1658. if (host) {
  1659. pm_runtime_get_sync(host->dev);
  1660. mmc_remove_host(host->mmc);
  1661. if (host->use_reg)
  1662. omap_hsmmc_reg_put(host);
  1663. if (host->pdata->cleanup)
  1664. host->pdata->cleanup(&pdev->dev);
  1665. free_irq(host->irq, host);
  1666. if (mmc_slot(host).card_detect_irq)
  1667. free_irq(mmc_slot(host).card_detect_irq, host);
  1668. pm_runtime_put_sync(host->dev);
  1669. pm_runtime_disable(host->dev);
  1670. clk_put(host->fclk);
  1671. if (host->got_dbclk) {
  1672. clk_disable(host->dbclk);
  1673. clk_put(host->dbclk);
  1674. }
  1675. mmc_free_host(host->mmc);
  1676. iounmap(host->base);
  1677. omap_hsmmc_gpio_free(pdev->dev.platform_data);
  1678. }
  1679. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1680. if (res)
  1681. release_mem_region(res->start, resource_size(res));
  1682. platform_set_drvdata(pdev, NULL);
  1683. return 0;
  1684. }
  1685. #ifdef CONFIG_PM
  1686. static int omap_hsmmc_suspend(struct device *dev)
  1687. {
  1688. int ret = 0;
  1689. struct platform_device *pdev = to_platform_device(dev);
  1690. struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
  1691. if (host && host->suspended)
  1692. return 0;
  1693. if (host) {
  1694. pm_runtime_get_sync(host->dev);
  1695. host->suspended = 1;
  1696. if (host->pdata->suspend) {
  1697. ret = host->pdata->suspend(&pdev->dev,
  1698. host->slot_id);
  1699. if (ret) {
  1700. dev_dbg(mmc_dev(host->mmc),
  1701. "Unable to handle MMC board"
  1702. " level suspend\n");
  1703. host->suspended = 0;
  1704. return ret;
  1705. }
  1706. }
  1707. ret = mmc_suspend_host(host->mmc);
  1708. if (ret) {
  1709. host->suspended = 0;
  1710. if (host->pdata->resume) {
  1711. ret = host->pdata->resume(&pdev->dev,
  1712. host->slot_id);
  1713. if (ret)
  1714. dev_dbg(mmc_dev(host->mmc),
  1715. "Unmask interrupt failed\n");
  1716. }
  1717. goto err;
  1718. }
  1719. if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
  1720. omap_hsmmc_disable_irq(host);
  1721. OMAP_HSMMC_WRITE(host->base, HCTL,
  1722. OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
  1723. }
  1724. if (host->got_dbclk)
  1725. clk_disable(host->dbclk);
  1726. }
  1727. err:
  1728. pm_runtime_put_sync(host->dev);
  1729. return ret;
  1730. }
  1731. /* Routine to resume the MMC device */
  1732. static int omap_hsmmc_resume(struct device *dev)
  1733. {
  1734. int ret = 0;
  1735. struct platform_device *pdev = to_platform_device(dev);
  1736. struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
  1737. if (host && !host->suspended)
  1738. return 0;
  1739. if (host) {
  1740. pm_runtime_get_sync(host->dev);
  1741. if (host->got_dbclk)
  1742. clk_enable(host->dbclk);
  1743. if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
  1744. omap_hsmmc_conf_bus_power(host);
  1745. if (host->pdata->resume) {
  1746. ret = host->pdata->resume(&pdev->dev, host->slot_id);
  1747. if (ret)
  1748. dev_dbg(mmc_dev(host->mmc),
  1749. "Unmask interrupt failed\n");
  1750. }
  1751. omap_hsmmc_protect_card(host);
  1752. /* Notify the core to resume the host */
  1753. ret = mmc_resume_host(host->mmc);
  1754. if (ret == 0)
  1755. host->suspended = 0;
  1756. pm_runtime_mark_last_busy(host->dev);
  1757. pm_runtime_put_autosuspend(host->dev);
  1758. }
  1759. return ret;
  1760. }
  1761. #else
  1762. #define omap_hsmmc_suspend NULL
  1763. #define omap_hsmmc_resume NULL
  1764. #endif
  1765. static int omap_hsmmc_runtime_suspend(struct device *dev)
  1766. {
  1767. struct omap_hsmmc_host *host;
  1768. host = platform_get_drvdata(to_platform_device(dev));
  1769. omap_hsmmc_context_save(host);
  1770. dev_dbg(mmc_dev(host->mmc), "disabled\n");
  1771. return 0;
  1772. }
  1773. static int omap_hsmmc_runtime_resume(struct device *dev)
  1774. {
  1775. struct omap_hsmmc_host *host;
  1776. host = platform_get_drvdata(to_platform_device(dev));
  1777. omap_hsmmc_context_restore(host);
  1778. dev_dbg(mmc_dev(host->mmc), "enabled\n");
  1779. return 0;
  1780. }
  1781. static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
  1782. .suspend = omap_hsmmc_suspend,
  1783. .resume = omap_hsmmc_resume,
  1784. .runtime_suspend = omap_hsmmc_runtime_suspend,
  1785. .runtime_resume = omap_hsmmc_runtime_resume,
  1786. };
  1787. static struct platform_driver omap_hsmmc_driver = {
  1788. .remove = omap_hsmmc_remove,
  1789. .driver = {
  1790. .name = DRIVER_NAME,
  1791. .owner = THIS_MODULE,
  1792. .pm = &omap_hsmmc_dev_pm_ops,
  1793. },
  1794. };
  1795. static int __init omap_hsmmc_init(void)
  1796. {
  1797. /* Register the MMC driver */
  1798. return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
  1799. }
  1800. static void __exit omap_hsmmc_cleanup(void)
  1801. {
  1802. /* Unregister MMC driver */
  1803. platform_driver_unregister(&omap_hsmmc_driver);
  1804. }
  1805. module_init(omap_hsmmc_init);
  1806. module_exit(omap_hsmmc_cleanup);
  1807. MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
  1808. MODULE_LICENSE("GPL");
  1809. MODULE_ALIAS("platform:" DRIVER_NAME);
  1810. MODULE_AUTHOR("Texas Instruments Inc");