intel_mid_dma.h 2.4 KB

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  1. /*
  2. * intel_mid_dma.h - Intel MID DMA Drivers
  3. *
  4. * Copyright (C) 2008-10 Intel Corp
  5. * Author: Vinod Koul <vinod.koul@intel.com>
  6. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along
  18. * with this program; if not, write to the Free Software Foundation, Inc.,
  19. * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  20. *
  21. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  22. *
  23. *
  24. */
  25. #ifndef __INTEL_MID_DMA_H__
  26. #define __INTEL_MID_DMA_H__
  27. #include <linux/dmaengine.h>
  28. #define DMA_PREP_CIRCULAR_LIST (1 << 10)
  29. /*DMA mode configurations*/
  30. enum intel_mid_dma_mode {
  31. LNW_DMA_PER_TO_MEM = 0, /*periphral to memory configuration*/
  32. LNW_DMA_MEM_TO_PER, /*memory to periphral configuration*/
  33. LNW_DMA_MEM_TO_MEM, /*mem to mem confg (testing only)*/
  34. };
  35. /*DMA handshaking*/
  36. enum intel_mid_dma_hs_mode {
  37. LNW_DMA_HW_HS = 0, /*HW Handshaking only*/
  38. LNW_DMA_SW_HS = 1, /*SW Handshaking not recommended*/
  39. };
  40. /*Burst size configuration*/
  41. enum intel_mid_dma_msize {
  42. LNW_DMA_MSIZE_1 = 0x0,
  43. LNW_DMA_MSIZE_4 = 0x1,
  44. LNW_DMA_MSIZE_8 = 0x2,
  45. LNW_DMA_MSIZE_16 = 0x3,
  46. LNW_DMA_MSIZE_32 = 0x4,
  47. LNW_DMA_MSIZE_64 = 0x5,
  48. };
  49. /**
  50. * struct intel_mid_dma_slave - DMA slave structure
  51. *
  52. * @dirn: DMA trf direction
  53. * @src_width: tx register width
  54. * @dst_width: rx register width
  55. * @hs_mode: HW/SW handshaking mode
  56. * @cfg_mode: DMA data transfer mode (per-per/mem-per/mem-mem)
  57. * @src_msize: Source DMA burst size
  58. * @dst_msize: Dst DMA burst size
  59. * @per_addr: Periphral address
  60. * @device_instance: DMA peripheral device instance, we can have multiple
  61. * peripheral device connected to single DMAC
  62. */
  63. struct intel_mid_dma_slave {
  64. enum intel_mid_dma_hs_mode hs_mode; /*handshaking*/
  65. enum intel_mid_dma_mode cfg_mode; /*mode configuration*/
  66. unsigned int device_instance; /*0, 1 for periphral instance*/
  67. struct dma_slave_config dma_slave;
  68. };
  69. #endif /*__INTEL_MID_DMA_H__*/