sonicvibes.c 80 KB

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  1. /*****************************************************************************/
  2. /*
  3. * sonicvibes.c -- S3 Sonic Vibes audio driver.
  4. *
  5. * Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. *
  21. * Special thanks to David C. Niemi
  22. *
  23. *
  24. * Module command line parameters:
  25. * none so far
  26. *
  27. *
  28. * Supported devices:
  29. * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
  30. * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
  31. * /dev/midi simple MIDI UART interface, no ioctl
  32. *
  33. * The card has both an FM and a Wavetable synth, but I have to figure
  34. * out first how to drive them...
  35. *
  36. * Revision history
  37. * 06.05.1998 0.1 Initial release
  38. * 10.05.1998 0.2 Fixed many bugs, esp. ADC rate calculation
  39. * First stab at a simple midi interface (no bells&whistles)
  40. * 13.05.1998 0.3 Fix stupid cut&paste error: set_adc_rate was called instead of
  41. * set_dac_rate in the FMODE_WRITE case in sv_open
  42. * Fix hwptr out of bounds (now mpg123 works)
  43. * 14.05.1998 0.4 Don't allow excessive interrupt rates
  44. * 08.06.1998 0.5 First release using Alan Cox' soundcore instead of miscdevice
  45. * 03.08.1998 0.6 Do not include modversions.h
  46. * Now mixer behaviour can basically be selected between
  47. * "OSS documented" and "OSS actual" behaviour
  48. * 31.08.1998 0.7 Fix realplayer problems - dac.count issues
  49. * 10.12.1998 0.8 Fix drain_dac trying to wait on not yet initialized DMA
  50. * 16.12.1998 0.9 Fix a few f_file & FMODE_ bugs
  51. * 06.01.1999 0.10 remove the silly SA_INTERRUPT flag.
  52. * hopefully killed the egcs section type conflict
  53. * 12.03.1999 0.11 cinfo.blocks should be reset after GETxPTR ioctl.
  54. * reported by Johan Maes <joma@telindus.be>
  55. * 22.03.1999 0.12 return EAGAIN instead of EBUSY when O_NONBLOCK
  56. * read/write cannot be executed
  57. * 05.04.1999 0.13 added code to sv_read and sv_write which should detect
  58. * lockups of the sound chip and revive it. This is basically
  59. * an ugly hack, but at least applications using this driver
  60. * won't hang forever. I don't know why these lockups happen,
  61. * it might well be the motherboard chipset (an early 486 PCI
  62. * board with ALI chipset), since every busmastering 100MB
  63. * ethernet card I've tried (Realtek 8139 and Macronix tulip clone)
  64. * exhibit similar behaviour (they work for a couple of packets
  65. * and then lock up and can be revived by ifconfig down/up).
  66. * 07.04.1999 0.14 implemented the following ioctl's: SOUND_PCM_READ_RATE,
  67. * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
  68. * Alpha fixes reported by Peter Jones <pjones@redhat.com>
  69. * Note: dmaio hack might still be wrong on archs other than i386
  70. * 15.06.1999 0.15 Fix bad allocation bug.
  71. * Thanks to Deti Fliegl <fliegl@in.tum.de>
  72. * 28.06.1999 0.16 Add pci_set_master
  73. * 03.08.1999 0.17 adapt to Linus' new __setup/__initcall
  74. * added kernel command line options "sonicvibes=reverb" and "sonicvibesdmaio=dmaioaddr"
  75. * 12.08.1999 0.18 module_init/__setup fixes
  76. * 24.08.1999 0.19 get rid of the dmaio kludge, replace with allocate_resource
  77. * 31.08.1999 0.20 add spin_lock_init
  78. * use new resource allocation to allocate DDMA IO space
  79. * replaced current->state = x with set_current_state(x)
  80. * 03.09.1999 0.21 change read semantics for MIDI to match
  81. * OSS more closely; remove possible wakeup race
  82. * 28.10.1999 0.22 More waitqueue races fixed
  83. * 01.12.1999 0.23 New argument to allocate_resource
  84. * 07.12.1999 0.24 More allocate_resource semantics change
  85. * 08.01.2000 0.25 Prevent some ioctl's from returning bad count values on underrun/overrun;
  86. * Tim Janik's BSE (Bedevilled Sound Engine) found this
  87. * use Martin Mares' pci_assign_resource
  88. * 07.02.2000 0.26 Use pci_alloc_consistent and pci_register_driver
  89. * 21.11.2000 0.27 Initialize dma buffers in poll, otherwise poll may return a bogus mask
  90. * 12.12.2000 0.28 More dma buffer initializations, patch from
  91. * Tjeerd Mulder <tjeerd.mulder@fujitsu-siemens.com>
  92. * 31.01.2001 0.29 Register/Unregister gameport
  93. * Fix SETTRIGGER non OSS API conformity
  94. * 18.05.2001 0.30 PCI probing and error values cleaned up by Marcus
  95. * Meissner <mm@caldera.de>
  96. * 03.01.2003 0.31 open_mode fixes from Georg Acher <acher@in.tum.de>
  97. *
  98. */
  99. /*****************************************************************************/
  100. #include <linux/module.h>
  101. #include <linux/string.h>
  102. #include <linux/ioport.h>
  103. #include <linux/interrupt.h>
  104. #include <linux/wait.h>
  105. #include <linux/mm.h>
  106. #include <linux/delay.h>
  107. #include <linux/sound.h>
  108. #include <linux/slab.h>
  109. #include <linux/soundcard.h>
  110. #include <linux/pci.h>
  111. #include <linux/init.h>
  112. #include <linux/poll.h>
  113. #include <linux/spinlock.h>
  114. #include <linux/smp_lock.h>
  115. #include <linux/gameport.h>
  116. #include <linux/mutex.h>
  117. #include <asm/io.h>
  118. #include <asm/uaccess.h>
  119. #include "dm.h"
  120. #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  121. #define SUPPORT_JOYSTICK 1
  122. #endif
  123. /* --------------------------------------------------------------------- */
  124. #undef OSS_DOCUMENTED_MIXER_SEMANTICS
  125. /* --------------------------------------------------------------------- */
  126. #ifndef PCI_VENDOR_ID_S3
  127. #define PCI_VENDOR_ID_S3 0x5333
  128. #endif
  129. #ifndef PCI_DEVICE_ID_S3_SONICVIBES
  130. #define PCI_DEVICE_ID_S3_SONICVIBES 0xca00
  131. #endif
  132. #define SV_MAGIC ((PCI_VENDOR_ID_S3<<16)|PCI_DEVICE_ID_S3_SONICVIBES)
  133. #define SV_EXTENT_SB 0x10
  134. #define SV_EXTENT_ENH 0x10
  135. #define SV_EXTENT_SYNTH 0x4
  136. #define SV_EXTENT_MIDI 0x4
  137. #define SV_EXTENT_GAME 0x8
  138. #define SV_EXTENT_DMA 0x10
  139. /*
  140. * we are not a bridge and thus use a resource for DDMA that is used for bridges but
  141. * left empty for normal devices
  142. */
  143. #define RESOURCE_SB 0
  144. #define RESOURCE_ENH 1
  145. #define RESOURCE_SYNTH 2
  146. #define RESOURCE_MIDI 3
  147. #define RESOURCE_GAME 4
  148. #define RESOURCE_DDMA 7
  149. #define SV_MIDI_DATA 0
  150. #define SV_MIDI_COMMAND 1
  151. #define SV_MIDI_STATUS 1
  152. #define SV_DMA_ADDR0 0
  153. #define SV_DMA_ADDR1 1
  154. #define SV_DMA_ADDR2 2
  155. #define SV_DMA_ADDR3 3
  156. #define SV_DMA_COUNT0 4
  157. #define SV_DMA_COUNT1 5
  158. #define SV_DMA_COUNT2 6
  159. #define SV_DMA_MODE 0xb
  160. #define SV_DMA_RESET 0xd
  161. #define SV_DMA_MASK 0xf
  162. /*
  163. * DONT reset the DMA controllers unless you understand
  164. * the reset semantics. Assuming reset semantics as in
  165. * the 8237 does not work.
  166. */
  167. #define DMA_MODE_AUTOINIT 0x10
  168. #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
  169. #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
  170. #define SV_CODEC_CONTROL 0
  171. #define SV_CODEC_INTMASK 1
  172. #define SV_CODEC_STATUS 2
  173. #define SV_CODEC_IADDR 4
  174. #define SV_CODEC_IDATA 5
  175. #define SV_CCTRL_RESET 0x80
  176. #define SV_CCTRL_INTADRIVE 0x20
  177. #define SV_CCTRL_WAVETABLE 0x08
  178. #define SV_CCTRL_REVERB 0x04
  179. #define SV_CCTRL_ENHANCED 0x01
  180. #define SV_CINTMASK_DMAA 0x01
  181. #define SV_CINTMASK_DMAC 0x04
  182. #define SV_CINTMASK_SPECIAL 0x08
  183. #define SV_CINTMASK_UPDOWN 0x40
  184. #define SV_CINTMASK_MIDI 0x80
  185. #define SV_CSTAT_DMAA 0x01
  186. #define SV_CSTAT_DMAC 0x04
  187. #define SV_CSTAT_SPECIAL 0x08
  188. #define SV_CSTAT_UPDOWN 0x40
  189. #define SV_CSTAT_MIDI 0x80
  190. #define SV_CIADDR_TRD 0x80
  191. #define SV_CIADDR_MCE 0x40
  192. /* codec indirect registers */
  193. #define SV_CIMIX_ADCINL 0x00
  194. #define SV_CIMIX_ADCINR 0x01
  195. #define SV_CIMIX_AUX1INL 0x02
  196. #define SV_CIMIX_AUX1INR 0x03
  197. #define SV_CIMIX_CDINL 0x04
  198. #define SV_CIMIX_CDINR 0x05
  199. #define SV_CIMIX_LINEINL 0x06
  200. #define SV_CIMIX_LINEINR 0x07
  201. #define SV_CIMIX_MICIN 0x08
  202. #define SV_CIMIX_SYNTHINL 0x0A
  203. #define SV_CIMIX_SYNTHINR 0x0B
  204. #define SV_CIMIX_AUX2INL 0x0C
  205. #define SV_CIMIX_AUX2INR 0x0D
  206. #define SV_CIMIX_ANALOGINL 0x0E
  207. #define SV_CIMIX_ANALOGINR 0x0F
  208. #define SV_CIMIX_PCMINL 0x10
  209. #define SV_CIMIX_PCMINR 0x11
  210. #define SV_CIGAMECONTROL 0x09
  211. #define SV_CIDATAFMT 0x12
  212. #define SV_CIENABLE 0x13
  213. #define SV_CIUPDOWN 0x14
  214. #define SV_CIREVISION 0x15
  215. #define SV_CIADCOUTPUT 0x16
  216. #define SV_CIDMAABASECOUNT1 0x18
  217. #define SV_CIDMAABASECOUNT0 0x19
  218. #define SV_CIDMACBASECOUNT1 0x1c
  219. #define SV_CIDMACBASECOUNT0 0x1d
  220. #define SV_CIPCMSR0 0x1e
  221. #define SV_CIPCMSR1 0x1f
  222. #define SV_CISYNTHSR0 0x20
  223. #define SV_CISYNTHSR1 0x21
  224. #define SV_CIADCCLKSOURCE 0x22
  225. #define SV_CIADCALTSR 0x23
  226. #define SV_CIADCPLLM 0x24
  227. #define SV_CIADCPLLN 0x25
  228. #define SV_CISYNTHPLLM 0x26
  229. #define SV_CISYNTHPLLN 0x27
  230. #define SV_CIUARTCONTROL 0x2a
  231. #define SV_CIDRIVECONTROL 0x2b
  232. #define SV_CISRSSPACE 0x2c
  233. #define SV_CISRSCENTER 0x2d
  234. #define SV_CIWAVETABLESRC 0x2e
  235. #define SV_CIANALOGPWRDOWN 0x30
  236. #define SV_CIDIGITALPWRDOWN 0x31
  237. #define SV_CIMIX_ADCSRC_CD 0x20
  238. #define SV_CIMIX_ADCSRC_DAC 0x40
  239. #define SV_CIMIX_ADCSRC_AUX2 0x60
  240. #define SV_CIMIX_ADCSRC_LINE 0x80
  241. #define SV_CIMIX_ADCSRC_AUX1 0xa0
  242. #define SV_CIMIX_ADCSRC_MIC 0xc0
  243. #define SV_CIMIX_ADCSRC_MIXOUT 0xe0
  244. #define SV_CIMIX_ADCSRC_MASK 0xe0
  245. #define SV_CFMT_STEREO 0x01
  246. #define SV_CFMT_16BIT 0x02
  247. #define SV_CFMT_MASK 0x03
  248. #define SV_CFMT_ASHIFT 0
  249. #define SV_CFMT_CSHIFT 4
  250. static const unsigned sample_size[] = { 1, 2, 2, 4 };
  251. static const unsigned sample_shift[] = { 0, 1, 1, 2 };
  252. #define SV_CENABLE_PPE 0x4
  253. #define SV_CENABLE_RE 0x2
  254. #define SV_CENABLE_PE 0x1
  255. /* MIDI buffer sizes */
  256. #define MIDIINBUF 256
  257. #define MIDIOUTBUF 256
  258. #define FMODE_MIDI_SHIFT 2
  259. #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
  260. #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
  261. #define FMODE_DMFM 0x10
  262. /* --------------------------------------------------------------------- */
  263. struct sv_state {
  264. /* magic */
  265. unsigned int magic;
  266. /* list of sonicvibes devices */
  267. struct list_head devs;
  268. /* the corresponding pci_dev structure */
  269. struct pci_dev *dev;
  270. /* soundcore stuff */
  271. int dev_audio;
  272. int dev_mixer;
  273. int dev_midi;
  274. int dev_dmfm;
  275. /* hardware resources */
  276. unsigned long iosb, ioenh, iosynth, iomidi; /* long for SPARC */
  277. unsigned int iodmaa, iodmac, irq;
  278. /* mixer stuff */
  279. struct {
  280. unsigned int modcnt;
  281. #ifndef OSS_DOCUMENTED_MIXER_SEMANTICS
  282. unsigned short vol[13];
  283. #endif /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  284. } mix;
  285. /* wave stuff */
  286. unsigned int rateadc, ratedac;
  287. unsigned char fmt, enable;
  288. spinlock_t lock;
  289. struct mutex open_mutex;
  290. mode_t open_mode;
  291. wait_queue_head_t open_wait;
  292. struct dmabuf {
  293. void *rawbuf;
  294. dma_addr_t dmaaddr;
  295. unsigned buforder;
  296. unsigned numfrag;
  297. unsigned fragshift;
  298. unsigned hwptr, swptr;
  299. unsigned total_bytes;
  300. int count;
  301. unsigned error; /* over/underrun */
  302. wait_queue_head_t wait;
  303. /* redundant, but makes calculations easier */
  304. unsigned fragsize;
  305. unsigned dmasize;
  306. unsigned fragsamples;
  307. /* OSS stuff */
  308. unsigned mapped:1;
  309. unsigned ready:1;
  310. unsigned endcleared:1;
  311. unsigned enabled:1;
  312. unsigned ossfragshift;
  313. int ossmaxfrags;
  314. unsigned subdivision;
  315. } dma_dac, dma_adc;
  316. /* midi stuff */
  317. struct {
  318. unsigned ird, iwr, icnt;
  319. unsigned ord, owr, ocnt;
  320. wait_queue_head_t iwait;
  321. wait_queue_head_t owait;
  322. struct timer_list timer;
  323. unsigned char ibuf[MIDIINBUF];
  324. unsigned char obuf[MIDIOUTBUF];
  325. } midi;
  326. #if SUPPORT_JOYSTICK
  327. struct gameport *gameport;
  328. #endif
  329. };
  330. /* --------------------------------------------------------------------- */
  331. static LIST_HEAD(devs);
  332. static unsigned long wavetable_mem;
  333. /* --------------------------------------------------------------------- */
  334. static inline unsigned ld2(unsigned int x)
  335. {
  336. unsigned r = 0;
  337. if (x >= 0x10000) {
  338. x >>= 16;
  339. r += 16;
  340. }
  341. if (x >= 0x100) {
  342. x >>= 8;
  343. r += 8;
  344. }
  345. if (x >= 0x10) {
  346. x >>= 4;
  347. r += 4;
  348. }
  349. if (x >= 4) {
  350. x >>= 2;
  351. r += 2;
  352. }
  353. if (x >= 2)
  354. r++;
  355. return r;
  356. }
  357. /*
  358. * hweightN: returns the hamming weight (i.e. the number
  359. * of bits set) of a N-bit word
  360. */
  361. #ifdef hweight32
  362. #undef hweight32
  363. #endif
  364. static inline unsigned int hweight32(unsigned int w)
  365. {
  366. unsigned int res = (w & 0x55555555) + ((w >> 1) & 0x55555555);
  367. res = (res & 0x33333333) + ((res >> 2) & 0x33333333);
  368. res = (res & 0x0F0F0F0F) + ((res >> 4) & 0x0F0F0F0F);
  369. res = (res & 0x00FF00FF) + ((res >> 8) & 0x00FF00FF);
  370. return (res & 0x0000FFFF) + ((res >> 16) & 0x0000FFFF);
  371. }
  372. /* --------------------------------------------------------------------- */
  373. /*
  374. * Why use byte IO? Nobody knows, but S3 does it also in their Windows driver.
  375. */
  376. #undef DMABYTEIO
  377. static void set_dmaa(struct sv_state *s, unsigned int addr, unsigned int count)
  378. {
  379. #ifdef DMABYTEIO
  380. unsigned io = s->iodmaa, u;
  381. count--;
  382. for (u = 4; u > 0; u--, addr >>= 8, io++)
  383. outb(addr & 0xff, io);
  384. for (u = 3; u > 0; u--, count >>= 8, io++)
  385. outb(count & 0xff, io);
  386. #else /* DMABYTEIO */
  387. count--;
  388. outl(addr, s->iodmaa + SV_DMA_ADDR0);
  389. outl(count, s->iodmaa + SV_DMA_COUNT0);
  390. #endif /* DMABYTEIO */
  391. outb(0x18, s->iodmaa + SV_DMA_MODE);
  392. }
  393. static void set_dmac(struct sv_state *s, unsigned int addr, unsigned int count)
  394. {
  395. #ifdef DMABYTEIO
  396. unsigned io = s->iodmac, u;
  397. count >>= 1;
  398. count--;
  399. for (u = 4; u > 0; u--, addr >>= 8, io++)
  400. outb(addr & 0xff, io);
  401. for (u = 3; u > 0; u--, count >>= 8, io++)
  402. outb(count & 0xff, io);
  403. #else /* DMABYTEIO */
  404. count >>= 1;
  405. count--;
  406. outl(addr, s->iodmac + SV_DMA_ADDR0);
  407. outl(count, s->iodmac + SV_DMA_COUNT0);
  408. #endif /* DMABYTEIO */
  409. outb(0x14, s->iodmac + SV_DMA_MODE);
  410. }
  411. static inline unsigned get_dmaa(struct sv_state *s)
  412. {
  413. #ifdef DMABYTEIO
  414. unsigned io = s->iodmaa+6, v = 0, u;
  415. for (u = 3; u > 0; u--, io--) {
  416. v <<= 8;
  417. v |= inb(io);
  418. }
  419. return v + 1;
  420. #else /* DMABYTEIO */
  421. return (inl(s->iodmaa + SV_DMA_COUNT0) & 0xffffff) + 1;
  422. #endif /* DMABYTEIO */
  423. }
  424. static inline unsigned get_dmac(struct sv_state *s)
  425. {
  426. #ifdef DMABYTEIO
  427. unsigned io = s->iodmac+6, v = 0, u;
  428. for (u = 3; u > 0; u--, io--) {
  429. v <<= 8;
  430. v |= inb(io);
  431. }
  432. return (v + 1) << 1;
  433. #else /* DMABYTEIO */
  434. return ((inl(s->iodmac + SV_DMA_COUNT0) & 0xffffff) + 1) << 1;
  435. #endif /* DMABYTEIO */
  436. }
  437. static void wrindir(struct sv_state *s, unsigned char idx, unsigned char data)
  438. {
  439. outb(idx & 0x3f, s->ioenh + SV_CODEC_IADDR);
  440. udelay(10);
  441. outb(data, s->ioenh + SV_CODEC_IDATA);
  442. udelay(10);
  443. }
  444. static unsigned char rdindir(struct sv_state *s, unsigned char idx)
  445. {
  446. unsigned char v;
  447. outb(idx & 0x3f, s->ioenh + SV_CODEC_IADDR);
  448. udelay(10);
  449. v = inb(s->ioenh + SV_CODEC_IDATA);
  450. udelay(10);
  451. return v;
  452. }
  453. static void set_fmt(struct sv_state *s, unsigned char mask, unsigned char data)
  454. {
  455. unsigned long flags;
  456. spin_lock_irqsave(&s->lock, flags);
  457. outb(SV_CIDATAFMT | SV_CIADDR_MCE, s->ioenh + SV_CODEC_IADDR);
  458. if (mask) {
  459. s->fmt = inb(s->ioenh + SV_CODEC_IDATA);
  460. udelay(10);
  461. }
  462. s->fmt = (s->fmt & mask) | data;
  463. outb(s->fmt, s->ioenh + SV_CODEC_IDATA);
  464. udelay(10);
  465. outb(0, s->ioenh + SV_CODEC_IADDR);
  466. spin_unlock_irqrestore(&s->lock, flags);
  467. udelay(10);
  468. }
  469. static void frobindir(struct sv_state *s, unsigned char idx, unsigned char mask, unsigned char data)
  470. {
  471. outb(idx & 0x3f, s->ioenh + SV_CODEC_IADDR);
  472. udelay(10);
  473. outb((inb(s->ioenh + SV_CODEC_IDATA) & mask) ^ data, s->ioenh + SV_CODEC_IDATA);
  474. udelay(10);
  475. }
  476. #define REFFREQUENCY 24576000
  477. #define ADCMULT 512
  478. #define FULLRATE 48000
  479. static unsigned setpll(struct sv_state *s, unsigned char reg, unsigned rate)
  480. {
  481. unsigned long flags;
  482. unsigned char r, m=0, n=0;
  483. unsigned xm, xn, xr, xd, metric = ~0U;
  484. /* the warnings about m and n used uninitialized are bogus and may safely be ignored */
  485. if (rate < 625000/ADCMULT)
  486. rate = 625000/ADCMULT;
  487. if (rate > 150000000/ADCMULT)
  488. rate = 150000000/ADCMULT;
  489. /* slight violation of specs, needed for continuous sampling rates */
  490. for (r = 0; rate < 75000000/ADCMULT; r += 0x20, rate <<= 1);
  491. for (xn = 3; xn < 35; xn++)
  492. for (xm = 3; xm < 130; xm++) {
  493. xr = REFFREQUENCY/ADCMULT * xm / xn;
  494. xd = abs((signed)(xr - rate));
  495. if (xd < metric) {
  496. metric = xd;
  497. m = xm - 2;
  498. n = xn - 2;
  499. }
  500. }
  501. reg &= 0x3f;
  502. spin_lock_irqsave(&s->lock, flags);
  503. outb(reg, s->ioenh + SV_CODEC_IADDR);
  504. udelay(10);
  505. outb(m, s->ioenh + SV_CODEC_IDATA);
  506. udelay(10);
  507. outb(reg+1, s->ioenh + SV_CODEC_IADDR);
  508. udelay(10);
  509. outb(r | n, s->ioenh + SV_CODEC_IDATA);
  510. spin_unlock_irqrestore(&s->lock, flags);
  511. udelay(10);
  512. return (REFFREQUENCY/ADCMULT * (m + 2) / (n + 2)) >> ((r >> 5) & 7);
  513. }
  514. #if 0
  515. static unsigned getpll(struct sv_state *s, unsigned char reg)
  516. {
  517. unsigned long flags;
  518. unsigned char m, n;
  519. reg &= 0x3f;
  520. spin_lock_irqsave(&s->lock, flags);
  521. outb(reg, s->ioenh + SV_CODEC_IADDR);
  522. udelay(10);
  523. m = inb(s->ioenh + SV_CODEC_IDATA);
  524. udelay(10);
  525. outb(reg+1, s->ioenh + SV_CODEC_IADDR);
  526. udelay(10);
  527. n = inb(s->ioenh + SV_CODEC_IDATA);
  528. spin_unlock_irqrestore(&s->lock, flags);
  529. udelay(10);
  530. return (REFFREQUENCY/ADCMULT * (m + 2) / ((n & 0x1f) + 2)) >> ((n >> 5) & 7);
  531. }
  532. #endif
  533. static void set_dac_rate(struct sv_state *s, unsigned rate)
  534. {
  535. unsigned div;
  536. unsigned long flags;
  537. if (rate > 48000)
  538. rate = 48000;
  539. if (rate < 4000)
  540. rate = 4000;
  541. div = (rate * 65536 + FULLRATE/2) / FULLRATE;
  542. if (div > 65535)
  543. div = 65535;
  544. spin_lock_irqsave(&s->lock, flags);
  545. wrindir(s, SV_CIPCMSR1, div >> 8);
  546. wrindir(s, SV_CIPCMSR0, div);
  547. spin_unlock_irqrestore(&s->lock, flags);
  548. s->ratedac = (div * FULLRATE + 32768) / 65536;
  549. }
  550. static void set_adc_rate(struct sv_state *s, unsigned rate)
  551. {
  552. unsigned long flags;
  553. unsigned rate1, rate2, div;
  554. if (rate > 48000)
  555. rate = 48000;
  556. if (rate < 4000)
  557. rate = 4000;
  558. rate1 = setpll(s, SV_CIADCPLLM, rate);
  559. div = (48000 + rate/2) / rate;
  560. if (div > 8)
  561. div = 8;
  562. rate2 = (48000 + div/2) / div;
  563. spin_lock_irqsave(&s->lock, flags);
  564. wrindir(s, SV_CIADCALTSR, (div-1) << 4);
  565. if (abs((signed)(rate-rate2)) <= abs((signed)(rate-rate1))) {
  566. wrindir(s, SV_CIADCCLKSOURCE, 0x10);
  567. s->rateadc = rate2;
  568. } else {
  569. wrindir(s, SV_CIADCCLKSOURCE, 0x00);
  570. s->rateadc = rate1;
  571. }
  572. spin_unlock_irqrestore(&s->lock, flags);
  573. }
  574. /* --------------------------------------------------------------------- */
  575. static inline void stop_adc(struct sv_state *s)
  576. {
  577. unsigned long flags;
  578. spin_lock_irqsave(&s->lock, flags);
  579. s->enable &= ~SV_CENABLE_RE;
  580. wrindir(s, SV_CIENABLE, s->enable);
  581. spin_unlock_irqrestore(&s->lock, flags);
  582. }
  583. static inline void stop_dac(struct sv_state *s)
  584. {
  585. unsigned long flags;
  586. spin_lock_irqsave(&s->lock, flags);
  587. s->enable &= ~(SV_CENABLE_PPE | SV_CENABLE_PE);
  588. wrindir(s, SV_CIENABLE, s->enable);
  589. spin_unlock_irqrestore(&s->lock, flags);
  590. }
  591. static void start_dac(struct sv_state *s)
  592. {
  593. unsigned long flags;
  594. spin_lock_irqsave(&s->lock, flags);
  595. if ((s->dma_dac.mapped || s->dma_dac.count > 0) && s->dma_dac.ready) {
  596. s->enable = (s->enable & ~SV_CENABLE_PPE) | SV_CENABLE_PE;
  597. wrindir(s, SV_CIENABLE, s->enable);
  598. }
  599. spin_unlock_irqrestore(&s->lock, flags);
  600. }
  601. static void start_adc(struct sv_state *s)
  602. {
  603. unsigned long flags;
  604. spin_lock_irqsave(&s->lock, flags);
  605. if ((s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
  606. && s->dma_adc.ready) {
  607. s->enable |= SV_CENABLE_RE;
  608. wrindir(s, SV_CIENABLE, s->enable);
  609. }
  610. spin_unlock_irqrestore(&s->lock, flags);
  611. }
  612. /* --------------------------------------------------------------------- */
  613. #define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
  614. #define DMABUF_MINORDER 1
  615. static void dealloc_dmabuf(struct sv_state *s, struct dmabuf *db)
  616. {
  617. struct page *page, *pend;
  618. if (db->rawbuf) {
  619. /* undo marking the pages as reserved */
  620. pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
  621. for (page = virt_to_page(db->rawbuf); page <= pend; page++)
  622. ClearPageReserved(page);
  623. pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
  624. }
  625. db->rawbuf = NULL;
  626. db->mapped = db->ready = 0;
  627. }
  628. /* DMAA is used for playback, DMAC is used for recording */
  629. static int prog_dmabuf(struct sv_state *s, unsigned rec)
  630. {
  631. struct dmabuf *db = rec ? &s->dma_adc : &s->dma_dac;
  632. unsigned rate = rec ? s->rateadc : s->ratedac;
  633. int order;
  634. unsigned bytepersec;
  635. unsigned bufs;
  636. struct page *page, *pend;
  637. unsigned char fmt;
  638. unsigned long flags;
  639. spin_lock_irqsave(&s->lock, flags);
  640. fmt = s->fmt;
  641. if (rec) {
  642. s->enable &= ~SV_CENABLE_RE;
  643. fmt >>= SV_CFMT_CSHIFT;
  644. } else {
  645. s->enable &= ~SV_CENABLE_PE;
  646. fmt >>= SV_CFMT_ASHIFT;
  647. }
  648. wrindir(s, SV_CIENABLE, s->enable);
  649. spin_unlock_irqrestore(&s->lock, flags);
  650. fmt &= SV_CFMT_MASK;
  651. db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
  652. if (!db->rawbuf) {
  653. db->ready = db->mapped = 0;
  654. for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
  655. if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
  656. break;
  657. if (!db->rawbuf)
  658. return -ENOMEM;
  659. db->buforder = order;
  660. if ((virt_to_bus(db->rawbuf) ^ (virt_to_bus(db->rawbuf) + (PAGE_SIZE << db->buforder) - 1)) & ~0xffff)
  661. printk(KERN_DEBUG "sv: DMA buffer crosses 64k boundary: busaddr 0x%lx size %ld\n",
  662. virt_to_bus(db->rawbuf), PAGE_SIZE << db->buforder);
  663. if ((virt_to_bus(db->rawbuf) + (PAGE_SIZE << db->buforder) - 1) & ~0xffffff)
  664. printk(KERN_DEBUG "sv: DMA buffer beyond 16MB: busaddr 0x%lx size %ld\n",
  665. virt_to_bus(db->rawbuf), PAGE_SIZE << db->buforder);
  666. /* now mark the pages as reserved; otherwise remap_pfn_range doesn't do what we want */
  667. pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
  668. for (page = virt_to_page(db->rawbuf); page <= pend; page++)
  669. SetPageReserved(page);
  670. }
  671. bytepersec = rate << sample_shift[fmt];
  672. bufs = PAGE_SIZE << db->buforder;
  673. if (db->ossfragshift) {
  674. if ((1000 << db->ossfragshift) < bytepersec)
  675. db->fragshift = ld2(bytepersec/1000);
  676. else
  677. db->fragshift = db->ossfragshift;
  678. } else {
  679. db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
  680. if (db->fragshift < 3)
  681. db->fragshift = 3;
  682. }
  683. db->numfrag = bufs >> db->fragshift;
  684. while (db->numfrag < 4 && db->fragshift > 3) {
  685. db->fragshift--;
  686. db->numfrag = bufs >> db->fragshift;
  687. }
  688. db->fragsize = 1 << db->fragshift;
  689. if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
  690. db->numfrag = db->ossmaxfrags;
  691. db->fragsamples = db->fragsize >> sample_shift[fmt];
  692. db->dmasize = db->numfrag << db->fragshift;
  693. memset(db->rawbuf, (fmt & SV_CFMT_16BIT) ? 0 : 0x80, db->dmasize);
  694. spin_lock_irqsave(&s->lock, flags);
  695. if (rec) {
  696. set_dmac(s, db->dmaaddr, db->numfrag << db->fragshift);
  697. /* program enhanced mode registers */
  698. wrindir(s, SV_CIDMACBASECOUNT1, (db->fragsamples-1) >> 8);
  699. wrindir(s, SV_CIDMACBASECOUNT0, db->fragsamples-1);
  700. } else {
  701. set_dmaa(s, db->dmaaddr, db->numfrag << db->fragshift);
  702. /* program enhanced mode registers */
  703. wrindir(s, SV_CIDMAABASECOUNT1, (db->fragsamples-1) >> 8);
  704. wrindir(s, SV_CIDMAABASECOUNT0, db->fragsamples-1);
  705. }
  706. spin_unlock_irqrestore(&s->lock, flags);
  707. db->enabled = 1;
  708. db->ready = 1;
  709. return 0;
  710. }
  711. static inline void clear_advance(struct sv_state *s)
  712. {
  713. unsigned char c = (s->fmt & (SV_CFMT_16BIT << SV_CFMT_ASHIFT)) ? 0 : 0x80;
  714. unsigned char *buf = s->dma_dac.rawbuf;
  715. unsigned bsize = s->dma_dac.dmasize;
  716. unsigned bptr = s->dma_dac.swptr;
  717. unsigned len = s->dma_dac.fragsize;
  718. if (bptr + len > bsize) {
  719. unsigned x = bsize - bptr;
  720. memset(buf + bptr, c, x);
  721. bptr = 0;
  722. len -= x;
  723. }
  724. memset(buf + bptr, c, len);
  725. }
  726. /* call with spinlock held! */
  727. static void sv_update_ptr(struct sv_state *s)
  728. {
  729. unsigned hwptr;
  730. int diff;
  731. /* update ADC pointer */
  732. if (s->dma_adc.ready) {
  733. hwptr = (s->dma_adc.dmasize - get_dmac(s)) % s->dma_adc.dmasize;
  734. diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
  735. s->dma_adc.hwptr = hwptr;
  736. s->dma_adc.total_bytes += diff;
  737. s->dma_adc.count += diff;
  738. if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
  739. wake_up(&s->dma_adc.wait);
  740. if (!s->dma_adc.mapped) {
  741. if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
  742. s->enable &= ~SV_CENABLE_RE;
  743. wrindir(s, SV_CIENABLE, s->enable);
  744. s->dma_adc.error++;
  745. }
  746. }
  747. }
  748. /* update DAC pointer */
  749. if (s->dma_dac.ready) {
  750. hwptr = (s->dma_dac.dmasize - get_dmaa(s)) % s->dma_dac.dmasize;
  751. diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
  752. s->dma_dac.hwptr = hwptr;
  753. s->dma_dac.total_bytes += diff;
  754. if (s->dma_dac.mapped) {
  755. s->dma_dac.count += diff;
  756. if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
  757. wake_up(&s->dma_dac.wait);
  758. } else {
  759. s->dma_dac.count -= diff;
  760. if (s->dma_dac.count <= 0) {
  761. s->enable &= ~SV_CENABLE_PE;
  762. wrindir(s, SV_CIENABLE, s->enable);
  763. s->dma_dac.error++;
  764. } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
  765. clear_advance(s);
  766. s->dma_dac.endcleared = 1;
  767. }
  768. if (s->dma_dac.count + (signed)s->dma_dac.fragsize <= (signed)s->dma_dac.dmasize)
  769. wake_up(&s->dma_dac.wait);
  770. }
  771. }
  772. }
  773. /* hold spinlock for the following! */
  774. static void sv_handle_midi(struct sv_state *s)
  775. {
  776. unsigned char ch;
  777. int wake;
  778. wake = 0;
  779. while (!(inb(s->iomidi+1) & 0x80)) {
  780. ch = inb(s->iomidi);
  781. if (s->midi.icnt < MIDIINBUF) {
  782. s->midi.ibuf[s->midi.iwr] = ch;
  783. s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
  784. s->midi.icnt++;
  785. }
  786. wake = 1;
  787. }
  788. if (wake)
  789. wake_up(&s->midi.iwait);
  790. wake = 0;
  791. while (!(inb(s->iomidi+1) & 0x40) && s->midi.ocnt > 0) {
  792. outb(s->midi.obuf[s->midi.ord], s->iomidi);
  793. s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
  794. s->midi.ocnt--;
  795. if (s->midi.ocnt < MIDIOUTBUF-16)
  796. wake = 1;
  797. }
  798. if (wake)
  799. wake_up(&s->midi.owait);
  800. }
  801. static irqreturn_t sv_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  802. {
  803. struct sv_state *s = (struct sv_state *)dev_id;
  804. unsigned int intsrc;
  805. /* fastpath out, to ease interrupt sharing */
  806. intsrc = inb(s->ioenh + SV_CODEC_STATUS);
  807. if (!(intsrc & (SV_CSTAT_DMAA | SV_CSTAT_DMAC | SV_CSTAT_MIDI)))
  808. return IRQ_NONE;
  809. spin_lock(&s->lock);
  810. sv_update_ptr(s);
  811. sv_handle_midi(s);
  812. spin_unlock(&s->lock);
  813. return IRQ_HANDLED;
  814. }
  815. static void sv_midi_timer(unsigned long data)
  816. {
  817. struct sv_state *s = (struct sv_state *)data;
  818. unsigned long flags;
  819. spin_lock_irqsave(&s->lock, flags);
  820. sv_handle_midi(s);
  821. spin_unlock_irqrestore(&s->lock, flags);
  822. s->midi.timer.expires = jiffies+1;
  823. add_timer(&s->midi.timer);
  824. }
  825. /* --------------------------------------------------------------------- */
  826. static const char invalid_magic[] = KERN_CRIT "sv: invalid magic value\n";
  827. #define VALIDATE_STATE(s) \
  828. ({ \
  829. if (!(s) || (s)->magic != SV_MAGIC) { \
  830. printk(invalid_magic); \
  831. return -ENXIO; \
  832. } \
  833. })
  834. /* --------------------------------------------------------------------- */
  835. #define MT_4 1
  836. #define MT_5MUTE 2
  837. #define MT_4MUTEMONO 3
  838. #define MT_6MUTE 4
  839. static const struct {
  840. unsigned left:5;
  841. unsigned right:5;
  842. unsigned type:3;
  843. unsigned rec:3;
  844. } mixtable[SOUND_MIXER_NRDEVICES] = {
  845. [SOUND_MIXER_RECLEV] = { SV_CIMIX_ADCINL, SV_CIMIX_ADCINR, MT_4, 0 },
  846. [SOUND_MIXER_LINE1] = { SV_CIMIX_AUX1INL, SV_CIMIX_AUX1INR, MT_5MUTE, 5 },
  847. [SOUND_MIXER_CD] = { SV_CIMIX_CDINL, SV_CIMIX_CDINR, MT_5MUTE, 1 },
  848. [SOUND_MIXER_LINE] = { SV_CIMIX_LINEINL, SV_CIMIX_LINEINR, MT_5MUTE, 4 },
  849. [SOUND_MIXER_MIC] = { SV_CIMIX_MICIN, SV_CIMIX_ADCINL, MT_4MUTEMONO, 6 },
  850. [SOUND_MIXER_SYNTH] = { SV_CIMIX_SYNTHINL, SV_CIMIX_SYNTHINR, MT_5MUTE, 2 },
  851. [SOUND_MIXER_LINE2] = { SV_CIMIX_AUX2INL, SV_CIMIX_AUX2INR, MT_5MUTE, 3 },
  852. [SOUND_MIXER_VOLUME] = { SV_CIMIX_ANALOGINL, SV_CIMIX_ANALOGINR, MT_5MUTE, 7 },
  853. [SOUND_MIXER_PCM] = { SV_CIMIX_PCMINL, SV_CIMIX_PCMINR, MT_6MUTE, 0 }
  854. };
  855. #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
  856. static int return_mixval(struct sv_state *s, unsigned i, int *arg)
  857. {
  858. unsigned long flags;
  859. unsigned char l, r, rl, rr;
  860. spin_lock_irqsave(&s->lock, flags);
  861. l = rdindir(s, mixtable[i].left);
  862. r = rdindir(s, mixtable[i].right);
  863. spin_unlock_irqrestore(&s->lock, flags);
  864. switch (mixtable[i].type) {
  865. case MT_4:
  866. r &= 0xf;
  867. l &= 0xf;
  868. rl = 10 + 6 * (l & 15);
  869. rr = 10 + 6 * (r & 15);
  870. break;
  871. case MT_4MUTEMONO:
  872. rl = 55 - 3 * (l & 15);
  873. if (r & 0x10)
  874. rl += 45;
  875. rr = rl;
  876. r = l;
  877. break;
  878. case MT_5MUTE:
  879. default:
  880. rl = 100 - 3 * (l & 31);
  881. rr = 100 - 3 * (r & 31);
  882. break;
  883. case MT_6MUTE:
  884. rl = 100 - 3 * (l & 63) / 2;
  885. rr = 100 - 3 * (r & 63) / 2;
  886. break;
  887. }
  888. if (l & 0x80)
  889. rl = 0;
  890. if (r & 0x80)
  891. rr = 0;
  892. return put_user((rr << 8) | rl, arg);
  893. }
  894. #else /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  895. static const unsigned char volidx[SOUND_MIXER_NRDEVICES] =
  896. {
  897. [SOUND_MIXER_RECLEV] = 1,
  898. [SOUND_MIXER_LINE1] = 2,
  899. [SOUND_MIXER_CD] = 3,
  900. [SOUND_MIXER_LINE] = 4,
  901. [SOUND_MIXER_MIC] = 5,
  902. [SOUND_MIXER_SYNTH] = 6,
  903. [SOUND_MIXER_LINE2] = 7,
  904. [SOUND_MIXER_VOLUME] = 8,
  905. [SOUND_MIXER_PCM] = 9
  906. };
  907. #endif /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  908. static unsigned mixer_recmask(struct sv_state *s)
  909. {
  910. unsigned long flags;
  911. int i, j;
  912. spin_lock_irqsave(&s->lock, flags);
  913. j = rdindir(s, SV_CIMIX_ADCINL) >> 5;
  914. spin_unlock_irqrestore(&s->lock, flags);
  915. j &= 7;
  916. for (i = 0; i < SOUND_MIXER_NRDEVICES && mixtable[i].rec != j; i++);
  917. return 1 << i;
  918. }
  919. static int mixer_ioctl(struct sv_state *s, unsigned int cmd, unsigned long arg)
  920. {
  921. unsigned long flags;
  922. int i, val;
  923. unsigned char l, r, rl, rr;
  924. int __user *p = (int __user *)arg;
  925. VALIDATE_STATE(s);
  926. if (cmd == SOUND_MIXER_INFO) {
  927. mixer_info info;
  928. memset(&info, 0, sizeof(info));
  929. strlcpy(info.id, "SonicVibes", sizeof(info.id));
  930. strlcpy(info.name, "S3 SonicVibes", sizeof(info.name));
  931. info.modify_counter = s->mix.modcnt;
  932. if (copy_to_user((void __user *)arg, &info, sizeof(info)))
  933. return -EFAULT;
  934. return 0;
  935. }
  936. if (cmd == SOUND_OLD_MIXER_INFO) {
  937. _old_mixer_info info;
  938. memset(&info, 0, sizeof(info));
  939. strlcpy(info.id, "SonicVibes", sizeof(info.id));
  940. strlcpy(info.name, "S3 SonicVibes", sizeof(info.name));
  941. if (copy_to_user((void __user *)arg, &info, sizeof(info)))
  942. return -EFAULT;
  943. return 0;
  944. }
  945. if (cmd == OSS_GETVERSION)
  946. return put_user(SOUND_VERSION, p);
  947. if (cmd == SOUND_MIXER_PRIVATE1) { /* SRS settings */
  948. if (get_user(val, p))
  949. return -EFAULT;
  950. spin_lock_irqsave(&s->lock, flags);
  951. if (val & 1) {
  952. if (val & 2) {
  953. l = 4 - ((val >> 2) & 7);
  954. if (l & ~3)
  955. l = 4;
  956. r = 4 - ((val >> 5) & 7);
  957. if (r & ~3)
  958. r = 4;
  959. wrindir(s, SV_CISRSSPACE, l);
  960. wrindir(s, SV_CISRSCENTER, r);
  961. } else
  962. wrindir(s, SV_CISRSSPACE, 0x80);
  963. }
  964. l = rdindir(s, SV_CISRSSPACE);
  965. r = rdindir(s, SV_CISRSCENTER);
  966. spin_unlock_irqrestore(&s->lock, flags);
  967. if (l & 0x80)
  968. return put_user(0, p);
  969. return put_user(((4 - (l & 7)) << 2) | ((4 - (r & 7)) << 5) | 2, p);
  970. }
  971. if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
  972. return -EINVAL;
  973. if (_SIOC_DIR(cmd) == _SIOC_READ) {
  974. switch (_IOC_NR(cmd)) {
  975. case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
  976. return put_user(mixer_recmask(s), p);
  977. case SOUND_MIXER_DEVMASK: /* Arg contains a bit for each supported device */
  978. for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
  979. if (mixtable[i].type)
  980. val |= 1 << i;
  981. return put_user(val, p);
  982. case SOUND_MIXER_RECMASK: /* Arg contains a bit for each supported recording source */
  983. for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
  984. if (mixtable[i].rec)
  985. val |= 1 << i;
  986. return put_user(val, p);
  987. case SOUND_MIXER_STEREODEVS: /* Mixer channels supporting stereo */
  988. for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
  989. if (mixtable[i].type && mixtable[i].type != MT_4MUTEMONO)
  990. val |= 1 << i;
  991. return put_user(val, p);
  992. case SOUND_MIXER_CAPS:
  993. return put_user(SOUND_CAP_EXCL_INPUT, p);
  994. default:
  995. i = _IOC_NR(cmd);
  996. if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].type)
  997. return -EINVAL;
  998. #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
  999. return return_mixval(s, i, p);
  1000. #else /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  1001. if (!volidx[i])
  1002. return -EINVAL;
  1003. return put_user(s->mix.vol[volidx[i]-1], p);
  1004. #endif /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  1005. }
  1006. }
  1007. if (_SIOC_DIR(cmd) != (_SIOC_READ|_SIOC_WRITE))
  1008. return -EINVAL;
  1009. s->mix.modcnt++;
  1010. switch (_IOC_NR(cmd)) {
  1011. case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
  1012. if (get_user(val, p))
  1013. return -EFAULT;
  1014. i = hweight32(val);
  1015. if (i == 0)
  1016. return 0; /*val = mixer_recmask(s);*/
  1017. else if (i > 1)
  1018. val &= ~mixer_recmask(s);
  1019. for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
  1020. if (!(val & (1 << i)))
  1021. continue;
  1022. if (mixtable[i].rec)
  1023. break;
  1024. }
  1025. if (i == SOUND_MIXER_NRDEVICES)
  1026. return 0;
  1027. spin_lock_irqsave(&s->lock, flags);
  1028. frobindir(s, SV_CIMIX_ADCINL, 0x1f, mixtable[i].rec << 5);
  1029. frobindir(s, SV_CIMIX_ADCINR, 0x1f, mixtable[i].rec << 5);
  1030. spin_unlock_irqrestore(&s->lock, flags);
  1031. return 0;
  1032. default:
  1033. i = _IOC_NR(cmd);
  1034. if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].type)
  1035. return -EINVAL;
  1036. if (get_user(val, p))
  1037. return -EFAULT;
  1038. l = val & 0xff;
  1039. r = (val >> 8) & 0xff;
  1040. if (mixtable[i].type == MT_4MUTEMONO)
  1041. l = (r + l) / 2;
  1042. if (l > 100)
  1043. l = 100;
  1044. if (r > 100)
  1045. r = 100;
  1046. spin_lock_irqsave(&s->lock, flags);
  1047. switch (mixtable[i].type) {
  1048. case MT_4:
  1049. if (l >= 10)
  1050. l -= 10;
  1051. if (r >= 10)
  1052. r -= 10;
  1053. frobindir(s, mixtable[i].left, 0xf0, l / 6);
  1054. frobindir(s, mixtable[i].right, 0xf0, l / 6);
  1055. break;
  1056. case MT_4MUTEMONO:
  1057. rr = 0;
  1058. if (l < 10)
  1059. rl = 0x80;
  1060. else {
  1061. if (l >= 55) {
  1062. rr = 0x10;
  1063. l -= 45;
  1064. }
  1065. rl = (55 - l) / 3;
  1066. }
  1067. wrindir(s, mixtable[i].left, rl);
  1068. frobindir(s, mixtable[i].right, ~0x10, rr);
  1069. break;
  1070. case MT_5MUTE:
  1071. if (l < 7)
  1072. rl = 0x80;
  1073. else
  1074. rl = (100 - l) / 3;
  1075. if (r < 7)
  1076. rr = 0x80;
  1077. else
  1078. rr = (100 - r) / 3;
  1079. wrindir(s, mixtable[i].left, rl);
  1080. wrindir(s, mixtable[i].right, rr);
  1081. break;
  1082. case MT_6MUTE:
  1083. if (l < 6)
  1084. rl = 0x80;
  1085. else
  1086. rl = (100 - l) * 2 / 3;
  1087. if (r < 6)
  1088. rr = 0x80;
  1089. else
  1090. rr = (100 - r) * 2 / 3;
  1091. wrindir(s, mixtable[i].left, rl);
  1092. wrindir(s, mixtable[i].right, rr);
  1093. break;
  1094. }
  1095. spin_unlock_irqrestore(&s->lock, flags);
  1096. #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
  1097. return return_mixval(s, i, p);
  1098. #else /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  1099. if (!volidx[i])
  1100. return -EINVAL;
  1101. s->mix.vol[volidx[i]-1] = val;
  1102. return put_user(s->mix.vol[volidx[i]-1], p);
  1103. #endif /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  1104. }
  1105. }
  1106. /* --------------------------------------------------------------------- */
  1107. static int sv_open_mixdev(struct inode *inode, struct file *file)
  1108. {
  1109. int minor = iminor(inode);
  1110. struct list_head *list;
  1111. struct sv_state *s;
  1112. for (list = devs.next; ; list = list->next) {
  1113. if (list == &devs)
  1114. return -ENODEV;
  1115. s = list_entry(list, struct sv_state, devs);
  1116. if (s->dev_mixer == minor)
  1117. break;
  1118. }
  1119. VALIDATE_STATE(s);
  1120. file->private_data = s;
  1121. return nonseekable_open(inode, file);
  1122. }
  1123. static int sv_release_mixdev(struct inode *inode, struct file *file)
  1124. {
  1125. struct sv_state *s = (struct sv_state *)file->private_data;
  1126. VALIDATE_STATE(s);
  1127. return 0;
  1128. }
  1129. static int sv_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
  1130. {
  1131. return mixer_ioctl((struct sv_state *)file->private_data, cmd, arg);
  1132. }
  1133. static /*const*/ struct file_operations sv_mixer_fops = {
  1134. .owner = THIS_MODULE,
  1135. .llseek = no_llseek,
  1136. .ioctl = sv_ioctl_mixdev,
  1137. .open = sv_open_mixdev,
  1138. .release = sv_release_mixdev,
  1139. };
  1140. /* --------------------------------------------------------------------- */
  1141. static int drain_dac(struct sv_state *s, int nonblock)
  1142. {
  1143. DECLARE_WAITQUEUE(wait, current);
  1144. unsigned long flags;
  1145. int count, tmo;
  1146. if (s->dma_dac.mapped || !s->dma_dac.ready)
  1147. return 0;
  1148. add_wait_queue(&s->dma_dac.wait, &wait);
  1149. for (;;) {
  1150. __set_current_state(TASK_INTERRUPTIBLE);
  1151. spin_lock_irqsave(&s->lock, flags);
  1152. count = s->dma_dac.count;
  1153. spin_unlock_irqrestore(&s->lock, flags);
  1154. if (count <= 0)
  1155. break;
  1156. if (signal_pending(current))
  1157. break;
  1158. if (nonblock) {
  1159. remove_wait_queue(&s->dma_dac.wait, &wait);
  1160. set_current_state(TASK_RUNNING);
  1161. return -EBUSY;
  1162. }
  1163. tmo = 3 * HZ * (count + s->dma_dac.fragsize) / 2 / s->ratedac;
  1164. tmo >>= sample_shift[(s->fmt >> SV_CFMT_ASHIFT) & SV_CFMT_MASK];
  1165. if (!schedule_timeout(tmo + 1))
  1166. printk(KERN_DEBUG "sv: dma timed out??\n");
  1167. }
  1168. remove_wait_queue(&s->dma_dac.wait, &wait);
  1169. set_current_state(TASK_RUNNING);
  1170. if (signal_pending(current))
  1171. return -ERESTARTSYS;
  1172. return 0;
  1173. }
  1174. /* --------------------------------------------------------------------- */
  1175. static ssize_t sv_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
  1176. {
  1177. struct sv_state *s = (struct sv_state *)file->private_data;
  1178. DECLARE_WAITQUEUE(wait, current);
  1179. ssize_t ret;
  1180. unsigned long flags;
  1181. unsigned swptr;
  1182. int cnt;
  1183. VALIDATE_STATE(s);
  1184. if (s->dma_adc.mapped)
  1185. return -ENXIO;
  1186. if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
  1187. return ret;
  1188. if (!access_ok(VERIFY_WRITE, buffer, count))
  1189. return -EFAULT;
  1190. ret = 0;
  1191. #if 0
  1192. spin_lock_irqsave(&s->lock, flags);
  1193. sv_update_ptr(s);
  1194. spin_unlock_irqrestore(&s->lock, flags);
  1195. #endif
  1196. add_wait_queue(&s->dma_adc.wait, &wait);
  1197. while (count > 0) {
  1198. spin_lock_irqsave(&s->lock, flags);
  1199. swptr = s->dma_adc.swptr;
  1200. cnt = s->dma_adc.dmasize-swptr;
  1201. if (s->dma_adc.count < cnt)
  1202. cnt = s->dma_adc.count;
  1203. if (cnt <= 0)
  1204. __set_current_state(TASK_INTERRUPTIBLE);
  1205. spin_unlock_irqrestore(&s->lock, flags);
  1206. if (cnt > count)
  1207. cnt = count;
  1208. if (cnt <= 0) {
  1209. if (s->dma_adc.enabled)
  1210. start_adc(s);
  1211. if (file->f_flags & O_NONBLOCK) {
  1212. if (!ret)
  1213. ret = -EAGAIN;
  1214. break;
  1215. }
  1216. if (!schedule_timeout(HZ)) {
  1217. printk(KERN_DEBUG "sv: read: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
  1218. s->dma_adc.dmasize, s->dma_adc.fragsize, s->dma_adc.count,
  1219. s->dma_adc.hwptr, s->dma_adc.swptr);
  1220. stop_adc(s);
  1221. spin_lock_irqsave(&s->lock, flags);
  1222. set_dmac(s, virt_to_bus(s->dma_adc.rawbuf), s->dma_adc.numfrag << s->dma_adc.fragshift);
  1223. /* program enhanced mode registers */
  1224. wrindir(s, SV_CIDMACBASECOUNT1, (s->dma_adc.fragsamples-1) >> 8);
  1225. wrindir(s, SV_CIDMACBASECOUNT0, s->dma_adc.fragsamples-1);
  1226. s->dma_adc.count = s->dma_adc.hwptr = s->dma_adc.swptr = 0;
  1227. spin_unlock_irqrestore(&s->lock, flags);
  1228. }
  1229. if (signal_pending(current)) {
  1230. if (!ret)
  1231. ret = -ERESTARTSYS;
  1232. break;
  1233. }
  1234. continue;
  1235. }
  1236. if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
  1237. if (!ret)
  1238. ret = -EFAULT;
  1239. break;
  1240. }
  1241. swptr = (swptr + cnt) % s->dma_adc.dmasize;
  1242. spin_lock_irqsave(&s->lock, flags);
  1243. s->dma_adc.swptr = swptr;
  1244. s->dma_adc.count -= cnt;
  1245. spin_unlock_irqrestore(&s->lock, flags);
  1246. count -= cnt;
  1247. buffer += cnt;
  1248. ret += cnt;
  1249. if (s->dma_adc.enabled)
  1250. start_adc(s);
  1251. }
  1252. remove_wait_queue(&s->dma_adc.wait, &wait);
  1253. set_current_state(TASK_RUNNING);
  1254. return ret;
  1255. }
  1256. static ssize_t sv_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
  1257. {
  1258. struct sv_state *s = (struct sv_state *)file->private_data;
  1259. DECLARE_WAITQUEUE(wait, current);
  1260. ssize_t ret;
  1261. unsigned long flags;
  1262. unsigned swptr;
  1263. int cnt;
  1264. VALIDATE_STATE(s);
  1265. if (s->dma_dac.mapped)
  1266. return -ENXIO;
  1267. if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
  1268. return ret;
  1269. if (!access_ok(VERIFY_READ, buffer, count))
  1270. return -EFAULT;
  1271. ret = 0;
  1272. #if 0
  1273. spin_lock_irqsave(&s->lock, flags);
  1274. sv_update_ptr(s);
  1275. spin_unlock_irqrestore(&s->lock, flags);
  1276. #endif
  1277. add_wait_queue(&s->dma_dac.wait, &wait);
  1278. while (count > 0) {
  1279. spin_lock_irqsave(&s->lock, flags);
  1280. if (s->dma_dac.count < 0) {
  1281. s->dma_dac.count = 0;
  1282. s->dma_dac.swptr = s->dma_dac.hwptr;
  1283. }
  1284. swptr = s->dma_dac.swptr;
  1285. cnt = s->dma_dac.dmasize-swptr;
  1286. if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
  1287. cnt = s->dma_dac.dmasize - s->dma_dac.count;
  1288. if (cnt <= 0)
  1289. __set_current_state(TASK_INTERRUPTIBLE);
  1290. spin_unlock_irqrestore(&s->lock, flags);
  1291. if (cnt > count)
  1292. cnt = count;
  1293. if (cnt <= 0) {
  1294. if (s->dma_dac.enabled)
  1295. start_dac(s);
  1296. if (file->f_flags & O_NONBLOCK) {
  1297. if (!ret)
  1298. ret = -EAGAIN;
  1299. break;
  1300. }
  1301. if (!schedule_timeout(HZ)) {
  1302. printk(KERN_DEBUG "sv: write: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
  1303. s->dma_dac.dmasize, s->dma_dac.fragsize, s->dma_dac.count,
  1304. s->dma_dac.hwptr, s->dma_dac.swptr);
  1305. stop_dac(s);
  1306. spin_lock_irqsave(&s->lock, flags);
  1307. set_dmaa(s, virt_to_bus(s->dma_dac.rawbuf), s->dma_dac.numfrag << s->dma_dac.fragshift);
  1308. /* program enhanced mode registers */
  1309. wrindir(s, SV_CIDMAABASECOUNT1, (s->dma_dac.fragsamples-1) >> 8);
  1310. wrindir(s, SV_CIDMAABASECOUNT0, s->dma_dac.fragsamples-1);
  1311. s->dma_dac.count = s->dma_dac.hwptr = s->dma_dac.swptr = 0;
  1312. spin_unlock_irqrestore(&s->lock, flags);
  1313. }
  1314. if (signal_pending(current)) {
  1315. if (!ret)
  1316. ret = -ERESTARTSYS;
  1317. break;
  1318. }
  1319. continue;
  1320. }
  1321. if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
  1322. if (!ret)
  1323. ret = -EFAULT;
  1324. break;
  1325. }
  1326. swptr = (swptr + cnt) % s->dma_dac.dmasize;
  1327. spin_lock_irqsave(&s->lock, flags);
  1328. s->dma_dac.swptr = swptr;
  1329. s->dma_dac.count += cnt;
  1330. s->dma_dac.endcleared = 0;
  1331. spin_unlock_irqrestore(&s->lock, flags);
  1332. count -= cnt;
  1333. buffer += cnt;
  1334. ret += cnt;
  1335. if (s->dma_dac.enabled)
  1336. start_dac(s);
  1337. }
  1338. remove_wait_queue(&s->dma_dac.wait, &wait);
  1339. set_current_state(TASK_RUNNING);
  1340. return ret;
  1341. }
  1342. /* No kernel lock - we have our own spinlock */
  1343. static unsigned int sv_poll(struct file *file, struct poll_table_struct *wait)
  1344. {
  1345. struct sv_state *s = (struct sv_state *)file->private_data;
  1346. unsigned long flags;
  1347. unsigned int mask = 0;
  1348. VALIDATE_STATE(s);
  1349. if (file->f_mode & FMODE_WRITE) {
  1350. if (!s->dma_dac.ready && prog_dmabuf(s, 1))
  1351. return 0;
  1352. poll_wait(file, &s->dma_dac.wait, wait);
  1353. }
  1354. if (file->f_mode & FMODE_READ) {
  1355. if (!s->dma_adc.ready && prog_dmabuf(s, 0))
  1356. return 0;
  1357. poll_wait(file, &s->dma_adc.wait, wait);
  1358. }
  1359. spin_lock_irqsave(&s->lock, flags);
  1360. sv_update_ptr(s);
  1361. if (file->f_mode & FMODE_READ) {
  1362. if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
  1363. mask |= POLLIN | POLLRDNORM;
  1364. }
  1365. if (file->f_mode & FMODE_WRITE) {
  1366. if (s->dma_dac.mapped) {
  1367. if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
  1368. mask |= POLLOUT | POLLWRNORM;
  1369. } else {
  1370. if ((signed)s->dma_dac.dmasize >= s->dma_dac.count + (signed)s->dma_dac.fragsize)
  1371. mask |= POLLOUT | POLLWRNORM;
  1372. }
  1373. }
  1374. spin_unlock_irqrestore(&s->lock, flags);
  1375. return mask;
  1376. }
  1377. static int sv_mmap(struct file *file, struct vm_area_struct *vma)
  1378. {
  1379. struct sv_state *s = (struct sv_state *)file->private_data;
  1380. struct dmabuf *db;
  1381. int ret = -EINVAL;
  1382. unsigned long size;
  1383. VALIDATE_STATE(s);
  1384. lock_kernel();
  1385. if (vma->vm_flags & VM_WRITE) {
  1386. if ((ret = prog_dmabuf(s, 1)) != 0)
  1387. goto out;
  1388. db = &s->dma_dac;
  1389. } else if (vma->vm_flags & VM_READ) {
  1390. if ((ret = prog_dmabuf(s, 0)) != 0)
  1391. goto out;
  1392. db = &s->dma_adc;
  1393. } else
  1394. goto out;
  1395. ret = -EINVAL;
  1396. if (vma->vm_pgoff != 0)
  1397. goto out;
  1398. size = vma->vm_end - vma->vm_start;
  1399. if (size > (PAGE_SIZE << db->buforder))
  1400. goto out;
  1401. ret = -EAGAIN;
  1402. if (remap_pfn_range(vma, vma->vm_start,
  1403. virt_to_phys(db->rawbuf) >> PAGE_SHIFT,
  1404. size, vma->vm_page_prot))
  1405. goto out;
  1406. db->mapped = 1;
  1407. ret = 0;
  1408. out:
  1409. unlock_kernel();
  1410. return ret;
  1411. }
  1412. static int sv_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
  1413. {
  1414. struct sv_state *s = (struct sv_state *)file->private_data;
  1415. unsigned long flags;
  1416. audio_buf_info abinfo;
  1417. count_info cinfo;
  1418. int count;
  1419. int val, mapped, ret;
  1420. unsigned char fmtm, fmtd;
  1421. void __user *argp = (void __user *)arg;
  1422. int __user *p = argp;
  1423. VALIDATE_STATE(s);
  1424. mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
  1425. ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
  1426. switch (cmd) {
  1427. case OSS_GETVERSION:
  1428. return put_user(SOUND_VERSION, p);
  1429. case SNDCTL_DSP_SYNC:
  1430. if (file->f_mode & FMODE_WRITE)
  1431. return drain_dac(s, 0/*file->f_flags & O_NONBLOCK*/);
  1432. return 0;
  1433. case SNDCTL_DSP_SETDUPLEX:
  1434. return 0;
  1435. case SNDCTL_DSP_GETCAPS:
  1436. return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
  1437. case SNDCTL_DSP_RESET:
  1438. if (file->f_mode & FMODE_WRITE) {
  1439. stop_dac(s);
  1440. synchronize_irq(s->irq);
  1441. s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0;
  1442. }
  1443. if (file->f_mode & FMODE_READ) {
  1444. stop_adc(s);
  1445. synchronize_irq(s->irq);
  1446. s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
  1447. }
  1448. return 0;
  1449. case SNDCTL_DSP_SPEED:
  1450. if (get_user(val, p))
  1451. return -EFAULT;
  1452. if (val >= 0) {
  1453. if (file->f_mode & FMODE_READ) {
  1454. stop_adc(s);
  1455. s->dma_adc.ready = 0;
  1456. set_adc_rate(s, val);
  1457. }
  1458. if (file->f_mode & FMODE_WRITE) {
  1459. stop_dac(s);
  1460. s->dma_dac.ready = 0;
  1461. set_dac_rate(s, val);
  1462. }
  1463. }
  1464. return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
  1465. case SNDCTL_DSP_STEREO:
  1466. if (get_user(val, p))
  1467. return -EFAULT;
  1468. fmtd = 0;
  1469. fmtm = ~0;
  1470. if (file->f_mode & FMODE_READ) {
  1471. stop_adc(s);
  1472. s->dma_adc.ready = 0;
  1473. if (val)
  1474. fmtd |= SV_CFMT_STEREO << SV_CFMT_CSHIFT;
  1475. else
  1476. fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_CSHIFT);
  1477. }
  1478. if (file->f_mode & FMODE_WRITE) {
  1479. stop_dac(s);
  1480. s->dma_dac.ready = 0;
  1481. if (val)
  1482. fmtd |= SV_CFMT_STEREO << SV_CFMT_ASHIFT;
  1483. else
  1484. fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_ASHIFT);
  1485. }
  1486. set_fmt(s, fmtm, fmtd);
  1487. return 0;
  1488. case SNDCTL_DSP_CHANNELS:
  1489. if (get_user(val, p))
  1490. return -EFAULT;
  1491. if (val != 0) {
  1492. fmtd = 0;
  1493. fmtm = ~0;
  1494. if (file->f_mode & FMODE_READ) {
  1495. stop_adc(s);
  1496. s->dma_adc.ready = 0;
  1497. if (val >= 2)
  1498. fmtd |= SV_CFMT_STEREO << SV_CFMT_CSHIFT;
  1499. else
  1500. fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_CSHIFT);
  1501. }
  1502. if (file->f_mode & FMODE_WRITE) {
  1503. stop_dac(s);
  1504. s->dma_dac.ready = 0;
  1505. if (val >= 2)
  1506. fmtd |= SV_CFMT_STEREO << SV_CFMT_ASHIFT;
  1507. else
  1508. fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_ASHIFT);
  1509. }
  1510. set_fmt(s, fmtm, fmtd);
  1511. }
  1512. return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_STEREO << SV_CFMT_CSHIFT)
  1513. : (SV_CFMT_STEREO << SV_CFMT_ASHIFT))) ? 2 : 1, p);
  1514. case SNDCTL_DSP_GETFMTS: /* Returns a mask */
  1515. return put_user(AFMT_S16_LE|AFMT_U8, p);
  1516. case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
  1517. if (get_user(val, p))
  1518. return -EFAULT;
  1519. if (val != AFMT_QUERY) {
  1520. fmtd = 0;
  1521. fmtm = ~0;
  1522. if (file->f_mode & FMODE_READ) {
  1523. stop_adc(s);
  1524. s->dma_adc.ready = 0;
  1525. if (val == AFMT_S16_LE)
  1526. fmtd |= SV_CFMT_16BIT << SV_CFMT_CSHIFT;
  1527. else
  1528. fmtm &= ~(SV_CFMT_16BIT << SV_CFMT_CSHIFT);
  1529. }
  1530. if (file->f_mode & FMODE_WRITE) {
  1531. stop_dac(s);
  1532. s->dma_dac.ready = 0;
  1533. if (val == AFMT_S16_LE)
  1534. fmtd |= SV_CFMT_16BIT << SV_CFMT_ASHIFT;
  1535. else
  1536. fmtm &= ~(SV_CFMT_16BIT << SV_CFMT_ASHIFT);
  1537. }
  1538. set_fmt(s, fmtm, fmtd);
  1539. }
  1540. return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_16BIT << SV_CFMT_CSHIFT)
  1541. : (SV_CFMT_16BIT << SV_CFMT_ASHIFT))) ? AFMT_S16_LE : AFMT_U8, p);
  1542. case SNDCTL_DSP_POST:
  1543. return 0;
  1544. case SNDCTL_DSP_GETTRIGGER:
  1545. val = 0;
  1546. if (file->f_mode & FMODE_READ && s->enable & SV_CENABLE_RE)
  1547. val |= PCM_ENABLE_INPUT;
  1548. if (file->f_mode & FMODE_WRITE && s->enable & SV_CENABLE_PE)
  1549. val |= PCM_ENABLE_OUTPUT;
  1550. return put_user(val, p);
  1551. case SNDCTL_DSP_SETTRIGGER:
  1552. if (get_user(val, p))
  1553. return -EFAULT;
  1554. if (file->f_mode & FMODE_READ) {
  1555. if (val & PCM_ENABLE_INPUT) {
  1556. if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
  1557. return ret;
  1558. s->dma_adc.enabled = 1;
  1559. start_adc(s);
  1560. } else {
  1561. s->dma_adc.enabled = 0;
  1562. stop_adc(s);
  1563. }
  1564. }
  1565. if (file->f_mode & FMODE_WRITE) {
  1566. if (val & PCM_ENABLE_OUTPUT) {
  1567. if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
  1568. return ret;
  1569. s->dma_dac.enabled = 1;
  1570. start_dac(s);
  1571. } else {
  1572. s->dma_dac.enabled = 0;
  1573. stop_dac(s);
  1574. }
  1575. }
  1576. return 0;
  1577. case SNDCTL_DSP_GETOSPACE:
  1578. if (!(file->f_mode & FMODE_WRITE))
  1579. return -EINVAL;
  1580. if (!s->dma_dac.ready && (val = prog_dmabuf(s, 0)) != 0)
  1581. return val;
  1582. spin_lock_irqsave(&s->lock, flags);
  1583. sv_update_ptr(s);
  1584. abinfo.fragsize = s->dma_dac.fragsize;
  1585. count = s->dma_dac.count;
  1586. if (count < 0)
  1587. count = 0;
  1588. abinfo.bytes = s->dma_dac.dmasize - count;
  1589. abinfo.fragstotal = s->dma_dac.numfrag;
  1590. abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
  1591. spin_unlock_irqrestore(&s->lock, flags);
  1592. return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
  1593. case SNDCTL_DSP_GETISPACE:
  1594. if (!(file->f_mode & FMODE_READ))
  1595. return -EINVAL;
  1596. if (!s->dma_adc.ready && (val = prog_dmabuf(s, 1)) != 0)
  1597. return val;
  1598. spin_lock_irqsave(&s->lock, flags);
  1599. sv_update_ptr(s);
  1600. abinfo.fragsize = s->dma_adc.fragsize;
  1601. count = s->dma_adc.count;
  1602. if (count < 0)
  1603. count = 0;
  1604. abinfo.bytes = count;
  1605. abinfo.fragstotal = s->dma_adc.numfrag;
  1606. abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
  1607. spin_unlock_irqrestore(&s->lock, flags);
  1608. return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
  1609. case SNDCTL_DSP_NONBLOCK:
  1610. file->f_flags |= O_NONBLOCK;
  1611. return 0;
  1612. case SNDCTL_DSP_GETODELAY:
  1613. if (!(file->f_mode & FMODE_WRITE))
  1614. return -EINVAL;
  1615. if (!s->dma_dac.ready && (val = prog_dmabuf(s, 0)) != 0)
  1616. return val;
  1617. spin_lock_irqsave(&s->lock, flags);
  1618. sv_update_ptr(s);
  1619. count = s->dma_dac.count;
  1620. spin_unlock_irqrestore(&s->lock, flags);
  1621. if (count < 0)
  1622. count = 0;
  1623. return put_user(count, p);
  1624. case SNDCTL_DSP_GETIPTR:
  1625. if (!(file->f_mode & FMODE_READ))
  1626. return -EINVAL;
  1627. if (!s->dma_adc.ready && (val = prog_dmabuf(s, 1)) != 0)
  1628. return val;
  1629. spin_lock_irqsave(&s->lock, flags);
  1630. sv_update_ptr(s);
  1631. cinfo.bytes = s->dma_adc.total_bytes;
  1632. count = s->dma_adc.count;
  1633. if (count < 0)
  1634. count = 0;
  1635. cinfo.blocks = count >> s->dma_adc.fragshift;
  1636. cinfo.ptr = s->dma_adc.hwptr;
  1637. if (s->dma_adc.mapped)
  1638. s->dma_adc.count &= s->dma_adc.fragsize-1;
  1639. spin_unlock_irqrestore(&s->lock, flags);
  1640. if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
  1641. return -EFAULT;
  1642. return 0;
  1643. case SNDCTL_DSP_GETOPTR:
  1644. if (!(file->f_mode & FMODE_WRITE))
  1645. return -EINVAL;
  1646. if (!s->dma_dac.ready && (val = prog_dmabuf(s, 0)) != 0)
  1647. return val;
  1648. spin_lock_irqsave(&s->lock, flags);
  1649. sv_update_ptr(s);
  1650. cinfo.bytes = s->dma_dac.total_bytes;
  1651. count = s->dma_dac.count;
  1652. if (count < 0)
  1653. count = 0;
  1654. cinfo.blocks = count >> s->dma_dac.fragshift;
  1655. cinfo.ptr = s->dma_dac.hwptr;
  1656. if (s->dma_dac.mapped)
  1657. s->dma_dac.count &= s->dma_dac.fragsize-1;
  1658. spin_unlock_irqrestore(&s->lock, flags);
  1659. if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
  1660. return -EFAULT;
  1661. return 0;
  1662. case SNDCTL_DSP_GETBLKSIZE:
  1663. if (file->f_mode & FMODE_WRITE) {
  1664. if ((val = prog_dmabuf(s, 0)))
  1665. return val;
  1666. return put_user(s->dma_dac.fragsize, p);
  1667. }
  1668. if ((val = prog_dmabuf(s, 1)))
  1669. return val;
  1670. return put_user(s->dma_adc.fragsize, p);
  1671. case SNDCTL_DSP_SETFRAGMENT:
  1672. if (get_user(val, p))
  1673. return -EFAULT;
  1674. if (file->f_mode & FMODE_READ) {
  1675. s->dma_adc.ossfragshift = val & 0xffff;
  1676. s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
  1677. if (s->dma_adc.ossfragshift < 4)
  1678. s->dma_adc.ossfragshift = 4;
  1679. if (s->dma_adc.ossfragshift > 15)
  1680. s->dma_adc.ossfragshift = 15;
  1681. if (s->dma_adc.ossmaxfrags < 4)
  1682. s->dma_adc.ossmaxfrags = 4;
  1683. }
  1684. if (file->f_mode & FMODE_WRITE) {
  1685. s->dma_dac.ossfragshift = val & 0xffff;
  1686. s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
  1687. if (s->dma_dac.ossfragshift < 4)
  1688. s->dma_dac.ossfragshift = 4;
  1689. if (s->dma_dac.ossfragshift > 15)
  1690. s->dma_dac.ossfragshift = 15;
  1691. if (s->dma_dac.ossmaxfrags < 4)
  1692. s->dma_dac.ossmaxfrags = 4;
  1693. }
  1694. return 0;
  1695. case SNDCTL_DSP_SUBDIVIDE:
  1696. if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
  1697. (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
  1698. return -EINVAL;
  1699. if (get_user(val, p))
  1700. return -EFAULT;
  1701. if (val != 1 && val != 2 && val != 4)
  1702. return -EINVAL;
  1703. if (file->f_mode & FMODE_READ)
  1704. s->dma_adc.subdivision = val;
  1705. if (file->f_mode & FMODE_WRITE)
  1706. s->dma_dac.subdivision = val;
  1707. return 0;
  1708. case SOUND_PCM_READ_RATE:
  1709. return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
  1710. case SOUND_PCM_READ_CHANNELS:
  1711. return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_STEREO << SV_CFMT_CSHIFT)
  1712. : (SV_CFMT_STEREO << SV_CFMT_ASHIFT))) ? 2 : 1, p);
  1713. case SOUND_PCM_READ_BITS:
  1714. return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_16BIT << SV_CFMT_CSHIFT)
  1715. : (SV_CFMT_16BIT << SV_CFMT_ASHIFT))) ? 16 : 8, p);
  1716. case SOUND_PCM_WRITE_FILTER:
  1717. case SNDCTL_DSP_SETSYNCRO:
  1718. case SOUND_PCM_READ_FILTER:
  1719. return -EINVAL;
  1720. }
  1721. return mixer_ioctl(s, cmd, arg);
  1722. }
  1723. static int sv_open(struct inode *inode, struct file *file)
  1724. {
  1725. int minor = iminor(inode);
  1726. DECLARE_WAITQUEUE(wait, current);
  1727. unsigned char fmtm = ~0, fmts = 0;
  1728. struct list_head *list;
  1729. struct sv_state *s;
  1730. for (list = devs.next; ; list = list->next) {
  1731. if (list == &devs)
  1732. return -ENODEV;
  1733. s = list_entry(list, struct sv_state, devs);
  1734. if (!((s->dev_audio ^ minor) & ~0xf))
  1735. break;
  1736. }
  1737. VALIDATE_STATE(s);
  1738. file->private_data = s;
  1739. /* wait for device to become free */
  1740. mutex_lock(&s->open_mutex);
  1741. while (s->open_mode & file->f_mode) {
  1742. if (file->f_flags & O_NONBLOCK) {
  1743. mutex_unlock(&s->open_mutex);
  1744. return -EBUSY;
  1745. }
  1746. add_wait_queue(&s->open_wait, &wait);
  1747. __set_current_state(TASK_INTERRUPTIBLE);
  1748. mutex_unlock(&s->open_mutex);
  1749. schedule();
  1750. remove_wait_queue(&s->open_wait, &wait);
  1751. set_current_state(TASK_RUNNING);
  1752. if (signal_pending(current))
  1753. return -ERESTARTSYS;
  1754. mutex_lock(&s->open_mutex);
  1755. }
  1756. if (file->f_mode & FMODE_READ) {
  1757. fmtm &= ~((SV_CFMT_STEREO | SV_CFMT_16BIT) << SV_CFMT_CSHIFT);
  1758. if ((minor & 0xf) == SND_DEV_DSP16)
  1759. fmts |= SV_CFMT_16BIT << SV_CFMT_CSHIFT;
  1760. s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
  1761. s->dma_adc.enabled = 1;
  1762. set_adc_rate(s, 8000);
  1763. }
  1764. if (file->f_mode & FMODE_WRITE) {
  1765. fmtm &= ~((SV_CFMT_STEREO | SV_CFMT_16BIT) << SV_CFMT_ASHIFT);
  1766. if ((minor & 0xf) == SND_DEV_DSP16)
  1767. fmts |= SV_CFMT_16BIT << SV_CFMT_ASHIFT;
  1768. s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0;
  1769. s->dma_dac.enabled = 1;
  1770. set_dac_rate(s, 8000);
  1771. }
  1772. set_fmt(s, fmtm, fmts);
  1773. s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
  1774. mutex_unlock(&s->open_mutex);
  1775. return nonseekable_open(inode, file);
  1776. }
  1777. static int sv_release(struct inode *inode, struct file *file)
  1778. {
  1779. struct sv_state *s = (struct sv_state *)file->private_data;
  1780. VALIDATE_STATE(s);
  1781. lock_kernel();
  1782. if (file->f_mode & FMODE_WRITE)
  1783. drain_dac(s, file->f_flags & O_NONBLOCK);
  1784. mutex_lock(&s->open_mutex);
  1785. if (file->f_mode & FMODE_WRITE) {
  1786. stop_dac(s);
  1787. dealloc_dmabuf(s, &s->dma_dac);
  1788. }
  1789. if (file->f_mode & FMODE_READ) {
  1790. stop_adc(s);
  1791. dealloc_dmabuf(s, &s->dma_adc);
  1792. }
  1793. s->open_mode &= ~(file->f_mode & (FMODE_READ|FMODE_WRITE));
  1794. wake_up(&s->open_wait);
  1795. mutex_unlock(&s->open_mutex);
  1796. unlock_kernel();
  1797. return 0;
  1798. }
  1799. static /*const*/ struct file_operations sv_audio_fops = {
  1800. .owner = THIS_MODULE,
  1801. .llseek = no_llseek,
  1802. .read = sv_read,
  1803. .write = sv_write,
  1804. .poll = sv_poll,
  1805. .ioctl = sv_ioctl,
  1806. .mmap = sv_mmap,
  1807. .open = sv_open,
  1808. .release = sv_release,
  1809. };
  1810. /* --------------------------------------------------------------------- */
  1811. static ssize_t sv_midi_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
  1812. {
  1813. struct sv_state *s = (struct sv_state *)file->private_data;
  1814. DECLARE_WAITQUEUE(wait, current);
  1815. ssize_t ret;
  1816. unsigned long flags;
  1817. unsigned ptr;
  1818. int cnt;
  1819. VALIDATE_STATE(s);
  1820. if (!access_ok(VERIFY_WRITE, buffer, count))
  1821. return -EFAULT;
  1822. if (count == 0)
  1823. return 0;
  1824. ret = 0;
  1825. add_wait_queue(&s->midi.iwait, &wait);
  1826. while (count > 0) {
  1827. spin_lock_irqsave(&s->lock, flags);
  1828. ptr = s->midi.ird;
  1829. cnt = MIDIINBUF - ptr;
  1830. if (s->midi.icnt < cnt)
  1831. cnt = s->midi.icnt;
  1832. if (cnt <= 0)
  1833. __set_current_state(TASK_INTERRUPTIBLE);
  1834. spin_unlock_irqrestore(&s->lock, flags);
  1835. if (cnt > count)
  1836. cnt = count;
  1837. if (cnt <= 0) {
  1838. if (file->f_flags & O_NONBLOCK) {
  1839. if (!ret)
  1840. ret = -EAGAIN;
  1841. break;
  1842. }
  1843. schedule();
  1844. if (signal_pending(current)) {
  1845. if (!ret)
  1846. ret = -ERESTARTSYS;
  1847. break;
  1848. }
  1849. continue;
  1850. }
  1851. if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
  1852. if (!ret)
  1853. ret = -EFAULT;
  1854. break;
  1855. }
  1856. ptr = (ptr + cnt) % MIDIINBUF;
  1857. spin_lock_irqsave(&s->lock, flags);
  1858. s->midi.ird = ptr;
  1859. s->midi.icnt -= cnt;
  1860. spin_unlock_irqrestore(&s->lock, flags);
  1861. count -= cnt;
  1862. buffer += cnt;
  1863. ret += cnt;
  1864. break;
  1865. }
  1866. __set_current_state(TASK_RUNNING);
  1867. remove_wait_queue(&s->midi.iwait, &wait);
  1868. return ret;
  1869. }
  1870. static ssize_t sv_midi_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
  1871. {
  1872. struct sv_state *s = (struct sv_state *)file->private_data;
  1873. DECLARE_WAITQUEUE(wait, current);
  1874. ssize_t ret;
  1875. unsigned long flags;
  1876. unsigned ptr;
  1877. int cnt;
  1878. VALIDATE_STATE(s);
  1879. if (!access_ok(VERIFY_READ, buffer, count))
  1880. return -EFAULT;
  1881. if (count == 0)
  1882. return 0;
  1883. ret = 0;
  1884. add_wait_queue(&s->midi.owait, &wait);
  1885. while (count > 0) {
  1886. spin_lock_irqsave(&s->lock, flags);
  1887. ptr = s->midi.owr;
  1888. cnt = MIDIOUTBUF - ptr;
  1889. if (s->midi.ocnt + cnt > MIDIOUTBUF)
  1890. cnt = MIDIOUTBUF - s->midi.ocnt;
  1891. if (cnt <= 0) {
  1892. __set_current_state(TASK_INTERRUPTIBLE);
  1893. sv_handle_midi(s);
  1894. }
  1895. spin_unlock_irqrestore(&s->lock, flags);
  1896. if (cnt > count)
  1897. cnt = count;
  1898. if (cnt <= 0) {
  1899. if (file->f_flags & O_NONBLOCK) {
  1900. if (!ret)
  1901. ret = -EAGAIN;
  1902. break;
  1903. }
  1904. schedule();
  1905. if (signal_pending(current)) {
  1906. if (!ret)
  1907. ret = -ERESTARTSYS;
  1908. break;
  1909. }
  1910. continue;
  1911. }
  1912. if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
  1913. if (!ret)
  1914. ret = -EFAULT;
  1915. break;
  1916. }
  1917. ptr = (ptr + cnt) % MIDIOUTBUF;
  1918. spin_lock_irqsave(&s->lock, flags);
  1919. s->midi.owr = ptr;
  1920. s->midi.ocnt += cnt;
  1921. spin_unlock_irqrestore(&s->lock, flags);
  1922. count -= cnt;
  1923. buffer += cnt;
  1924. ret += cnt;
  1925. spin_lock_irqsave(&s->lock, flags);
  1926. sv_handle_midi(s);
  1927. spin_unlock_irqrestore(&s->lock, flags);
  1928. }
  1929. __set_current_state(TASK_RUNNING);
  1930. remove_wait_queue(&s->midi.owait, &wait);
  1931. return ret;
  1932. }
  1933. /* No kernel lock - we have our own spinlock */
  1934. static unsigned int sv_midi_poll(struct file *file, struct poll_table_struct *wait)
  1935. {
  1936. struct sv_state *s = (struct sv_state *)file->private_data;
  1937. unsigned long flags;
  1938. unsigned int mask = 0;
  1939. VALIDATE_STATE(s);
  1940. if (file->f_mode & FMODE_WRITE)
  1941. poll_wait(file, &s->midi.owait, wait);
  1942. if (file->f_mode & FMODE_READ)
  1943. poll_wait(file, &s->midi.iwait, wait);
  1944. spin_lock_irqsave(&s->lock, flags);
  1945. if (file->f_mode & FMODE_READ) {
  1946. if (s->midi.icnt > 0)
  1947. mask |= POLLIN | POLLRDNORM;
  1948. }
  1949. if (file->f_mode & FMODE_WRITE) {
  1950. if (s->midi.ocnt < MIDIOUTBUF)
  1951. mask |= POLLOUT | POLLWRNORM;
  1952. }
  1953. spin_unlock_irqrestore(&s->lock, flags);
  1954. return mask;
  1955. }
  1956. static int sv_midi_open(struct inode *inode, struct file *file)
  1957. {
  1958. int minor = iminor(inode);
  1959. DECLARE_WAITQUEUE(wait, current);
  1960. unsigned long flags;
  1961. struct list_head *list;
  1962. struct sv_state *s;
  1963. for (list = devs.next; ; list = list->next) {
  1964. if (list == &devs)
  1965. return -ENODEV;
  1966. s = list_entry(list, struct sv_state, devs);
  1967. if (s->dev_midi == minor)
  1968. break;
  1969. }
  1970. VALIDATE_STATE(s);
  1971. file->private_data = s;
  1972. /* wait for device to become free */
  1973. mutex_lock(&s->open_mutex);
  1974. while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
  1975. if (file->f_flags & O_NONBLOCK) {
  1976. mutex_unlock(&s->open_mutex);
  1977. return -EBUSY;
  1978. }
  1979. add_wait_queue(&s->open_wait, &wait);
  1980. __set_current_state(TASK_INTERRUPTIBLE);
  1981. mutex_unlock(&s->open_mutex);
  1982. schedule();
  1983. remove_wait_queue(&s->open_wait, &wait);
  1984. set_current_state(TASK_RUNNING);
  1985. if (signal_pending(current))
  1986. return -ERESTARTSYS;
  1987. mutex_lock(&s->open_mutex);
  1988. }
  1989. spin_lock_irqsave(&s->lock, flags);
  1990. if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
  1991. s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
  1992. s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
  1993. //outb(inb(s->ioenh + SV_CODEC_CONTROL) | SV_CCTRL_WAVETABLE, s->ioenh + SV_CODEC_CONTROL);
  1994. outb(inb(s->ioenh + SV_CODEC_INTMASK) | SV_CINTMASK_MIDI, s->ioenh + SV_CODEC_INTMASK);
  1995. wrindir(s, SV_CIUARTCONTROL, 5); /* output MIDI data to external and internal synth */
  1996. wrindir(s, SV_CIWAVETABLESRC, 1); /* Wavetable in PC RAM */
  1997. outb(0xff, s->iomidi+1); /* reset command */
  1998. outb(0x3f, s->iomidi+1); /* uart command */
  1999. if (!(inb(s->iomidi+1) & 0x80))
  2000. inb(s->iomidi);
  2001. s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
  2002. init_timer(&s->midi.timer);
  2003. s->midi.timer.expires = jiffies+1;
  2004. s->midi.timer.data = (unsigned long)s;
  2005. s->midi.timer.function = sv_midi_timer;
  2006. add_timer(&s->midi.timer);
  2007. }
  2008. if (file->f_mode & FMODE_READ) {
  2009. s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
  2010. }
  2011. if (file->f_mode & FMODE_WRITE) {
  2012. s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
  2013. }
  2014. spin_unlock_irqrestore(&s->lock, flags);
  2015. s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
  2016. mutex_unlock(&s->open_mutex);
  2017. return nonseekable_open(inode, file);
  2018. }
  2019. static int sv_midi_release(struct inode *inode, struct file *file)
  2020. {
  2021. struct sv_state *s = (struct sv_state *)file->private_data;
  2022. DECLARE_WAITQUEUE(wait, current);
  2023. unsigned long flags;
  2024. unsigned count, tmo;
  2025. VALIDATE_STATE(s);
  2026. lock_kernel();
  2027. if (file->f_mode & FMODE_WRITE) {
  2028. add_wait_queue(&s->midi.owait, &wait);
  2029. for (;;) {
  2030. __set_current_state(TASK_INTERRUPTIBLE);
  2031. spin_lock_irqsave(&s->lock, flags);
  2032. count = s->midi.ocnt;
  2033. spin_unlock_irqrestore(&s->lock, flags);
  2034. if (count <= 0)
  2035. break;
  2036. if (signal_pending(current))
  2037. break;
  2038. if (file->f_flags & O_NONBLOCK) {
  2039. remove_wait_queue(&s->midi.owait, &wait);
  2040. set_current_state(TASK_RUNNING);
  2041. unlock_kernel();
  2042. return -EBUSY;
  2043. }
  2044. tmo = (count * HZ) / 3100;
  2045. if (!schedule_timeout(tmo ? : 1) && tmo)
  2046. printk(KERN_DEBUG "sv: midi timed out??\n");
  2047. }
  2048. remove_wait_queue(&s->midi.owait, &wait);
  2049. set_current_state(TASK_RUNNING);
  2050. }
  2051. mutex_lock(&s->open_mutex);
  2052. s->open_mode &= ~((file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE));
  2053. spin_lock_irqsave(&s->lock, flags);
  2054. if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
  2055. outb(inb(s->ioenh + SV_CODEC_INTMASK) & ~SV_CINTMASK_MIDI, s->ioenh + SV_CODEC_INTMASK);
  2056. del_timer(&s->midi.timer);
  2057. }
  2058. spin_unlock_irqrestore(&s->lock, flags);
  2059. wake_up(&s->open_wait);
  2060. mutex_unlock(&s->open_mutex);
  2061. unlock_kernel();
  2062. return 0;
  2063. }
  2064. static /*const*/ struct file_operations sv_midi_fops = {
  2065. .owner = THIS_MODULE,
  2066. .llseek = no_llseek,
  2067. .read = sv_midi_read,
  2068. .write = sv_midi_write,
  2069. .poll = sv_midi_poll,
  2070. .open = sv_midi_open,
  2071. .release = sv_midi_release,
  2072. };
  2073. /* --------------------------------------------------------------------- */
  2074. static int sv_dmfm_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
  2075. {
  2076. static const unsigned char op_offset[18] = {
  2077. 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
  2078. 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D,
  2079. 0x10, 0x11, 0x12, 0x13, 0x14, 0x15
  2080. };
  2081. struct sv_state *s = (struct sv_state *)file->private_data;
  2082. struct dm_fm_voice v;
  2083. struct dm_fm_note n;
  2084. struct dm_fm_params p;
  2085. unsigned int io;
  2086. unsigned int regb;
  2087. switch (cmd) {
  2088. case FM_IOCTL_RESET:
  2089. for (regb = 0xb0; regb < 0xb9; regb++) {
  2090. outb(regb, s->iosynth);
  2091. outb(0, s->iosynth+1);
  2092. outb(regb, s->iosynth+2);
  2093. outb(0, s->iosynth+3);
  2094. }
  2095. return 0;
  2096. case FM_IOCTL_PLAY_NOTE:
  2097. if (copy_from_user(&n, (void __user *)arg, sizeof(n)))
  2098. return -EFAULT;
  2099. if (n.voice >= 18)
  2100. return -EINVAL;
  2101. if (n.voice >= 9) {
  2102. regb = n.voice - 9;
  2103. io = s->iosynth+2;
  2104. } else {
  2105. regb = n.voice;
  2106. io = s->iosynth;
  2107. }
  2108. outb(0xa0 + regb, io);
  2109. outb(n.fnum & 0xff, io+1);
  2110. outb(0xb0 + regb, io);
  2111. outb(((n.fnum >> 8) & 3) | ((n.octave & 7) << 2) | ((n.key_on & 1) << 5), io+1);
  2112. return 0;
  2113. case FM_IOCTL_SET_VOICE:
  2114. if (copy_from_user(&v, (void __user *)arg, sizeof(v)))
  2115. return -EFAULT;
  2116. if (v.voice >= 18)
  2117. return -EINVAL;
  2118. regb = op_offset[v.voice];
  2119. io = s->iosynth + ((v.op & 1) << 1);
  2120. outb(0x20 + regb, io);
  2121. outb(((v.am & 1) << 7) | ((v.vibrato & 1) << 6) | ((v.do_sustain & 1) << 5) |
  2122. ((v.kbd_scale & 1) << 4) | (v.harmonic & 0xf), io+1);
  2123. outb(0x40 + regb, io);
  2124. outb(((v.scale_level & 0x3) << 6) | (v.volume & 0x3f), io+1);
  2125. outb(0x60 + regb, io);
  2126. outb(((v.attack & 0xf) << 4) | (v.decay & 0xf), io+1);
  2127. outb(0x80 + regb, io);
  2128. outb(((v.sustain & 0xf) << 4) | (v.release & 0xf), io+1);
  2129. outb(0xe0 + regb, io);
  2130. outb(v.waveform & 0x7, io+1);
  2131. if (n.voice >= 9) {
  2132. regb = n.voice - 9;
  2133. io = s->iosynth+2;
  2134. } else {
  2135. regb = n.voice;
  2136. io = s->iosynth;
  2137. }
  2138. outb(0xc0 + regb, io);
  2139. outb(((v.right & 1) << 5) | ((v.left & 1) << 4) | ((v.feedback & 7) << 1) |
  2140. (v.connection & 1), io+1);
  2141. return 0;
  2142. case FM_IOCTL_SET_PARAMS:
  2143. if (copy_from_user(&p, (void *__user )arg, sizeof(p)))
  2144. return -EFAULT;
  2145. outb(0x08, s->iosynth);
  2146. outb((p.kbd_split & 1) << 6, s->iosynth+1);
  2147. outb(0xbd, s->iosynth);
  2148. outb(((p.am_depth & 1) << 7) | ((p.vib_depth & 1) << 6) | ((p.rhythm & 1) << 5) | ((p.bass & 1) << 4) |
  2149. ((p.snare & 1) << 3) | ((p.tomtom & 1) << 2) | ((p.cymbal & 1) << 1) | (p.hihat & 1), s->iosynth+1);
  2150. return 0;
  2151. case FM_IOCTL_SET_OPL:
  2152. outb(4, s->iosynth+2);
  2153. outb(arg, s->iosynth+3);
  2154. return 0;
  2155. case FM_IOCTL_SET_MODE:
  2156. outb(5, s->iosynth+2);
  2157. outb(arg & 1, s->iosynth+3);
  2158. return 0;
  2159. default:
  2160. return -EINVAL;
  2161. }
  2162. }
  2163. static int sv_dmfm_open(struct inode *inode, struct file *file)
  2164. {
  2165. int minor = iminor(inode);
  2166. DECLARE_WAITQUEUE(wait, current);
  2167. struct list_head *list;
  2168. struct sv_state *s;
  2169. for (list = devs.next; ; list = list->next) {
  2170. if (list == &devs)
  2171. return -ENODEV;
  2172. s = list_entry(list, struct sv_state, devs);
  2173. if (s->dev_dmfm == minor)
  2174. break;
  2175. }
  2176. VALIDATE_STATE(s);
  2177. file->private_data = s;
  2178. /* wait for device to become free */
  2179. mutex_lock(&s->open_mutex);
  2180. while (s->open_mode & FMODE_DMFM) {
  2181. if (file->f_flags & O_NONBLOCK) {
  2182. mutex_unlock(&s->open_mutex);
  2183. return -EBUSY;
  2184. }
  2185. add_wait_queue(&s->open_wait, &wait);
  2186. __set_current_state(TASK_INTERRUPTIBLE);
  2187. mutex_unlock(&s->open_mutex);
  2188. schedule();
  2189. remove_wait_queue(&s->open_wait, &wait);
  2190. set_current_state(TASK_RUNNING);
  2191. if (signal_pending(current))
  2192. return -ERESTARTSYS;
  2193. mutex_lock(&s->open_mutex);
  2194. }
  2195. /* init the stuff */
  2196. outb(1, s->iosynth);
  2197. outb(0x20, s->iosynth+1); /* enable waveforms */
  2198. outb(4, s->iosynth+2);
  2199. outb(0, s->iosynth+3); /* no 4op enabled */
  2200. outb(5, s->iosynth+2);
  2201. outb(1, s->iosynth+3); /* enable OPL3 */
  2202. s->open_mode |= FMODE_DMFM;
  2203. mutex_unlock(&s->open_mutex);
  2204. return nonseekable_open(inode, file);
  2205. }
  2206. static int sv_dmfm_release(struct inode *inode, struct file *file)
  2207. {
  2208. struct sv_state *s = (struct sv_state *)file->private_data;
  2209. unsigned int regb;
  2210. VALIDATE_STATE(s);
  2211. lock_kernel();
  2212. mutex_lock(&s->open_mutex);
  2213. s->open_mode &= ~FMODE_DMFM;
  2214. for (regb = 0xb0; regb < 0xb9; regb++) {
  2215. outb(regb, s->iosynth);
  2216. outb(0, s->iosynth+1);
  2217. outb(regb, s->iosynth+2);
  2218. outb(0, s->iosynth+3);
  2219. }
  2220. wake_up(&s->open_wait);
  2221. mutex_unlock(&s->open_mutex);
  2222. unlock_kernel();
  2223. return 0;
  2224. }
  2225. static /*const*/ struct file_operations sv_dmfm_fops = {
  2226. .owner = THIS_MODULE,
  2227. .llseek = no_llseek,
  2228. .ioctl = sv_dmfm_ioctl,
  2229. .open = sv_dmfm_open,
  2230. .release = sv_dmfm_release,
  2231. };
  2232. /* --------------------------------------------------------------------- */
  2233. /* maximum number of devices; only used for command line params */
  2234. #define NR_DEVICE 5
  2235. static int reverb[NR_DEVICE];
  2236. #if 0
  2237. static int wavetable[NR_DEVICE];
  2238. #endif
  2239. static unsigned int devindex;
  2240. module_param_array(reverb, bool, NULL, 0);
  2241. MODULE_PARM_DESC(reverb, "if 1 enables the reverb circuitry. NOTE: your card must have the reverb RAM");
  2242. #if 0
  2243. MODULE_PARM(wavetable, "1-" __MODULE_STRING(NR_DEVICE) "i");
  2244. MODULE_PARM_DESC(wavetable, "if 1 the wavetable synth is enabled");
  2245. #endif
  2246. MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
  2247. MODULE_DESCRIPTION("S3 SonicVibes Driver");
  2248. MODULE_LICENSE("GPL");
  2249. /* --------------------------------------------------------------------- */
  2250. static struct initvol {
  2251. int mixch;
  2252. int vol;
  2253. } initvol[] __devinitdata = {
  2254. { SOUND_MIXER_WRITE_RECLEV, 0x4040 },
  2255. { SOUND_MIXER_WRITE_LINE1, 0x4040 },
  2256. { SOUND_MIXER_WRITE_CD, 0x4040 },
  2257. { SOUND_MIXER_WRITE_LINE, 0x4040 },
  2258. { SOUND_MIXER_WRITE_MIC, 0x4040 },
  2259. { SOUND_MIXER_WRITE_SYNTH, 0x4040 },
  2260. { SOUND_MIXER_WRITE_LINE2, 0x4040 },
  2261. { SOUND_MIXER_WRITE_VOLUME, 0x4040 },
  2262. { SOUND_MIXER_WRITE_PCM, 0x4040 }
  2263. };
  2264. #define RSRCISIOREGION(dev,num) (pci_resource_start((dev), (num)) != 0 && \
  2265. (pci_resource_flags((dev), (num)) & IORESOURCE_IO))
  2266. #ifdef SUPPORT_JOYSTICK
  2267. static int __devinit sv_register_gameport(struct sv_state *s, int io_port)
  2268. {
  2269. struct gameport *gp;
  2270. if (!request_region(io_port, SV_EXTENT_GAME, "S3 SonicVibes Gameport")) {
  2271. printk(KERN_ERR "sv: gameport io ports are in use\n");
  2272. return -EBUSY;
  2273. }
  2274. s->gameport = gp = gameport_allocate_port();
  2275. if (!gp) {
  2276. printk(KERN_ERR "sv: can not allocate memory for gameport\n");
  2277. release_region(io_port, SV_EXTENT_GAME);
  2278. return -ENOMEM;
  2279. }
  2280. gameport_set_name(gp, "S3 SonicVibes Gameport");
  2281. gameport_set_phys(gp, "isa%04x/gameport0", io_port);
  2282. gp->dev.parent = &s->dev->dev;
  2283. gp->io = io_port;
  2284. gameport_register_port(gp);
  2285. return 0;
  2286. }
  2287. static inline void sv_unregister_gameport(struct sv_state *s)
  2288. {
  2289. if (s->gameport) {
  2290. int gpio = s->gameport->io;
  2291. gameport_unregister_port(s->gameport);
  2292. release_region(gpio, SV_EXTENT_GAME);
  2293. }
  2294. }
  2295. #else
  2296. static inline int sv_register_gameport(struct sv_state *s, int io_port) { return -ENOSYS; }
  2297. static inline void sv_unregister_gameport(struct sv_state *s) { }
  2298. #endif /* SUPPORT_JOYSTICK */
  2299. static int __devinit sv_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
  2300. {
  2301. static char __devinitdata sv_ddma_name[] = "S3 Inc. SonicVibes DDMA Controller";
  2302. struct sv_state *s;
  2303. mm_segment_t fs;
  2304. int i, val, ret;
  2305. int gpio;
  2306. char *ddmaname;
  2307. unsigned ddmanamelen;
  2308. if ((ret=pci_enable_device(pcidev)))
  2309. return ret;
  2310. if (!RSRCISIOREGION(pcidev, RESOURCE_SB) ||
  2311. !RSRCISIOREGION(pcidev, RESOURCE_ENH) ||
  2312. !RSRCISIOREGION(pcidev, RESOURCE_SYNTH) ||
  2313. !RSRCISIOREGION(pcidev, RESOURCE_MIDI) ||
  2314. !RSRCISIOREGION(pcidev, RESOURCE_GAME))
  2315. return -ENODEV;
  2316. if (pcidev->irq == 0)
  2317. return -ENODEV;
  2318. if (pci_set_dma_mask(pcidev, 0x00ffffff)) {
  2319. printk(KERN_WARNING "sonicvibes: architecture does not support 24bit PCI busmaster DMA\n");
  2320. return -ENODEV;
  2321. }
  2322. /* try to allocate a DDMA resource if not already available */
  2323. if (!RSRCISIOREGION(pcidev, RESOURCE_DDMA)) {
  2324. pcidev->resource[RESOURCE_DDMA].start = 0;
  2325. pcidev->resource[RESOURCE_DDMA].end = 2*SV_EXTENT_DMA-1;
  2326. pcidev->resource[RESOURCE_DDMA].flags = PCI_BASE_ADDRESS_SPACE_IO | IORESOURCE_IO;
  2327. ddmanamelen = strlen(sv_ddma_name)+1;
  2328. if (!(ddmaname = kmalloc(ddmanamelen, GFP_KERNEL)))
  2329. return -1;
  2330. memcpy(ddmaname, sv_ddma_name, ddmanamelen);
  2331. pcidev->resource[RESOURCE_DDMA].name = ddmaname;
  2332. if (pci_assign_resource(pcidev, RESOURCE_DDMA)) {
  2333. pcidev->resource[RESOURCE_DDMA].name = NULL;
  2334. kfree(ddmaname);
  2335. printk(KERN_ERR "sv: cannot allocate DDMA controller io ports\n");
  2336. return -EBUSY;
  2337. }
  2338. }
  2339. if (!(s = kmalloc(sizeof(struct sv_state), GFP_KERNEL))) {
  2340. printk(KERN_WARNING "sv: out of memory\n");
  2341. return -ENOMEM;
  2342. }
  2343. memset(s, 0, sizeof(struct sv_state));
  2344. init_waitqueue_head(&s->dma_adc.wait);
  2345. init_waitqueue_head(&s->dma_dac.wait);
  2346. init_waitqueue_head(&s->open_wait);
  2347. init_waitqueue_head(&s->midi.iwait);
  2348. init_waitqueue_head(&s->midi.owait);
  2349. mutex_init(&s->open_mutex);
  2350. spin_lock_init(&s->lock);
  2351. s->magic = SV_MAGIC;
  2352. s->dev = pcidev;
  2353. s->iosb = pci_resource_start(pcidev, RESOURCE_SB);
  2354. s->ioenh = pci_resource_start(pcidev, RESOURCE_ENH);
  2355. s->iosynth = pci_resource_start(pcidev, RESOURCE_SYNTH);
  2356. s->iomidi = pci_resource_start(pcidev, RESOURCE_MIDI);
  2357. s->iodmaa = pci_resource_start(pcidev, RESOURCE_DDMA);
  2358. s->iodmac = pci_resource_start(pcidev, RESOURCE_DDMA) + SV_EXTENT_DMA;
  2359. gpio = pci_resource_start(pcidev, RESOURCE_GAME);
  2360. pci_write_config_dword(pcidev, 0x40, s->iodmaa | 9); /* enable and use extended mode */
  2361. pci_write_config_dword(pcidev, 0x48, s->iodmac | 9); /* enable */
  2362. printk(KERN_DEBUG "sv: io ports: %#lx %#lx %#lx %#lx %#x %#x %#x\n",
  2363. s->iosb, s->ioenh, s->iosynth, s->iomidi, gpio, s->iodmaa, s->iodmac);
  2364. s->irq = pcidev->irq;
  2365. /* hack */
  2366. pci_write_config_dword(pcidev, 0x60, wavetable_mem >> 12); /* wavetable base address */
  2367. ret = -EBUSY;
  2368. if (!request_region(s->ioenh, SV_EXTENT_ENH, "S3 SonicVibes PCM")) {
  2369. printk(KERN_ERR "sv: io ports %#lx-%#lx in use\n", s->ioenh, s->ioenh+SV_EXTENT_ENH-1);
  2370. goto err_region5;
  2371. }
  2372. if (!request_region(s->iodmaa, SV_EXTENT_DMA, "S3 SonicVibes DMAA")) {
  2373. printk(KERN_ERR "sv: io ports %#x-%#x in use\n", s->iodmaa, s->iodmaa+SV_EXTENT_DMA-1);
  2374. goto err_region4;
  2375. }
  2376. if (!request_region(s->iodmac, SV_EXTENT_DMA, "S3 SonicVibes DMAC")) {
  2377. printk(KERN_ERR "sv: io ports %#x-%#x in use\n", s->iodmac, s->iodmac+SV_EXTENT_DMA-1);
  2378. goto err_region3;
  2379. }
  2380. if (!request_region(s->iomidi, SV_EXTENT_MIDI, "S3 SonicVibes Midi")) {
  2381. printk(KERN_ERR "sv: io ports %#lx-%#lx in use\n", s->iomidi, s->iomidi+SV_EXTENT_MIDI-1);
  2382. goto err_region2;
  2383. }
  2384. if (!request_region(s->iosynth, SV_EXTENT_SYNTH, "S3 SonicVibes Synth")) {
  2385. printk(KERN_ERR "sv: io ports %#lx-%#lx in use\n", s->iosynth, s->iosynth+SV_EXTENT_SYNTH-1);
  2386. goto err_region1;
  2387. }
  2388. /* initialize codec registers */
  2389. outb(0x80, s->ioenh + SV_CODEC_CONTROL); /* assert reset */
  2390. udelay(50);
  2391. outb(0x00, s->ioenh + SV_CODEC_CONTROL); /* deassert reset */
  2392. udelay(50);
  2393. outb(SV_CCTRL_INTADRIVE | SV_CCTRL_ENHANCED /*| SV_CCTRL_WAVETABLE */
  2394. | (reverb[devindex] ? SV_CCTRL_REVERB : 0), s->ioenh + SV_CODEC_CONTROL);
  2395. inb(s->ioenh + SV_CODEC_STATUS); /* clear ints */
  2396. wrindir(s, SV_CIDRIVECONTROL, 0); /* drive current 16mA */
  2397. wrindir(s, SV_CIENABLE, s->enable = 0); /* disable DMAA and DMAC */
  2398. outb(~(SV_CINTMASK_DMAA | SV_CINTMASK_DMAC), s->ioenh + SV_CODEC_INTMASK);
  2399. /* outb(0xff, s->iodmaa + SV_DMA_RESET); */
  2400. /* outb(0xff, s->iodmac + SV_DMA_RESET); */
  2401. inb(s->ioenh + SV_CODEC_STATUS); /* ack interrupts */
  2402. wrindir(s, SV_CIADCCLKSOURCE, 0); /* use pll as ADC clock source */
  2403. wrindir(s, SV_CIANALOGPWRDOWN, 0); /* power up the analog parts of the device */
  2404. wrindir(s, SV_CIDIGITALPWRDOWN, 0); /* power up the digital parts of the device */
  2405. setpll(s, SV_CIADCPLLM, 8000);
  2406. wrindir(s, SV_CISRSSPACE, 0x80); /* SRS off */
  2407. wrindir(s, SV_CIPCMSR0, (8000 * 65536 / FULLRATE) & 0xff);
  2408. wrindir(s, SV_CIPCMSR1, ((8000 * 65536 / FULLRATE) >> 8) & 0xff);
  2409. wrindir(s, SV_CIADCOUTPUT, 0);
  2410. /* request irq */
  2411. if ((ret=request_irq(s->irq,sv_interrupt,SA_SHIRQ,"S3 SonicVibes",s))) {
  2412. printk(KERN_ERR "sv: irq %u in use\n", s->irq);
  2413. goto err_irq;
  2414. }
  2415. printk(KERN_INFO "sv: found adapter at io %#lx irq %u dmaa %#06x dmac %#06x revision %u\n",
  2416. s->ioenh, s->irq, s->iodmaa, s->iodmac, rdindir(s, SV_CIREVISION));
  2417. /* register devices */
  2418. if ((s->dev_audio = register_sound_dsp(&sv_audio_fops, -1)) < 0) {
  2419. ret = s->dev_audio;
  2420. goto err_dev1;
  2421. }
  2422. if ((s->dev_mixer = register_sound_mixer(&sv_mixer_fops, -1)) < 0) {
  2423. ret = s->dev_mixer;
  2424. goto err_dev2;
  2425. }
  2426. if ((s->dev_midi = register_sound_midi(&sv_midi_fops, -1)) < 0) {
  2427. ret = s->dev_midi;
  2428. goto err_dev3;
  2429. }
  2430. if ((s->dev_dmfm = register_sound_special(&sv_dmfm_fops, 15 /* ?? */)) < 0) {
  2431. ret = s->dev_dmfm;
  2432. goto err_dev4;
  2433. }
  2434. pci_set_master(pcidev); /* enable bus mastering */
  2435. /* initialize the chips */
  2436. fs = get_fs();
  2437. set_fs(KERNEL_DS);
  2438. val = SOUND_MASK_LINE|SOUND_MASK_SYNTH;
  2439. mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
  2440. for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
  2441. val = initvol[i].vol;
  2442. mixer_ioctl(s, initvol[i].mixch, (unsigned long)&val);
  2443. }
  2444. set_fs(fs);
  2445. /* register gameport */
  2446. sv_register_gameport(s, gpio);
  2447. /* store it in the driver field */
  2448. pci_set_drvdata(pcidev, s);
  2449. /* put it into driver list */
  2450. list_add_tail(&s->devs, &devs);
  2451. /* increment devindex */
  2452. if (devindex < NR_DEVICE-1)
  2453. devindex++;
  2454. return 0;
  2455. err_dev4:
  2456. unregister_sound_midi(s->dev_midi);
  2457. err_dev3:
  2458. unregister_sound_mixer(s->dev_mixer);
  2459. err_dev2:
  2460. unregister_sound_dsp(s->dev_audio);
  2461. err_dev1:
  2462. printk(KERN_ERR "sv: cannot register misc device\n");
  2463. free_irq(s->irq, s);
  2464. err_irq:
  2465. release_region(s->iosynth, SV_EXTENT_SYNTH);
  2466. err_region1:
  2467. release_region(s->iomidi, SV_EXTENT_MIDI);
  2468. err_region2:
  2469. release_region(s->iodmac, SV_EXTENT_DMA);
  2470. err_region3:
  2471. release_region(s->iodmaa, SV_EXTENT_DMA);
  2472. err_region4:
  2473. release_region(s->ioenh, SV_EXTENT_ENH);
  2474. err_region5:
  2475. kfree(s);
  2476. return ret;
  2477. }
  2478. static void __devexit sv_remove(struct pci_dev *dev)
  2479. {
  2480. struct sv_state *s = pci_get_drvdata(dev);
  2481. if (!s)
  2482. return;
  2483. list_del(&s->devs);
  2484. outb(~0, s->ioenh + SV_CODEC_INTMASK); /* disable ints */
  2485. synchronize_irq(s->irq);
  2486. inb(s->ioenh + SV_CODEC_STATUS); /* ack interrupts */
  2487. wrindir(s, SV_CIENABLE, 0); /* disable DMAA and DMAC */
  2488. /*outb(0, s->iodmaa + SV_DMA_RESET);*/
  2489. /*outb(0, s->iodmac + SV_DMA_RESET);*/
  2490. free_irq(s->irq, s);
  2491. sv_unregister_gameport(s);
  2492. release_region(s->iodmac, SV_EXTENT_DMA);
  2493. release_region(s->iodmaa, SV_EXTENT_DMA);
  2494. release_region(s->ioenh, SV_EXTENT_ENH);
  2495. release_region(s->iomidi, SV_EXTENT_MIDI);
  2496. release_region(s->iosynth, SV_EXTENT_SYNTH);
  2497. unregister_sound_dsp(s->dev_audio);
  2498. unregister_sound_mixer(s->dev_mixer);
  2499. unregister_sound_midi(s->dev_midi);
  2500. unregister_sound_special(s->dev_dmfm);
  2501. kfree(s);
  2502. pci_set_drvdata(dev, NULL);
  2503. }
  2504. static struct pci_device_id id_table[] = {
  2505. { PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_SONICVIBES, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
  2506. { 0, }
  2507. };
  2508. MODULE_DEVICE_TABLE(pci, id_table);
  2509. static struct pci_driver sv_driver = {
  2510. .name = "sonicvibes",
  2511. .id_table = id_table,
  2512. .probe = sv_probe,
  2513. .remove = __devexit_p(sv_remove),
  2514. };
  2515. static int __init init_sonicvibes(void)
  2516. {
  2517. printk(KERN_INFO "sv: version v0.31 time " __TIME__ " " __DATE__ "\n");
  2518. #if 0
  2519. if (!(wavetable_mem = __get_free_pages(GFP_KERNEL, 20-PAGE_SHIFT)))
  2520. printk(KERN_INFO "sv: cannot allocate 1MB of contiguous nonpageable memory for wavetable data\n");
  2521. #endif
  2522. return pci_register_driver(&sv_driver);
  2523. }
  2524. static void __exit cleanup_sonicvibes(void)
  2525. {
  2526. printk(KERN_INFO "sv: unloading\n");
  2527. pci_unregister_driver(&sv_driver);
  2528. if (wavetable_mem)
  2529. free_pages(wavetable_mem, 20-PAGE_SHIFT);
  2530. }
  2531. module_init(init_sonicvibes);
  2532. module_exit(cleanup_sonicvibes);
  2533. /* --------------------------------------------------------------------- */
  2534. #ifndef MODULE
  2535. /* format is: sonicvibes=[reverb] sonicvibesdmaio=dmaioaddr */
  2536. static int __init sonicvibes_setup(char *str)
  2537. {
  2538. static unsigned __initdata nr_dev = 0;
  2539. if (nr_dev >= NR_DEVICE)
  2540. return 0;
  2541. #if 0
  2542. if (get_option(&str, &reverb[nr_dev]) == 2)
  2543. (void)get_option(&str, &wavetable[nr_dev]);
  2544. #else
  2545. (void)get_option(&str, &reverb[nr_dev]);
  2546. #endif
  2547. nr_dev++;
  2548. return 1;
  2549. }
  2550. __setup("sonicvibes=", sonicvibes_setup);
  2551. #endif /* MODULE */