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arch
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arm
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plat-s3c64xx
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include
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plat
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regs-gpio.h

regs-gpio.h 3.6 KB
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  1. /* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h
    2. 

  2.  *
    3. 

  3.  * Copyright 2008 Openmoko, Inc.
    4. 

  4.  * Copyright 2008 Simtec Electronics
    5. 

  5.  *      Ben Dooks <ben@simtec.co.uk>
    6. 

  6.  *      http://armlinux.simtec.co.uk/
    7. 

  7.  *
    8. 

  8.  * S3C64XX - GPIO register definitions
    9. 

  9.  */
    10. 

  10. 

  11. #ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H
    12. 

  12. #define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__
    13. 

  13. 

  14. /* Base addresses for each of the banks */
    15. 

  15. 

  16. #define S3C64XX_GPIOREG(reg)	(S3C64XX_VA_GPIO + (reg))
    17. 

  17. 

  18. #define S3C64XX_GPA_BASE	S3C64XX_GPIOREG(0x0000)
    19. 

  19. #define S3C64XX_GPB_BASE	S3C64XX_GPIOREG(0x0020)
    20. 

  20. #define S3C64XX_GPC_BASE	S3C64XX_GPIOREG(0x0040)
    21. 

  21. #define S3C64XX_GPD_BASE	S3C64XX_GPIOREG(0x0060)
    22. 

  22. #define S3C64XX_GPE_BASE	S3C64XX_GPIOREG(0x0080)
    23. 

  23. #define S3C64XX_GPF_BASE	S3C64XX_GPIOREG(0x00A0)
    24. 

  24. #define S3C64XX_GPG_BASE	S3C64XX_GPIOREG(0x00C0)
    25. 

  25. #define S3C64XX_GPH_BASE	S3C64XX_GPIOREG(0x00E0)
    26. 

  26. #define S3C64XX_GPI_BASE	S3C64XX_GPIOREG(0x0100)
    27. 

  27. #define S3C64XX_GPJ_BASE	S3C64XX_GPIOREG(0x0120)
    28. 

  28. #define S3C64XX_GPK_BASE	S3C64XX_GPIOREG(0x0800)
    29. 

  29. #define S3C64XX_GPL_BASE	S3C64XX_GPIOREG(0x0810)
    30. 

  30. #define S3C64XX_GPM_BASE	S3C64XX_GPIOREG(0x0820)
    31. 

  31. #define S3C64XX_GPN_BASE	S3C64XX_GPIOREG(0x0830)
    32. 

  32. #define S3C64XX_GPO_BASE	S3C64XX_GPIOREG(0x0140)
    33. 

  33. #define S3C64XX_GPP_BASE	S3C64XX_GPIOREG(0x0160)
    34. 

  34. #define S3C64XX_GPQ_BASE	S3C64XX_GPIOREG(0x0180)
    35. 

  35. 

  36. /* SPCON */
    37. 

  37. 

  38. #define S3C64XX_SPCON		S3C64XX_GPIOREG(0x1A0)
    39. 

  39. 

  40. /* External interrupt registers */
    41. 

  41. 

  42. #define S3C64XX_EINT12CON	S3C64XX_GPIOREG(0x200)
    43. 

  43. #define S3C64XX_EINT34CON	S3C64XX_GPIOREG(0x204)
    44. 

  44. #define S3C64XX_EINT56CON	S3C64XX_GPIOREG(0x208)
    45. 

  45. #define S3C64XX_EINT78CON	S3C64XX_GPIOREG(0x20C)
    46. 

  46. #define S3C64XX_EINT9CON	S3C64XX_GPIOREG(0x210)
    47. 

  47. 

  48. #define S3C64XX_EINT12FLTCON	S3C64XX_GPIOREG(0x220)
    49. 

  49. #define S3C64XX_EINT34FLTCON	S3C64XX_GPIOREG(0x224)
    50. 

  50. #define S3C64XX_EINT56FLTCON	S3C64XX_GPIOREG(0x228)
    51. 

  51. #define S3C64XX_EINT78FLTCON	S3C64XX_GPIOREG(0x22C)
    52. 

  52. #define S3C64XX_EINT9FLTCON	S3C64XX_GPIOREG(0x230)
    53. 

  53. 

  54. #define S3C64XX_EINT12MASK	S3C64XX_GPIOREG(0x240)
    55. 

  55. #define S3C64XX_EINT34MASK	S3C64XX_GPIOREG(0x244)
    56. 

  56. #define S3C64XX_EINT56MASK	S3C64XX_GPIOREG(0x248)
    57. 

  57. #define S3C64XX_EINT78MASK	S3C64XX_GPIOREG(0x24C)
    58. 

  58. #define S3C64XX_EINT9MASK	S3C64XX_GPIOREG(0x250)
    59. 

  59. 

  60. #define S3C64XX_EINT12PEND	S3C64XX_GPIOREG(0x260)
    61. 

  61. #define S3C64XX_EINT34PEND	S3C64XX_GPIOREG(0x264)
    62. 

  62. #define S3C64XX_EINT56PEND	S3C64XX_GPIOREG(0x268)
    63. 

  63. #define S3C64XX_EINT78PEND	S3C64XX_GPIOREG(0x26C)
    64. 

  64. #define S3C64XX_EINT9PEND	S3C64XX_GPIOREG(0x270)
    65. 

  65. 

  66. #define S3C64XX_PRIORITY	S3C64XX_GPIOREG(0x280)
    67. 

  67. #define S3C64XX_PRIORITY_ARB(x)	(1 << (x))
    68. 

  68. 

  69. #define S3C64XX_SERVICE		S3C64XX_GPIOREG(0x284)
    70. 

  70. #define S3C64XX_SERVICEPEND	S3C64XX_GPIOREG(0x288)
    71. 

  71. 

  72. #define S3C64XX_EINT0CON0	S3C64XX_GPIOREG(0x900)
    73. 

  73. #define S3C64XX_EINT0CON1	S3C64XX_GPIOREG(0x904)
    74. 

  74. #define S3C64XX_EINT0FLTCON0	S3C64XX_GPIOREG(0x910)
    75. 

  75. #define S3C64XX_EINT0FLTCON1	S3C64XX_GPIOREG(0x914)
    76. 

  76. #define S3C64XX_EINT0FLTCON2	S3C64XX_GPIOREG(0x918)
    77. 

  77. #define S3C64XX_EINT0FLTCON3	S3C64XX_GPIOREG(0x91C)
    78. 

  78. 

  79. #define S3C64XX_EINT0MASK	S3C64XX_GPIOREG(0x920)
    80. 

  80. #define S3C64XX_EINT0PEND	S3C64XX_GPIOREG(0x924)
    81. 

  81. 

  82. /* GPIO sleep configuration */
    83. 

  83. 

  84. #define S3C64XX_SPCONSLP	S3C64XX_GPIOREG(0x880)
    85. 

  85. 

  86. #define S3C64XX_SPCONSLP_TDO_PULLDOWN	(1 << 14)
    87. 

  87. #define S3C64XX_SPCONSLP_CKE1INIT	(1 << 5)
    88. 

  88. 

  89. #define S3C64XX_SPCONSLP_RSTOUT_MASK	(0x3 << 12)
    90. 

  90. #define S3C64XX_SPCONSLP_RSTOUT_OUT0	(0x0 << 12)
    91. 

  91. #define S3C64XX_SPCONSLP_RSTOUT_OUT1	(0x1 << 12)
    92. 

  92. #define S3C64XX_SPCONSLP_RSTOUT_HIZ	(0x2 << 12)
    93. 

  93. 

  94. #define S3C64XX_SPCONSLP_KPCOL_MASK	(0x3 << 0)
    95. 

  95. #define S3C64XX_SPCONSLP_KPCOL_OUT0	(0x0 << 0)
    96. 

  96. #define S3C64XX_SPCONSLP_KPCOL_OUT1	(0x1 << 0)
    97. 

  97. #define S3C64XX_SPCONSLP_KPCOL_INP	(0x2 << 0)
    98. 

  98. 

  99. 

  100. #define S3C64XX_SLPEN		S3C64XX_GPIOREG(0x930)
    101. 

  101. 

  102. #define S3C64XX_SLPEN_USE_xSLP		(1 << 0)
    103. 

  103. #define S3C64XX_SLPEN_CFG_BYSLPEN	(1 << 1)
    104. 

  104. 

  105. #endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */
    106. 

  106.