cciss.c 140 KB

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  1. /*
  2. * Disk Array driver for HP Smart Array controllers.
  3. * (C) Copyright 2000, 2007 Hewlett-Packard Development Company, L.P.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; version 2 of the License.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  12. * General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  17. * 02111-1307, USA.
  18. *
  19. * Questions/Comments/Bugfixes to iss_storagedev@hp.com
  20. *
  21. */
  22. #include <linux/module.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/types.h>
  25. #include <linux/pci.h>
  26. #include <linux/kernel.h>
  27. #include <linux/slab.h>
  28. #include <linux/delay.h>
  29. #include <linux/major.h>
  30. #include <linux/fs.h>
  31. #include <linux/bio.h>
  32. #include <linux/blkpg.h>
  33. #include <linux/timer.h>
  34. #include <linux/proc_fs.h>
  35. #include <linux/seq_file.h>
  36. #include <linux/init.h>
  37. #include <linux/jiffies.h>
  38. #include <linux/hdreg.h>
  39. #include <linux/spinlock.h>
  40. #include <linux/compat.h>
  41. #include <linux/mutex.h>
  42. #include <asm/uaccess.h>
  43. #include <asm/io.h>
  44. #include <linux/dma-mapping.h>
  45. #include <linux/blkdev.h>
  46. #include <linux/genhd.h>
  47. #include <linux/completion.h>
  48. #include <scsi/scsi.h>
  49. #include <scsi/sg.h>
  50. #include <scsi/scsi_ioctl.h>
  51. #include <linux/cdrom.h>
  52. #include <linux/scatterlist.h>
  53. #include <linux/kthread.h>
  54. #define CCISS_DRIVER_VERSION(maj,min,submin) ((maj<<16)|(min<<8)|(submin))
  55. #define DRIVER_NAME "HP CISS Driver (v 3.6.26)"
  56. #define DRIVER_VERSION CCISS_DRIVER_VERSION(3, 6, 26)
  57. /* Embedded module documentation macros - see modules.h */
  58. MODULE_AUTHOR("Hewlett-Packard Company");
  59. MODULE_DESCRIPTION("Driver for HP Smart Array Controllers");
  60. MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
  61. MODULE_VERSION("3.6.26");
  62. MODULE_LICENSE("GPL");
  63. static DEFINE_MUTEX(cciss_mutex);
  64. static struct proc_dir_entry *proc_cciss;
  65. #include "cciss_cmd.h"
  66. #include "cciss.h"
  67. #include <linux/cciss_ioctl.h>
  68. /* define the PCI info for the cards we can control */
  69. static const struct pci_device_id cciss_pci_device_id[] = {
  70. {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISS, 0x0E11, 0x4070},
  71. {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSB, 0x0E11, 0x4080},
  72. {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSB, 0x0E11, 0x4082},
  73. {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSB, 0x0E11, 0x4083},
  74. {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x4091},
  75. {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x409A},
  76. {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x409B},
  77. {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x409C},
  78. {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x409D},
  79. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSA, 0x103C, 0x3225},
  80. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x3223},
  81. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x3234},
  82. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x3235},
  83. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3211},
  84. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3212},
  85. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3213},
  86. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3214},
  87. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3215},
  88. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x3237},
  89. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x323D},
  90. {0,}
  91. };
  92. MODULE_DEVICE_TABLE(pci, cciss_pci_device_id);
  93. /* board_id = Subsystem Device ID & Vendor ID
  94. * product = Marketing Name for the board
  95. * access = Address of the struct of function pointers
  96. */
  97. static struct board_type products[] = {
  98. {0x40700E11, "Smart Array 5300", &SA5_access},
  99. {0x40800E11, "Smart Array 5i", &SA5B_access},
  100. {0x40820E11, "Smart Array 532", &SA5B_access},
  101. {0x40830E11, "Smart Array 5312", &SA5B_access},
  102. {0x409A0E11, "Smart Array 641", &SA5_access},
  103. {0x409B0E11, "Smart Array 642", &SA5_access},
  104. {0x409C0E11, "Smart Array 6400", &SA5_access},
  105. {0x409D0E11, "Smart Array 6400 EM", &SA5_access},
  106. {0x40910E11, "Smart Array 6i", &SA5_access},
  107. {0x3225103C, "Smart Array P600", &SA5_access},
  108. {0x3223103C, "Smart Array P800", &SA5_access},
  109. {0x3234103C, "Smart Array P400", &SA5_access},
  110. {0x3235103C, "Smart Array P400i", &SA5_access},
  111. {0x3211103C, "Smart Array E200i", &SA5_access},
  112. {0x3212103C, "Smart Array E200", &SA5_access},
  113. {0x3213103C, "Smart Array E200i", &SA5_access},
  114. {0x3214103C, "Smart Array E200i", &SA5_access},
  115. {0x3215103C, "Smart Array E200i", &SA5_access},
  116. {0x3237103C, "Smart Array E500", &SA5_access},
  117. {0x3223103C, "Smart Array P800", &SA5_access},
  118. {0x3234103C, "Smart Array P400", &SA5_access},
  119. {0x323D103C, "Smart Array P700m", &SA5_access},
  120. };
  121. /* How long to wait (in milliseconds) for board to go into simple mode */
  122. #define MAX_CONFIG_WAIT 30000
  123. #define MAX_IOCTL_CONFIG_WAIT 1000
  124. /*define how many times we will try a command because of bus resets */
  125. #define MAX_CMD_RETRIES 3
  126. #define MAX_CTLR 32
  127. /* Originally cciss driver only supports 8 major numbers */
  128. #define MAX_CTLR_ORIG 8
  129. static ctlr_info_t *hba[MAX_CTLR];
  130. static struct task_struct *cciss_scan_thread;
  131. static DEFINE_MUTEX(scan_mutex);
  132. static LIST_HEAD(scan_q);
  133. static void do_cciss_request(struct request_queue *q);
  134. static irqreturn_t do_cciss_intx(int irq, void *dev_id);
  135. static irqreturn_t do_cciss_msix_intr(int irq, void *dev_id);
  136. static int cciss_open(struct block_device *bdev, fmode_t mode);
  137. static int cciss_unlocked_open(struct block_device *bdev, fmode_t mode);
  138. static int cciss_release(struct gendisk *disk, fmode_t mode);
  139. static int do_ioctl(struct block_device *bdev, fmode_t mode,
  140. unsigned int cmd, unsigned long arg);
  141. static int cciss_ioctl(struct block_device *bdev, fmode_t mode,
  142. unsigned int cmd, unsigned long arg);
  143. static int cciss_getgeo(struct block_device *bdev, struct hd_geometry *geo);
  144. static int cciss_revalidate(struct gendisk *disk);
  145. static int rebuild_lun_table(ctlr_info_t *h, int first_time, int via_ioctl);
  146. static int deregister_disk(ctlr_info_t *h, int drv_index,
  147. int clear_all, int via_ioctl);
  148. static void cciss_read_capacity(ctlr_info_t *h, int logvol,
  149. sector_t *total_size, unsigned int *block_size);
  150. static void cciss_read_capacity_16(ctlr_info_t *h, int logvol,
  151. sector_t *total_size, unsigned int *block_size);
  152. static void cciss_geometry_inquiry(ctlr_info_t *h, int logvol,
  153. sector_t total_size,
  154. unsigned int block_size, InquiryData_struct *inq_buff,
  155. drive_info_struct *drv);
  156. static void __devinit cciss_interrupt_mode(ctlr_info_t *);
  157. static void start_io(ctlr_info_t *h);
  158. static int sendcmd_withirq(ctlr_info_t *h, __u8 cmd, void *buff, size_t size,
  159. __u8 page_code, unsigned char scsi3addr[],
  160. int cmd_type);
  161. static int sendcmd_withirq_core(ctlr_info_t *h, CommandList_struct *c,
  162. int attempt_retry);
  163. static int process_sendcmd_error(ctlr_info_t *h, CommandList_struct *c);
  164. static int add_to_scan_list(struct ctlr_info *h);
  165. static int scan_thread(void *data);
  166. static int check_for_unit_attention(ctlr_info_t *h, CommandList_struct *c);
  167. static void cciss_hba_release(struct device *dev);
  168. static void cciss_device_release(struct device *dev);
  169. static void cciss_free_gendisk(ctlr_info_t *h, int drv_index);
  170. static void cciss_free_drive_info(ctlr_info_t *h, int drv_index);
  171. static inline u32 next_command(ctlr_info_t *h);
  172. static int __devinit cciss_find_cfg_addrs(struct pci_dev *pdev,
  173. void __iomem *vaddr, u32 *cfg_base_addr, u64 *cfg_base_addr_index,
  174. u64 *cfg_offset);
  175. static int __devinit cciss_pci_find_memory_BAR(struct pci_dev *pdev,
  176. unsigned long *memory_bar);
  177. static inline u32 cciss_tag_discard_error_bits(ctlr_info_t *h, u32 tag);
  178. static __devinit int write_driver_ver_to_cfgtable(
  179. CfgTable_struct __iomem *cfgtable);
  180. /* performant mode helper functions */
  181. static void calc_bucket_map(int *bucket, int num_buckets, int nsgs,
  182. int *bucket_map);
  183. static void cciss_put_controller_into_performant_mode(ctlr_info_t *h);
  184. #ifdef CONFIG_PROC_FS
  185. static void cciss_procinit(ctlr_info_t *h);
  186. #else
  187. static void cciss_procinit(ctlr_info_t *h)
  188. {
  189. }
  190. #endif /* CONFIG_PROC_FS */
  191. #ifdef CONFIG_COMPAT
  192. static int cciss_compat_ioctl(struct block_device *, fmode_t,
  193. unsigned, unsigned long);
  194. #endif
  195. static const struct block_device_operations cciss_fops = {
  196. .owner = THIS_MODULE,
  197. .open = cciss_unlocked_open,
  198. .release = cciss_release,
  199. .ioctl = do_ioctl,
  200. .getgeo = cciss_getgeo,
  201. #ifdef CONFIG_COMPAT
  202. .compat_ioctl = cciss_compat_ioctl,
  203. #endif
  204. .revalidate_disk = cciss_revalidate,
  205. };
  206. /* set_performant_mode: Modify the tag for cciss performant
  207. * set bit 0 for pull model, bits 3-1 for block fetch
  208. * register number
  209. */
  210. static void set_performant_mode(ctlr_info_t *h, CommandList_struct *c)
  211. {
  212. if (likely(h->transMethod & CFGTBL_Trans_Performant))
  213. c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
  214. }
  215. /*
  216. * Enqueuing and dequeuing functions for cmdlists.
  217. */
  218. static inline void addQ(struct list_head *list, CommandList_struct *c)
  219. {
  220. list_add_tail(&c->list, list);
  221. }
  222. static inline void removeQ(CommandList_struct *c)
  223. {
  224. /*
  225. * After kexec/dump some commands might still
  226. * be in flight, which the firmware will try
  227. * to complete. Resetting the firmware doesn't work
  228. * with old fw revisions, so we have to mark
  229. * them off as 'stale' to prevent the driver from
  230. * falling over.
  231. */
  232. if (WARN_ON(list_empty(&c->list))) {
  233. c->cmd_type = CMD_MSG_STALE;
  234. return;
  235. }
  236. list_del_init(&c->list);
  237. }
  238. static void enqueue_cmd_and_start_io(ctlr_info_t *h,
  239. CommandList_struct *c)
  240. {
  241. unsigned long flags;
  242. set_performant_mode(h, c);
  243. spin_lock_irqsave(&h->lock, flags);
  244. addQ(&h->reqQ, c);
  245. h->Qdepth++;
  246. if (h->Qdepth > h->maxQsinceinit)
  247. h->maxQsinceinit = h->Qdepth;
  248. start_io(h);
  249. spin_unlock_irqrestore(&h->lock, flags);
  250. }
  251. static void cciss_free_sg_chain_blocks(SGDescriptor_struct **cmd_sg_list,
  252. int nr_cmds)
  253. {
  254. int i;
  255. if (!cmd_sg_list)
  256. return;
  257. for (i = 0; i < nr_cmds; i++) {
  258. kfree(cmd_sg_list[i]);
  259. cmd_sg_list[i] = NULL;
  260. }
  261. kfree(cmd_sg_list);
  262. }
  263. static SGDescriptor_struct **cciss_allocate_sg_chain_blocks(
  264. ctlr_info_t *h, int chainsize, int nr_cmds)
  265. {
  266. int j;
  267. SGDescriptor_struct **cmd_sg_list;
  268. if (chainsize <= 0)
  269. return NULL;
  270. cmd_sg_list = kmalloc(sizeof(*cmd_sg_list) * nr_cmds, GFP_KERNEL);
  271. if (!cmd_sg_list)
  272. return NULL;
  273. /* Build up chain blocks for each command */
  274. for (j = 0; j < nr_cmds; j++) {
  275. /* Need a block of chainsized s/g elements. */
  276. cmd_sg_list[j] = kmalloc((chainsize *
  277. sizeof(*cmd_sg_list[j])), GFP_KERNEL);
  278. if (!cmd_sg_list[j]) {
  279. dev_err(&h->pdev->dev, "Cannot get memory "
  280. "for s/g chains.\n");
  281. goto clean;
  282. }
  283. }
  284. return cmd_sg_list;
  285. clean:
  286. cciss_free_sg_chain_blocks(cmd_sg_list, nr_cmds);
  287. return NULL;
  288. }
  289. static void cciss_unmap_sg_chain_block(ctlr_info_t *h, CommandList_struct *c)
  290. {
  291. SGDescriptor_struct *chain_sg;
  292. u64bit temp64;
  293. if (c->Header.SGTotal <= h->max_cmd_sgentries)
  294. return;
  295. chain_sg = &c->SG[h->max_cmd_sgentries - 1];
  296. temp64.val32.lower = chain_sg->Addr.lower;
  297. temp64.val32.upper = chain_sg->Addr.upper;
  298. pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
  299. }
  300. static void cciss_map_sg_chain_block(ctlr_info_t *h, CommandList_struct *c,
  301. SGDescriptor_struct *chain_block, int len)
  302. {
  303. SGDescriptor_struct *chain_sg;
  304. u64bit temp64;
  305. chain_sg = &c->SG[h->max_cmd_sgentries - 1];
  306. chain_sg->Ext = CCISS_SG_CHAIN;
  307. chain_sg->Len = len;
  308. temp64.val = pci_map_single(h->pdev, chain_block, len,
  309. PCI_DMA_TODEVICE);
  310. chain_sg->Addr.lower = temp64.val32.lower;
  311. chain_sg->Addr.upper = temp64.val32.upper;
  312. }
  313. #include "cciss_scsi.c" /* For SCSI tape support */
  314. static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
  315. "UNKNOWN"
  316. };
  317. #define RAID_UNKNOWN (ARRAY_SIZE(raid_label)-1)
  318. #ifdef CONFIG_PROC_FS
  319. /*
  320. * Report information about this controller.
  321. */
  322. #define ENG_GIG 1000000000
  323. #define ENG_GIG_FACTOR (ENG_GIG/512)
  324. #define ENGAGE_SCSI "engage scsi"
  325. static void cciss_seq_show_header(struct seq_file *seq)
  326. {
  327. ctlr_info_t *h = seq->private;
  328. seq_printf(seq, "%s: HP %s Controller\n"
  329. "Board ID: 0x%08lx\n"
  330. "Firmware Version: %c%c%c%c\n"
  331. "IRQ: %d\n"
  332. "Logical drives: %d\n"
  333. "Current Q depth: %d\n"
  334. "Current # commands on controller: %d\n"
  335. "Max Q depth since init: %d\n"
  336. "Max # commands on controller since init: %d\n"
  337. "Max SG entries since init: %d\n",
  338. h->devname,
  339. h->product_name,
  340. (unsigned long)h->board_id,
  341. h->firm_ver[0], h->firm_ver[1], h->firm_ver[2],
  342. h->firm_ver[3], (unsigned int)h->intr[PERF_MODE_INT],
  343. h->num_luns,
  344. h->Qdepth, h->commands_outstanding,
  345. h->maxQsinceinit, h->max_outstanding, h->maxSG);
  346. #ifdef CONFIG_CISS_SCSI_TAPE
  347. cciss_seq_tape_report(seq, h);
  348. #endif /* CONFIG_CISS_SCSI_TAPE */
  349. }
  350. static void *cciss_seq_start(struct seq_file *seq, loff_t *pos)
  351. {
  352. ctlr_info_t *h = seq->private;
  353. unsigned long flags;
  354. /* prevent displaying bogus info during configuration
  355. * or deconfiguration of a logical volume
  356. */
  357. spin_lock_irqsave(&h->lock, flags);
  358. if (h->busy_configuring) {
  359. spin_unlock_irqrestore(&h->lock, flags);
  360. return ERR_PTR(-EBUSY);
  361. }
  362. h->busy_configuring = 1;
  363. spin_unlock_irqrestore(&h->lock, flags);
  364. if (*pos == 0)
  365. cciss_seq_show_header(seq);
  366. return pos;
  367. }
  368. static int cciss_seq_show(struct seq_file *seq, void *v)
  369. {
  370. sector_t vol_sz, vol_sz_frac;
  371. ctlr_info_t *h = seq->private;
  372. unsigned ctlr = h->ctlr;
  373. loff_t *pos = v;
  374. drive_info_struct *drv = h->drv[*pos];
  375. if (*pos > h->highest_lun)
  376. return 0;
  377. if (drv == NULL) /* it's possible for h->drv[] to have holes. */
  378. return 0;
  379. if (drv->heads == 0)
  380. return 0;
  381. vol_sz = drv->nr_blocks;
  382. vol_sz_frac = sector_div(vol_sz, ENG_GIG_FACTOR);
  383. vol_sz_frac *= 100;
  384. sector_div(vol_sz_frac, ENG_GIG_FACTOR);
  385. if (drv->raid_level < 0 || drv->raid_level > RAID_UNKNOWN)
  386. drv->raid_level = RAID_UNKNOWN;
  387. seq_printf(seq, "cciss/c%dd%d:"
  388. "\t%4u.%02uGB\tRAID %s\n",
  389. ctlr, (int) *pos, (int)vol_sz, (int)vol_sz_frac,
  390. raid_label[drv->raid_level]);
  391. return 0;
  392. }
  393. static void *cciss_seq_next(struct seq_file *seq, void *v, loff_t *pos)
  394. {
  395. ctlr_info_t *h = seq->private;
  396. if (*pos > h->highest_lun)
  397. return NULL;
  398. *pos += 1;
  399. return pos;
  400. }
  401. static void cciss_seq_stop(struct seq_file *seq, void *v)
  402. {
  403. ctlr_info_t *h = seq->private;
  404. /* Only reset h->busy_configuring if we succeeded in setting
  405. * it during cciss_seq_start. */
  406. if (v == ERR_PTR(-EBUSY))
  407. return;
  408. h->busy_configuring = 0;
  409. }
  410. static const struct seq_operations cciss_seq_ops = {
  411. .start = cciss_seq_start,
  412. .show = cciss_seq_show,
  413. .next = cciss_seq_next,
  414. .stop = cciss_seq_stop,
  415. };
  416. static int cciss_seq_open(struct inode *inode, struct file *file)
  417. {
  418. int ret = seq_open(file, &cciss_seq_ops);
  419. struct seq_file *seq = file->private_data;
  420. if (!ret)
  421. seq->private = PDE(inode)->data;
  422. return ret;
  423. }
  424. static ssize_t
  425. cciss_proc_write(struct file *file, const char __user *buf,
  426. size_t length, loff_t *ppos)
  427. {
  428. int err;
  429. char *buffer;
  430. #ifndef CONFIG_CISS_SCSI_TAPE
  431. return -EINVAL;
  432. #endif
  433. if (!buf || length > PAGE_SIZE - 1)
  434. return -EINVAL;
  435. buffer = (char *)__get_free_page(GFP_KERNEL);
  436. if (!buffer)
  437. return -ENOMEM;
  438. err = -EFAULT;
  439. if (copy_from_user(buffer, buf, length))
  440. goto out;
  441. buffer[length] = '\0';
  442. #ifdef CONFIG_CISS_SCSI_TAPE
  443. if (strncmp(ENGAGE_SCSI, buffer, sizeof ENGAGE_SCSI - 1) == 0) {
  444. struct seq_file *seq = file->private_data;
  445. ctlr_info_t *h = seq->private;
  446. err = cciss_engage_scsi(h);
  447. if (err == 0)
  448. err = length;
  449. } else
  450. #endif /* CONFIG_CISS_SCSI_TAPE */
  451. err = -EINVAL;
  452. /* might be nice to have "disengage" too, but it's not
  453. safely possible. (only 1 module use count, lock issues.) */
  454. out:
  455. free_page((unsigned long)buffer);
  456. return err;
  457. }
  458. static const struct file_operations cciss_proc_fops = {
  459. .owner = THIS_MODULE,
  460. .open = cciss_seq_open,
  461. .read = seq_read,
  462. .llseek = seq_lseek,
  463. .release = seq_release,
  464. .write = cciss_proc_write,
  465. };
  466. static void __devinit cciss_procinit(ctlr_info_t *h)
  467. {
  468. struct proc_dir_entry *pde;
  469. if (proc_cciss == NULL)
  470. proc_cciss = proc_mkdir("driver/cciss", NULL);
  471. if (!proc_cciss)
  472. return;
  473. pde = proc_create_data(h->devname, S_IWUSR | S_IRUSR | S_IRGRP |
  474. S_IROTH, proc_cciss,
  475. &cciss_proc_fops, h);
  476. }
  477. #endif /* CONFIG_PROC_FS */
  478. #define MAX_PRODUCT_NAME_LEN 19
  479. #define to_hba(n) container_of(n, struct ctlr_info, dev)
  480. #define to_drv(n) container_of(n, drive_info_struct, dev)
  481. /* List of controllers which cannot be reset on kexec with reset_devices */
  482. static u32 unresettable_controller[] = {
  483. 0x324a103C, /* Smart Array P712m */
  484. 0x324b103C, /* SmartArray P711m */
  485. 0x3223103C, /* Smart Array P800 */
  486. 0x3234103C, /* Smart Array P400 */
  487. 0x3235103C, /* Smart Array P400i */
  488. 0x3211103C, /* Smart Array E200i */
  489. 0x3212103C, /* Smart Array E200 */
  490. 0x3213103C, /* Smart Array E200i */
  491. 0x3214103C, /* Smart Array E200i */
  492. 0x3215103C, /* Smart Array E200i */
  493. 0x3237103C, /* Smart Array E500 */
  494. 0x323D103C, /* Smart Array P700m */
  495. 0x409C0E11, /* Smart Array 6400 */
  496. 0x409D0E11, /* Smart Array 6400 EM */
  497. };
  498. static int ctlr_is_resettable(struct ctlr_info *h)
  499. {
  500. int i;
  501. for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
  502. if (unresettable_controller[i] == h->board_id)
  503. return 0;
  504. return 1;
  505. }
  506. static ssize_t host_show_resettable(struct device *dev,
  507. struct device_attribute *attr,
  508. char *buf)
  509. {
  510. struct ctlr_info *h = to_hba(dev);
  511. return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h));
  512. }
  513. static DEVICE_ATTR(resettable, S_IRUGO, host_show_resettable, NULL);
  514. static ssize_t host_store_rescan(struct device *dev,
  515. struct device_attribute *attr,
  516. const char *buf, size_t count)
  517. {
  518. struct ctlr_info *h = to_hba(dev);
  519. add_to_scan_list(h);
  520. wake_up_process(cciss_scan_thread);
  521. wait_for_completion_interruptible(&h->scan_wait);
  522. return count;
  523. }
  524. static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
  525. static ssize_t dev_show_unique_id(struct device *dev,
  526. struct device_attribute *attr,
  527. char *buf)
  528. {
  529. drive_info_struct *drv = to_drv(dev);
  530. struct ctlr_info *h = to_hba(drv->dev.parent);
  531. __u8 sn[16];
  532. unsigned long flags;
  533. int ret = 0;
  534. spin_lock_irqsave(&h->lock, flags);
  535. if (h->busy_configuring)
  536. ret = -EBUSY;
  537. else
  538. memcpy(sn, drv->serial_no, sizeof(sn));
  539. spin_unlock_irqrestore(&h->lock, flags);
  540. if (ret)
  541. return ret;
  542. else
  543. return snprintf(buf, 16 * 2 + 2,
  544. "%02X%02X%02X%02X%02X%02X%02X%02X"
  545. "%02X%02X%02X%02X%02X%02X%02X%02X\n",
  546. sn[0], sn[1], sn[2], sn[3],
  547. sn[4], sn[5], sn[6], sn[7],
  548. sn[8], sn[9], sn[10], sn[11],
  549. sn[12], sn[13], sn[14], sn[15]);
  550. }
  551. static DEVICE_ATTR(unique_id, S_IRUGO, dev_show_unique_id, NULL);
  552. static ssize_t dev_show_vendor(struct device *dev,
  553. struct device_attribute *attr,
  554. char *buf)
  555. {
  556. drive_info_struct *drv = to_drv(dev);
  557. struct ctlr_info *h = to_hba(drv->dev.parent);
  558. char vendor[VENDOR_LEN + 1];
  559. unsigned long flags;
  560. int ret = 0;
  561. spin_lock_irqsave(&h->lock, flags);
  562. if (h->busy_configuring)
  563. ret = -EBUSY;
  564. else
  565. memcpy(vendor, drv->vendor, VENDOR_LEN + 1);
  566. spin_unlock_irqrestore(&h->lock, flags);
  567. if (ret)
  568. return ret;
  569. else
  570. return snprintf(buf, sizeof(vendor) + 1, "%s\n", drv->vendor);
  571. }
  572. static DEVICE_ATTR(vendor, S_IRUGO, dev_show_vendor, NULL);
  573. static ssize_t dev_show_model(struct device *dev,
  574. struct device_attribute *attr,
  575. char *buf)
  576. {
  577. drive_info_struct *drv = to_drv(dev);
  578. struct ctlr_info *h = to_hba(drv->dev.parent);
  579. char model[MODEL_LEN + 1];
  580. unsigned long flags;
  581. int ret = 0;
  582. spin_lock_irqsave(&h->lock, flags);
  583. if (h->busy_configuring)
  584. ret = -EBUSY;
  585. else
  586. memcpy(model, drv->model, MODEL_LEN + 1);
  587. spin_unlock_irqrestore(&h->lock, flags);
  588. if (ret)
  589. return ret;
  590. else
  591. return snprintf(buf, sizeof(model) + 1, "%s\n", drv->model);
  592. }
  593. static DEVICE_ATTR(model, S_IRUGO, dev_show_model, NULL);
  594. static ssize_t dev_show_rev(struct device *dev,
  595. struct device_attribute *attr,
  596. char *buf)
  597. {
  598. drive_info_struct *drv = to_drv(dev);
  599. struct ctlr_info *h = to_hba(drv->dev.parent);
  600. char rev[REV_LEN + 1];
  601. unsigned long flags;
  602. int ret = 0;
  603. spin_lock_irqsave(&h->lock, flags);
  604. if (h->busy_configuring)
  605. ret = -EBUSY;
  606. else
  607. memcpy(rev, drv->rev, REV_LEN + 1);
  608. spin_unlock_irqrestore(&h->lock, flags);
  609. if (ret)
  610. return ret;
  611. else
  612. return snprintf(buf, sizeof(rev) + 1, "%s\n", drv->rev);
  613. }
  614. static DEVICE_ATTR(rev, S_IRUGO, dev_show_rev, NULL);
  615. static ssize_t cciss_show_lunid(struct device *dev,
  616. struct device_attribute *attr, char *buf)
  617. {
  618. drive_info_struct *drv = to_drv(dev);
  619. struct ctlr_info *h = to_hba(drv->dev.parent);
  620. unsigned long flags;
  621. unsigned char lunid[8];
  622. spin_lock_irqsave(&h->lock, flags);
  623. if (h->busy_configuring) {
  624. spin_unlock_irqrestore(&h->lock, flags);
  625. return -EBUSY;
  626. }
  627. if (!drv->heads) {
  628. spin_unlock_irqrestore(&h->lock, flags);
  629. return -ENOTTY;
  630. }
  631. memcpy(lunid, drv->LunID, sizeof(lunid));
  632. spin_unlock_irqrestore(&h->lock, flags);
  633. return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
  634. lunid[0], lunid[1], lunid[2], lunid[3],
  635. lunid[4], lunid[5], lunid[6], lunid[7]);
  636. }
  637. static DEVICE_ATTR(lunid, S_IRUGO, cciss_show_lunid, NULL);
  638. static ssize_t cciss_show_raid_level(struct device *dev,
  639. struct device_attribute *attr, char *buf)
  640. {
  641. drive_info_struct *drv = to_drv(dev);
  642. struct ctlr_info *h = to_hba(drv->dev.parent);
  643. int raid;
  644. unsigned long flags;
  645. spin_lock_irqsave(&h->lock, flags);
  646. if (h->busy_configuring) {
  647. spin_unlock_irqrestore(&h->lock, flags);
  648. return -EBUSY;
  649. }
  650. raid = drv->raid_level;
  651. spin_unlock_irqrestore(&h->lock, flags);
  652. if (raid < 0 || raid > RAID_UNKNOWN)
  653. raid = RAID_UNKNOWN;
  654. return snprintf(buf, strlen(raid_label[raid]) + 7, "RAID %s\n",
  655. raid_label[raid]);
  656. }
  657. static DEVICE_ATTR(raid_level, S_IRUGO, cciss_show_raid_level, NULL);
  658. static ssize_t cciss_show_usage_count(struct device *dev,
  659. struct device_attribute *attr, char *buf)
  660. {
  661. drive_info_struct *drv = to_drv(dev);
  662. struct ctlr_info *h = to_hba(drv->dev.parent);
  663. unsigned long flags;
  664. int count;
  665. spin_lock_irqsave(&h->lock, flags);
  666. if (h->busy_configuring) {
  667. spin_unlock_irqrestore(&h->lock, flags);
  668. return -EBUSY;
  669. }
  670. count = drv->usage_count;
  671. spin_unlock_irqrestore(&h->lock, flags);
  672. return snprintf(buf, 20, "%d\n", count);
  673. }
  674. static DEVICE_ATTR(usage_count, S_IRUGO, cciss_show_usage_count, NULL);
  675. static struct attribute *cciss_host_attrs[] = {
  676. &dev_attr_rescan.attr,
  677. &dev_attr_resettable.attr,
  678. NULL
  679. };
  680. static struct attribute_group cciss_host_attr_group = {
  681. .attrs = cciss_host_attrs,
  682. };
  683. static const struct attribute_group *cciss_host_attr_groups[] = {
  684. &cciss_host_attr_group,
  685. NULL
  686. };
  687. static struct device_type cciss_host_type = {
  688. .name = "cciss_host",
  689. .groups = cciss_host_attr_groups,
  690. .release = cciss_hba_release,
  691. };
  692. static struct attribute *cciss_dev_attrs[] = {
  693. &dev_attr_unique_id.attr,
  694. &dev_attr_model.attr,
  695. &dev_attr_vendor.attr,
  696. &dev_attr_rev.attr,
  697. &dev_attr_lunid.attr,
  698. &dev_attr_raid_level.attr,
  699. &dev_attr_usage_count.attr,
  700. NULL
  701. };
  702. static struct attribute_group cciss_dev_attr_group = {
  703. .attrs = cciss_dev_attrs,
  704. };
  705. static const struct attribute_group *cciss_dev_attr_groups[] = {
  706. &cciss_dev_attr_group,
  707. NULL
  708. };
  709. static struct device_type cciss_dev_type = {
  710. .name = "cciss_device",
  711. .groups = cciss_dev_attr_groups,
  712. .release = cciss_device_release,
  713. };
  714. static struct bus_type cciss_bus_type = {
  715. .name = "cciss",
  716. };
  717. /*
  718. * cciss_hba_release is called when the reference count
  719. * of h->dev goes to zero.
  720. */
  721. static void cciss_hba_release(struct device *dev)
  722. {
  723. /*
  724. * nothing to do, but need this to avoid a warning
  725. * about not having a release handler from lib/kref.c.
  726. */
  727. }
  728. /*
  729. * Initialize sysfs entry for each controller. This sets up and registers
  730. * the 'cciss#' directory for each individual controller under
  731. * /sys/bus/pci/devices/<dev>/.
  732. */
  733. static int cciss_create_hba_sysfs_entry(struct ctlr_info *h)
  734. {
  735. device_initialize(&h->dev);
  736. h->dev.type = &cciss_host_type;
  737. h->dev.bus = &cciss_bus_type;
  738. dev_set_name(&h->dev, "%s", h->devname);
  739. h->dev.parent = &h->pdev->dev;
  740. return device_add(&h->dev);
  741. }
  742. /*
  743. * Remove sysfs entries for an hba.
  744. */
  745. static void cciss_destroy_hba_sysfs_entry(struct ctlr_info *h)
  746. {
  747. device_del(&h->dev);
  748. put_device(&h->dev); /* final put. */
  749. }
  750. /* cciss_device_release is called when the reference count
  751. * of h->drv[x]dev goes to zero.
  752. */
  753. static void cciss_device_release(struct device *dev)
  754. {
  755. drive_info_struct *drv = to_drv(dev);
  756. kfree(drv);
  757. }
  758. /*
  759. * Initialize sysfs for each logical drive. This sets up and registers
  760. * the 'c#d#' directory for each individual logical drive under
  761. * /sys/bus/pci/devices/<dev/ccis#/. We also create a link from
  762. * /sys/block/cciss!c#d# to this entry.
  763. */
  764. static long cciss_create_ld_sysfs_entry(struct ctlr_info *h,
  765. int drv_index)
  766. {
  767. struct device *dev;
  768. if (h->drv[drv_index]->device_initialized)
  769. return 0;
  770. dev = &h->drv[drv_index]->dev;
  771. device_initialize(dev);
  772. dev->type = &cciss_dev_type;
  773. dev->bus = &cciss_bus_type;
  774. dev_set_name(dev, "c%dd%d", h->ctlr, drv_index);
  775. dev->parent = &h->dev;
  776. h->drv[drv_index]->device_initialized = 1;
  777. return device_add(dev);
  778. }
  779. /*
  780. * Remove sysfs entries for a logical drive.
  781. */
  782. static void cciss_destroy_ld_sysfs_entry(struct ctlr_info *h, int drv_index,
  783. int ctlr_exiting)
  784. {
  785. struct device *dev = &h->drv[drv_index]->dev;
  786. /* special case for c*d0, we only destroy it on controller exit */
  787. if (drv_index == 0 && !ctlr_exiting)
  788. return;
  789. device_del(dev);
  790. put_device(dev); /* the "final" put. */
  791. h->drv[drv_index] = NULL;
  792. }
  793. /*
  794. * For operations that cannot sleep, a command block is allocated at init,
  795. * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
  796. * which ones are free or in use.
  797. */
  798. static CommandList_struct *cmd_alloc(ctlr_info_t *h)
  799. {
  800. CommandList_struct *c;
  801. int i;
  802. u64bit temp64;
  803. dma_addr_t cmd_dma_handle, err_dma_handle;
  804. do {
  805. i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
  806. if (i == h->nr_cmds)
  807. return NULL;
  808. } while (test_and_set_bit(i & (BITS_PER_LONG - 1),
  809. h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
  810. c = h->cmd_pool + i;
  811. memset(c, 0, sizeof(CommandList_struct));
  812. cmd_dma_handle = h->cmd_pool_dhandle + i * sizeof(CommandList_struct);
  813. c->err_info = h->errinfo_pool + i;
  814. memset(c->err_info, 0, sizeof(ErrorInfo_struct));
  815. err_dma_handle = h->errinfo_pool_dhandle
  816. + i * sizeof(ErrorInfo_struct);
  817. h->nr_allocs++;
  818. c->cmdindex = i;
  819. INIT_LIST_HEAD(&c->list);
  820. c->busaddr = (__u32) cmd_dma_handle;
  821. temp64.val = (__u64) err_dma_handle;
  822. c->ErrDesc.Addr.lower = temp64.val32.lower;
  823. c->ErrDesc.Addr.upper = temp64.val32.upper;
  824. c->ErrDesc.Len = sizeof(ErrorInfo_struct);
  825. c->ctlr = h->ctlr;
  826. return c;
  827. }
  828. /* allocate a command using pci_alloc_consistent, used for ioctls,
  829. * etc., not for the main i/o path.
  830. */
  831. static CommandList_struct *cmd_special_alloc(ctlr_info_t *h)
  832. {
  833. CommandList_struct *c;
  834. u64bit temp64;
  835. dma_addr_t cmd_dma_handle, err_dma_handle;
  836. c = (CommandList_struct *) pci_alloc_consistent(h->pdev,
  837. sizeof(CommandList_struct), &cmd_dma_handle);
  838. if (c == NULL)
  839. return NULL;
  840. memset(c, 0, sizeof(CommandList_struct));
  841. c->cmdindex = -1;
  842. c->err_info = (ErrorInfo_struct *)
  843. pci_alloc_consistent(h->pdev, sizeof(ErrorInfo_struct),
  844. &err_dma_handle);
  845. if (c->err_info == NULL) {
  846. pci_free_consistent(h->pdev,
  847. sizeof(CommandList_struct), c, cmd_dma_handle);
  848. return NULL;
  849. }
  850. memset(c->err_info, 0, sizeof(ErrorInfo_struct));
  851. INIT_LIST_HEAD(&c->list);
  852. c->busaddr = (__u32) cmd_dma_handle;
  853. temp64.val = (__u64) err_dma_handle;
  854. c->ErrDesc.Addr.lower = temp64.val32.lower;
  855. c->ErrDesc.Addr.upper = temp64.val32.upper;
  856. c->ErrDesc.Len = sizeof(ErrorInfo_struct);
  857. c->ctlr = h->ctlr;
  858. return c;
  859. }
  860. static void cmd_free(ctlr_info_t *h, CommandList_struct *c)
  861. {
  862. int i;
  863. i = c - h->cmd_pool;
  864. clear_bit(i & (BITS_PER_LONG - 1),
  865. h->cmd_pool_bits + (i / BITS_PER_LONG));
  866. h->nr_frees++;
  867. }
  868. static void cmd_special_free(ctlr_info_t *h, CommandList_struct *c)
  869. {
  870. u64bit temp64;
  871. temp64.val32.lower = c->ErrDesc.Addr.lower;
  872. temp64.val32.upper = c->ErrDesc.Addr.upper;
  873. pci_free_consistent(h->pdev, sizeof(ErrorInfo_struct),
  874. c->err_info, (dma_addr_t) temp64.val);
  875. pci_free_consistent(h->pdev, sizeof(CommandList_struct), c,
  876. (dma_addr_t) cciss_tag_discard_error_bits(h, (u32) c->busaddr));
  877. }
  878. static inline ctlr_info_t *get_host(struct gendisk *disk)
  879. {
  880. return disk->queue->queuedata;
  881. }
  882. static inline drive_info_struct *get_drv(struct gendisk *disk)
  883. {
  884. return disk->private_data;
  885. }
  886. /*
  887. * Open. Make sure the device is really there.
  888. */
  889. static int cciss_open(struct block_device *bdev, fmode_t mode)
  890. {
  891. ctlr_info_t *h = get_host(bdev->bd_disk);
  892. drive_info_struct *drv = get_drv(bdev->bd_disk);
  893. dev_dbg(&h->pdev->dev, "cciss_open %s\n", bdev->bd_disk->disk_name);
  894. if (drv->busy_configuring)
  895. return -EBUSY;
  896. /*
  897. * Root is allowed to open raw volume zero even if it's not configured
  898. * so array config can still work. Root is also allowed to open any
  899. * volume that has a LUN ID, so it can issue IOCTL to reread the
  900. * disk information. I don't think I really like this
  901. * but I'm already using way to many device nodes to claim another one
  902. * for "raw controller".
  903. */
  904. if (drv->heads == 0) {
  905. if (MINOR(bdev->bd_dev) != 0) { /* not node 0? */
  906. /* if not node 0 make sure it is a partition = 0 */
  907. if (MINOR(bdev->bd_dev) & 0x0f) {
  908. return -ENXIO;
  909. /* if it is, make sure we have a LUN ID */
  910. } else if (memcmp(drv->LunID, CTLR_LUNID,
  911. sizeof(drv->LunID))) {
  912. return -ENXIO;
  913. }
  914. }
  915. if (!capable(CAP_SYS_ADMIN))
  916. return -EPERM;
  917. }
  918. drv->usage_count++;
  919. h->usage_count++;
  920. return 0;
  921. }
  922. static int cciss_unlocked_open(struct block_device *bdev, fmode_t mode)
  923. {
  924. int ret;
  925. mutex_lock(&cciss_mutex);
  926. ret = cciss_open(bdev, mode);
  927. mutex_unlock(&cciss_mutex);
  928. return ret;
  929. }
  930. /*
  931. * Close. Sync first.
  932. */
  933. static int cciss_release(struct gendisk *disk, fmode_t mode)
  934. {
  935. ctlr_info_t *h;
  936. drive_info_struct *drv;
  937. mutex_lock(&cciss_mutex);
  938. h = get_host(disk);
  939. drv = get_drv(disk);
  940. dev_dbg(&h->pdev->dev, "cciss_release %s\n", disk->disk_name);
  941. drv->usage_count--;
  942. h->usage_count--;
  943. mutex_unlock(&cciss_mutex);
  944. return 0;
  945. }
  946. static int do_ioctl(struct block_device *bdev, fmode_t mode,
  947. unsigned cmd, unsigned long arg)
  948. {
  949. int ret;
  950. mutex_lock(&cciss_mutex);
  951. ret = cciss_ioctl(bdev, mode, cmd, arg);
  952. mutex_unlock(&cciss_mutex);
  953. return ret;
  954. }
  955. #ifdef CONFIG_COMPAT
  956. static int cciss_ioctl32_passthru(struct block_device *bdev, fmode_t mode,
  957. unsigned cmd, unsigned long arg);
  958. static int cciss_ioctl32_big_passthru(struct block_device *bdev, fmode_t mode,
  959. unsigned cmd, unsigned long arg);
  960. static int cciss_compat_ioctl(struct block_device *bdev, fmode_t mode,
  961. unsigned cmd, unsigned long arg)
  962. {
  963. switch (cmd) {
  964. case CCISS_GETPCIINFO:
  965. case CCISS_GETINTINFO:
  966. case CCISS_SETINTINFO:
  967. case CCISS_GETNODENAME:
  968. case CCISS_SETNODENAME:
  969. case CCISS_GETHEARTBEAT:
  970. case CCISS_GETBUSTYPES:
  971. case CCISS_GETFIRMVER:
  972. case CCISS_GETDRIVVER:
  973. case CCISS_REVALIDVOLS:
  974. case CCISS_DEREGDISK:
  975. case CCISS_REGNEWDISK:
  976. case CCISS_REGNEWD:
  977. case CCISS_RESCANDISK:
  978. case CCISS_GETLUNINFO:
  979. return do_ioctl(bdev, mode, cmd, arg);
  980. case CCISS_PASSTHRU32:
  981. return cciss_ioctl32_passthru(bdev, mode, cmd, arg);
  982. case CCISS_BIG_PASSTHRU32:
  983. return cciss_ioctl32_big_passthru(bdev, mode, cmd, arg);
  984. default:
  985. return -ENOIOCTLCMD;
  986. }
  987. }
  988. static int cciss_ioctl32_passthru(struct block_device *bdev, fmode_t mode,
  989. unsigned cmd, unsigned long arg)
  990. {
  991. IOCTL32_Command_struct __user *arg32 =
  992. (IOCTL32_Command_struct __user *) arg;
  993. IOCTL_Command_struct arg64;
  994. IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
  995. int err;
  996. u32 cp;
  997. err = 0;
  998. err |=
  999. copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
  1000. sizeof(arg64.LUN_info));
  1001. err |=
  1002. copy_from_user(&arg64.Request, &arg32->Request,
  1003. sizeof(arg64.Request));
  1004. err |=
  1005. copy_from_user(&arg64.error_info, &arg32->error_info,
  1006. sizeof(arg64.error_info));
  1007. err |= get_user(arg64.buf_size, &arg32->buf_size);
  1008. err |= get_user(cp, &arg32->buf);
  1009. arg64.buf = compat_ptr(cp);
  1010. err |= copy_to_user(p, &arg64, sizeof(arg64));
  1011. if (err)
  1012. return -EFAULT;
  1013. err = do_ioctl(bdev, mode, CCISS_PASSTHRU, (unsigned long)p);
  1014. if (err)
  1015. return err;
  1016. err |=
  1017. copy_in_user(&arg32->error_info, &p->error_info,
  1018. sizeof(arg32->error_info));
  1019. if (err)
  1020. return -EFAULT;
  1021. return err;
  1022. }
  1023. static int cciss_ioctl32_big_passthru(struct block_device *bdev, fmode_t mode,
  1024. unsigned cmd, unsigned long arg)
  1025. {
  1026. BIG_IOCTL32_Command_struct __user *arg32 =
  1027. (BIG_IOCTL32_Command_struct __user *) arg;
  1028. BIG_IOCTL_Command_struct arg64;
  1029. BIG_IOCTL_Command_struct __user *p =
  1030. compat_alloc_user_space(sizeof(arg64));
  1031. int err;
  1032. u32 cp;
  1033. memset(&arg64, 0, sizeof(arg64));
  1034. err = 0;
  1035. err |=
  1036. copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
  1037. sizeof(arg64.LUN_info));
  1038. err |=
  1039. copy_from_user(&arg64.Request, &arg32->Request,
  1040. sizeof(arg64.Request));
  1041. err |=
  1042. copy_from_user(&arg64.error_info, &arg32->error_info,
  1043. sizeof(arg64.error_info));
  1044. err |= get_user(arg64.buf_size, &arg32->buf_size);
  1045. err |= get_user(arg64.malloc_size, &arg32->malloc_size);
  1046. err |= get_user(cp, &arg32->buf);
  1047. arg64.buf = compat_ptr(cp);
  1048. err |= copy_to_user(p, &arg64, sizeof(arg64));
  1049. if (err)
  1050. return -EFAULT;
  1051. err = do_ioctl(bdev, mode, CCISS_BIG_PASSTHRU, (unsigned long)p);
  1052. if (err)
  1053. return err;
  1054. err |=
  1055. copy_in_user(&arg32->error_info, &p->error_info,
  1056. sizeof(arg32->error_info));
  1057. if (err)
  1058. return -EFAULT;
  1059. return err;
  1060. }
  1061. #endif
  1062. static int cciss_getgeo(struct block_device *bdev, struct hd_geometry *geo)
  1063. {
  1064. drive_info_struct *drv = get_drv(bdev->bd_disk);
  1065. if (!drv->cylinders)
  1066. return -ENXIO;
  1067. geo->heads = drv->heads;
  1068. geo->sectors = drv->sectors;
  1069. geo->cylinders = drv->cylinders;
  1070. return 0;
  1071. }
  1072. static void check_ioctl_unit_attention(ctlr_info_t *h, CommandList_struct *c)
  1073. {
  1074. if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
  1075. c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
  1076. (void)check_for_unit_attention(h, c);
  1077. }
  1078. static int cciss_getpciinfo(ctlr_info_t *h, void __user *argp)
  1079. {
  1080. cciss_pci_info_struct pciinfo;
  1081. if (!argp)
  1082. return -EINVAL;
  1083. pciinfo.domain = pci_domain_nr(h->pdev->bus);
  1084. pciinfo.bus = h->pdev->bus->number;
  1085. pciinfo.dev_fn = h->pdev->devfn;
  1086. pciinfo.board_id = h->board_id;
  1087. if (copy_to_user(argp, &pciinfo, sizeof(cciss_pci_info_struct)))
  1088. return -EFAULT;
  1089. return 0;
  1090. }
  1091. static int cciss_getintinfo(ctlr_info_t *h, void __user *argp)
  1092. {
  1093. cciss_coalint_struct intinfo;
  1094. if (!argp)
  1095. return -EINVAL;
  1096. intinfo.delay = readl(&h->cfgtable->HostWrite.CoalIntDelay);
  1097. intinfo.count = readl(&h->cfgtable->HostWrite.CoalIntCount);
  1098. if (copy_to_user
  1099. (argp, &intinfo, sizeof(cciss_coalint_struct)))
  1100. return -EFAULT;
  1101. return 0;
  1102. }
  1103. static int cciss_setintinfo(ctlr_info_t *h, void __user *argp)
  1104. {
  1105. cciss_coalint_struct intinfo;
  1106. unsigned long flags;
  1107. int i;
  1108. if (!argp)
  1109. return -EINVAL;
  1110. if (!capable(CAP_SYS_ADMIN))
  1111. return -EPERM;
  1112. if (copy_from_user(&intinfo, argp, sizeof(intinfo)))
  1113. return -EFAULT;
  1114. if ((intinfo.delay == 0) && (intinfo.count == 0))
  1115. return -EINVAL;
  1116. spin_lock_irqsave(&h->lock, flags);
  1117. /* Update the field, and then ring the doorbell */
  1118. writel(intinfo.delay, &(h->cfgtable->HostWrite.CoalIntDelay));
  1119. writel(intinfo.count, &(h->cfgtable->HostWrite.CoalIntCount));
  1120. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  1121. for (i = 0; i < MAX_IOCTL_CONFIG_WAIT; i++) {
  1122. if (!(readl(h->vaddr + SA5_DOORBELL) & CFGTBL_ChangeReq))
  1123. break;
  1124. udelay(1000); /* delay and try again */
  1125. }
  1126. spin_unlock_irqrestore(&h->lock, flags);
  1127. if (i >= MAX_IOCTL_CONFIG_WAIT)
  1128. return -EAGAIN;
  1129. return 0;
  1130. }
  1131. static int cciss_getnodename(ctlr_info_t *h, void __user *argp)
  1132. {
  1133. NodeName_type NodeName;
  1134. int i;
  1135. if (!argp)
  1136. return -EINVAL;
  1137. for (i = 0; i < 16; i++)
  1138. NodeName[i] = readb(&h->cfgtable->ServerName[i]);
  1139. if (copy_to_user(argp, NodeName, sizeof(NodeName_type)))
  1140. return -EFAULT;
  1141. return 0;
  1142. }
  1143. static int cciss_setnodename(ctlr_info_t *h, void __user *argp)
  1144. {
  1145. NodeName_type NodeName;
  1146. unsigned long flags;
  1147. int i;
  1148. if (!argp)
  1149. return -EINVAL;
  1150. if (!capable(CAP_SYS_ADMIN))
  1151. return -EPERM;
  1152. if (copy_from_user(NodeName, argp, sizeof(NodeName_type)))
  1153. return -EFAULT;
  1154. spin_lock_irqsave(&h->lock, flags);
  1155. /* Update the field, and then ring the doorbell */
  1156. for (i = 0; i < 16; i++)
  1157. writeb(NodeName[i], &h->cfgtable->ServerName[i]);
  1158. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  1159. for (i = 0; i < MAX_IOCTL_CONFIG_WAIT; i++) {
  1160. if (!(readl(h->vaddr + SA5_DOORBELL) & CFGTBL_ChangeReq))
  1161. break;
  1162. udelay(1000); /* delay and try again */
  1163. }
  1164. spin_unlock_irqrestore(&h->lock, flags);
  1165. if (i >= MAX_IOCTL_CONFIG_WAIT)
  1166. return -EAGAIN;
  1167. return 0;
  1168. }
  1169. static int cciss_getheartbeat(ctlr_info_t *h, void __user *argp)
  1170. {
  1171. Heartbeat_type heartbeat;
  1172. if (!argp)
  1173. return -EINVAL;
  1174. heartbeat = readl(&h->cfgtable->HeartBeat);
  1175. if (copy_to_user(argp, &heartbeat, sizeof(Heartbeat_type)))
  1176. return -EFAULT;
  1177. return 0;
  1178. }
  1179. static int cciss_getbustypes(ctlr_info_t *h, void __user *argp)
  1180. {
  1181. BusTypes_type BusTypes;
  1182. if (!argp)
  1183. return -EINVAL;
  1184. BusTypes = readl(&h->cfgtable->BusTypes);
  1185. if (copy_to_user(argp, &BusTypes, sizeof(BusTypes_type)))
  1186. return -EFAULT;
  1187. return 0;
  1188. }
  1189. static int cciss_getfirmver(ctlr_info_t *h, void __user *argp)
  1190. {
  1191. FirmwareVer_type firmware;
  1192. if (!argp)
  1193. return -EINVAL;
  1194. memcpy(firmware, h->firm_ver, 4);
  1195. if (copy_to_user
  1196. (argp, firmware, sizeof(FirmwareVer_type)))
  1197. return -EFAULT;
  1198. return 0;
  1199. }
  1200. static int cciss_getdrivver(ctlr_info_t *h, void __user *argp)
  1201. {
  1202. DriverVer_type DriverVer = DRIVER_VERSION;
  1203. if (!argp)
  1204. return -EINVAL;
  1205. if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
  1206. return -EFAULT;
  1207. return 0;
  1208. }
  1209. static int cciss_getluninfo(ctlr_info_t *h,
  1210. struct gendisk *disk, void __user *argp)
  1211. {
  1212. LogvolInfo_struct luninfo;
  1213. drive_info_struct *drv = get_drv(disk);
  1214. if (!argp)
  1215. return -EINVAL;
  1216. memcpy(&luninfo.LunID, drv->LunID, sizeof(luninfo.LunID));
  1217. luninfo.num_opens = drv->usage_count;
  1218. luninfo.num_parts = 0;
  1219. if (copy_to_user(argp, &luninfo, sizeof(LogvolInfo_struct)))
  1220. return -EFAULT;
  1221. return 0;
  1222. }
  1223. static int cciss_passthru(ctlr_info_t *h, void __user *argp)
  1224. {
  1225. IOCTL_Command_struct iocommand;
  1226. CommandList_struct *c;
  1227. char *buff = NULL;
  1228. u64bit temp64;
  1229. DECLARE_COMPLETION_ONSTACK(wait);
  1230. if (!argp)
  1231. return -EINVAL;
  1232. if (!capable(CAP_SYS_RAWIO))
  1233. return -EPERM;
  1234. if (copy_from_user
  1235. (&iocommand, argp, sizeof(IOCTL_Command_struct)))
  1236. return -EFAULT;
  1237. if ((iocommand.buf_size < 1) &&
  1238. (iocommand.Request.Type.Direction != XFER_NONE)) {
  1239. return -EINVAL;
  1240. }
  1241. if (iocommand.buf_size > 0) {
  1242. buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
  1243. if (buff == NULL)
  1244. return -EFAULT;
  1245. }
  1246. if (iocommand.Request.Type.Direction == XFER_WRITE) {
  1247. /* Copy the data into the buffer we created */
  1248. if (copy_from_user(buff, iocommand.buf, iocommand.buf_size)) {
  1249. kfree(buff);
  1250. return -EFAULT;
  1251. }
  1252. } else {
  1253. memset(buff, 0, iocommand.buf_size);
  1254. }
  1255. c = cmd_special_alloc(h);
  1256. if (!c) {
  1257. kfree(buff);
  1258. return -ENOMEM;
  1259. }
  1260. /* Fill in the command type */
  1261. c->cmd_type = CMD_IOCTL_PEND;
  1262. /* Fill in Command Header */
  1263. c->Header.ReplyQueue = 0; /* unused in simple mode */
  1264. if (iocommand.buf_size > 0) { /* buffer to fill */
  1265. c->Header.SGList = 1;
  1266. c->Header.SGTotal = 1;
  1267. } else { /* no buffers to fill */
  1268. c->Header.SGList = 0;
  1269. c->Header.SGTotal = 0;
  1270. }
  1271. c->Header.LUN = iocommand.LUN_info;
  1272. /* use the kernel address the cmd block for tag */
  1273. c->Header.Tag.lower = c->busaddr;
  1274. /* Fill in Request block */
  1275. c->Request = iocommand.Request;
  1276. /* Fill in the scatter gather information */
  1277. if (iocommand.buf_size > 0) {
  1278. temp64.val = pci_map_single(h->pdev, buff,
  1279. iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
  1280. c->SG[0].Addr.lower = temp64.val32.lower;
  1281. c->SG[0].Addr.upper = temp64.val32.upper;
  1282. c->SG[0].Len = iocommand.buf_size;
  1283. c->SG[0].Ext = 0; /* we are not chaining */
  1284. }
  1285. c->waiting = &wait;
  1286. enqueue_cmd_and_start_io(h, c);
  1287. wait_for_completion(&wait);
  1288. /* unlock the buffers from DMA */
  1289. temp64.val32.lower = c->SG[0].Addr.lower;
  1290. temp64.val32.upper = c->SG[0].Addr.upper;
  1291. pci_unmap_single(h->pdev, (dma_addr_t) temp64.val, iocommand.buf_size,
  1292. PCI_DMA_BIDIRECTIONAL);
  1293. check_ioctl_unit_attention(h, c);
  1294. /* Copy the error information out */
  1295. iocommand.error_info = *(c->err_info);
  1296. if (copy_to_user(argp, &iocommand, sizeof(IOCTL_Command_struct))) {
  1297. kfree(buff);
  1298. cmd_special_free(h, c);
  1299. return -EFAULT;
  1300. }
  1301. if (iocommand.Request.Type.Direction == XFER_READ) {
  1302. /* Copy the data out of the buffer we created */
  1303. if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
  1304. kfree(buff);
  1305. cmd_special_free(h, c);
  1306. return -EFAULT;
  1307. }
  1308. }
  1309. kfree(buff);
  1310. cmd_special_free(h, c);
  1311. return 0;
  1312. }
  1313. static int cciss_bigpassthru(ctlr_info_t *h, void __user *argp)
  1314. {
  1315. BIG_IOCTL_Command_struct *ioc;
  1316. CommandList_struct *c;
  1317. unsigned char **buff = NULL;
  1318. int *buff_size = NULL;
  1319. u64bit temp64;
  1320. BYTE sg_used = 0;
  1321. int status = 0;
  1322. int i;
  1323. DECLARE_COMPLETION_ONSTACK(wait);
  1324. __u32 left;
  1325. __u32 sz;
  1326. BYTE __user *data_ptr;
  1327. if (!argp)
  1328. return -EINVAL;
  1329. if (!capable(CAP_SYS_RAWIO))
  1330. return -EPERM;
  1331. ioc = kmalloc(sizeof(*ioc), GFP_KERNEL);
  1332. if (!ioc) {
  1333. status = -ENOMEM;
  1334. goto cleanup1;
  1335. }
  1336. if (copy_from_user(ioc, argp, sizeof(*ioc))) {
  1337. status = -EFAULT;
  1338. goto cleanup1;
  1339. }
  1340. if ((ioc->buf_size < 1) &&
  1341. (ioc->Request.Type.Direction != XFER_NONE)) {
  1342. status = -EINVAL;
  1343. goto cleanup1;
  1344. }
  1345. /* Check kmalloc limits using all SGs */
  1346. if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
  1347. status = -EINVAL;
  1348. goto cleanup1;
  1349. }
  1350. if (ioc->buf_size > ioc->malloc_size * MAXSGENTRIES) {
  1351. status = -EINVAL;
  1352. goto cleanup1;
  1353. }
  1354. buff = kzalloc(MAXSGENTRIES * sizeof(char *), GFP_KERNEL);
  1355. if (!buff) {
  1356. status = -ENOMEM;
  1357. goto cleanup1;
  1358. }
  1359. buff_size = kmalloc(MAXSGENTRIES * sizeof(int), GFP_KERNEL);
  1360. if (!buff_size) {
  1361. status = -ENOMEM;
  1362. goto cleanup1;
  1363. }
  1364. left = ioc->buf_size;
  1365. data_ptr = ioc->buf;
  1366. while (left) {
  1367. sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
  1368. buff_size[sg_used] = sz;
  1369. buff[sg_used] = kmalloc(sz, GFP_KERNEL);
  1370. if (buff[sg_used] == NULL) {
  1371. status = -ENOMEM;
  1372. goto cleanup1;
  1373. }
  1374. if (ioc->Request.Type.Direction == XFER_WRITE) {
  1375. if (copy_from_user(buff[sg_used], data_ptr, sz)) {
  1376. status = -EFAULT;
  1377. goto cleanup1;
  1378. }
  1379. } else {
  1380. memset(buff[sg_used], 0, sz);
  1381. }
  1382. left -= sz;
  1383. data_ptr += sz;
  1384. sg_used++;
  1385. }
  1386. c = cmd_special_alloc(h);
  1387. if (!c) {
  1388. status = -ENOMEM;
  1389. goto cleanup1;
  1390. }
  1391. c->cmd_type = CMD_IOCTL_PEND;
  1392. c->Header.ReplyQueue = 0;
  1393. c->Header.SGList = sg_used;
  1394. c->Header.SGTotal = sg_used;
  1395. c->Header.LUN = ioc->LUN_info;
  1396. c->Header.Tag.lower = c->busaddr;
  1397. c->Request = ioc->Request;
  1398. for (i = 0; i < sg_used; i++) {
  1399. temp64.val = pci_map_single(h->pdev, buff[i], buff_size[i],
  1400. PCI_DMA_BIDIRECTIONAL);
  1401. c->SG[i].Addr.lower = temp64.val32.lower;
  1402. c->SG[i].Addr.upper = temp64.val32.upper;
  1403. c->SG[i].Len = buff_size[i];
  1404. c->SG[i].Ext = 0; /* we are not chaining */
  1405. }
  1406. c->waiting = &wait;
  1407. enqueue_cmd_and_start_io(h, c);
  1408. wait_for_completion(&wait);
  1409. /* unlock the buffers from DMA */
  1410. for (i = 0; i < sg_used; i++) {
  1411. temp64.val32.lower = c->SG[i].Addr.lower;
  1412. temp64.val32.upper = c->SG[i].Addr.upper;
  1413. pci_unmap_single(h->pdev,
  1414. (dma_addr_t) temp64.val, buff_size[i],
  1415. PCI_DMA_BIDIRECTIONAL);
  1416. }
  1417. check_ioctl_unit_attention(h, c);
  1418. /* Copy the error information out */
  1419. ioc->error_info = *(c->err_info);
  1420. if (copy_to_user(argp, ioc, sizeof(*ioc))) {
  1421. cmd_special_free(h, c);
  1422. status = -EFAULT;
  1423. goto cleanup1;
  1424. }
  1425. if (ioc->Request.Type.Direction == XFER_READ) {
  1426. /* Copy the data out of the buffer we created */
  1427. BYTE __user *ptr = ioc->buf;
  1428. for (i = 0; i < sg_used; i++) {
  1429. if (copy_to_user(ptr, buff[i], buff_size[i])) {
  1430. cmd_special_free(h, c);
  1431. status = -EFAULT;
  1432. goto cleanup1;
  1433. }
  1434. ptr += buff_size[i];
  1435. }
  1436. }
  1437. cmd_special_free(h, c);
  1438. status = 0;
  1439. cleanup1:
  1440. if (buff) {
  1441. for (i = 0; i < sg_used; i++)
  1442. kfree(buff[i]);
  1443. kfree(buff);
  1444. }
  1445. kfree(buff_size);
  1446. kfree(ioc);
  1447. return status;
  1448. }
  1449. static int cciss_ioctl(struct block_device *bdev, fmode_t mode,
  1450. unsigned int cmd, unsigned long arg)
  1451. {
  1452. struct gendisk *disk = bdev->bd_disk;
  1453. ctlr_info_t *h = get_host(disk);
  1454. void __user *argp = (void __user *)arg;
  1455. dev_dbg(&h->pdev->dev, "cciss_ioctl: Called with cmd=%x %lx\n",
  1456. cmd, arg);
  1457. switch (cmd) {
  1458. case CCISS_GETPCIINFO:
  1459. return cciss_getpciinfo(h, argp);
  1460. case CCISS_GETINTINFO:
  1461. return cciss_getintinfo(h, argp);
  1462. case CCISS_SETINTINFO:
  1463. return cciss_setintinfo(h, argp);
  1464. case CCISS_GETNODENAME:
  1465. return cciss_getnodename(h, argp);
  1466. case CCISS_SETNODENAME:
  1467. return cciss_setnodename(h, argp);
  1468. case CCISS_GETHEARTBEAT:
  1469. return cciss_getheartbeat(h, argp);
  1470. case CCISS_GETBUSTYPES:
  1471. return cciss_getbustypes(h, argp);
  1472. case CCISS_GETFIRMVER:
  1473. return cciss_getfirmver(h, argp);
  1474. case CCISS_GETDRIVVER:
  1475. return cciss_getdrivver(h, argp);
  1476. case CCISS_DEREGDISK:
  1477. case CCISS_REGNEWD:
  1478. case CCISS_REVALIDVOLS:
  1479. return rebuild_lun_table(h, 0, 1);
  1480. case CCISS_GETLUNINFO:
  1481. return cciss_getluninfo(h, disk, argp);
  1482. case CCISS_PASSTHRU:
  1483. return cciss_passthru(h, argp);
  1484. case CCISS_BIG_PASSTHRU:
  1485. return cciss_bigpassthru(h, argp);
  1486. /* scsi_cmd_ioctl handles these, below, though some are not */
  1487. /* very meaningful for cciss. SG_IO is the main one people want. */
  1488. case SG_GET_VERSION_NUM:
  1489. case SG_SET_TIMEOUT:
  1490. case SG_GET_TIMEOUT:
  1491. case SG_GET_RESERVED_SIZE:
  1492. case SG_SET_RESERVED_SIZE:
  1493. case SG_EMULATED_HOST:
  1494. case SG_IO:
  1495. case SCSI_IOCTL_SEND_COMMAND:
  1496. return scsi_cmd_ioctl(disk->queue, disk, mode, cmd, argp);
  1497. /* scsi_cmd_ioctl would normally handle these, below, but */
  1498. /* they aren't a good fit for cciss, as CD-ROMs are */
  1499. /* not supported, and we don't have any bus/target/lun */
  1500. /* which we present to the kernel. */
  1501. case CDROM_SEND_PACKET:
  1502. case CDROMCLOSETRAY:
  1503. case CDROMEJECT:
  1504. case SCSI_IOCTL_GET_IDLUN:
  1505. case SCSI_IOCTL_GET_BUS_NUMBER:
  1506. default:
  1507. return -ENOTTY;
  1508. }
  1509. }
  1510. static void cciss_check_queues(ctlr_info_t *h)
  1511. {
  1512. int start_queue = h->next_to_run;
  1513. int i;
  1514. /* check to see if we have maxed out the number of commands that can
  1515. * be placed on the queue. If so then exit. We do this check here
  1516. * in case the interrupt we serviced was from an ioctl and did not
  1517. * free any new commands.
  1518. */
  1519. if ((find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds)) == h->nr_cmds)
  1520. return;
  1521. /* We have room on the queue for more commands. Now we need to queue
  1522. * them up. We will also keep track of the next queue to run so
  1523. * that every queue gets a chance to be started first.
  1524. */
  1525. for (i = 0; i < h->highest_lun + 1; i++) {
  1526. int curr_queue = (start_queue + i) % (h->highest_lun + 1);
  1527. /* make sure the disk has been added and the drive is real
  1528. * because this can be called from the middle of init_one.
  1529. */
  1530. if (!h->drv[curr_queue])
  1531. continue;
  1532. if (!(h->drv[curr_queue]->queue) ||
  1533. !(h->drv[curr_queue]->heads))
  1534. continue;
  1535. blk_start_queue(h->gendisk[curr_queue]->queue);
  1536. /* check to see if we have maxed out the number of commands
  1537. * that can be placed on the queue.
  1538. */
  1539. if ((find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds)) == h->nr_cmds) {
  1540. if (curr_queue == start_queue) {
  1541. h->next_to_run =
  1542. (start_queue + 1) % (h->highest_lun + 1);
  1543. break;
  1544. } else {
  1545. h->next_to_run = curr_queue;
  1546. break;
  1547. }
  1548. }
  1549. }
  1550. }
  1551. static void cciss_softirq_done(struct request *rq)
  1552. {
  1553. CommandList_struct *c = rq->completion_data;
  1554. ctlr_info_t *h = hba[c->ctlr];
  1555. SGDescriptor_struct *curr_sg = c->SG;
  1556. u64bit temp64;
  1557. unsigned long flags;
  1558. int i, ddir;
  1559. int sg_index = 0;
  1560. if (c->Request.Type.Direction == XFER_READ)
  1561. ddir = PCI_DMA_FROMDEVICE;
  1562. else
  1563. ddir = PCI_DMA_TODEVICE;
  1564. /* command did not need to be retried */
  1565. /* unmap the DMA mapping for all the scatter gather elements */
  1566. for (i = 0; i < c->Header.SGList; i++) {
  1567. if (curr_sg[sg_index].Ext == CCISS_SG_CHAIN) {
  1568. cciss_unmap_sg_chain_block(h, c);
  1569. /* Point to the next block */
  1570. curr_sg = h->cmd_sg_list[c->cmdindex];
  1571. sg_index = 0;
  1572. }
  1573. temp64.val32.lower = curr_sg[sg_index].Addr.lower;
  1574. temp64.val32.upper = curr_sg[sg_index].Addr.upper;
  1575. pci_unmap_page(h->pdev, temp64.val, curr_sg[sg_index].Len,
  1576. ddir);
  1577. ++sg_index;
  1578. }
  1579. dev_dbg(&h->pdev->dev, "Done with %p\n", rq);
  1580. /* set the residual count for pc requests */
  1581. if (rq->cmd_type == REQ_TYPE_BLOCK_PC)
  1582. rq->resid_len = c->err_info->ResidualCnt;
  1583. blk_end_request_all(rq, (rq->errors == 0) ? 0 : -EIO);
  1584. spin_lock_irqsave(&h->lock, flags);
  1585. cmd_free(h, c);
  1586. cciss_check_queues(h);
  1587. spin_unlock_irqrestore(&h->lock, flags);
  1588. }
  1589. static inline void log_unit_to_scsi3addr(ctlr_info_t *h,
  1590. unsigned char scsi3addr[], uint32_t log_unit)
  1591. {
  1592. memcpy(scsi3addr, h->drv[log_unit]->LunID,
  1593. sizeof(h->drv[log_unit]->LunID));
  1594. }
  1595. /* This function gets the SCSI vendor, model, and revision of a logical drive
  1596. * via the inquiry page 0. Model, vendor, and rev are set to empty strings if
  1597. * they cannot be read.
  1598. */
  1599. static void cciss_get_device_descr(ctlr_info_t *h, int logvol,
  1600. char *vendor, char *model, char *rev)
  1601. {
  1602. int rc;
  1603. InquiryData_struct *inq_buf;
  1604. unsigned char scsi3addr[8];
  1605. *vendor = '\0';
  1606. *model = '\0';
  1607. *rev = '\0';
  1608. inq_buf = kzalloc(sizeof(InquiryData_struct), GFP_KERNEL);
  1609. if (!inq_buf)
  1610. return;
  1611. log_unit_to_scsi3addr(h, scsi3addr, logvol);
  1612. rc = sendcmd_withirq(h, CISS_INQUIRY, inq_buf, sizeof(*inq_buf), 0,
  1613. scsi3addr, TYPE_CMD);
  1614. if (rc == IO_OK) {
  1615. memcpy(vendor, &inq_buf->data_byte[8], VENDOR_LEN);
  1616. vendor[VENDOR_LEN] = '\0';
  1617. memcpy(model, &inq_buf->data_byte[16], MODEL_LEN);
  1618. model[MODEL_LEN] = '\0';
  1619. memcpy(rev, &inq_buf->data_byte[32], REV_LEN);
  1620. rev[REV_LEN] = '\0';
  1621. }
  1622. kfree(inq_buf);
  1623. return;
  1624. }
  1625. /* This function gets the serial number of a logical drive via
  1626. * inquiry page 0x83. Serial no. is 16 bytes. If the serial
  1627. * number cannot be had, for whatever reason, 16 bytes of 0xff
  1628. * are returned instead.
  1629. */
  1630. static void cciss_get_serial_no(ctlr_info_t *h, int logvol,
  1631. unsigned char *serial_no, int buflen)
  1632. {
  1633. #define PAGE_83_INQ_BYTES 64
  1634. int rc;
  1635. unsigned char *buf;
  1636. unsigned char scsi3addr[8];
  1637. if (buflen > 16)
  1638. buflen = 16;
  1639. memset(serial_no, 0xff, buflen);
  1640. buf = kzalloc(PAGE_83_INQ_BYTES, GFP_KERNEL);
  1641. if (!buf)
  1642. return;
  1643. memset(serial_no, 0, buflen);
  1644. log_unit_to_scsi3addr(h, scsi3addr, logvol);
  1645. rc = sendcmd_withirq(h, CISS_INQUIRY, buf,
  1646. PAGE_83_INQ_BYTES, 0x83, scsi3addr, TYPE_CMD);
  1647. if (rc == IO_OK)
  1648. memcpy(serial_no, &buf[8], buflen);
  1649. kfree(buf);
  1650. return;
  1651. }
  1652. /*
  1653. * cciss_add_disk sets up the block device queue for a logical drive
  1654. */
  1655. static int cciss_add_disk(ctlr_info_t *h, struct gendisk *disk,
  1656. int drv_index)
  1657. {
  1658. disk->queue = blk_init_queue(do_cciss_request, &h->lock);
  1659. if (!disk->queue)
  1660. goto init_queue_failure;
  1661. sprintf(disk->disk_name, "cciss/c%dd%d", h->ctlr, drv_index);
  1662. disk->major = h->major;
  1663. disk->first_minor = drv_index << NWD_SHIFT;
  1664. disk->fops = &cciss_fops;
  1665. if (cciss_create_ld_sysfs_entry(h, drv_index))
  1666. goto cleanup_queue;
  1667. disk->private_data = h->drv[drv_index];
  1668. disk->driverfs_dev = &h->drv[drv_index]->dev;
  1669. /* Set up queue information */
  1670. blk_queue_bounce_limit(disk->queue, h->pdev->dma_mask);
  1671. /* This is a hardware imposed limit. */
  1672. blk_queue_max_segments(disk->queue, h->maxsgentries);
  1673. blk_queue_max_hw_sectors(disk->queue, h->cciss_max_sectors);
  1674. blk_queue_softirq_done(disk->queue, cciss_softirq_done);
  1675. disk->queue->queuedata = h;
  1676. blk_queue_logical_block_size(disk->queue,
  1677. h->drv[drv_index]->block_size);
  1678. /* Make sure all queue data is written out before */
  1679. /* setting h->drv[drv_index]->queue, as setting this */
  1680. /* allows the interrupt handler to start the queue */
  1681. wmb();
  1682. h->drv[drv_index]->queue = disk->queue;
  1683. add_disk(disk);
  1684. return 0;
  1685. cleanup_queue:
  1686. blk_cleanup_queue(disk->queue);
  1687. disk->queue = NULL;
  1688. init_queue_failure:
  1689. return -1;
  1690. }
  1691. /* This function will check the usage_count of the drive to be updated/added.
  1692. * If the usage_count is zero and it is a heretofore unknown drive, or,
  1693. * the drive's capacity, geometry, or serial number has changed,
  1694. * then the drive information will be updated and the disk will be
  1695. * re-registered with the kernel. If these conditions don't hold,
  1696. * then it will be left alone for the next reboot. The exception to this
  1697. * is disk 0 which will always be left registered with the kernel since it
  1698. * is also the controller node. Any changes to disk 0 will show up on
  1699. * the next reboot.
  1700. */
  1701. static void cciss_update_drive_info(ctlr_info_t *h, int drv_index,
  1702. int first_time, int via_ioctl)
  1703. {
  1704. struct gendisk *disk;
  1705. InquiryData_struct *inq_buff = NULL;
  1706. unsigned int block_size;
  1707. sector_t total_size;
  1708. unsigned long flags = 0;
  1709. int ret = 0;
  1710. drive_info_struct *drvinfo;
  1711. /* Get information about the disk and modify the driver structure */
  1712. inq_buff = kmalloc(sizeof(InquiryData_struct), GFP_KERNEL);
  1713. drvinfo = kzalloc(sizeof(*drvinfo), GFP_KERNEL);
  1714. if (inq_buff == NULL || drvinfo == NULL)
  1715. goto mem_msg;
  1716. /* testing to see if 16-byte CDBs are already being used */
  1717. if (h->cciss_read == CCISS_READ_16) {
  1718. cciss_read_capacity_16(h, drv_index,
  1719. &total_size, &block_size);
  1720. } else {
  1721. cciss_read_capacity(h, drv_index, &total_size, &block_size);
  1722. /* if read_capacity returns all F's this volume is >2TB */
  1723. /* in size so we switch to 16-byte CDB's for all */
  1724. /* read/write ops */
  1725. if (total_size == 0xFFFFFFFFULL) {
  1726. cciss_read_capacity_16(h, drv_index,
  1727. &total_size, &block_size);
  1728. h->cciss_read = CCISS_READ_16;
  1729. h->cciss_write = CCISS_WRITE_16;
  1730. } else {
  1731. h->cciss_read = CCISS_READ_10;
  1732. h->cciss_write = CCISS_WRITE_10;
  1733. }
  1734. }
  1735. cciss_geometry_inquiry(h, drv_index, total_size, block_size,
  1736. inq_buff, drvinfo);
  1737. drvinfo->block_size = block_size;
  1738. drvinfo->nr_blocks = total_size + 1;
  1739. cciss_get_device_descr(h, drv_index, drvinfo->vendor,
  1740. drvinfo->model, drvinfo->rev);
  1741. cciss_get_serial_no(h, drv_index, drvinfo->serial_no,
  1742. sizeof(drvinfo->serial_no));
  1743. /* Save the lunid in case we deregister the disk, below. */
  1744. memcpy(drvinfo->LunID, h->drv[drv_index]->LunID,
  1745. sizeof(drvinfo->LunID));
  1746. /* Is it the same disk we already know, and nothing's changed? */
  1747. if (h->drv[drv_index]->raid_level != -1 &&
  1748. ((memcmp(drvinfo->serial_no,
  1749. h->drv[drv_index]->serial_no, 16) == 0) &&
  1750. drvinfo->block_size == h->drv[drv_index]->block_size &&
  1751. drvinfo->nr_blocks == h->drv[drv_index]->nr_blocks &&
  1752. drvinfo->heads == h->drv[drv_index]->heads &&
  1753. drvinfo->sectors == h->drv[drv_index]->sectors &&
  1754. drvinfo->cylinders == h->drv[drv_index]->cylinders))
  1755. /* The disk is unchanged, nothing to update */
  1756. goto freeret;
  1757. /* If we get here it's not the same disk, or something's changed,
  1758. * so we need to * deregister it, and re-register it, if it's not
  1759. * in use.
  1760. * If the disk already exists then deregister it before proceeding
  1761. * (unless it's the first disk (for the controller node).
  1762. */
  1763. if (h->drv[drv_index]->raid_level != -1 && drv_index != 0) {
  1764. dev_warn(&h->pdev->dev, "disk %d has changed.\n", drv_index);
  1765. spin_lock_irqsave(&h->lock, flags);
  1766. h->drv[drv_index]->busy_configuring = 1;
  1767. spin_unlock_irqrestore(&h->lock, flags);
  1768. /* deregister_disk sets h->drv[drv_index]->queue = NULL
  1769. * which keeps the interrupt handler from starting
  1770. * the queue.
  1771. */
  1772. ret = deregister_disk(h, drv_index, 0, via_ioctl);
  1773. }
  1774. /* If the disk is in use return */
  1775. if (ret)
  1776. goto freeret;
  1777. /* Save the new information from cciss_geometry_inquiry
  1778. * and serial number inquiry. If the disk was deregistered
  1779. * above, then h->drv[drv_index] will be NULL.
  1780. */
  1781. if (h->drv[drv_index] == NULL) {
  1782. drvinfo->device_initialized = 0;
  1783. h->drv[drv_index] = drvinfo;
  1784. drvinfo = NULL; /* so it won't be freed below. */
  1785. } else {
  1786. /* special case for cxd0 */
  1787. h->drv[drv_index]->block_size = drvinfo->block_size;
  1788. h->drv[drv_index]->nr_blocks = drvinfo->nr_blocks;
  1789. h->drv[drv_index]->heads = drvinfo->heads;
  1790. h->drv[drv_index]->sectors = drvinfo->sectors;
  1791. h->drv[drv_index]->cylinders = drvinfo->cylinders;
  1792. h->drv[drv_index]->raid_level = drvinfo->raid_level;
  1793. memcpy(h->drv[drv_index]->serial_no, drvinfo->serial_no, 16);
  1794. memcpy(h->drv[drv_index]->vendor, drvinfo->vendor,
  1795. VENDOR_LEN + 1);
  1796. memcpy(h->drv[drv_index]->model, drvinfo->model, MODEL_LEN + 1);
  1797. memcpy(h->drv[drv_index]->rev, drvinfo->rev, REV_LEN + 1);
  1798. }
  1799. ++h->num_luns;
  1800. disk = h->gendisk[drv_index];
  1801. set_capacity(disk, h->drv[drv_index]->nr_blocks);
  1802. /* If it's not disk 0 (drv_index != 0)
  1803. * or if it was disk 0, but there was previously
  1804. * no actual corresponding configured logical drive
  1805. * (raid_leve == -1) then we want to update the
  1806. * logical drive's information.
  1807. */
  1808. if (drv_index || first_time) {
  1809. if (cciss_add_disk(h, disk, drv_index) != 0) {
  1810. cciss_free_gendisk(h, drv_index);
  1811. cciss_free_drive_info(h, drv_index);
  1812. dev_warn(&h->pdev->dev, "could not update disk %d\n",
  1813. drv_index);
  1814. --h->num_luns;
  1815. }
  1816. }
  1817. freeret:
  1818. kfree(inq_buff);
  1819. kfree(drvinfo);
  1820. return;
  1821. mem_msg:
  1822. dev_err(&h->pdev->dev, "out of memory\n");
  1823. goto freeret;
  1824. }
  1825. /* This function will find the first index of the controllers drive array
  1826. * that has a null drv pointer and allocate the drive info struct and
  1827. * will return that index This is where new drives will be added.
  1828. * If the index to be returned is greater than the highest_lun index for
  1829. * the controller then highest_lun is set * to this new index.
  1830. * If there are no available indexes or if tha allocation fails, then -1
  1831. * is returned. * "controller_node" is used to know if this is a real
  1832. * logical drive, or just the controller node, which determines if this
  1833. * counts towards highest_lun.
  1834. */
  1835. static int cciss_alloc_drive_info(ctlr_info_t *h, int controller_node)
  1836. {
  1837. int i;
  1838. drive_info_struct *drv;
  1839. /* Search for an empty slot for our drive info */
  1840. for (i = 0; i < CISS_MAX_LUN; i++) {
  1841. /* if not cxd0 case, and it's occupied, skip it. */
  1842. if (h->drv[i] && i != 0)
  1843. continue;
  1844. /*
  1845. * If it's cxd0 case, and drv is alloc'ed already, and a
  1846. * disk is configured there, skip it.
  1847. */
  1848. if (i == 0 && h->drv[i] && h->drv[i]->raid_level != -1)
  1849. continue;
  1850. /*
  1851. * We've found an empty slot. Update highest_lun
  1852. * provided this isn't just the fake cxd0 controller node.
  1853. */
  1854. if (i > h->highest_lun && !controller_node)
  1855. h->highest_lun = i;
  1856. /* If adding a real disk at cxd0, and it's already alloc'ed */
  1857. if (i == 0 && h->drv[i] != NULL)
  1858. return i;
  1859. /*
  1860. * Found an empty slot, not already alloc'ed. Allocate it.
  1861. * Mark it with raid_level == -1, so we know it's new later on.
  1862. */
  1863. drv = kzalloc(sizeof(*drv), GFP_KERNEL);
  1864. if (!drv)
  1865. return -1;
  1866. drv->raid_level = -1; /* so we know it's new */
  1867. h->drv[i] = drv;
  1868. return i;
  1869. }
  1870. return -1;
  1871. }
  1872. static void cciss_free_drive_info(ctlr_info_t *h, int drv_index)
  1873. {
  1874. kfree(h->drv[drv_index]);
  1875. h->drv[drv_index] = NULL;
  1876. }
  1877. static void cciss_free_gendisk(ctlr_info_t *h, int drv_index)
  1878. {
  1879. put_disk(h->gendisk[drv_index]);
  1880. h->gendisk[drv_index] = NULL;
  1881. }
  1882. /* cciss_add_gendisk finds a free hba[]->drv structure
  1883. * and allocates a gendisk if needed, and sets the lunid
  1884. * in the drvinfo structure. It returns the index into
  1885. * the ->drv[] array, or -1 if none are free.
  1886. * is_controller_node indicates whether highest_lun should
  1887. * count this disk, or if it's only being added to provide
  1888. * a means to talk to the controller in case no logical
  1889. * drives have yet been configured.
  1890. */
  1891. static int cciss_add_gendisk(ctlr_info_t *h, unsigned char lunid[],
  1892. int controller_node)
  1893. {
  1894. int drv_index;
  1895. drv_index = cciss_alloc_drive_info(h, controller_node);
  1896. if (drv_index == -1)
  1897. return -1;
  1898. /*Check if the gendisk needs to be allocated */
  1899. if (!h->gendisk[drv_index]) {
  1900. h->gendisk[drv_index] =
  1901. alloc_disk(1 << NWD_SHIFT);
  1902. if (!h->gendisk[drv_index]) {
  1903. dev_err(&h->pdev->dev,
  1904. "could not allocate a new disk %d\n",
  1905. drv_index);
  1906. goto err_free_drive_info;
  1907. }
  1908. }
  1909. memcpy(h->drv[drv_index]->LunID, lunid,
  1910. sizeof(h->drv[drv_index]->LunID));
  1911. if (cciss_create_ld_sysfs_entry(h, drv_index))
  1912. goto err_free_disk;
  1913. /* Don't need to mark this busy because nobody */
  1914. /* else knows about this disk yet to contend */
  1915. /* for access to it. */
  1916. h->drv[drv_index]->busy_configuring = 0;
  1917. wmb();
  1918. return drv_index;
  1919. err_free_disk:
  1920. cciss_free_gendisk(h, drv_index);
  1921. err_free_drive_info:
  1922. cciss_free_drive_info(h, drv_index);
  1923. return -1;
  1924. }
  1925. /* This is for the special case of a controller which
  1926. * has no logical drives. In this case, we still need
  1927. * to register a disk so the controller can be accessed
  1928. * by the Array Config Utility.
  1929. */
  1930. static void cciss_add_controller_node(ctlr_info_t *h)
  1931. {
  1932. struct gendisk *disk;
  1933. int drv_index;
  1934. if (h->gendisk[0] != NULL) /* already did this? Then bail. */
  1935. return;
  1936. drv_index = cciss_add_gendisk(h, CTLR_LUNID, 1);
  1937. if (drv_index == -1)
  1938. goto error;
  1939. h->drv[drv_index]->block_size = 512;
  1940. h->drv[drv_index]->nr_blocks = 0;
  1941. h->drv[drv_index]->heads = 0;
  1942. h->drv[drv_index]->sectors = 0;
  1943. h->drv[drv_index]->cylinders = 0;
  1944. h->drv[drv_index]->raid_level = -1;
  1945. memset(h->drv[drv_index]->serial_no, 0, 16);
  1946. disk = h->gendisk[drv_index];
  1947. if (cciss_add_disk(h, disk, drv_index) == 0)
  1948. return;
  1949. cciss_free_gendisk(h, drv_index);
  1950. cciss_free_drive_info(h, drv_index);
  1951. error:
  1952. dev_warn(&h->pdev->dev, "could not add disk 0.\n");
  1953. return;
  1954. }
  1955. /* This function will add and remove logical drives from the Logical
  1956. * drive array of the controller and maintain persistency of ordering
  1957. * so that mount points are preserved until the next reboot. This allows
  1958. * for the removal of logical drives in the middle of the drive array
  1959. * without a re-ordering of those drives.
  1960. * INPUT
  1961. * h = The controller to perform the operations on
  1962. */
  1963. static int rebuild_lun_table(ctlr_info_t *h, int first_time,
  1964. int via_ioctl)
  1965. {
  1966. int num_luns;
  1967. ReportLunData_struct *ld_buff = NULL;
  1968. int return_code;
  1969. int listlength = 0;
  1970. int i;
  1971. int drv_found;
  1972. int drv_index = 0;
  1973. unsigned char lunid[8] = CTLR_LUNID;
  1974. unsigned long flags;
  1975. if (!capable(CAP_SYS_RAWIO))
  1976. return -EPERM;
  1977. /* Set busy_configuring flag for this operation */
  1978. spin_lock_irqsave(&h->lock, flags);
  1979. if (h->busy_configuring) {
  1980. spin_unlock_irqrestore(&h->lock, flags);
  1981. return -EBUSY;
  1982. }
  1983. h->busy_configuring = 1;
  1984. spin_unlock_irqrestore(&h->lock, flags);
  1985. ld_buff = kzalloc(sizeof(ReportLunData_struct), GFP_KERNEL);
  1986. if (ld_buff == NULL)
  1987. goto mem_msg;
  1988. return_code = sendcmd_withirq(h, CISS_REPORT_LOG, ld_buff,
  1989. sizeof(ReportLunData_struct),
  1990. 0, CTLR_LUNID, TYPE_CMD);
  1991. if (return_code == IO_OK)
  1992. listlength = be32_to_cpu(*(__be32 *) ld_buff->LUNListLength);
  1993. else { /* reading number of logical volumes failed */
  1994. dev_warn(&h->pdev->dev,
  1995. "report logical volume command failed\n");
  1996. listlength = 0;
  1997. goto freeret;
  1998. }
  1999. num_luns = listlength / 8; /* 8 bytes per entry */
  2000. if (num_luns > CISS_MAX_LUN) {
  2001. num_luns = CISS_MAX_LUN;
  2002. dev_warn(&h->pdev->dev, "more luns configured"
  2003. " on controller than can be handled by"
  2004. " this driver.\n");
  2005. }
  2006. if (num_luns == 0)
  2007. cciss_add_controller_node(h);
  2008. /* Compare controller drive array to driver's drive array
  2009. * to see if any drives are missing on the controller due
  2010. * to action of Array Config Utility (user deletes drive)
  2011. * and deregister logical drives which have disappeared.
  2012. */
  2013. for (i = 0; i <= h->highest_lun; i++) {
  2014. int j;
  2015. drv_found = 0;
  2016. /* skip holes in the array from already deleted drives */
  2017. if (h->drv[i] == NULL)
  2018. continue;
  2019. for (j = 0; j < num_luns; j++) {
  2020. memcpy(lunid, &ld_buff->LUN[j][0], sizeof(lunid));
  2021. if (memcmp(h->drv[i]->LunID, lunid,
  2022. sizeof(lunid)) == 0) {
  2023. drv_found = 1;
  2024. break;
  2025. }
  2026. }
  2027. if (!drv_found) {
  2028. /* Deregister it from the OS, it's gone. */
  2029. spin_lock_irqsave(&h->lock, flags);
  2030. h->drv[i]->busy_configuring = 1;
  2031. spin_unlock_irqrestore(&h->lock, flags);
  2032. return_code = deregister_disk(h, i, 1, via_ioctl);
  2033. if (h->drv[i] != NULL)
  2034. h->drv[i]->busy_configuring = 0;
  2035. }
  2036. }
  2037. /* Compare controller drive array to driver's drive array.
  2038. * Check for updates in the drive information and any new drives
  2039. * on the controller due to ACU adding logical drives, or changing
  2040. * a logical drive's size, etc. Reregister any new/changed drives
  2041. */
  2042. for (i = 0; i < num_luns; i++) {
  2043. int j;
  2044. drv_found = 0;
  2045. memcpy(lunid, &ld_buff->LUN[i][0], sizeof(lunid));
  2046. /* Find if the LUN is already in the drive array
  2047. * of the driver. If so then update its info
  2048. * if not in use. If it does not exist then find
  2049. * the first free index and add it.
  2050. */
  2051. for (j = 0; j <= h->highest_lun; j++) {
  2052. if (h->drv[j] != NULL &&
  2053. memcmp(h->drv[j]->LunID, lunid,
  2054. sizeof(h->drv[j]->LunID)) == 0) {
  2055. drv_index = j;
  2056. drv_found = 1;
  2057. break;
  2058. }
  2059. }
  2060. /* check if the drive was found already in the array */
  2061. if (!drv_found) {
  2062. drv_index = cciss_add_gendisk(h, lunid, 0);
  2063. if (drv_index == -1)
  2064. goto freeret;
  2065. }
  2066. cciss_update_drive_info(h, drv_index, first_time, via_ioctl);
  2067. } /* end for */
  2068. freeret:
  2069. kfree(ld_buff);
  2070. h->busy_configuring = 0;
  2071. /* We return -1 here to tell the ACU that we have registered/updated
  2072. * all of the drives that we can and to keep it from calling us
  2073. * additional times.
  2074. */
  2075. return -1;
  2076. mem_msg:
  2077. dev_err(&h->pdev->dev, "out of memory\n");
  2078. h->busy_configuring = 0;
  2079. goto freeret;
  2080. }
  2081. static void cciss_clear_drive_info(drive_info_struct *drive_info)
  2082. {
  2083. /* zero out the disk size info */
  2084. drive_info->nr_blocks = 0;
  2085. drive_info->block_size = 0;
  2086. drive_info->heads = 0;
  2087. drive_info->sectors = 0;
  2088. drive_info->cylinders = 0;
  2089. drive_info->raid_level = -1;
  2090. memset(drive_info->serial_no, 0, sizeof(drive_info->serial_no));
  2091. memset(drive_info->model, 0, sizeof(drive_info->model));
  2092. memset(drive_info->rev, 0, sizeof(drive_info->rev));
  2093. memset(drive_info->vendor, 0, sizeof(drive_info->vendor));
  2094. /*
  2095. * don't clear the LUNID though, we need to remember which
  2096. * one this one is.
  2097. */
  2098. }
  2099. /* This function will deregister the disk and it's queue from the
  2100. * kernel. It must be called with the controller lock held and the
  2101. * drv structures busy_configuring flag set. It's parameters are:
  2102. *
  2103. * disk = This is the disk to be deregistered
  2104. * drv = This is the drive_info_struct associated with the disk to be
  2105. * deregistered. It contains information about the disk used
  2106. * by the driver.
  2107. * clear_all = This flag determines whether or not the disk information
  2108. * is going to be completely cleared out and the highest_lun
  2109. * reset. Sometimes we want to clear out information about
  2110. * the disk in preparation for re-adding it. In this case
  2111. * the highest_lun should be left unchanged and the LunID
  2112. * should not be cleared.
  2113. * via_ioctl
  2114. * This indicates whether we've reached this path via ioctl.
  2115. * This affects the maximum usage count allowed for c0d0 to be messed with.
  2116. * If this path is reached via ioctl(), then the max_usage_count will
  2117. * be 1, as the process calling ioctl() has got to have the device open.
  2118. * If we get here via sysfs, then the max usage count will be zero.
  2119. */
  2120. static int deregister_disk(ctlr_info_t *h, int drv_index,
  2121. int clear_all, int via_ioctl)
  2122. {
  2123. int i;
  2124. struct gendisk *disk;
  2125. drive_info_struct *drv;
  2126. int recalculate_highest_lun;
  2127. if (!capable(CAP_SYS_RAWIO))
  2128. return -EPERM;
  2129. drv = h->drv[drv_index];
  2130. disk = h->gendisk[drv_index];
  2131. /* make sure logical volume is NOT is use */
  2132. if (clear_all || (h->gendisk[0] == disk)) {
  2133. if (drv->usage_count > via_ioctl)
  2134. return -EBUSY;
  2135. } else if (drv->usage_count > 0)
  2136. return -EBUSY;
  2137. recalculate_highest_lun = (drv == h->drv[h->highest_lun]);
  2138. /* invalidate the devices and deregister the disk. If it is disk
  2139. * zero do not deregister it but just zero out it's values. This
  2140. * allows us to delete disk zero but keep the controller registered.
  2141. */
  2142. if (h->gendisk[0] != disk) {
  2143. struct request_queue *q = disk->queue;
  2144. if (disk->flags & GENHD_FL_UP) {
  2145. cciss_destroy_ld_sysfs_entry(h, drv_index, 0);
  2146. del_gendisk(disk);
  2147. }
  2148. if (q)
  2149. blk_cleanup_queue(q);
  2150. /* If clear_all is set then we are deleting the logical
  2151. * drive, not just refreshing its info. For drives
  2152. * other than disk 0 we will call put_disk. We do not
  2153. * do this for disk 0 as we need it to be able to
  2154. * configure the controller.
  2155. */
  2156. if (clear_all){
  2157. /* This isn't pretty, but we need to find the
  2158. * disk in our array and NULL our the pointer.
  2159. * This is so that we will call alloc_disk if
  2160. * this index is used again later.
  2161. */
  2162. for (i=0; i < CISS_MAX_LUN; i++){
  2163. if (h->gendisk[i] == disk) {
  2164. h->gendisk[i] = NULL;
  2165. break;
  2166. }
  2167. }
  2168. put_disk(disk);
  2169. }
  2170. } else {
  2171. set_capacity(disk, 0);
  2172. cciss_clear_drive_info(drv);
  2173. }
  2174. --h->num_luns;
  2175. /* if it was the last disk, find the new hightest lun */
  2176. if (clear_all && recalculate_highest_lun) {
  2177. int newhighest = -1;
  2178. for (i = 0; i <= h->highest_lun; i++) {
  2179. /* if the disk has size > 0, it is available */
  2180. if (h->drv[i] && h->drv[i]->heads)
  2181. newhighest = i;
  2182. }
  2183. h->highest_lun = newhighest;
  2184. }
  2185. return 0;
  2186. }
  2187. static int fill_cmd(ctlr_info_t *h, CommandList_struct *c, __u8 cmd, void *buff,
  2188. size_t size, __u8 page_code, unsigned char *scsi3addr,
  2189. int cmd_type)
  2190. {
  2191. u64bit buff_dma_handle;
  2192. int status = IO_OK;
  2193. c->cmd_type = CMD_IOCTL_PEND;
  2194. c->Header.ReplyQueue = 0;
  2195. if (buff != NULL) {
  2196. c->Header.SGList = 1;
  2197. c->Header.SGTotal = 1;
  2198. } else {
  2199. c->Header.SGList = 0;
  2200. c->Header.SGTotal = 0;
  2201. }
  2202. c->Header.Tag.lower = c->busaddr;
  2203. memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
  2204. c->Request.Type.Type = cmd_type;
  2205. if (cmd_type == TYPE_CMD) {
  2206. switch (cmd) {
  2207. case CISS_INQUIRY:
  2208. /* are we trying to read a vital product page */
  2209. if (page_code != 0) {
  2210. c->Request.CDB[1] = 0x01;
  2211. c->Request.CDB[2] = page_code;
  2212. }
  2213. c->Request.CDBLen = 6;
  2214. c->Request.Type.Attribute = ATTR_SIMPLE;
  2215. c->Request.Type.Direction = XFER_READ;
  2216. c->Request.Timeout = 0;
  2217. c->Request.CDB[0] = CISS_INQUIRY;
  2218. c->Request.CDB[4] = size & 0xFF;
  2219. break;
  2220. case CISS_REPORT_LOG:
  2221. case CISS_REPORT_PHYS:
  2222. /* Talking to controller so It's a physical command
  2223. mode = 00 target = 0. Nothing to write.
  2224. */
  2225. c->Request.CDBLen = 12;
  2226. c->Request.Type.Attribute = ATTR_SIMPLE;
  2227. c->Request.Type.Direction = XFER_READ;
  2228. c->Request.Timeout = 0;
  2229. c->Request.CDB[0] = cmd;
  2230. c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
  2231. c->Request.CDB[7] = (size >> 16) & 0xFF;
  2232. c->Request.CDB[8] = (size >> 8) & 0xFF;
  2233. c->Request.CDB[9] = size & 0xFF;
  2234. break;
  2235. case CCISS_READ_CAPACITY:
  2236. c->Request.CDBLen = 10;
  2237. c->Request.Type.Attribute = ATTR_SIMPLE;
  2238. c->Request.Type.Direction = XFER_READ;
  2239. c->Request.Timeout = 0;
  2240. c->Request.CDB[0] = cmd;
  2241. break;
  2242. case CCISS_READ_CAPACITY_16:
  2243. c->Request.CDBLen = 16;
  2244. c->Request.Type.Attribute = ATTR_SIMPLE;
  2245. c->Request.Type.Direction = XFER_READ;
  2246. c->Request.Timeout = 0;
  2247. c->Request.CDB[0] = cmd;
  2248. c->Request.CDB[1] = 0x10;
  2249. c->Request.CDB[10] = (size >> 24) & 0xFF;
  2250. c->Request.CDB[11] = (size >> 16) & 0xFF;
  2251. c->Request.CDB[12] = (size >> 8) & 0xFF;
  2252. c->Request.CDB[13] = size & 0xFF;
  2253. c->Request.Timeout = 0;
  2254. c->Request.CDB[0] = cmd;
  2255. break;
  2256. case CCISS_CACHE_FLUSH:
  2257. c->Request.CDBLen = 12;
  2258. c->Request.Type.Attribute = ATTR_SIMPLE;
  2259. c->Request.Type.Direction = XFER_WRITE;
  2260. c->Request.Timeout = 0;
  2261. c->Request.CDB[0] = BMIC_WRITE;
  2262. c->Request.CDB[6] = BMIC_CACHE_FLUSH;
  2263. break;
  2264. case TEST_UNIT_READY:
  2265. c->Request.CDBLen = 6;
  2266. c->Request.Type.Attribute = ATTR_SIMPLE;
  2267. c->Request.Type.Direction = XFER_NONE;
  2268. c->Request.Timeout = 0;
  2269. break;
  2270. default:
  2271. dev_warn(&h->pdev->dev, "Unknown Command 0x%c\n", cmd);
  2272. return IO_ERROR;
  2273. }
  2274. } else if (cmd_type == TYPE_MSG) {
  2275. switch (cmd) {
  2276. case 0: /* ABORT message */
  2277. c->Request.CDBLen = 12;
  2278. c->Request.Type.Attribute = ATTR_SIMPLE;
  2279. c->Request.Type.Direction = XFER_WRITE;
  2280. c->Request.Timeout = 0;
  2281. c->Request.CDB[0] = cmd; /* abort */
  2282. c->Request.CDB[1] = 0; /* abort a command */
  2283. /* buff contains the tag of the command to abort */
  2284. memcpy(&c->Request.CDB[4], buff, 8);
  2285. break;
  2286. case 1: /* RESET message */
  2287. c->Request.CDBLen = 16;
  2288. c->Request.Type.Attribute = ATTR_SIMPLE;
  2289. c->Request.Type.Direction = XFER_NONE;
  2290. c->Request.Timeout = 0;
  2291. memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
  2292. c->Request.CDB[0] = cmd; /* reset */
  2293. c->Request.CDB[1] = 0x03; /* reset a target */
  2294. break;
  2295. case 3: /* No-Op message */
  2296. c->Request.CDBLen = 1;
  2297. c->Request.Type.Attribute = ATTR_SIMPLE;
  2298. c->Request.Type.Direction = XFER_WRITE;
  2299. c->Request.Timeout = 0;
  2300. c->Request.CDB[0] = cmd;
  2301. break;
  2302. default:
  2303. dev_warn(&h->pdev->dev,
  2304. "unknown message type %d\n", cmd);
  2305. return IO_ERROR;
  2306. }
  2307. } else {
  2308. dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
  2309. return IO_ERROR;
  2310. }
  2311. /* Fill in the scatter gather information */
  2312. if (size > 0) {
  2313. buff_dma_handle.val = (__u64) pci_map_single(h->pdev,
  2314. buff, size,
  2315. PCI_DMA_BIDIRECTIONAL);
  2316. c->SG[0].Addr.lower = buff_dma_handle.val32.lower;
  2317. c->SG[0].Addr.upper = buff_dma_handle.val32.upper;
  2318. c->SG[0].Len = size;
  2319. c->SG[0].Ext = 0; /* we are not chaining */
  2320. }
  2321. return status;
  2322. }
  2323. static int check_target_status(ctlr_info_t *h, CommandList_struct *c)
  2324. {
  2325. switch (c->err_info->ScsiStatus) {
  2326. case SAM_STAT_GOOD:
  2327. return IO_OK;
  2328. case SAM_STAT_CHECK_CONDITION:
  2329. switch (0xf & c->err_info->SenseInfo[2]) {
  2330. case 0: return IO_OK; /* no sense */
  2331. case 1: return IO_OK; /* recovered error */
  2332. default:
  2333. if (check_for_unit_attention(h, c))
  2334. return IO_NEEDS_RETRY;
  2335. dev_warn(&h->pdev->dev, "cmd 0x%02x "
  2336. "check condition, sense key = 0x%02x\n",
  2337. c->Request.CDB[0], c->err_info->SenseInfo[2]);
  2338. }
  2339. break;
  2340. default:
  2341. dev_warn(&h->pdev->dev, "cmd 0x%02x"
  2342. "scsi status = 0x%02x\n",
  2343. c->Request.CDB[0], c->err_info->ScsiStatus);
  2344. break;
  2345. }
  2346. return IO_ERROR;
  2347. }
  2348. static int process_sendcmd_error(ctlr_info_t *h, CommandList_struct *c)
  2349. {
  2350. int return_status = IO_OK;
  2351. if (c->err_info->CommandStatus == CMD_SUCCESS)
  2352. return IO_OK;
  2353. switch (c->err_info->CommandStatus) {
  2354. case CMD_TARGET_STATUS:
  2355. return_status = check_target_status(h, c);
  2356. break;
  2357. case CMD_DATA_UNDERRUN:
  2358. case CMD_DATA_OVERRUN:
  2359. /* expected for inquiry and report lun commands */
  2360. break;
  2361. case CMD_INVALID:
  2362. dev_warn(&h->pdev->dev, "cmd 0x%02x is "
  2363. "reported invalid\n", c->Request.CDB[0]);
  2364. return_status = IO_ERROR;
  2365. break;
  2366. case CMD_PROTOCOL_ERR:
  2367. dev_warn(&h->pdev->dev, "cmd 0x%02x has "
  2368. "protocol error\n", c->Request.CDB[0]);
  2369. return_status = IO_ERROR;
  2370. break;
  2371. case CMD_HARDWARE_ERR:
  2372. dev_warn(&h->pdev->dev, "cmd 0x%02x had "
  2373. " hardware error\n", c->Request.CDB[0]);
  2374. return_status = IO_ERROR;
  2375. break;
  2376. case CMD_CONNECTION_LOST:
  2377. dev_warn(&h->pdev->dev, "cmd 0x%02x had "
  2378. "connection lost\n", c->Request.CDB[0]);
  2379. return_status = IO_ERROR;
  2380. break;
  2381. case CMD_ABORTED:
  2382. dev_warn(&h->pdev->dev, "cmd 0x%02x was "
  2383. "aborted\n", c->Request.CDB[0]);
  2384. return_status = IO_ERROR;
  2385. break;
  2386. case CMD_ABORT_FAILED:
  2387. dev_warn(&h->pdev->dev, "cmd 0x%02x reports "
  2388. "abort failed\n", c->Request.CDB[0]);
  2389. return_status = IO_ERROR;
  2390. break;
  2391. case CMD_UNSOLICITED_ABORT:
  2392. dev_warn(&h->pdev->dev, "unsolicited abort 0x%02x\n",
  2393. c->Request.CDB[0]);
  2394. return_status = IO_NEEDS_RETRY;
  2395. break;
  2396. case CMD_UNABORTABLE:
  2397. dev_warn(&h->pdev->dev, "cmd unabortable\n");
  2398. return_status = IO_ERROR;
  2399. break;
  2400. default:
  2401. dev_warn(&h->pdev->dev, "cmd 0x%02x returned "
  2402. "unknown status %x\n", c->Request.CDB[0],
  2403. c->err_info->CommandStatus);
  2404. return_status = IO_ERROR;
  2405. }
  2406. return return_status;
  2407. }
  2408. static int sendcmd_withirq_core(ctlr_info_t *h, CommandList_struct *c,
  2409. int attempt_retry)
  2410. {
  2411. DECLARE_COMPLETION_ONSTACK(wait);
  2412. u64bit buff_dma_handle;
  2413. int return_status = IO_OK;
  2414. resend_cmd2:
  2415. c->waiting = &wait;
  2416. enqueue_cmd_and_start_io(h, c);
  2417. wait_for_completion(&wait);
  2418. if (c->err_info->CommandStatus == 0 || !attempt_retry)
  2419. goto command_done;
  2420. return_status = process_sendcmd_error(h, c);
  2421. if (return_status == IO_NEEDS_RETRY &&
  2422. c->retry_count < MAX_CMD_RETRIES) {
  2423. dev_warn(&h->pdev->dev, "retrying 0x%02x\n",
  2424. c->Request.CDB[0]);
  2425. c->retry_count++;
  2426. /* erase the old error information */
  2427. memset(c->err_info, 0, sizeof(ErrorInfo_struct));
  2428. return_status = IO_OK;
  2429. INIT_COMPLETION(wait);
  2430. goto resend_cmd2;
  2431. }
  2432. command_done:
  2433. /* unlock the buffers from DMA */
  2434. buff_dma_handle.val32.lower = c->SG[0].Addr.lower;
  2435. buff_dma_handle.val32.upper = c->SG[0].Addr.upper;
  2436. pci_unmap_single(h->pdev, (dma_addr_t) buff_dma_handle.val,
  2437. c->SG[0].Len, PCI_DMA_BIDIRECTIONAL);
  2438. return return_status;
  2439. }
  2440. static int sendcmd_withirq(ctlr_info_t *h, __u8 cmd, void *buff, size_t size,
  2441. __u8 page_code, unsigned char scsi3addr[],
  2442. int cmd_type)
  2443. {
  2444. CommandList_struct *c;
  2445. int return_status;
  2446. c = cmd_special_alloc(h);
  2447. if (!c)
  2448. return -ENOMEM;
  2449. return_status = fill_cmd(h, c, cmd, buff, size, page_code,
  2450. scsi3addr, cmd_type);
  2451. if (return_status == IO_OK)
  2452. return_status = sendcmd_withirq_core(h, c, 1);
  2453. cmd_special_free(h, c);
  2454. return return_status;
  2455. }
  2456. static void cciss_geometry_inquiry(ctlr_info_t *h, int logvol,
  2457. sector_t total_size,
  2458. unsigned int block_size,
  2459. InquiryData_struct *inq_buff,
  2460. drive_info_struct *drv)
  2461. {
  2462. int return_code;
  2463. unsigned long t;
  2464. unsigned char scsi3addr[8];
  2465. memset(inq_buff, 0, sizeof(InquiryData_struct));
  2466. log_unit_to_scsi3addr(h, scsi3addr, logvol);
  2467. return_code = sendcmd_withirq(h, CISS_INQUIRY, inq_buff,
  2468. sizeof(*inq_buff), 0xC1, scsi3addr, TYPE_CMD);
  2469. if (return_code == IO_OK) {
  2470. if (inq_buff->data_byte[8] == 0xFF) {
  2471. dev_warn(&h->pdev->dev,
  2472. "reading geometry failed, volume "
  2473. "does not support reading geometry\n");
  2474. drv->heads = 255;
  2475. drv->sectors = 32; /* Sectors per track */
  2476. drv->cylinders = total_size + 1;
  2477. drv->raid_level = RAID_UNKNOWN;
  2478. } else {
  2479. drv->heads = inq_buff->data_byte[6];
  2480. drv->sectors = inq_buff->data_byte[7];
  2481. drv->cylinders = (inq_buff->data_byte[4] & 0xff) << 8;
  2482. drv->cylinders += inq_buff->data_byte[5];
  2483. drv->raid_level = inq_buff->data_byte[8];
  2484. }
  2485. drv->block_size = block_size;
  2486. drv->nr_blocks = total_size + 1;
  2487. t = drv->heads * drv->sectors;
  2488. if (t > 1) {
  2489. sector_t real_size = total_size + 1;
  2490. unsigned long rem = sector_div(real_size, t);
  2491. if (rem)
  2492. real_size++;
  2493. drv->cylinders = real_size;
  2494. }
  2495. } else { /* Get geometry failed */
  2496. dev_warn(&h->pdev->dev, "reading geometry failed\n");
  2497. }
  2498. }
  2499. static void
  2500. cciss_read_capacity(ctlr_info_t *h, int logvol, sector_t *total_size,
  2501. unsigned int *block_size)
  2502. {
  2503. ReadCapdata_struct *buf;
  2504. int return_code;
  2505. unsigned char scsi3addr[8];
  2506. buf = kzalloc(sizeof(ReadCapdata_struct), GFP_KERNEL);
  2507. if (!buf) {
  2508. dev_warn(&h->pdev->dev, "out of memory\n");
  2509. return;
  2510. }
  2511. log_unit_to_scsi3addr(h, scsi3addr, logvol);
  2512. return_code = sendcmd_withirq(h, CCISS_READ_CAPACITY, buf,
  2513. sizeof(ReadCapdata_struct), 0, scsi3addr, TYPE_CMD);
  2514. if (return_code == IO_OK) {
  2515. *total_size = be32_to_cpu(*(__be32 *) buf->total_size);
  2516. *block_size = be32_to_cpu(*(__be32 *) buf->block_size);
  2517. } else { /* read capacity command failed */
  2518. dev_warn(&h->pdev->dev, "read capacity failed\n");
  2519. *total_size = 0;
  2520. *block_size = BLOCK_SIZE;
  2521. }
  2522. kfree(buf);
  2523. }
  2524. static void cciss_read_capacity_16(ctlr_info_t *h, int logvol,
  2525. sector_t *total_size, unsigned int *block_size)
  2526. {
  2527. ReadCapdata_struct_16 *buf;
  2528. int return_code;
  2529. unsigned char scsi3addr[8];
  2530. buf = kzalloc(sizeof(ReadCapdata_struct_16), GFP_KERNEL);
  2531. if (!buf) {
  2532. dev_warn(&h->pdev->dev, "out of memory\n");
  2533. return;
  2534. }
  2535. log_unit_to_scsi3addr(h, scsi3addr, logvol);
  2536. return_code = sendcmd_withirq(h, CCISS_READ_CAPACITY_16,
  2537. buf, sizeof(ReadCapdata_struct_16),
  2538. 0, scsi3addr, TYPE_CMD);
  2539. if (return_code == IO_OK) {
  2540. *total_size = be64_to_cpu(*(__be64 *) buf->total_size);
  2541. *block_size = be32_to_cpu(*(__be32 *) buf->block_size);
  2542. } else { /* read capacity command failed */
  2543. dev_warn(&h->pdev->dev, "read capacity failed\n");
  2544. *total_size = 0;
  2545. *block_size = BLOCK_SIZE;
  2546. }
  2547. dev_info(&h->pdev->dev, " blocks= %llu block_size= %d\n",
  2548. (unsigned long long)*total_size+1, *block_size);
  2549. kfree(buf);
  2550. }
  2551. static int cciss_revalidate(struct gendisk *disk)
  2552. {
  2553. ctlr_info_t *h = get_host(disk);
  2554. drive_info_struct *drv = get_drv(disk);
  2555. int logvol;
  2556. int FOUND = 0;
  2557. unsigned int block_size;
  2558. sector_t total_size;
  2559. InquiryData_struct *inq_buff = NULL;
  2560. for (logvol = 0; logvol <= h->highest_lun; logvol++) {
  2561. if (!h->drv[logvol])
  2562. continue;
  2563. if (memcmp(h->drv[logvol]->LunID, drv->LunID,
  2564. sizeof(drv->LunID)) == 0) {
  2565. FOUND = 1;
  2566. break;
  2567. }
  2568. }
  2569. if (!FOUND)
  2570. return 1;
  2571. inq_buff = kmalloc(sizeof(InquiryData_struct), GFP_KERNEL);
  2572. if (inq_buff == NULL) {
  2573. dev_warn(&h->pdev->dev, "out of memory\n");
  2574. return 1;
  2575. }
  2576. if (h->cciss_read == CCISS_READ_10) {
  2577. cciss_read_capacity(h, logvol,
  2578. &total_size, &block_size);
  2579. } else {
  2580. cciss_read_capacity_16(h, logvol,
  2581. &total_size, &block_size);
  2582. }
  2583. cciss_geometry_inquiry(h, logvol, total_size, block_size,
  2584. inq_buff, drv);
  2585. blk_queue_logical_block_size(drv->queue, drv->block_size);
  2586. set_capacity(disk, drv->nr_blocks);
  2587. kfree(inq_buff);
  2588. return 0;
  2589. }
  2590. /*
  2591. * Map (physical) PCI mem into (virtual) kernel space
  2592. */
  2593. static void __iomem *remap_pci_mem(ulong base, ulong size)
  2594. {
  2595. ulong page_base = ((ulong) base) & PAGE_MASK;
  2596. ulong page_offs = ((ulong) base) - page_base;
  2597. void __iomem *page_remapped = ioremap(page_base, page_offs + size);
  2598. return page_remapped ? (page_remapped + page_offs) : NULL;
  2599. }
  2600. /*
  2601. * Takes jobs of the Q and sends them to the hardware, then puts it on
  2602. * the Q to wait for completion.
  2603. */
  2604. static void start_io(ctlr_info_t *h)
  2605. {
  2606. CommandList_struct *c;
  2607. while (!list_empty(&h->reqQ)) {
  2608. c = list_entry(h->reqQ.next, CommandList_struct, list);
  2609. /* can't do anything if fifo is full */
  2610. if ((h->access.fifo_full(h))) {
  2611. dev_warn(&h->pdev->dev, "fifo full\n");
  2612. break;
  2613. }
  2614. /* Get the first entry from the Request Q */
  2615. removeQ(c);
  2616. h->Qdepth--;
  2617. /* Tell the controller execute command */
  2618. h->access.submit_command(h, c);
  2619. /* Put job onto the completed Q */
  2620. addQ(&h->cmpQ, c);
  2621. }
  2622. }
  2623. /* Assumes that h->lock is held. */
  2624. /* Zeros out the error record and then resends the command back */
  2625. /* to the controller */
  2626. static inline void resend_cciss_cmd(ctlr_info_t *h, CommandList_struct *c)
  2627. {
  2628. /* erase the old error information */
  2629. memset(c->err_info, 0, sizeof(ErrorInfo_struct));
  2630. /* add it to software queue and then send it to the controller */
  2631. addQ(&h->reqQ, c);
  2632. h->Qdepth++;
  2633. if (h->Qdepth > h->maxQsinceinit)
  2634. h->maxQsinceinit = h->Qdepth;
  2635. start_io(h);
  2636. }
  2637. static inline unsigned int make_status_bytes(unsigned int scsi_status_byte,
  2638. unsigned int msg_byte, unsigned int host_byte,
  2639. unsigned int driver_byte)
  2640. {
  2641. /* inverse of macros in scsi.h */
  2642. return (scsi_status_byte & 0xff) |
  2643. ((msg_byte & 0xff) << 8) |
  2644. ((host_byte & 0xff) << 16) |
  2645. ((driver_byte & 0xff) << 24);
  2646. }
  2647. static inline int evaluate_target_status(ctlr_info_t *h,
  2648. CommandList_struct *cmd, int *retry_cmd)
  2649. {
  2650. unsigned char sense_key;
  2651. unsigned char status_byte, msg_byte, host_byte, driver_byte;
  2652. int error_value;
  2653. *retry_cmd = 0;
  2654. /* If we get in here, it means we got "target status", that is, scsi status */
  2655. status_byte = cmd->err_info->ScsiStatus;
  2656. driver_byte = DRIVER_OK;
  2657. msg_byte = cmd->err_info->CommandStatus; /* correct? seems too device specific */
  2658. if (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC)
  2659. host_byte = DID_PASSTHROUGH;
  2660. else
  2661. host_byte = DID_OK;
  2662. error_value = make_status_bytes(status_byte, msg_byte,
  2663. host_byte, driver_byte);
  2664. if (cmd->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION) {
  2665. if (cmd->rq->cmd_type != REQ_TYPE_BLOCK_PC)
  2666. dev_warn(&h->pdev->dev, "cmd %p "
  2667. "has SCSI Status 0x%x\n",
  2668. cmd, cmd->err_info->ScsiStatus);
  2669. return error_value;
  2670. }
  2671. /* check the sense key */
  2672. sense_key = 0xf & cmd->err_info->SenseInfo[2];
  2673. /* no status or recovered error */
  2674. if (((sense_key == 0x0) || (sense_key == 0x1)) &&
  2675. (cmd->rq->cmd_type != REQ_TYPE_BLOCK_PC))
  2676. error_value = 0;
  2677. if (check_for_unit_attention(h, cmd)) {
  2678. *retry_cmd = !(cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC);
  2679. return 0;
  2680. }
  2681. /* Not SG_IO or similar? */
  2682. if (cmd->rq->cmd_type != REQ_TYPE_BLOCK_PC) {
  2683. if (error_value != 0)
  2684. dev_warn(&h->pdev->dev, "cmd %p has CHECK CONDITION"
  2685. " sense key = 0x%x\n", cmd, sense_key);
  2686. return error_value;
  2687. }
  2688. /* SG_IO or similar, copy sense data back */
  2689. if (cmd->rq->sense) {
  2690. if (cmd->rq->sense_len > cmd->err_info->SenseLen)
  2691. cmd->rq->sense_len = cmd->err_info->SenseLen;
  2692. memcpy(cmd->rq->sense, cmd->err_info->SenseInfo,
  2693. cmd->rq->sense_len);
  2694. } else
  2695. cmd->rq->sense_len = 0;
  2696. return error_value;
  2697. }
  2698. /* checks the status of the job and calls complete buffers to mark all
  2699. * buffers for the completed job. Note that this function does not need
  2700. * to hold the hba/queue lock.
  2701. */
  2702. static inline void complete_command(ctlr_info_t *h, CommandList_struct *cmd,
  2703. int timeout)
  2704. {
  2705. int retry_cmd = 0;
  2706. struct request *rq = cmd->rq;
  2707. rq->errors = 0;
  2708. if (timeout)
  2709. rq->errors = make_status_bytes(0, 0, 0, DRIVER_TIMEOUT);
  2710. if (cmd->err_info->CommandStatus == 0) /* no error has occurred */
  2711. goto after_error_processing;
  2712. switch (cmd->err_info->CommandStatus) {
  2713. case CMD_TARGET_STATUS:
  2714. rq->errors = evaluate_target_status(h, cmd, &retry_cmd);
  2715. break;
  2716. case CMD_DATA_UNDERRUN:
  2717. if (cmd->rq->cmd_type == REQ_TYPE_FS) {
  2718. dev_warn(&h->pdev->dev, "cmd %p has"
  2719. " completed with data underrun "
  2720. "reported\n", cmd);
  2721. cmd->rq->resid_len = cmd->err_info->ResidualCnt;
  2722. }
  2723. break;
  2724. case CMD_DATA_OVERRUN:
  2725. if (cmd->rq->cmd_type == REQ_TYPE_FS)
  2726. dev_warn(&h->pdev->dev, "cciss: cmd %p has"
  2727. " completed with data overrun "
  2728. "reported\n", cmd);
  2729. break;
  2730. case CMD_INVALID:
  2731. dev_warn(&h->pdev->dev, "cciss: cmd %p is "
  2732. "reported invalid\n", cmd);
  2733. rq->errors = make_status_bytes(SAM_STAT_GOOD,
  2734. cmd->err_info->CommandStatus, DRIVER_OK,
  2735. (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
  2736. DID_PASSTHROUGH : DID_ERROR);
  2737. break;
  2738. case CMD_PROTOCOL_ERR:
  2739. dev_warn(&h->pdev->dev, "cciss: cmd %p has "
  2740. "protocol error\n", cmd);
  2741. rq->errors = make_status_bytes(SAM_STAT_GOOD,
  2742. cmd->err_info->CommandStatus, DRIVER_OK,
  2743. (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
  2744. DID_PASSTHROUGH : DID_ERROR);
  2745. break;
  2746. case CMD_HARDWARE_ERR:
  2747. dev_warn(&h->pdev->dev, "cciss: cmd %p had "
  2748. " hardware error\n", cmd);
  2749. rq->errors = make_status_bytes(SAM_STAT_GOOD,
  2750. cmd->err_info->CommandStatus, DRIVER_OK,
  2751. (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
  2752. DID_PASSTHROUGH : DID_ERROR);
  2753. break;
  2754. case CMD_CONNECTION_LOST:
  2755. dev_warn(&h->pdev->dev, "cciss: cmd %p had "
  2756. "connection lost\n", cmd);
  2757. rq->errors = make_status_bytes(SAM_STAT_GOOD,
  2758. cmd->err_info->CommandStatus, DRIVER_OK,
  2759. (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
  2760. DID_PASSTHROUGH : DID_ERROR);
  2761. break;
  2762. case CMD_ABORTED:
  2763. dev_warn(&h->pdev->dev, "cciss: cmd %p was "
  2764. "aborted\n", cmd);
  2765. rq->errors = make_status_bytes(SAM_STAT_GOOD,
  2766. cmd->err_info->CommandStatus, DRIVER_OK,
  2767. (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
  2768. DID_PASSTHROUGH : DID_ABORT);
  2769. break;
  2770. case CMD_ABORT_FAILED:
  2771. dev_warn(&h->pdev->dev, "cciss: cmd %p reports "
  2772. "abort failed\n", cmd);
  2773. rq->errors = make_status_bytes(SAM_STAT_GOOD,
  2774. cmd->err_info->CommandStatus, DRIVER_OK,
  2775. (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
  2776. DID_PASSTHROUGH : DID_ERROR);
  2777. break;
  2778. case CMD_UNSOLICITED_ABORT:
  2779. dev_warn(&h->pdev->dev, "cciss%d: unsolicited "
  2780. "abort %p\n", h->ctlr, cmd);
  2781. if (cmd->retry_count < MAX_CMD_RETRIES) {
  2782. retry_cmd = 1;
  2783. dev_warn(&h->pdev->dev, "retrying %p\n", cmd);
  2784. cmd->retry_count++;
  2785. } else
  2786. dev_warn(&h->pdev->dev,
  2787. "%p retried too many times\n", cmd);
  2788. rq->errors = make_status_bytes(SAM_STAT_GOOD,
  2789. cmd->err_info->CommandStatus, DRIVER_OK,
  2790. (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
  2791. DID_PASSTHROUGH : DID_ABORT);
  2792. break;
  2793. case CMD_TIMEOUT:
  2794. dev_warn(&h->pdev->dev, "cmd %p timedout\n", cmd);
  2795. rq->errors = make_status_bytes(SAM_STAT_GOOD,
  2796. cmd->err_info->CommandStatus, DRIVER_OK,
  2797. (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
  2798. DID_PASSTHROUGH : DID_ERROR);
  2799. break;
  2800. case CMD_UNABORTABLE:
  2801. dev_warn(&h->pdev->dev, "cmd %p unabortable\n", cmd);
  2802. rq->errors = make_status_bytes(SAM_STAT_GOOD,
  2803. cmd->err_info->CommandStatus, DRIVER_OK,
  2804. cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC ?
  2805. DID_PASSTHROUGH : DID_ERROR);
  2806. break;
  2807. default:
  2808. dev_warn(&h->pdev->dev, "cmd %p returned "
  2809. "unknown status %x\n", cmd,
  2810. cmd->err_info->CommandStatus);
  2811. rq->errors = make_status_bytes(SAM_STAT_GOOD,
  2812. cmd->err_info->CommandStatus, DRIVER_OK,
  2813. (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
  2814. DID_PASSTHROUGH : DID_ERROR);
  2815. }
  2816. after_error_processing:
  2817. /* We need to return this command */
  2818. if (retry_cmd) {
  2819. resend_cciss_cmd(h, cmd);
  2820. return;
  2821. }
  2822. cmd->rq->completion_data = cmd;
  2823. blk_complete_request(cmd->rq);
  2824. }
  2825. static inline u32 cciss_tag_contains_index(u32 tag)
  2826. {
  2827. #define DIRECT_LOOKUP_BIT 0x10
  2828. return tag & DIRECT_LOOKUP_BIT;
  2829. }
  2830. static inline u32 cciss_tag_to_index(u32 tag)
  2831. {
  2832. #define DIRECT_LOOKUP_SHIFT 5
  2833. return tag >> DIRECT_LOOKUP_SHIFT;
  2834. }
  2835. static inline u32 cciss_tag_discard_error_bits(ctlr_info_t *h, u32 tag)
  2836. {
  2837. #define CCISS_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
  2838. #define CCISS_SIMPLE_ERROR_BITS 0x03
  2839. if (likely(h->transMethod & CFGTBL_Trans_Performant))
  2840. return tag & ~CCISS_PERF_ERROR_BITS;
  2841. return tag & ~CCISS_SIMPLE_ERROR_BITS;
  2842. }
  2843. static inline void cciss_mark_tag_indexed(u32 *tag)
  2844. {
  2845. *tag |= DIRECT_LOOKUP_BIT;
  2846. }
  2847. static inline void cciss_set_tag_index(u32 *tag, u32 index)
  2848. {
  2849. *tag |= (index << DIRECT_LOOKUP_SHIFT);
  2850. }
  2851. /*
  2852. * Get a request and submit it to the controller.
  2853. */
  2854. static void do_cciss_request(struct request_queue *q)
  2855. {
  2856. ctlr_info_t *h = q->queuedata;
  2857. CommandList_struct *c;
  2858. sector_t start_blk;
  2859. int seg;
  2860. struct request *creq;
  2861. u64bit temp64;
  2862. struct scatterlist *tmp_sg;
  2863. SGDescriptor_struct *curr_sg;
  2864. drive_info_struct *drv;
  2865. int i, dir;
  2866. int sg_index = 0;
  2867. int chained = 0;
  2868. queue:
  2869. creq = blk_peek_request(q);
  2870. if (!creq)
  2871. goto startio;
  2872. BUG_ON(creq->nr_phys_segments > h->maxsgentries);
  2873. c = cmd_alloc(h);
  2874. if (!c)
  2875. goto full;
  2876. blk_start_request(creq);
  2877. tmp_sg = h->scatter_list[c->cmdindex];
  2878. spin_unlock_irq(q->queue_lock);
  2879. c->cmd_type = CMD_RWREQ;
  2880. c->rq = creq;
  2881. /* fill in the request */
  2882. drv = creq->rq_disk->private_data;
  2883. c->Header.ReplyQueue = 0; /* unused in simple mode */
  2884. /* got command from pool, so use the command block index instead */
  2885. /* for direct lookups. */
  2886. /* The first 2 bits are reserved for controller error reporting. */
  2887. cciss_set_tag_index(&c->Header.Tag.lower, c->cmdindex);
  2888. cciss_mark_tag_indexed(&c->Header.Tag.lower);
  2889. memcpy(&c->Header.LUN, drv->LunID, sizeof(drv->LunID));
  2890. c->Request.CDBLen = 10; /* 12 byte commands not in FW yet; */
  2891. c->Request.Type.Type = TYPE_CMD; /* It is a command. */
  2892. c->Request.Type.Attribute = ATTR_SIMPLE;
  2893. c->Request.Type.Direction =
  2894. (rq_data_dir(creq) == READ) ? XFER_READ : XFER_WRITE;
  2895. c->Request.Timeout = 0; /* Don't time out */
  2896. c->Request.CDB[0] =
  2897. (rq_data_dir(creq) == READ) ? h->cciss_read : h->cciss_write;
  2898. start_blk = blk_rq_pos(creq);
  2899. dev_dbg(&h->pdev->dev, "sector =%d nr_sectors=%d\n",
  2900. (int)blk_rq_pos(creq), (int)blk_rq_sectors(creq));
  2901. sg_init_table(tmp_sg, h->maxsgentries);
  2902. seg = blk_rq_map_sg(q, creq, tmp_sg);
  2903. /* get the DMA records for the setup */
  2904. if (c->Request.Type.Direction == XFER_READ)
  2905. dir = PCI_DMA_FROMDEVICE;
  2906. else
  2907. dir = PCI_DMA_TODEVICE;
  2908. curr_sg = c->SG;
  2909. sg_index = 0;
  2910. chained = 0;
  2911. for (i = 0; i < seg; i++) {
  2912. if (((sg_index+1) == (h->max_cmd_sgentries)) &&
  2913. !chained && ((seg - i) > 1)) {
  2914. /* Point to next chain block. */
  2915. curr_sg = h->cmd_sg_list[c->cmdindex];
  2916. sg_index = 0;
  2917. chained = 1;
  2918. }
  2919. curr_sg[sg_index].Len = tmp_sg[i].length;
  2920. temp64.val = (__u64) pci_map_page(h->pdev, sg_page(&tmp_sg[i]),
  2921. tmp_sg[i].offset,
  2922. tmp_sg[i].length, dir);
  2923. curr_sg[sg_index].Addr.lower = temp64.val32.lower;
  2924. curr_sg[sg_index].Addr.upper = temp64.val32.upper;
  2925. curr_sg[sg_index].Ext = 0; /* we are not chaining */
  2926. ++sg_index;
  2927. }
  2928. if (chained)
  2929. cciss_map_sg_chain_block(h, c, h->cmd_sg_list[c->cmdindex],
  2930. (seg - (h->max_cmd_sgentries - 1)) *
  2931. sizeof(SGDescriptor_struct));
  2932. /* track how many SG entries we are using */
  2933. if (seg > h->maxSG)
  2934. h->maxSG = seg;
  2935. dev_dbg(&h->pdev->dev, "Submitting %u sectors in %d segments "
  2936. "chained[%d]\n",
  2937. blk_rq_sectors(creq), seg, chained);
  2938. c->Header.SGTotal = seg + chained;
  2939. if (seg <= h->max_cmd_sgentries)
  2940. c->Header.SGList = c->Header.SGTotal;
  2941. else
  2942. c->Header.SGList = h->max_cmd_sgentries;
  2943. set_performant_mode(h, c);
  2944. if (likely(creq->cmd_type == REQ_TYPE_FS)) {
  2945. if(h->cciss_read == CCISS_READ_10) {
  2946. c->Request.CDB[1] = 0;
  2947. c->Request.CDB[2] = (start_blk >> 24) & 0xff; /* MSB */
  2948. c->Request.CDB[3] = (start_blk >> 16) & 0xff;
  2949. c->Request.CDB[4] = (start_blk >> 8) & 0xff;
  2950. c->Request.CDB[5] = start_blk & 0xff;
  2951. c->Request.CDB[6] = 0; /* (sect >> 24) & 0xff; MSB */
  2952. c->Request.CDB[7] = (blk_rq_sectors(creq) >> 8) & 0xff;
  2953. c->Request.CDB[8] = blk_rq_sectors(creq) & 0xff;
  2954. c->Request.CDB[9] = c->Request.CDB[11] = c->Request.CDB[12] = 0;
  2955. } else {
  2956. u32 upper32 = upper_32_bits(start_blk);
  2957. c->Request.CDBLen = 16;
  2958. c->Request.CDB[1]= 0;
  2959. c->Request.CDB[2]= (upper32 >> 24) & 0xff; /* MSB */
  2960. c->Request.CDB[3]= (upper32 >> 16) & 0xff;
  2961. c->Request.CDB[4]= (upper32 >> 8) & 0xff;
  2962. c->Request.CDB[5]= upper32 & 0xff;
  2963. c->Request.CDB[6]= (start_blk >> 24) & 0xff;
  2964. c->Request.CDB[7]= (start_blk >> 16) & 0xff;
  2965. c->Request.CDB[8]= (start_blk >> 8) & 0xff;
  2966. c->Request.CDB[9]= start_blk & 0xff;
  2967. c->Request.CDB[10]= (blk_rq_sectors(creq) >> 24) & 0xff;
  2968. c->Request.CDB[11]= (blk_rq_sectors(creq) >> 16) & 0xff;
  2969. c->Request.CDB[12]= (blk_rq_sectors(creq) >> 8) & 0xff;
  2970. c->Request.CDB[13]= blk_rq_sectors(creq) & 0xff;
  2971. c->Request.CDB[14] = c->Request.CDB[15] = 0;
  2972. }
  2973. } else if (creq->cmd_type == REQ_TYPE_BLOCK_PC) {
  2974. c->Request.CDBLen = creq->cmd_len;
  2975. memcpy(c->Request.CDB, creq->cmd, BLK_MAX_CDB);
  2976. } else {
  2977. dev_warn(&h->pdev->dev, "bad request type %d\n",
  2978. creq->cmd_type);
  2979. BUG();
  2980. }
  2981. spin_lock_irq(q->queue_lock);
  2982. addQ(&h->reqQ, c);
  2983. h->Qdepth++;
  2984. if (h->Qdepth > h->maxQsinceinit)
  2985. h->maxQsinceinit = h->Qdepth;
  2986. goto queue;
  2987. full:
  2988. blk_stop_queue(q);
  2989. startio:
  2990. /* We will already have the driver lock here so not need
  2991. * to lock it.
  2992. */
  2993. start_io(h);
  2994. }
  2995. static inline unsigned long get_next_completion(ctlr_info_t *h)
  2996. {
  2997. return h->access.command_completed(h);
  2998. }
  2999. static inline int interrupt_pending(ctlr_info_t *h)
  3000. {
  3001. return h->access.intr_pending(h);
  3002. }
  3003. static inline long interrupt_not_for_us(ctlr_info_t *h)
  3004. {
  3005. return ((h->access.intr_pending(h) == 0) ||
  3006. (h->interrupts_enabled == 0));
  3007. }
  3008. static inline int bad_tag(ctlr_info_t *h, u32 tag_index,
  3009. u32 raw_tag)
  3010. {
  3011. if (unlikely(tag_index >= h->nr_cmds)) {
  3012. dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
  3013. return 1;
  3014. }
  3015. return 0;
  3016. }
  3017. static inline void finish_cmd(ctlr_info_t *h, CommandList_struct *c,
  3018. u32 raw_tag)
  3019. {
  3020. removeQ(c);
  3021. if (likely(c->cmd_type == CMD_RWREQ))
  3022. complete_command(h, c, 0);
  3023. else if (c->cmd_type == CMD_IOCTL_PEND)
  3024. complete(c->waiting);
  3025. #ifdef CONFIG_CISS_SCSI_TAPE
  3026. else if (c->cmd_type == CMD_SCSI)
  3027. complete_scsi_command(c, 0, raw_tag);
  3028. #endif
  3029. }
  3030. static inline u32 next_command(ctlr_info_t *h)
  3031. {
  3032. u32 a;
  3033. if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
  3034. return h->access.command_completed(h);
  3035. if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
  3036. a = *(h->reply_pool_head); /* Next cmd in ring buffer */
  3037. (h->reply_pool_head)++;
  3038. h->commands_outstanding--;
  3039. } else {
  3040. a = FIFO_EMPTY;
  3041. }
  3042. /* Check for wraparound */
  3043. if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
  3044. h->reply_pool_head = h->reply_pool;
  3045. h->reply_pool_wraparound ^= 1;
  3046. }
  3047. return a;
  3048. }
  3049. /* process completion of an indexed ("direct lookup") command */
  3050. static inline u32 process_indexed_cmd(ctlr_info_t *h, u32 raw_tag)
  3051. {
  3052. u32 tag_index;
  3053. CommandList_struct *c;
  3054. tag_index = cciss_tag_to_index(raw_tag);
  3055. if (bad_tag(h, tag_index, raw_tag))
  3056. return next_command(h);
  3057. c = h->cmd_pool + tag_index;
  3058. finish_cmd(h, c, raw_tag);
  3059. return next_command(h);
  3060. }
  3061. /* process completion of a non-indexed command */
  3062. static inline u32 process_nonindexed_cmd(ctlr_info_t *h, u32 raw_tag)
  3063. {
  3064. CommandList_struct *c = NULL;
  3065. __u32 busaddr_masked, tag_masked;
  3066. tag_masked = cciss_tag_discard_error_bits(h, raw_tag);
  3067. list_for_each_entry(c, &h->cmpQ, list) {
  3068. busaddr_masked = cciss_tag_discard_error_bits(h, c->busaddr);
  3069. if (busaddr_masked == tag_masked) {
  3070. finish_cmd(h, c, raw_tag);
  3071. return next_command(h);
  3072. }
  3073. }
  3074. bad_tag(h, h->nr_cmds + 1, raw_tag);
  3075. return next_command(h);
  3076. }
  3077. static irqreturn_t do_cciss_intx(int irq, void *dev_id)
  3078. {
  3079. ctlr_info_t *h = dev_id;
  3080. unsigned long flags;
  3081. u32 raw_tag;
  3082. if (interrupt_not_for_us(h))
  3083. return IRQ_NONE;
  3084. spin_lock_irqsave(&h->lock, flags);
  3085. while (interrupt_pending(h)) {
  3086. raw_tag = get_next_completion(h);
  3087. while (raw_tag != FIFO_EMPTY) {
  3088. if (cciss_tag_contains_index(raw_tag))
  3089. raw_tag = process_indexed_cmd(h, raw_tag);
  3090. else
  3091. raw_tag = process_nonindexed_cmd(h, raw_tag);
  3092. }
  3093. }
  3094. spin_unlock_irqrestore(&h->lock, flags);
  3095. return IRQ_HANDLED;
  3096. }
  3097. /* Add a second interrupt handler for MSI/MSI-X mode. In this mode we never
  3098. * check the interrupt pending register because it is not set.
  3099. */
  3100. static irqreturn_t do_cciss_msix_intr(int irq, void *dev_id)
  3101. {
  3102. ctlr_info_t *h = dev_id;
  3103. unsigned long flags;
  3104. u32 raw_tag;
  3105. spin_lock_irqsave(&h->lock, flags);
  3106. raw_tag = get_next_completion(h);
  3107. while (raw_tag != FIFO_EMPTY) {
  3108. if (cciss_tag_contains_index(raw_tag))
  3109. raw_tag = process_indexed_cmd(h, raw_tag);
  3110. else
  3111. raw_tag = process_nonindexed_cmd(h, raw_tag);
  3112. }
  3113. spin_unlock_irqrestore(&h->lock, flags);
  3114. return IRQ_HANDLED;
  3115. }
  3116. /**
  3117. * add_to_scan_list() - add controller to rescan queue
  3118. * @h: Pointer to the controller.
  3119. *
  3120. * Adds the controller to the rescan queue if not already on the queue.
  3121. *
  3122. * returns 1 if added to the queue, 0 if skipped (could be on the
  3123. * queue already, or the controller could be initializing or shutting
  3124. * down).
  3125. **/
  3126. static int add_to_scan_list(struct ctlr_info *h)
  3127. {
  3128. struct ctlr_info *test_h;
  3129. int found = 0;
  3130. int ret = 0;
  3131. if (h->busy_initializing)
  3132. return 0;
  3133. if (!mutex_trylock(&h->busy_shutting_down))
  3134. return 0;
  3135. mutex_lock(&scan_mutex);
  3136. list_for_each_entry(test_h, &scan_q, scan_list) {
  3137. if (test_h == h) {
  3138. found = 1;
  3139. break;
  3140. }
  3141. }
  3142. if (!found && !h->busy_scanning) {
  3143. INIT_COMPLETION(h->scan_wait);
  3144. list_add_tail(&h->scan_list, &scan_q);
  3145. ret = 1;
  3146. }
  3147. mutex_unlock(&scan_mutex);
  3148. mutex_unlock(&h->busy_shutting_down);
  3149. return ret;
  3150. }
  3151. /**
  3152. * remove_from_scan_list() - remove controller from rescan queue
  3153. * @h: Pointer to the controller.
  3154. *
  3155. * Removes the controller from the rescan queue if present. Blocks if
  3156. * the controller is currently conducting a rescan. The controller
  3157. * can be in one of three states:
  3158. * 1. Doesn't need a scan
  3159. * 2. On the scan list, but not scanning yet (we remove it)
  3160. * 3. Busy scanning (and not on the list). In this case we want to wait for
  3161. * the scan to complete to make sure the scanning thread for this
  3162. * controller is completely idle.
  3163. **/
  3164. static void remove_from_scan_list(struct ctlr_info *h)
  3165. {
  3166. struct ctlr_info *test_h, *tmp_h;
  3167. mutex_lock(&scan_mutex);
  3168. list_for_each_entry_safe(test_h, tmp_h, &scan_q, scan_list) {
  3169. if (test_h == h) { /* state 2. */
  3170. list_del(&h->scan_list);
  3171. complete_all(&h->scan_wait);
  3172. mutex_unlock(&scan_mutex);
  3173. return;
  3174. }
  3175. }
  3176. if (h->busy_scanning) { /* state 3. */
  3177. mutex_unlock(&scan_mutex);
  3178. wait_for_completion(&h->scan_wait);
  3179. } else { /* state 1, nothing to do. */
  3180. mutex_unlock(&scan_mutex);
  3181. }
  3182. }
  3183. /**
  3184. * scan_thread() - kernel thread used to rescan controllers
  3185. * @data: Ignored.
  3186. *
  3187. * A kernel thread used scan for drive topology changes on
  3188. * controllers. The thread processes only one controller at a time
  3189. * using a queue. Controllers are added to the queue using
  3190. * add_to_scan_list() and removed from the queue either after done
  3191. * processing or using remove_from_scan_list().
  3192. *
  3193. * returns 0.
  3194. **/
  3195. static int scan_thread(void *data)
  3196. {
  3197. struct ctlr_info *h;
  3198. while (1) {
  3199. set_current_state(TASK_INTERRUPTIBLE);
  3200. schedule();
  3201. if (kthread_should_stop())
  3202. break;
  3203. while (1) {
  3204. mutex_lock(&scan_mutex);
  3205. if (list_empty(&scan_q)) {
  3206. mutex_unlock(&scan_mutex);
  3207. break;
  3208. }
  3209. h = list_entry(scan_q.next,
  3210. struct ctlr_info,
  3211. scan_list);
  3212. list_del(&h->scan_list);
  3213. h->busy_scanning = 1;
  3214. mutex_unlock(&scan_mutex);
  3215. rebuild_lun_table(h, 0, 0);
  3216. complete_all(&h->scan_wait);
  3217. mutex_lock(&scan_mutex);
  3218. h->busy_scanning = 0;
  3219. mutex_unlock(&scan_mutex);
  3220. }
  3221. }
  3222. return 0;
  3223. }
  3224. static int check_for_unit_attention(ctlr_info_t *h, CommandList_struct *c)
  3225. {
  3226. if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
  3227. return 0;
  3228. switch (c->err_info->SenseInfo[12]) {
  3229. case STATE_CHANGED:
  3230. dev_warn(&h->pdev->dev, "a state change "
  3231. "detected, command retried\n");
  3232. return 1;
  3233. break;
  3234. case LUN_FAILED:
  3235. dev_warn(&h->pdev->dev, "LUN failure "
  3236. "detected, action required\n");
  3237. return 1;
  3238. break;
  3239. case REPORT_LUNS_CHANGED:
  3240. dev_warn(&h->pdev->dev, "report LUN data changed\n");
  3241. /*
  3242. * Here, we could call add_to_scan_list and wake up the scan thread,
  3243. * except that it's quite likely that we will get more than one
  3244. * REPORT_LUNS_CHANGED condition in quick succession, which means
  3245. * that those which occur after the first one will likely happen
  3246. * *during* the scan_thread's rescan. And the rescan code is not
  3247. * robust enough to restart in the middle, undoing what it has already
  3248. * done, and it's not clear that it's even possible to do this, since
  3249. * part of what it does is notify the block layer, which starts
  3250. * doing it's own i/o to read partition tables and so on, and the
  3251. * driver doesn't have visibility to know what might need undoing.
  3252. * In any event, if possible, it is horribly complicated to get right
  3253. * so we just don't do it for now.
  3254. *
  3255. * Note: this REPORT_LUNS_CHANGED condition only occurs on the MSA2012.
  3256. */
  3257. return 1;
  3258. break;
  3259. case POWER_OR_RESET:
  3260. dev_warn(&h->pdev->dev,
  3261. "a power on or device reset detected\n");
  3262. return 1;
  3263. break;
  3264. case UNIT_ATTENTION_CLEARED:
  3265. dev_warn(&h->pdev->dev,
  3266. "unit attention cleared by another initiator\n");
  3267. return 1;
  3268. break;
  3269. default:
  3270. dev_warn(&h->pdev->dev, "unknown unit attention detected\n");
  3271. return 1;
  3272. }
  3273. }
  3274. /*
  3275. * We cannot read the structure directly, for portability we must use
  3276. * the io functions.
  3277. * This is for debug only.
  3278. */
  3279. static void print_cfg_table(ctlr_info_t *h)
  3280. {
  3281. int i;
  3282. char temp_name[17];
  3283. CfgTable_struct *tb = h->cfgtable;
  3284. dev_dbg(&h->pdev->dev, "Controller Configuration information\n");
  3285. dev_dbg(&h->pdev->dev, "------------------------------------\n");
  3286. for (i = 0; i < 4; i++)
  3287. temp_name[i] = readb(&(tb->Signature[i]));
  3288. temp_name[4] = '\0';
  3289. dev_dbg(&h->pdev->dev, " Signature = %s\n", temp_name);
  3290. dev_dbg(&h->pdev->dev, " Spec Number = %d\n",
  3291. readl(&(tb->SpecValence)));
  3292. dev_dbg(&h->pdev->dev, " Transport methods supported = 0x%x\n",
  3293. readl(&(tb->TransportSupport)));
  3294. dev_dbg(&h->pdev->dev, " Transport methods active = 0x%x\n",
  3295. readl(&(tb->TransportActive)));
  3296. dev_dbg(&h->pdev->dev, " Requested transport Method = 0x%x\n",
  3297. readl(&(tb->HostWrite.TransportRequest)));
  3298. dev_dbg(&h->pdev->dev, " Coalesce Interrupt Delay = 0x%x\n",
  3299. readl(&(tb->HostWrite.CoalIntDelay)));
  3300. dev_dbg(&h->pdev->dev, " Coalesce Interrupt Count = 0x%x\n",
  3301. readl(&(tb->HostWrite.CoalIntCount)));
  3302. dev_dbg(&h->pdev->dev, " Max outstanding commands = 0x%d\n",
  3303. readl(&(tb->CmdsOutMax)));
  3304. dev_dbg(&h->pdev->dev, " Bus Types = 0x%x\n",
  3305. readl(&(tb->BusTypes)));
  3306. for (i = 0; i < 16; i++)
  3307. temp_name[i] = readb(&(tb->ServerName[i]));
  3308. temp_name[16] = '\0';
  3309. dev_dbg(&h->pdev->dev, " Server Name = %s\n", temp_name);
  3310. dev_dbg(&h->pdev->dev, " Heartbeat Counter = 0x%x\n\n\n",
  3311. readl(&(tb->HeartBeat)));
  3312. }
  3313. static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
  3314. {
  3315. int i, offset, mem_type, bar_type;
  3316. if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
  3317. return 0;
  3318. offset = 0;
  3319. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  3320. bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
  3321. if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
  3322. offset += 4;
  3323. else {
  3324. mem_type = pci_resource_flags(pdev, i) &
  3325. PCI_BASE_ADDRESS_MEM_TYPE_MASK;
  3326. switch (mem_type) {
  3327. case PCI_BASE_ADDRESS_MEM_TYPE_32:
  3328. case PCI_BASE_ADDRESS_MEM_TYPE_1M:
  3329. offset += 4; /* 32 bit */
  3330. break;
  3331. case PCI_BASE_ADDRESS_MEM_TYPE_64:
  3332. offset += 8;
  3333. break;
  3334. default: /* reserved in PCI 2.2 */
  3335. dev_warn(&pdev->dev,
  3336. "Base address is invalid\n");
  3337. return -1;
  3338. break;
  3339. }
  3340. }
  3341. if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
  3342. return i + 1;
  3343. }
  3344. return -1;
  3345. }
  3346. /* Fill in bucket_map[], given nsgs (the max number of
  3347. * scatter gather elements supported) and bucket[],
  3348. * which is an array of 8 integers. The bucket[] array
  3349. * contains 8 different DMA transfer sizes (in 16
  3350. * byte increments) which the controller uses to fetch
  3351. * commands. This function fills in bucket_map[], which
  3352. * maps a given number of scatter gather elements to one of
  3353. * the 8 DMA transfer sizes. The point of it is to allow the
  3354. * controller to only do as much DMA as needed to fetch the
  3355. * command, with the DMA transfer size encoded in the lower
  3356. * bits of the command address.
  3357. */
  3358. static void calc_bucket_map(int bucket[], int num_buckets,
  3359. int nsgs, int *bucket_map)
  3360. {
  3361. int i, j, b, size;
  3362. /* even a command with 0 SGs requires 4 blocks */
  3363. #define MINIMUM_TRANSFER_BLOCKS 4
  3364. #define NUM_BUCKETS 8
  3365. /* Note, bucket_map must have nsgs+1 entries. */
  3366. for (i = 0; i <= nsgs; i++) {
  3367. /* Compute size of a command with i SG entries */
  3368. size = i + MINIMUM_TRANSFER_BLOCKS;
  3369. b = num_buckets; /* Assume the biggest bucket */
  3370. /* Find the bucket that is just big enough */
  3371. for (j = 0; j < 8; j++) {
  3372. if (bucket[j] >= size) {
  3373. b = j;
  3374. break;
  3375. }
  3376. }
  3377. /* for a command with i SG entries, use bucket b. */
  3378. bucket_map[i] = b;
  3379. }
  3380. }
  3381. static void __devinit cciss_wait_for_mode_change_ack(ctlr_info_t *h)
  3382. {
  3383. int i;
  3384. /* under certain very rare conditions, this can take awhile.
  3385. * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
  3386. * as we enter this code.) */
  3387. for (i = 0; i < MAX_CONFIG_WAIT; i++) {
  3388. if (!(readl(h->vaddr + SA5_DOORBELL) & CFGTBL_ChangeReq))
  3389. break;
  3390. usleep_range(10000, 20000);
  3391. }
  3392. }
  3393. static __devinit void cciss_enter_performant_mode(ctlr_info_t *h,
  3394. u32 use_short_tags)
  3395. {
  3396. /* This is a bit complicated. There are 8 registers on
  3397. * the controller which we write to to tell it 8 different
  3398. * sizes of commands which there may be. It's a way of
  3399. * reducing the DMA done to fetch each command. Encoded into
  3400. * each command's tag are 3 bits which communicate to the controller
  3401. * which of the eight sizes that command fits within. The size of
  3402. * each command depends on how many scatter gather entries there are.
  3403. * Each SG entry requires 16 bytes. The eight registers are programmed
  3404. * with the number of 16-byte blocks a command of that size requires.
  3405. * The smallest command possible requires 5 such 16 byte blocks.
  3406. * the largest command possible requires MAXSGENTRIES + 4 16-byte
  3407. * blocks. Note, this only extends to the SG entries contained
  3408. * within the command block, and does not extend to chained blocks
  3409. * of SG elements. bft[] contains the eight values we write to
  3410. * the registers. They are not evenly distributed, but have more
  3411. * sizes for small commands, and fewer sizes for larger commands.
  3412. */
  3413. __u32 trans_offset;
  3414. int bft[8] = { 5, 6, 8, 10, 12, 20, 28, MAXSGENTRIES + 4};
  3415. /*
  3416. * 5 = 1 s/g entry or 4k
  3417. * 6 = 2 s/g entry or 8k
  3418. * 8 = 4 s/g entry or 16k
  3419. * 10 = 6 s/g entry or 24k
  3420. */
  3421. unsigned long register_value;
  3422. BUILD_BUG_ON(28 > MAXSGENTRIES + 4);
  3423. h->reply_pool_wraparound = 1; /* spec: init to 1 */
  3424. /* Controller spec: zero out this buffer. */
  3425. memset(h->reply_pool, 0, h->max_commands * sizeof(__u64));
  3426. h->reply_pool_head = h->reply_pool;
  3427. trans_offset = readl(&(h->cfgtable->TransMethodOffset));
  3428. calc_bucket_map(bft, ARRAY_SIZE(bft), h->maxsgentries,
  3429. h->blockFetchTable);
  3430. writel(bft[0], &h->transtable->BlockFetch0);
  3431. writel(bft[1], &h->transtable->BlockFetch1);
  3432. writel(bft[2], &h->transtable->BlockFetch2);
  3433. writel(bft[3], &h->transtable->BlockFetch3);
  3434. writel(bft[4], &h->transtable->BlockFetch4);
  3435. writel(bft[5], &h->transtable->BlockFetch5);
  3436. writel(bft[6], &h->transtable->BlockFetch6);
  3437. writel(bft[7], &h->transtable->BlockFetch7);
  3438. /* size of controller ring buffer */
  3439. writel(h->max_commands, &h->transtable->RepQSize);
  3440. writel(1, &h->transtable->RepQCount);
  3441. writel(0, &h->transtable->RepQCtrAddrLow32);
  3442. writel(0, &h->transtable->RepQCtrAddrHigh32);
  3443. writel(h->reply_pool_dhandle, &h->transtable->RepQAddr0Low32);
  3444. writel(0, &h->transtable->RepQAddr0High32);
  3445. writel(CFGTBL_Trans_Performant | use_short_tags,
  3446. &(h->cfgtable->HostWrite.TransportRequest));
  3447. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  3448. cciss_wait_for_mode_change_ack(h);
  3449. register_value = readl(&(h->cfgtable->TransportActive));
  3450. if (!(register_value & CFGTBL_Trans_Performant))
  3451. dev_warn(&h->pdev->dev, "cciss: unable to get board into"
  3452. " performant mode\n");
  3453. }
  3454. static void __devinit cciss_put_controller_into_performant_mode(ctlr_info_t *h)
  3455. {
  3456. __u32 trans_support;
  3457. dev_dbg(&h->pdev->dev, "Trying to put board into Performant mode\n");
  3458. /* Attempt to put controller into performant mode if supported */
  3459. /* Does board support performant mode? */
  3460. trans_support = readl(&(h->cfgtable->TransportSupport));
  3461. if (!(trans_support & PERFORMANT_MODE))
  3462. return;
  3463. dev_dbg(&h->pdev->dev, "Placing controller into performant mode\n");
  3464. /* Performant mode demands commands on a 32 byte boundary
  3465. * pci_alloc_consistent aligns on page boundarys already.
  3466. * Just need to check if divisible by 32
  3467. */
  3468. if ((sizeof(CommandList_struct) % 32) != 0) {
  3469. dev_warn(&h->pdev->dev, "%s %d %s\n",
  3470. "cciss info: command size[",
  3471. (int)sizeof(CommandList_struct),
  3472. "] not divisible by 32, no performant mode..\n");
  3473. return;
  3474. }
  3475. /* Performant mode ring buffer and supporting data structures */
  3476. h->reply_pool = (__u64 *)pci_alloc_consistent(
  3477. h->pdev, h->max_commands * sizeof(__u64),
  3478. &(h->reply_pool_dhandle));
  3479. /* Need a block fetch table for performant mode */
  3480. h->blockFetchTable = kmalloc(((h->maxsgentries+1) *
  3481. sizeof(__u32)), GFP_KERNEL);
  3482. if ((h->reply_pool == NULL) || (h->blockFetchTable == NULL))
  3483. goto clean_up;
  3484. cciss_enter_performant_mode(h,
  3485. trans_support & CFGTBL_Trans_use_short_tags);
  3486. /* Change the access methods to the performant access methods */
  3487. h->access = SA5_performant_access;
  3488. h->transMethod = CFGTBL_Trans_Performant;
  3489. return;
  3490. clean_up:
  3491. kfree(h->blockFetchTable);
  3492. if (h->reply_pool)
  3493. pci_free_consistent(h->pdev,
  3494. h->max_commands * sizeof(__u64),
  3495. h->reply_pool,
  3496. h->reply_pool_dhandle);
  3497. return;
  3498. } /* cciss_put_controller_into_performant_mode */
  3499. /* If MSI/MSI-X is supported by the kernel we will try to enable it on
  3500. * controllers that are capable. If not, we use IO-APIC mode.
  3501. */
  3502. static void __devinit cciss_interrupt_mode(ctlr_info_t *h)
  3503. {
  3504. #ifdef CONFIG_PCI_MSI
  3505. int err;
  3506. struct msix_entry cciss_msix_entries[4] = { {0, 0}, {0, 1},
  3507. {0, 2}, {0, 3}
  3508. };
  3509. /* Some boards advertise MSI but don't really support it */
  3510. if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
  3511. (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
  3512. goto default_int_mode;
  3513. if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
  3514. err = pci_enable_msix(h->pdev, cciss_msix_entries, 4);
  3515. if (!err) {
  3516. h->intr[0] = cciss_msix_entries[0].vector;
  3517. h->intr[1] = cciss_msix_entries[1].vector;
  3518. h->intr[2] = cciss_msix_entries[2].vector;
  3519. h->intr[3] = cciss_msix_entries[3].vector;
  3520. h->msix_vector = 1;
  3521. return;
  3522. }
  3523. if (err > 0) {
  3524. dev_warn(&h->pdev->dev,
  3525. "only %d MSI-X vectors available\n", err);
  3526. goto default_int_mode;
  3527. } else {
  3528. dev_warn(&h->pdev->dev,
  3529. "MSI-X init failed %d\n", err);
  3530. goto default_int_mode;
  3531. }
  3532. }
  3533. if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
  3534. if (!pci_enable_msi(h->pdev))
  3535. h->msi_vector = 1;
  3536. else
  3537. dev_warn(&h->pdev->dev, "MSI init failed\n");
  3538. }
  3539. default_int_mode:
  3540. #endif /* CONFIG_PCI_MSI */
  3541. /* if we get here we're going to use the default interrupt mode */
  3542. h->intr[PERF_MODE_INT] = h->pdev->irq;
  3543. return;
  3544. }
  3545. static int __devinit cciss_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
  3546. {
  3547. int i;
  3548. u32 subsystem_vendor_id, subsystem_device_id;
  3549. subsystem_vendor_id = pdev->subsystem_vendor;
  3550. subsystem_device_id = pdev->subsystem_device;
  3551. *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
  3552. subsystem_vendor_id;
  3553. for (i = 0; i < ARRAY_SIZE(products); i++)
  3554. if (*board_id == products[i].board_id)
  3555. return i;
  3556. dev_warn(&pdev->dev, "unrecognized board ID: 0x%08x, ignoring.\n",
  3557. *board_id);
  3558. return -ENODEV;
  3559. }
  3560. static inline bool cciss_board_disabled(ctlr_info_t *h)
  3561. {
  3562. u16 command;
  3563. (void) pci_read_config_word(h->pdev, PCI_COMMAND, &command);
  3564. return ((command & PCI_COMMAND_MEMORY) == 0);
  3565. }
  3566. static int __devinit cciss_pci_find_memory_BAR(struct pci_dev *pdev,
  3567. unsigned long *memory_bar)
  3568. {
  3569. int i;
  3570. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
  3571. if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
  3572. /* addressing mode bits already removed */
  3573. *memory_bar = pci_resource_start(pdev, i);
  3574. dev_dbg(&pdev->dev, "memory BAR = %lx\n",
  3575. *memory_bar);
  3576. return 0;
  3577. }
  3578. dev_warn(&pdev->dev, "no memory BAR found\n");
  3579. return -ENODEV;
  3580. }
  3581. static int __devinit cciss_wait_for_board_state(struct pci_dev *pdev,
  3582. void __iomem *vaddr, int wait_for_ready)
  3583. #define BOARD_READY 1
  3584. #define BOARD_NOT_READY 0
  3585. {
  3586. int i, iterations;
  3587. u32 scratchpad;
  3588. if (wait_for_ready)
  3589. iterations = CCISS_BOARD_READY_ITERATIONS;
  3590. else
  3591. iterations = CCISS_BOARD_NOT_READY_ITERATIONS;
  3592. for (i = 0; i < iterations; i++) {
  3593. scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
  3594. if (wait_for_ready) {
  3595. if (scratchpad == CCISS_FIRMWARE_READY)
  3596. return 0;
  3597. } else {
  3598. if (scratchpad != CCISS_FIRMWARE_READY)
  3599. return 0;
  3600. }
  3601. msleep(CCISS_BOARD_READY_POLL_INTERVAL_MSECS);
  3602. }
  3603. dev_warn(&pdev->dev, "board not ready, timed out.\n");
  3604. return -ENODEV;
  3605. }
  3606. static int __devinit cciss_find_cfg_addrs(struct pci_dev *pdev,
  3607. void __iomem *vaddr, u32 *cfg_base_addr, u64 *cfg_base_addr_index,
  3608. u64 *cfg_offset)
  3609. {
  3610. *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
  3611. *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
  3612. *cfg_base_addr &= (u32) 0x0000ffff;
  3613. *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
  3614. if (*cfg_base_addr_index == -1) {
  3615. dev_warn(&pdev->dev, "cannot find cfg_base_addr_index, "
  3616. "*cfg_base_addr = 0x%08x\n", *cfg_base_addr);
  3617. return -ENODEV;
  3618. }
  3619. return 0;
  3620. }
  3621. static int __devinit cciss_find_cfgtables(ctlr_info_t *h)
  3622. {
  3623. u64 cfg_offset;
  3624. u32 cfg_base_addr;
  3625. u64 cfg_base_addr_index;
  3626. u32 trans_offset;
  3627. int rc;
  3628. rc = cciss_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
  3629. &cfg_base_addr_index, &cfg_offset);
  3630. if (rc)
  3631. return rc;
  3632. h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
  3633. cfg_base_addr_index) + cfg_offset, sizeof(h->cfgtable));
  3634. if (!h->cfgtable)
  3635. return -ENOMEM;
  3636. rc = write_driver_ver_to_cfgtable(h->cfgtable);
  3637. if (rc)
  3638. return rc;
  3639. /* Find performant mode table. */
  3640. trans_offset = readl(&h->cfgtable->TransMethodOffset);
  3641. h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
  3642. cfg_base_addr_index)+cfg_offset+trans_offset,
  3643. sizeof(*h->transtable));
  3644. if (!h->transtable)
  3645. return -ENOMEM;
  3646. return 0;
  3647. }
  3648. static void __devinit cciss_get_max_perf_mode_cmds(struct ctlr_info *h)
  3649. {
  3650. h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
  3651. /* Limit commands in memory limited kdump scenario. */
  3652. if (reset_devices && h->max_commands > 32)
  3653. h->max_commands = 32;
  3654. if (h->max_commands < 16) {
  3655. dev_warn(&h->pdev->dev, "Controller reports "
  3656. "max supported commands of %d, an obvious lie. "
  3657. "Using 16. Ensure that firmware is up to date.\n",
  3658. h->max_commands);
  3659. h->max_commands = 16;
  3660. }
  3661. }
  3662. /* Interrogate the hardware for some limits:
  3663. * max commands, max SG elements without chaining, and with chaining,
  3664. * SG chain block size, etc.
  3665. */
  3666. static void __devinit cciss_find_board_params(ctlr_info_t *h)
  3667. {
  3668. cciss_get_max_perf_mode_cmds(h);
  3669. h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
  3670. h->maxsgentries = readl(&(h->cfgtable->MaxSGElements));
  3671. /*
  3672. * Limit in-command s/g elements to 32 save dma'able memory.
  3673. * Howvever spec says if 0, use 31
  3674. */
  3675. h->max_cmd_sgentries = 31;
  3676. if (h->maxsgentries > 512) {
  3677. h->max_cmd_sgentries = 32;
  3678. h->chainsize = h->maxsgentries - h->max_cmd_sgentries + 1;
  3679. h->maxsgentries--; /* save one for chain pointer */
  3680. } else {
  3681. h->maxsgentries = 31; /* default to traditional values */
  3682. h->chainsize = 0;
  3683. }
  3684. }
  3685. static inline bool CISS_signature_present(ctlr_info_t *h)
  3686. {
  3687. if ((readb(&h->cfgtable->Signature[0]) != 'C') ||
  3688. (readb(&h->cfgtable->Signature[1]) != 'I') ||
  3689. (readb(&h->cfgtable->Signature[2]) != 'S') ||
  3690. (readb(&h->cfgtable->Signature[3]) != 'S')) {
  3691. dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
  3692. return false;
  3693. }
  3694. return true;
  3695. }
  3696. /* Need to enable prefetch in the SCSI core for 6400 in x86 */
  3697. static inline void cciss_enable_scsi_prefetch(ctlr_info_t *h)
  3698. {
  3699. #ifdef CONFIG_X86
  3700. u32 prefetch;
  3701. prefetch = readl(&(h->cfgtable->SCSI_Prefetch));
  3702. prefetch |= 0x100;
  3703. writel(prefetch, &(h->cfgtable->SCSI_Prefetch));
  3704. #endif
  3705. }
  3706. /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
  3707. * in a prefetch beyond physical memory.
  3708. */
  3709. static inline void cciss_p600_dma_prefetch_quirk(ctlr_info_t *h)
  3710. {
  3711. u32 dma_prefetch;
  3712. __u32 dma_refetch;
  3713. if (h->board_id != 0x3225103C)
  3714. return;
  3715. dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
  3716. dma_prefetch |= 0x8000;
  3717. writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
  3718. pci_read_config_dword(h->pdev, PCI_COMMAND_PARITY, &dma_refetch);
  3719. dma_refetch |= 0x1;
  3720. pci_write_config_dword(h->pdev, PCI_COMMAND_PARITY, dma_refetch);
  3721. }
  3722. static int __devinit cciss_pci_init(ctlr_info_t *h)
  3723. {
  3724. int prod_index, err;
  3725. prod_index = cciss_lookup_board_id(h->pdev, &h->board_id);
  3726. if (prod_index < 0)
  3727. return -ENODEV;
  3728. h->product_name = products[prod_index].product_name;
  3729. h->access = *(products[prod_index].access);
  3730. if (cciss_board_disabled(h)) {
  3731. dev_warn(&h->pdev->dev, "controller appears to be disabled\n");
  3732. return -ENODEV;
  3733. }
  3734. err = pci_enable_device(h->pdev);
  3735. if (err) {
  3736. dev_warn(&h->pdev->dev, "Unable to Enable PCI device\n");
  3737. return err;
  3738. }
  3739. err = pci_request_regions(h->pdev, "cciss");
  3740. if (err) {
  3741. dev_warn(&h->pdev->dev,
  3742. "Cannot obtain PCI resources, aborting\n");
  3743. return err;
  3744. }
  3745. dev_dbg(&h->pdev->dev, "irq = %x\n", h->pdev->irq);
  3746. dev_dbg(&h->pdev->dev, "board_id = %x\n", h->board_id);
  3747. /* If the kernel supports MSI/MSI-X we will try to enable that functionality,
  3748. * else we use the IO-APIC interrupt assigned to us by system ROM.
  3749. */
  3750. cciss_interrupt_mode(h);
  3751. err = cciss_pci_find_memory_BAR(h->pdev, &h->paddr);
  3752. if (err)
  3753. goto err_out_free_res;
  3754. h->vaddr = remap_pci_mem(h->paddr, 0x250);
  3755. if (!h->vaddr) {
  3756. err = -ENOMEM;
  3757. goto err_out_free_res;
  3758. }
  3759. err = cciss_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
  3760. if (err)
  3761. goto err_out_free_res;
  3762. err = cciss_find_cfgtables(h);
  3763. if (err)
  3764. goto err_out_free_res;
  3765. print_cfg_table(h);
  3766. cciss_find_board_params(h);
  3767. if (!CISS_signature_present(h)) {
  3768. err = -ENODEV;
  3769. goto err_out_free_res;
  3770. }
  3771. cciss_enable_scsi_prefetch(h);
  3772. cciss_p600_dma_prefetch_quirk(h);
  3773. cciss_put_controller_into_performant_mode(h);
  3774. return 0;
  3775. err_out_free_res:
  3776. /*
  3777. * Deliberately omit pci_disable_device(): it does something nasty to
  3778. * Smart Array controllers that pci_enable_device does not undo
  3779. */
  3780. if (h->transtable)
  3781. iounmap(h->transtable);
  3782. if (h->cfgtable)
  3783. iounmap(h->cfgtable);
  3784. if (h->vaddr)
  3785. iounmap(h->vaddr);
  3786. pci_release_regions(h->pdev);
  3787. return err;
  3788. }
  3789. /* Function to find the first free pointer into our hba[] array
  3790. * Returns -1 if no free entries are left.
  3791. */
  3792. static int alloc_cciss_hba(struct pci_dev *pdev)
  3793. {
  3794. int i;
  3795. for (i = 0; i < MAX_CTLR; i++) {
  3796. if (!hba[i]) {
  3797. ctlr_info_t *h;
  3798. h = kzalloc(sizeof(ctlr_info_t), GFP_KERNEL);
  3799. if (!h)
  3800. goto Enomem;
  3801. hba[i] = h;
  3802. return i;
  3803. }
  3804. }
  3805. dev_warn(&pdev->dev, "This driver supports a maximum"
  3806. " of %d controllers.\n", MAX_CTLR);
  3807. return -1;
  3808. Enomem:
  3809. dev_warn(&pdev->dev, "out of memory.\n");
  3810. return -1;
  3811. }
  3812. static void free_hba(ctlr_info_t *h)
  3813. {
  3814. int i;
  3815. hba[h->ctlr] = NULL;
  3816. for (i = 0; i < h->highest_lun + 1; i++)
  3817. if (h->gendisk[i] != NULL)
  3818. put_disk(h->gendisk[i]);
  3819. kfree(h);
  3820. }
  3821. /* Send a message CDB to the firmware. */
  3822. static __devinit int cciss_message(struct pci_dev *pdev, unsigned char opcode, unsigned char type)
  3823. {
  3824. typedef struct {
  3825. CommandListHeader_struct CommandHeader;
  3826. RequestBlock_struct Request;
  3827. ErrDescriptor_struct ErrorDescriptor;
  3828. } Command;
  3829. static const size_t cmd_sz = sizeof(Command) + sizeof(ErrorInfo_struct);
  3830. Command *cmd;
  3831. dma_addr_t paddr64;
  3832. uint32_t paddr32, tag;
  3833. void __iomem *vaddr;
  3834. int i, err;
  3835. vaddr = ioremap_nocache(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  3836. if (vaddr == NULL)
  3837. return -ENOMEM;
  3838. /* The Inbound Post Queue only accepts 32-bit physical addresses for the
  3839. CCISS commands, so they must be allocated from the lower 4GiB of
  3840. memory. */
  3841. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3842. if (err) {
  3843. iounmap(vaddr);
  3844. return -ENOMEM;
  3845. }
  3846. cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
  3847. if (cmd == NULL) {
  3848. iounmap(vaddr);
  3849. return -ENOMEM;
  3850. }
  3851. /* This must fit, because of the 32-bit consistent DMA mask. Also,
  3852. although there's no guarantee, we assume that the address is at
  3853. least 4-byte aligned (most likely, it's page-aligned). */
  3854. paddr32 = paddr64;
  3855. cmd->CommandHeader.ReplyQueue = 0;
  3856. cmd->CommandHeader.SGList = 0;
  3857. cmd->CommandHeader.SGTotal = 0;
  3858. cmd->CommandHeader.Tag.lower = paddr32;
  3859. cmd->CommandHeader.Tag.upper = 0;
  3860. memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
  3861. cmd->Request.CDBLen = 16;
  3862. cmd->Request.Type.Type = TYPE_MSG;
  3863. cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
  3864. cmd->Request.Type.Direction = XFER_NONE;
  3865. cmd->Request.Timeout = 0; /* Don't time out */
  3866. cmd->Request.CDB[0] = opcode;
  3867. cmd->Request.CDB[1] = type;
  3868. memset(&cmd->Request.CDB[2], 0, 14); /* the rest of the CDB is reserved */
  3869. cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(Command);
  3870. cmd->ErrorDescriptor.Addr.upper = 0;
  3871. cmd->ErrorDescriptor.Len = sizeof(ErrorInfo_struct);
  3872. writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
  3873. for (i = 0; i < 10; i++) {
  3874. tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
  3875. if ((tag & ~3) == paddr32)
  3876. break;
  3877. schedule_timeout_uninterruptible(HZ);
  3878. }
  3879. iounmap(vaddr);
  3880. /* we leak the DMA buffer here ... no choice since the controller could
  3881. still complete the command. */
  3882. if (i == 10) {
  3883. dev_err(&pdev->dev,
  3884. "controller message %02x:%02x timed out\n",
  3885. opcode, type);
  3886. return -ETIMEDOUT;
  3887. }
  3888. pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
  3889. if (tag & 2) {
  3890. dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
  3891. opcode, type);
  3892. return -EIO;
  3893. }
  3894. dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
  3895. opcode, type);
  3896. return 0;
  3897. }
  3898. #define cciss_soft_reset_controller(p) cciss_message(p, 1, 0)
  3899. #define cciss_noop(p) cciss_message(p, 3, 0)
  3900. static int cciss_controller_hard_reset(struct pci_dev *pdev,
  3901. void * __iomem vaddr, bool use_doorbell)
  3902. {
  3903. u16 pmcsr;
  3904. int pos;
  3905. if (use_doorbell) {
  3906. /* For everything after the P600, the PCI power state method
  3907. * of resetting the controller doesn't work, so we have this
  3908. * other way using the doorbell register.
  3909. */
  3910. dev_info(&pdev->dev, "using doorbell to reset controller\n");
  3911. writel(DOORBELL_CTLR_RESET, vaddr + SA5_DOORBELL);
  3912. msleep(1000);
  3913. } else { /* Try to do it the PCI power state way */
  3914. /* Quoting from the Open CISS Specification: "The Power
  3915. * Management Control/Status Register (CSR) controls the power
  3916. * state of the device. The normal operating state is D0,
  3917. * CSR=00h. The software off state is D3, CSR=03h. To reset
  3918. * the controller, place the interface device in D3 then to D0,
  3919. * this causes a secondary PCI reset which will reset the
  3920. * controller." */
  3921. pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
  3922. if (pos == 0) {
  3923. dev_err(&pdev->dev,
  3924. "cciss_controller_hard_reset: "
  3925. "PCI PM not supported\n");
  3926. return -ENODEV;
  3927. }
  3928. dev_info(&pdev->dev, "using PCI PM to reset controller\n");
  3929. /* enter the D3hot power management state */
  3930. pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
  3931. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  3932. pmcsr |= PCI_D3hot;
  3933. pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
  3934. msleep(500);
  3935. /* enter the D0 power management state */
  3936. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  3937. pmcsr |= PCI_D0;
  3938. pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
  3939. msleep(500);
  3940. }
  3941. return 0;
  3942. }
  3943. static __devinit void init_driver_version(char *driver_version, int len)
  3944. {
  3945. memset(driver_version, 0, len);
  3946. strncpy(driver_version, "cciss " DRIVER_NAME, len - 1);
  3947. }
  3948. static __devinit int write_driver_ver_to_cfgtable(
  3949. CfgTable_struct __iomem *cfgtable)
  3950. {
  3951. char *driver_version;
  3952. int i, size = sizeof(cfgtable->driver_version);
  3953. driver_version = kmalloc(size, GFP_KERNEL);
  3954. if (!driver_version)
  3955. return -ENOMEM;
  3956. init_driver_version(driver_version, size);
  3957. for (i = 0; i < size; i++)
  3958. writeb(driver_version[i], &cfgtable->driver_version[i]);
  3959. kfree(driver_version);
  3960. return 0;
  3961. }
  3962. static __devinit void read_driver_ver_from_cfgtable(
  3963. CfgTable_struct __iomem *cfgtable, unsigned char *driver_ver)
  3964. {
  3965. int i;
  3966. for (i = 0; i < sizeof(cfgtable->driver_version); i++)
  3967. driver_ver[i] = readb(&cfgtable->driver_version[i]);
  3968. }
  3969. static __devinit int controller_reset_failed(
  3970. CfgTable_struct __iomem *cfgtable)
  3971. {
  3972. char *driver_ver, *old_driver_ver;
  3973. int rc, size = sizeof(cfgtable->driver_version);
  3974. old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
  3975. if (!old_driver_ver)
  3976. return -ENOMEM;
  3977. driver_ver = old_driver_ver + size;
  3978. /* After a reset, the 32 bytes of "driver version" in the cfgtable
  3979. * should have been changed, otherwise we know the reset failed.
  3980. */
  3981. init_driver_version(old_driver_ver, size);
  3982. read_driver_ver_from_cfgtable(cfgtable, driver_ver);
  3983. rc = !memcmp(driver_ver, old_driver_ver, size);
  3984. kfree(old_driver_ver);
  3985. return rc;
  3986. }
  3987. /* This does a hard reset of the controller using PCI power management
  3988. * states or using the doorbell register. */
  3989. static __devinit int cciss_kdump_hard_reset_controller(struct pci_dev *pdev)
  3990. {
  3991. u64 cfg_offset;
  3992. u32 cfg_base_addr;
  3993. u64 cfg_base_addr_index;
  3994. void __iomem *vaddr;
  3995. unsigned long paddr;
  3996. u32 misc_fw_support;
  3997. int rc;
  3998. CfgTable_struct __iomem *cfgtable;
  3999. bool use_doorbell;
  4000. u32 board_id;
  4001. u16 command_register;
  4002. /* For controllers as old a the p600, this is very nearly
  4003. * the same thing as
  4004. *
  4005. * pci_save_state(pci_dev);
  4006. * pci_set_power_state(pci_dev, PCI_D3hot);
  4007. * pci_set_power_state(pci_dev, PCI_D0);
  4008. * pci_restore_state(pci_dev);
  4009. *
  4010. * For controllers newer than the P600, the pci power state
  4011. * method of resetting doesn't work so we have another way
  4012. * using the doorbell register.
  4013. */
  4014. /* Exclude 640x boards. These are two pci devices in one slot
  4015. * which share a battery backed cache module. One controls the
  4016. * cache, the other accesses the cache through the one that controls
  4017. * it. If we reset the one controlling the cache, the other will
  4018. * likely not be happy. Just forbid resetting this conjoined mess.
  4019. */
  4020. cciss_lookup_board_id(pdev, &board_id);
  4021. if (board_id == 0x409C0E11 || board_id == 0x409D0E11) {
  4022. dev_warn(&pdev->dev, "Cannot reset Smart Array 640x "
  4023. "due to shared cache module.");
  4024. return -ENODEV;
  4025. }
  4026. /* Save the PCI command register */
  4027. pci_read_config_word(pdev, 4, &command_register);
  4028. /* Turn the board off. This is so that later pci_restore_state()
  4029. * won't turn the board on before the rest of config space is ready.
  4030. */
  4031. pci_disable_device(pdev);
  4032. pci_save_state(pdev);
  4033. /* find the first memory BAR, so we can find the cfg table */
  4034. rc = cciss_pci_find_memory_BAR(pdev, &paddr);
  4035. if (rc)
  4036. return rc;
  4037. vaddr = remap_pci_mem(paddr, 0x250);
  4038. if (!vaddr)
  4039. return -ENOMEM;
  4040. /* find cfgtable in order to check if reset via doorbell is supported */
  4041. rc = cciss_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
  4042. &cfg_base_addr_index, &cfg_offset);
  4043. if (rc)
  4044. goto unmap_vaddr;
  4045. cfgtable = remap_pci_mem(pci_resource_start(pdev,
  4046. cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
  4047. if (!cfgtable) {
  4048. rc = -ENOMEM;
  4049. goto unmap_vaddr;
  4050. }
  4051. rc = write_driver_ver_to_cfgtable(cfgtable);
  4052. if (rc)
  4053. goto unmap_vaddr;
  4054. /* If reset via doorbell register is supported, use that. */
  4055. misc_fw_support = readl(&cfgtable->misc_fw_support);
  4056. use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
  4057. /* The doorbell reset seems to cause lockups on some Smart
  4058. * Arrays (e.g. P410, P410i, maybe others). Until this is
  4059. * fixed or at least isolated, avoid the doorbell reset.
  4060. */
  4061. use_doorbell = 0;
  4062. rc = cciss_controller_hard_reset(pdev, vaddr, use_doorbell);
  4063. if (rc)
  4064. goto unmap_cfgtable;
  4065. pci_restore_state(pdev);
  4066. rc = pci_enable_device(pdev);
  4067. if (rc) {
  4068. dev_warn(&pdev->dev, "failed to enable device.\n");
  4069. goto unmap_cfgtable;
  4070. }
  4071. pci_write_config_word(pdev, 4, command_register);
  4072. /* Some devices (notably the HP Smart Array 5i Controller)
  4073. need a little pause here */
  4074. msleep(CCISS_POST_RESET_PAUSE_MSECS);
  4075. /* Wait for board to become not ready, then ready. */
  4076. dev_info(&pdev->dev, "Waiting for board to become ready.\n");
  4077. rc = cciss_wait_for_board_state(pdev, vaddr, BOARD_NOT_READY);
  4078. if (rc) /* Don't bail, might be E500, etc. which can't be reset */
  4079. dev_warn(&pdev->dev,
  4080. "failed waiting for board to become not ready\n");
  4081. rc = cciss_wait_for_board_state(pdev, vaddr, BOARD_READY);
  4082. if (rc) {
  4083. dev_warn(&pdev->dev,
  4084. "failed waiting for board to become ready\n");
  4085. goto unmap_cfgtable;
  4086. }
  4087. rc = controller_reset_failed(vaddr);
  4088. if (rc < 0)
  4089. goto unmap_cfgtable;
  4090. if (rc) {
  4091. dev_warn(&pdev->dev, "Unable to successfully reset controller,"
  4092. " Ignoring controller.\n");
  4093. rc = -ENODEV;
  4094. goto unmap_cfgtable;
  4095. } else {
  4096. dev_info(&pdev->dev, "board ready.\n");
  4097. }
  4098. dev_info(&pdev->dev, "board ready.\n");
  4099. unmap_cfgtable:
  4100. iounmap(cfgtable);
  4101. unmap_vaddr:
  4102. iounmap(vaddr);
  4103. return rc;
  4104. }
  4105. static __devinit int cciss_init_reset_devices(struct pci_dev *pdev)
  4106. {
  4107. int rc, i;
  4108. if (!reset_devices)
  4109. return 0;
  4110. /* Reset the controller with a PCI power-cycle or via doorbell */
  4111. rc = cciss_kdump_hard_reset_controller(pdev);
  4112. /* -ENOTSUPP here means we cannot reset the controller
  4113. * but it's already (and still) up and running in
  4114. * "performant mode". Or, it might be 640x, which can't reset
  4115. * due to concerns about shared bbwc between 6402/6404 pair.
  4116. */
  4117. if (rc == -ENOTSUPP)
  4118. return 0; /* just try to do the kdump anyhow. */
  4119. if (rc)
  4120. return -ENODEV;
  4121. /* Now try to get the controller to respond to a no-op */
  4122. for (i = 0; i < CCISS_POST_RESET_NOOP_RETRIES; i++) {
  4123. if (cciss_noop(pdev) == 0)
  4124. break;
  4125. else
  4126. dev_warn(&pdev->dev, "no-op failed%s\n",
  4127. (i < CCISS_POST_RESET_NOOP_RETRIES - 1 ?
  4128. "; re-trying" : ""));
  4129. msleep(CCISS_POST_RESET_NOOP_INTERVAL_MSECS);
  4130. }
  4131. return 0;
  4132. }
  4133. static __devinit int cciss_allocate_cmd_pool(ctlr_info_t *h)
  4134. {
  4135. h->cmd_pool_bits = kmalloc(
  4136. DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
  4137. sizeof(unsigned long), GFP_KERNEL);
  4138. h->cmd_pool = pci_alloc_consistent(h->pdev,
  4139. h->nr_cmds * sizeof(CommandList_struct),
  4140. &(h->cmd_pool_dhandle));
  4141. h->errinfo_pool = pci_alloc_consistent(h->pdev,
  4142. h->nr_cmds * sizeof(ErrorInfo_struct),
  4143. &(h->errinfo_pool_dhandle));
  4144. if ((h->cmd_pool_bits == NULL)
  4145. || (h->cmd_pool == NULL)
  4146. || (h->errinfo_pool == NULL)) {
  4147. dev_err(&h->pdev->dev, "out of memory");
  4148. return -ENOMEM;
  4149. }
  4150. return 0;
  4151. }
  4152. static __devinit int cciss_allocate_scatterlists(ctlr_info_t *h)
  4153. {
  4154. int i;
  4155. /* zero it, so that on free we need not know how many were alloc'ed */
  4156. h->scatter_list = kzalloc(h->max_commands *
  4157. sizeof(struct scatterlist *), GFP_KERNEL);
  4158. if (!h->scatter_list)
  4159. return -ENOMEM;
  4160. for (i = 0; i < h->nr_cmds; i++) {
  4161. h->scatter_list[i] = kmalloc(sizeof(struct scatterlist) *
  4162. h->maxsgentries, GFP_KERNEL);
  4163. if (h->scatter_list[i] == NULL) {
  4164. dev_err(&h->pdev->dev, "could not allocate "
  4165. "s/g lists\n");
  4166. return -ENOMEM;
  4167. }
  4168. }
  4169. return 0;
  4170. }
  4171. static void cciss_free_scatterlists(ctlr_info_t *h)
  4172. {
  4173. int i;
  4174. if (h->scatter_list) {
  4175. for (i = 0; i < h->nr_cmds; i++)
  4176. kfree(h->scatter_list[i]);
  4177. kfree(h->scatter_list);
  4178. }
  4179. }
  4180. static void cciss_free_cmd_pool(ctlr_info_t *h)
  4181. {
  4182. kfree(h->cmd_pool_bits);
  4183. if (h->cmd_pool)
  4184. pci_free_consistent(h->pdev,
  4185. h->nr_cmds * sizeof(CommandList_struct),
  4186. h->cmd_pool, h->cmd_pool_dhandle);
  4187. if (h->errinfo_pool)
  4188. pci_free_consistent(h->pdev,
  4189. h->nr_cmds * sizeof(ErrorInfo_struct),
  4190. h->errinfo_pool, h->errinfo_pool_dhandle);
  4191. }
  4192. static int cciss_request_irq(ctlr_info_t *h,
  4193. irqreturn_t (*msixhandler)(int, void *),
  4194. irqreturn_t (*intxhandler)(int, void *))
  4195. {
  4196. if (h->msix_vector || h->msi_vector) {
  4197. if (!request_irq(h->intr[PERF_MODE_INT], msixhandler,
  4198. IRQF_DISABLED, h->devname, h))
  4199. return 0;
  4200. dev_err(&h->pdev->dev, "Unable to get msi irq %d"
  4201. " for %s\n", h->intr[PERF_MODE_INT],
  4202. h->devname);
  4203. return -1;
  4204. }
  4205. if (!request_irq(h->intr[PERF_MODE_INT], intxhandler,
  4206. IRQF_DISABLED, h->devname, h))
  4207. return 0;
  4208. dev_err(&h->pdev->dev, "Unable to get irq %d for %s\n",
  4209. h->intr[PERF_MODE_INT], h->devname);
  4210. return -1;
  4211. }
  4212. /*
  4213. * This is it. Find all the controllers and register them. I really hate
  4214. * stealing all these major device numbers.
  4215. * returns the number of block devices registered.
  4216. */
  4217. static int __devinit cciss_init_one(struct pci_dev *pdev,
  4218. const struct pci_device_id *ent)
  4219. {
  4220. int i;
  4221. int j = 0;
  4222. int rc;
  4223. int dac, return_code;
  4224. InquiryData_struct *inq_buff;
  4225. ctlr_info_t *h;
  4226. rc = cciss_init_reset_devices(pdev);
  4227. if (rc)
  4228. return rc;
  4229. i = alloc_cciss_hba(pdev);
  4230. if (i < 0)
  4231. return -1;
  4232. h = hba[i];
  4233. h->pdev = pdev;
  4234. h->busy_initializing = 1;
  4235. INIT_LIST_HEAD(&h->cmpQ);
  4236. INIT_LIST_HEAD(&h->reqQ);
  4237. mutex_init(&h->busy_shutting_down);
  4238. if (cciss_pci_init(h) != 0)
  4239. goto clean_no_release_regions;
  4240. sprintf(h->devname, "cciss%d", i);
  4241. h->ctlr = i;
  4242. init_completion(&h->scan_wait);
  4243. if (cciss_create_hba_sysfs_entry(h))
  4244. goto clean0;
  4245. /* configure PCI DMA stuff */
  4246. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
  4247. dac = 1;
  4248. else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
  4249. dac = 0;
  4250. else {
  4251. dev_err(&h->pdev->dev, "no suitable DMA available\n");
  4252. goto clean1;
  4253. }
  4254. /*
  4255. * register with the major number, or get a dynamic major number
  4256. * by passing 0 as argument. This is done for greater than
  4257. * 8 controller support.
  4258. */
  4259. if (i < MAX_CTLR_ORIG)
  4260. h->major = COMPAQ_CISS_MAJOR + i;
  4261. rc = register_blkdev(h->major, h->devname);
  4262. if (rc == -EBUSY || rc == -EINVAL) {
  4263. dev_err(&h->pdev->dev,
  4264. "Unable to get major number %d for %s "
  4265. "on hba %d\n", h->major, h->devname, i);
  4266. goto clean1;
  4267. } else {
  4268. if (i >= MAX_CTLR_ORIG)
  4269. h->major = rc;
  4270. }
  4271. /* make sure the board interrupts are off */
  4272. h->access.set_intr_mask(h, CCISS_INTR_OFF);
  4273. rc = cciss_request_irq(h, do_cciss_msix_intr, do_cciss_intx);
  4274. if (rc)
  4275. goto clean2;
  4276. dev_info(&h->pdev->dev, "%s: <0x%x> at PCI %s IRQ %d%s using DAC\n",
  4277. h->devname, pdev->device, pci_name(pdev),
  4278. h->intr[PERF_MODE_INT], dac ? "" : " not");
  4279. if (cciss_allocate_cmd_pool(h))
  4280. goto clean4;
  4281. if (cciss_allocate_scatterlists(h))
  4282. goto clean4;
  4283. h->cmd_sg_list = cciss_allocate_sg_chain_blocks(h,
  4284. h->chainsize, h->nr_cmds);
  4285. if (!h->cmd_sg_list && h->chainsize > 0)
  4286. goto clean4;
  4287. spin_lock_init(&h->lock);
  4288. /* Initialize the pdev driver private data.
  4289. have it point to h. */
  4290. pci_set_drvdata(pdev, h);
  4291. /* command and error info recs zeroed out before
  4292. they are used */
  4293. memset(h->cmd_pool_bits, 0,
  4294. DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG)
  4295. * sizeof(unsigned long));
  4296. h->num_luns = 0;
  4297. h->highest_lun = -1;
  4298. for (j = 0; j < CISS_MAX_LUN; j++) {
  4299. h->drv[j] = NULL;
  4300. h->gendisk[j] = NULL;
  4301. }
  4302. cciss_scsi_setup(h);
  4303. /* Turn the interrupts on so we can service requests */
  4304. h->access.set_intr_mask(h, CCISS_INTR_ON);
  4305. /* Get the firmware version */
  4306. inq_buff = kzalloc(sizeof(InquiryData_struct), GFP_KERNEL);
  4307. if (inq_buff == NULL) {
  4308. dev_err(&h->pdev->dev, "out of memory\n");
  4309. goto clean4;
  4310. }
  4311. return_code = sendcmd_withirq(h, CISS_INQUIRY, inq_buff,
  4312. sizeof(InquiryData_struct), 0, CTLR_LUNID, TYPE_CMD);
  4313. if (return_code == IO_OK) {
  4314. h->firm_ver[0] = inq_buff->data_byte[32];
  4315. h->firm_ver[1] = inq_buff->data_byte[33];
  4316. h->firm_ver[2] = inq_buff->data_byte[34];
  4317. h->firm_ver[3] = inq_buff->data_byte[35];
  4318. } else { /* send command failed */
  4319. dev_warn(&h->pdev->dev, "unable to determine firmware"
  4320. " version of controller\n");
  4321. }
  4322. kfree(inq_buff);
  4323. cciss_procinit(h);
  4324. h->cciss_max_sectors = 8192;
  4325. rebuild_lun_table(h, 1, 0);
  4326. h->busy_initializing = 0;
  4327. return 1;
  4328. clean4:
  4329. cciss_free_cmd_pool(h);
  4330. cciss_free_scatterlists(h);
  4331. cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);
  4332. free_irq(h->intr[PERF_MODE_INT], h);
  4333. clean2:
  4334. unregister_blkdev(h->major, h->devname);
  4335. clean1:
  4336. cciss_destroy_hba_sysfs_entry(h);
  4337. clean0:
  4338. pci_release_regions(pdev);
  4339. clean_no_release_regions:
  4340. h->busy_initializing = 0;
  4341. /*
  4342. * Deliberately omit pci_disable_device(): it does something nasty to
  4343. * Smart Array controllers that pci_enable_device does not undo
  4344. */
  4345. pci_set_drvdata(pdev, NULL);
  4346. free_hba(h);
  4347. return -1;
  4348. }
  4349. static void cciss_shutdown(struct pci_dev *pdev)
  4350. {
  4351. ctlr_info_t *h;
  4352. char *flush_buf;
  4353. int return_code;
  4354. h = pci_get_drvdata(pdev);
  4355. flush_buf = kzalloc(4, GFP_KERNEL);
  4356. if (!flush_buf) {
  4357. dev_warn(&h->pdev->dev, "cache not flushed, out of memory.\n");
  4358. return;
  4359. }
  4360. /* write all data in the battery backed cache to disk */
  4361. memset(flush_buf, 0, 4);
  4362. return_code = sendcmd_withirq(h, CCISS_CACHE_FLUSH, flush_buf,
  4363. 4, 0, CTLR_LUNID, TYPE_CMD);
  4364. kfree(flush_buf);
  4365. if (return_code != IO_OK)
  4366. dev_warn(&h->pdev->dev, "Error flushing cache\n");
  4367. h->access.set_intr_mask(h, CCISS_INTR_OFF);
  4368. free_irq(h->intr[PERF_MODE_INT], h);
  4369. }
  4370. static void __devexit cciss_remove_one(struct pci_dev *pdev)
  4371. {
  4372. ctlr_info_t *h;
  4373. int i, j;
  4374. if (pci_get_drvdata(pdev) == NULL) {
  4375. dev_err(&pdev->dev, "Unable to remove device\n");
  4376. return;
  4377. }
  4378. h = pci_get_drvdata(pdev);
  4379. i = h->ctlr;
  4380. if (hba[i] == NULL) {
  4381. dev_err(&pdev->dev, "device appears to already be removed\n");
  4382. return;
  4383. }
  4384. mutex_lock(&h->busy_shutting_down);
  4385. remove_from_scan_list(h);
  4386. remove_proc_entry(h->devname, proc_cciss);
  4387. unregister_blkdev(h->major, h->devname);
  4388. /* remove it from the disk list */
  4389. for (j = 0; j < CISS_MAX_LUN; j++) {
  4390. struct gendisk *disk = h->gendisk[j];
  4391. if (disk) {
  4392. struct request_queue *q = disk->queue;
  4393. if (disk->flags & GENHD_FL_UP) {
  4394. cciss_destroy_ld_sysfs_entry(h, j, 1);
  4395. del_gendisk(disk);
  4396. }
  4397. if (q)
  4398. blk_cleanup_queue(q);
  4399. }
  4400. }
  4401. #ifdef CONFIG_CISS_SCSI_TAPE
  4402. cciss_unregister_scsi(h); /* unhook from SCSI subsystem */
  4403. #endif
  4404. cciss_shutdown(pdev);
  4405. #ifdef CONFIG_PCI_MSI
  4406. if (h->msix_vector)
  4407. pci_disable_msix(h->pdev);
  4408. else if (h->msi_vector)
  4409. pci_disable_msi(h->pdev);
  4410. #endif /* CONFIG_PCI_MSI */
  4411. iounmap(h->transtable);
  4412. iounmap(h->cfgtable);
  4413. iounmap(h->vaddr);
  4414. cciss_free_cmd_pool(h);
  4415. /* Free up sg elements */
  4416. for (j = 0; j < h->nr_cmds; j++)
  4417. kfree(h->scatter_list[j]);
  4418. kfree(h->scatter_list);
  4419. cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);
  4420. kfree(h->blockFetchTable);
  4421. if (h->reply_pool)
  4422. pci_free_consistent(h->pdev, h->max_commands * sizeof(__u64),
  4423. h->reply_pool, h->reply_pool_dhandle);
  4424. /*
  4425. * Deliberately omit pci_disable_device(): it does something nasty to
  4426. * Smart Array controllers that pci_enable_device does not undo
  4427. */
  4428. pci_release_regions(pdev);
  4429. pci_set_drvdata(pdev, NULL);
  4430. cciss_destroy_hba_sysfs_entry(h);
  4431. mutex_unlock(&h->busy_shutting_down);
  4432. free_hba(h);
  4433. }
  4434. static struct pci_driver cciss_pci_driver = {
  4435. .name = "cciss",
  4436. .probe = cciss_init_one,
  4437. .remove = __devexit_p(cciss_remove_one),
  4438. .id_table = cciss_pci_device_id, /* id_table */
  4439. .shutdown = cciss_shutdown,
  4440. };
  4441. /*
  4442. * This is it. Register the PCI driver information for the cards we control
  4443. * the OS will call our registered routines when it finds one of our cards.
  4444. */
  4445. static int __init cciss_init(void)
  4446. {
  4447. int err;
  4448. /*
  4449. * The hardware requires that commands are aligned on a 64-bit
  4450. * boundary. Given that we use pci_alloc_consistent() to allocate an
  4451. * array of them, the size must be a multiple of 8 bytes.
  4452. */
  4453. BUILD_BUG_ON(sizeof(CommandList_struct) % COMMANDLIST_ALIGNMENT);
  4454. printk(KERN_INFO DRIVER_NAME "\n");
  4455. err = bus_register(&cciss_bus_type);
  4456. if (err)
  4457. return err;
  4458. /* Start the scan thread */
  4459. cciss_scan_thread = kthread_run(scan_thread, NULL, "cciss_scan");
  4460. if (IS_ERR(cciss_scan_thread)) {
  4461. err = PTR_ERR(cciss_scan_thread);
  4462. goto err_bus_unregister;
  4463. }
  4464. /* Register for our PCI devices */
  4465. err = pci_register_driver(&cciss_pci_driver);
  4466. if (err)
  4467. goto err_thread_stop;
  4468. return err;
  4469. err_thread_stop:
  4470. kthread_stop(cciss_scan_thread);
  4471. err_bus_unregister:
  4472. bus_unregister(&cciss_bus_type);
  4473. return err;
  4474. }
  4475. static void __exit cciss_cleanup(void)
  4476. {
  4477. int i;
  4478. pci_unregister_driver(&cciss_pci_driver);
  4479. /* double check that all controller entrys have been removed */
  4480. for (i = 0; i < MAX_CTLR; i++) {
  4481. if (hba[i] != NULL) {
  4482. dev_warn(&hba[i]->pdev->dev,
  4483. "had to remove controller\n");
  4484. cciss_remove_one(hba[i]->pdev);
  4485. }
  4486. }
  4487. kthread_stop(cciss_scan_thread);
  4488. if (proc_cciss)
  4489. remove_proc_entry("driver/cciss", NULL);
  4490. bus_unregister(&cciss_bus_type);
  4491. }
  4492. module_init(cciss_init);
  4493. module_exit(cciss_cleanup);