pcxhr_mix22.c 27 KB

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  1. /*
  2. * Driver for Digigram pcxhr compatible soundcards
  3. *
  4. * mixer interface for stereo cards
  5. *
  6. * Copyright (c) 2004 by Digigram <alsa@digigram.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/delay.h>
  23. #include <linux/io.h>
  24. #include <sound/core.h>
  25. #include <sound/control.h>
  26. #include <sound/tlv.h>
  27. #include <sound/asoundef.h>
  28. #include "pcxhr.h"
  29. #include "pcxhr_core.h"
  30. #include "pcxhr_mix22.h"
  31. /* registers used on the DSP and Xilinx (port 2) : HR stereo cards only */
  32. #define PCXHR_DSP_RESET 0x20
  33. #define PCXHR_XLX_CFG 0x24
  34. #define PCXHR_XLX_RUER 0x28
  35. #define PCXHR_XLX_DATA 0x2C
  36. #define PCXHR_XLX_STATUS 0x30
  37. #define PCXHR_XLX_LOFREQ 0x34
  38. #define PCXHR_XLX_HIFREQ 0x38
  39. #define PCXHR_XLX_CSUER 0x3C
  40. #define PCXHR_XLX_SELMIC 0x40
  41. #define PCXHR_DSP 2
  42. /* byte access only ! */
  43. #define PCXHR_INPB(mgr, x) inb((mgr)->port[PCXHR_DSP] + (x))
  44. #define PCXHR_OUTPB(mgr, x, data) outb((data), (mgr)->port[PCXHR_DSP] + (x))
  45. /* values for PCHR_DSP_RESET register */
  46. #define PCXHR_DSP_RESET_DSP 0x01
  47. #define PCXHR_DSP_RESET_MUTE 0x02
  48. #define PCXHR_DSP_RESET_CODEC 0x08
  49. /* values for PCHR_XLX_CFG register */
  50. #define PCXHR_CFG_SYNCDSP_MASK 0x80
  51. #define PCXHR_CFG_DEPENDENCY_MASK 0x60
  52. #define PCXHR_CFG_INDEPENDANT_SEL 0x00
  53. #define PCXHR_CFG_MASTER_SEL 0x40
  54. #define PCXHR_CFG_SLAVE_SEL 0x20
  55. #define PCXHR_CFG_DATA_UER1_SEL_MASK 0x10 /* 0 (UER0), 1(UER1) */
  56. #define PCXHR_CFG_DATAIN_SEL_MASK 0x08 /* 0 (ana), 1 (UER) */
  57. #define PCXHR_CFG_SRC_MASK 0x04 /* 0 (Bypass), 1 (SRC Actif) */
  58. #define PCXHR_CFG_CLOCK_UER1_SEL_MASK 0x02 /* 0 (UER0), 1(UER1) */
  59. #define PCXHR_CFG_CLOCKIN_SEL_MASK 0x01 /* 0 (internal), 1 (AES/EBU) */
  60. /* values for PCHR_XLX_DATA register */
  61. #define PCXHR_DATA_CODEC 0x80
  62. #define AKM_POWER_CONTROL_CMD 0xA007
  63. #define AKM_RESET_ON_CMD 0xA100
  64. #define AKM_RESET_OFF_CMD 0xA103
  65. #define AKM_CLOCK_INF_55K_CMD 0xA240
  66. #define AKM_CLOCK_SUP_55K_CMD 0xA24D
  67. #define AKM_MUTE_CMD 0xA38D
  68. #define AKM_UNMUTE_CMD 0xA30D
  69. #define AKM_LEFT_LEVEL_CMD 0xA600
  70. #define AKM_RIGHT_LEVEL_CMD 0xA700
  71. /* values for PCHR_XLX_STATUS register - READ */
  72. #define PCXHR_STAT_SRC_LOCK 0x01
  73. #define PCXHR_STAT_LEVEL_IN 0x02
  74. #define PCXHR_STAT_MIC_CAPS 0x10
  75. /* values for PCHR_XLX_STATUS register - WRITE */
  76. #define PCXHR_STAT_FREQ_SYNC_MASK 0x01
  77. #define PCXHR_STAT_FREQ_UER1_MASK 0x02
  78. #define PCXHR_STAT_FREQ_SAVE_MASK 0x80
  79. /* values for PCHR_XLX_CSUER register */
  80. #define PCXHR_SUER1_BIT_U_READ_MASK 0x80
  81. #define PCXHR_SUER1_BIT_C_READ_MASK 0x40
  82. #define PCXHR_SUER1_DATA_PRESENT_MASK 0x20
  83. #define PCXHR_SUER1_CLOCK_PRESENT_MASK 0x10
  84. #define PCXHR_SUER_BIT_U_READ_MASK 0x08
  85. #define PCXHR_SUER_BIT_C_READ_MASK 0x04
  86. #define PCXHR_SUER_DATA_PRESENT_MASK 0x02
  87. #define PCXHR_SUER_CLOCK_PRESENT_MASK 0x01
  88. #define PCXHR_SUER_BIT_U_WRITE_MASK 0x02
  89. #define PCXHR_SUER_BIT_C_WRITE_MASK 0x01
  90. /* values for PCXHR_XLX_SELMIC register - WRITE */
  91. #define PCXHR_SELMIC_PREAMPLI_OFFSET 2
  92. #define PCXHR_SELMIC_PREAMPLI_MASK 0x0C
  93. #define PCXHR_SELMIC_PHANTOM_ALIM 0x80
  94. static const unsigned char g_hr222_p_level[] = {
  95. 0x00, /* [000] -49.5 dB: AKM[000] = -1.#INF dB (mute) */
  96. 0x01, /* [001] -49.0 dB: AKM[001] = -48.131 dB (diff=0.86920 dB) */
  97. 0x01, /* [002] -48.5 dB: AKM[001] = -48.131 dB (diff=0.36920 dB) */
  98. 0x01, /* [003] -48.0 dB: AKM[001] = -48.131 dB (diff=0.13080 dB) */
  99. 0x01, /* [004] -47.5 dB: AKM[001] = -48.131 dB (diff=0.63080 dB) */
  100. 0x01, /* [005] -46.5 dB: AKM[001] = -48.131 dB (diff=1.63080 dB) */
  101. 0x01, /* [006] -47.0 dB: AKM[001] = -48.131 dB (diff=1.13080 dB) */
  102. 0x01, /* [007] -46.0 dB: AKM[001] = -48.131 dB (diff=2.13080 dB) */
  103. 0x01, /* [008] -45.5 dB: AKM[001] = -48.131 dB (diff=2.63080 dB) */
  104. 0x02, /* [009] -45.0 dB: AKM[002] = -42.110 dB (diff=2.88980 dB) */
  105. 0x02, /* [010] -44.5 dB: AKM[002] = -42.110 dB (diff=2.38980 dB) */
  106. 0x02, /* [011] -44.0 dB: AKM[002] = -42.110 dB (diff=1.88980 dB) */
  107. 0x02, /* [012] -43.5 dB: AKM[002] = -42.110 dB (diff=1.38980 dB) */
  108. 0x02, /* [013] -43.0 dB: AKM[002] = -42.110 dB (diff=0.88980 dB) */
  109. 0x02, /* [014] -42.5 dB: AKM[002] = -42.110 dB (diff=0.38980 dB) */
  110. 0x02, /* [015] -42.0 dB: AKM[002] = -42.110 dB (diff=0.11020 dB) */
  111. 0x02, /* [016] -41.5 dB: AKM[002] = -42.110 dB (diff=0.61020 dB) */
  112. 0x02, /* [017] -41.0 dB: AKM[002] = -42.110 dB (diff=1.11020 dB) */
  113. 0x02, /* [018] -40.5 dB: AKM[002] = -42.110 dB (diff=1.61020 dB) */
  114. 0x03, /* [019] -40.0 dB: AKM[003] = -38.588 dB (diff=1.41162 dB) */
  115. 0x03, /* [020] -39.5 dB: AKM[003] = -38.588 dB (diff=0.91162 dB) */
  116. 0x03, /* [021] -39.0 dB: AKM[003] = -38.588 dB (diff=0.41162 dB) */
  117. 0x03, /* [022] -38.5 dB: AKM[003] = -38.588 dB (diff=0.08838 dB) */
  118. 0x03, /* [023] -38.0 dB: AKM[003] = -38.588 dB (diff=0.58838 dB) */
  119. 0x03, /* [024] -37.5 dB: AKM[003] = -38.588 dB (diff=1.08838 dB) */
  120. 0x04, /* [025] -37.0 dB: AKM[004] = -36.090 dB (diff=0.91040 dB) */
  121. 0x04, /* [026] -36.5 dB: AKM[004] = -36.090 dB (diff=0.41040 dB) */
  122. 0x04, /* [027] -36.0 dB: AKM[004] = -36.090 dB (diff=0.08960 dB) */
  123. 0x04, /* [028] -35.5 dB: AKM[004] = -36.090 dB (diff=0.58960 dB) */
  124. 0x05, /* [029] -35.0 dB: AKM[005] = -34.151 dB (diff=0.84860 dB) */
  125. 0x05, /* [030] -34.5 dB: AKM[005] = -34.151 dB (diff=0.34860 dB) */
  126. 0x05, /* [031] -34.0 dB: AKM[005] = -34.151 dB (diff=0.15140 dB) */
  127. 0x05, /* [032] -33.5 dB: AKM[005] = -34.151 dB (diff=0.65140 dB) */
  128. 0x06, /* [033] -33.0 dB: AKM[006] = -32.568 dB (diff=0.43222 dB) */
  129. 0x06, /* [034] -32.5 dB: AKM[006] = -32.568 dB (diff=0.06778 dB) */
  130. 0x06, /* [035] -32.0 dB: AKM[006] = -32.568 dB (diff=0.56778 dB) */
  131. 0x07, /* [036] -31.5 dB: AKM[007] = -31.229 dB (diff=0.27116 dB) */
  132. 0x07, /* [037] -31.0 dB: AKM[007] = -31.229 dB (diff=0.22884 dB) */
  133. 0x08, /* [038] -30.5 dB: AKM[008] = -30.069 dB (diff=0.43100 dB) */
  134. 0x08, /* [039] -30.0 dB: AKM[008] = -30.069 dB (diff=0.06900 dB) */
  135. 0x09, /* [040] -29.5 dB: AKM[009] = -29.046 dB (diff=0.45405 dB) */
  136. 0x09, /* [041] -29.0 dB: AKM[009] = -29.046 dB (diff=0.04595 dB) */
  137. 0x0a, /* [042] -28.5 dB: AKM[010] = -28.131 dB (diff=0.36920 dB) */
  138. 0x0a, /* [043] -28.0 dB: AKM[010] = -28.131 dB (diff=0.13080 dB) */
  139. 0x0b, /* [044] -27.5 dB: AKM[011] = -27.303 dB (diff=0.19705 dB) */
  140. 0x0b, /* [045] -27.0 dB: AKM[011] = -27.303 dB (diff=0.30295 dB) */
  141. 0x0c, /* [046] -26.5 dB: AKM[012] = -26.547 dB (diff=0.04718 dB) */
  142. 0x0d, /* [047] -26.0 dB: AKM[013] = -25.852 dB (diff=0.14806 dB) */
  143. 0x0e, /* [048] -25.5 dB: AKM[014] = -25.208 dB (diff=0.29176 dB) */
  144. 0x0e, /* [049] -25.0 dB: AKM[014] = -25.208 dB (diff=0.20824 dB) */
  145. 0x0f, /* [050] -24.5 dB: AKM[015] = -24.609 dB (diff=0.10898 dB) */
  146. 0x10, /* [051] -24.0 dB: AKM[016] = -24.048 dB (diff=0.04840 dB) */
  147. 0x11, /* [052] -23.5 dB: AKM[017] = -23.522 dB (diff=0.02183 dB) */
  148. 0x12, /* [053] -23.0 dB: AKM[018] = -23.025 dB (diff=0.02535 dB) */
  149. 0x13, /* [054] -22.5 dB: AKM[019] = -22.556 dB (diff=0.05573 dB) */
  150. 0x14, /* [055] -22.0 dB: AKM[020] = -22.110 dB (diff=0.11020 dB) */
  151. 0x15, /* [056] -21.5 dB: AKM[021] = -21.686 dB (diff=0.18642 dB) */
  152. 0x17, /* [057] -21.0 dB: AKM[023] = -20.896 dB (diff=0.10375 dB) */
  153. 0x18, /* [058] -20.5 dB: AKM[024] = -20.527 dB (diff=0.02658 dB) */
  154. 0x1a, /* [059] -20.0 dB: AKM[026] = -19.831 dB (diff=0.16866 dB) */
  155. 0x1b, /* [060] -19.5 dB: AKM[027] = -19.504 dB (diff=0.00353 dB) */
  156. 0x1d, /* [061] -19.0 dB: AKM[029] = -18.883 dB (diff=0.11716 dB) */
  157. 0x1e, /* [062] -18.5 dB: AKM[030] = -18.588 dB (diff=0.08838 dB) */
  158. 0x20, /* [063] -18.0 dB: AKM[032] = -18.028 dB (diff=0.02780 dB) */
  159. 0x22, /* [064] -17.5 dB: AKM[034] = -17.501 dB (diff=0.00123 dB) */
  160. 0x24, /* [065] -17.0 dB: AKM[036] = -17.005 dB (diff=0.00475 dB) */
  161. 0x26, /* [066] -16.5 dB: AKM[038] = -16.535 dB (diff=0.03513 dB) */
  162. 0x28, /* [067] -16.0 dB: AKM[040] = -16.090 dB (diff=0.08960 dB) */
  163. 0x2b, /* [068] -15.5 dB: AKM[043] = -15.461 dB (diff=0.03857 dB) */
  164. 0x2d, /* [069] -15.0 dB: AKM[045] = -15.067 dB (diff=0.06655 dB) */
  165. 0x30, /* [070] -14.5 dB: AKM[048] = -14.506 dB (diff=0.00598 dB) */
  166. 0x33, /* [071] -14.0 dB: AKM[051] = -13.979 dB (diff=0.02060 dB) */
  167. 0x36, /* [072] -13.5 dB: AKM[054] = -13.483 dB (diff=0.01707 dB) */
  168. 0x39, /* [073] -13.0 dB: AKM[057] = -13.013 dB (diff=0.01331 dB) */
  169. 0x3c, /* [074] -12.5 dB: AKM[060] = -12.568 dB (diff=0.06778 dB) */
  170. 0x40, /* [075] -12.0 dB: AKM[064] = -12.007 dB (diff=0.00720 dB) */
  171. 0x44, /* [076] -11.5 dB: AKM[068] = -11.481 dB (diff=0.01937 dB) */
  172. 0x48, /* [077] -11.0 dB: AKM[072] = -10.984 dB (diff=0.01585 dB) */
  173. 0x4c, /* [078] -10.5 dB: AKM[076] = -10.515 dB (diff=0.01453 dB) */
  174. 0x51, /* [079] -10.0 dB: AKM[081] = -9.961 dB (diff=0.03890 dB) */
  175. 0x55, /* [080] -9.5 dB: AKM[085] = -9.542 dB (diff=0.04243 dB) */
  176. 0x5a, /* [081] -9.0 dB: AKM[090] = -9.046 dB (diff=0.04595 dB) */
  177. 0x60, /* [082] -8.5 dB: AKM[096] = -8.485 dB (diff=0.01462 dB) */
  178. 0x66, /* [083] -8.0 dB: AKM[102] = -7.959 dB (diff=0.04120 dB) */
  179. 0x6c, /* [084] -7.5 dB: AKM[108] = -7.462 dB (diff=0.03767 dB) */
  180. 0x72, /* [085] -7.0 dB: AKM[114] = -6.993 dB (diff=0.00729 dB) */
  181. 0x79, /* [086] -6.5 dB: AKM[121] = -6.475 dB (diff=0.02490 dB) */
  182. 0x80, /* [087] -6.0 dB: AKM[128] = -5.987 dB (diff=0.01340 dB) */
  183. 0x87, /* [088] -5.5 dB: AKM[135] = -5.524 dB (diff=0.02413 dB) */
  184. 0x8f, /* [089] -5.0 dB: AKM[143] = -5.024 dB (diff=0.02408 dB) */
  185. 0x98, /* [090] -4.5 dB: AKM[152] = -4.494 dB (diff=0.00607 dB) */
  186. 0xa1, /* [091] -4.0 dB: AKM[161] = -3.994 dB (diff=0.00571 dB) */
  187. 0xaa, /* [092] -3.5 dB: AKM[170] = -3.522 dB (diff=0.02183 dB) */
  188. 0xb5, /* [093] -3.0 dB: AKM[181] = -2.977 dB (diff=0.02277 dB) */
  189. 0xbf, /* [094] -2.5 dB: AKM[191] = -2.510 dB (diff=0.01014 dB) */
  190. 0xcb, /* [095] -2.0 dB: AKM[203] = -1.981 dB (diff=0.01912 dB) */
  191. 0xd7, /* [096] -1.5 dB: AKM[215] = -1.482 dB (diff=0.01797 dB) */
  192. 0xe3, /* [097] -1.0 dB: AKM[227] = -1.010 dB (diff=0.01029 dB) */
  193. 0xf1, /* [098] -0.5 dB: AKM[241] = -0.490 dB (diff=0.00954 dB) */
  194. 0xff, /* [099] +0.0 dB: AKM[255] = +0.000 dB (diff=0.00000 dB) */
  195. };
  196. static void hr222_config_akm(struct pcxhr_mgr *mgr, unsigned short data)
  197. {
  198. unsigned short mask = 0x8000;
  199. /* activate access to codec registers */
  200. PCXHR_INPB(mgr, PCXHR_XLX_HIFREQ);
  201. while (mask) {
  202. PCXHR_OUTPB(mgr, PCXHR_XLX_DATA,
  203. data & mask ? PCXHR_DATA_CODEC : 0);
  204. mask >>= 1;
  205. }
  206. /* termiate access to codec registers */
  207. PCXHR_INPB(mgr, PCXHR_XLX_RUER);
  208. }
  209. static int hr222_set_hw_playback_level(struct pcxhr_mgr *mgr,
  210. int idx, int level)
  211. {
  212. unsigned short cmd;
  213. if (idx > 1 ||
  214. level < 0 ||
  215. level >= ARRAY_SIZE(g_hr222_p_level))
  216. return -EINVAL;
  217. if (idx == 0)
  218. cmd = AKM_LEFT_LEVEL_CMD;
  219. else
  220. cmd = AKM_RIGHT_LEVEL_CMD;
  221. /* conversion from PmBoardCodedLevel to AKM nonlinear programming */
  222. cmd += g_hr222_p_level[level];
  223. hr222_config_akm(mgr, cmd);
  224. return 0;
  225. }
  226. static int hr222_set_hw_capture_level(struct pcxhr_mgr *mgr,
  227. int level_l, int level_r, int level_mic)
  228. {
  229. /* program all input levels at the same time */
  230. unsigned int data;
  231. int i;
  232. if (!mgr->capture_chips)
  233. return -EINVAL; /* no PCX22 */
  234. data = ((level_mic & 0xff) << 24); /* micro is mono, but apply */
  235. data |= ((level_mic & 0xff) << 16); /* level on both channels */
  236. data |= ((level_r & 0xff) << 8); /* line input right channel */
  237. data |= (level_l & 0xff); /* line input left channel */
  238. PCXHR_INPB(mgr, PCXHR_XLX_DATA); /* activate input codec */
  239. /* send 32 bits (4 x 8 bits) */
  240. for (i = 0; i < 32; i++, data <<= 1) {
  241. PCXHR_OUTPB(mgr, PCXHR_XLX_DATA,
  242. (data & 0x80000000) ? PCXHR_DATA_CODEC : 0);
  243. }
  244. PCXHR_INPB(mgr, PCXHR_XLX_RUER); /* close input level codec */
  245. return 0;
  246. }
  247. static void hr222_micro_boost(struct pcxhr_mgr *mgr, int level);
  248. int hr222_sub_init(struct pcxhr_mgr *mgr)
  249. {
  250. unsigned char reg;
  251. mgr->board_has_analog = 1; /* analog always available */
  252. mgr->xlx_cfg = PCXHR_CFG_SYNCDSP_MASK;
  253. reg = PCXHR_INPB(mgr, PCXHR_XLX_STATUS);
  254. if (reg & PCXHR_STAT_MIC_CAPS)
  255. mgr->board_has_mic = 1; /* microphone available */
  256. snd_printdd("MIC input available = %d\n", mgr->board_has_mic);
  257. /* reset codec */
  258. PCXHR_OUTPB(mgr, PCXHR_DSP_RESET,
  259. PCXHR_DSP_RESET_DSP);
  260. msleep(5);
  261. PCXHR_OUTPB(mgr, PCXHR_DSP_RESET,
  262. PCXHR_DSP_RESET_DSP |
  263. PCXHR_DSP_RESET_MUTE |
  264. PCXHR_DSP_RESET_CODEC);
  265. msleep(5);
  266. /* config AKM */
  267. hr222_config_akm(mgr, AKM_POWER_CONTROL_CMD);
  268. hr222_config_akm(mgr, AKM_CLOCK_INF_55K_CMD);
  269. hr222_config_akm(mgr, AKM_UNMUTE_CMD);
  270. hr222_config_akm(mgr, AKM_RESET_OFF_CMD);
  271. /* init micro boost */
  272. hr222_micro_boost(mgr, 0);
  273. return 0;
  274. }
  275. /* calc PLL register */
  276. /* TODO : there is a very similar fct in pcxhr.c */
  277. static int hr222_pll_freq_register(unsigned int freq,
  278. unsigned int *pllreg,
  279. unsigned int *realfreq)
  280. {
  281. unsigned int reg;
  282. if (freq < 6900 || freq > 219000)
  283. return -EINVAL;
  284. reg = (28224000 * 2) / freq;
  285. reg = (reg - 1) / 2;
  286. if (reg < 0x100)
  287. *pllreg = reg + 0xC00;
  288. else if (reg < 0x200)
  289. *pllreg = reg + 0x800;
  290. else if (reg < 0x400)
  291. *pllreg = reg & 0x1ff;
  292. else if (reg < 0x800) {
  293. *pllreg = ((reg >> 1) & 0x1ff) + 0x200;
  294. reg &= ~1;
  295. } else {
  296. *pllreg = ((reg >> 2) & 0x1ff) + 0x400;
  297. reg &= ~3;
  298. }
  299. if (realfreq)
  300. *realfreq = (28224000 / (reg + 1));
  301. return 0;
  302. }
  303. int hr222_sub_set_clock(struct pcxhr_mgr *mgr,
  304. unsigned int rate,
  305. int *changed)
  306. {
  307. unsigned int speed, pllreg = 0;
  308. int err;
  309. unsigned realfreq = rate;
  310. switch (mgr->use_clock_type) {
  311. case HR22_CLOCK_TYPE_INTERNAL:
  312. err = hr222_pll_freq_register(rate, &pllreg, &realfreq);
  313. if (err)
  314. return err;
  315. mgr->xlx_cfg &= ~(PCXHR_CFG_CLOCKIN_SEL_MASK |
  316. PCXHR_CFG_CLOCK_UER1_SEL_MASK);
  317. break;
  318. case HR22_CLOCK_TYPE_AES_SYNC:
  319. mgr->xlx_cfg |= PCXHR_CFG_CLOCKIN_SEL_MASK;
  320. mgr->xlx_cfg &= ~PCXHR_CFG_CLOCK_UER1_SEL_MASK;
  321. break;
  322. case HR22_CLOCK_TYPE_AES_1:
  323. if (!mgr->board_has_aes1)
  324. return -EINVAL;
  325. mgr->xlx_cfg |= (PCXHR_CFG_CLOCKIN_SEL_MASK |
  326. PCXHR_CFG_CLOCK_UER1_SEL_MASK);
  327. break;
  328. default:
  329. return -EINVAL;
  330. }
  331. hr222_config_akm(mgr, AKM_MUTE_CMD);
  332. if (mgr->use_clock_type == HR22_CLOCK_TYPE_INTERNAL) {
  333. PCXHR_OUTPB(mgr, PCXHR_XLX_HIFREQ, pllreg >> 8);
  334. PCXHR_OUTPB(mgr, PCXHR_XLX_LOFREQ, pllreg & 0xff);
  335. }
  336. /* set clock source */
  337. PCXHR_OUTPB(mgr, PCXHR_XLX_CFG, mgr->xlx_cfg);
  338. /* codec speed modes */
  339. speed = rate < 55000 ? 0 : 1;
  340. if (mgr->codec_speed != speed) {
  341. mgr->codec_speed = speed;
  342. if (speed == 0)
  343. hr222_config_akm(mgr, AKM_CLOCK_INF_55K_CMD);
  344. else
  345. hr222_config_akm(mgr, AKM_CLOCK_SUP_55K_CMD);
  346. }
  347. mgr->sample_rate_real = realfreq;
  348. mgr->cur_clock_type = mgr->use_clock_type;
  349. if (changed)
  350. *changed = 1;
  351. hr222_config_akm(mgr, AKM_UNMUTE_CMD);
  352. snd_printdd("set_clock to %dHz (realfreq=%d pllreg=%x)\n",
  353. rate, realfreq, pllreg);
  354. return 0;
  355. }
  356. int hr222_get_external_clock(struct pcxhr_mgr *mgr,
  357. enum pcxhr_clock_type clock_type,
  358. int *sample_rate)
  359. {
  360. int rate, calc_rate = 0;
  361. unsigned int ticks;
  362. unsigned char mask, reg;
  363. if (clock_type == HR22_CLOCK_TYPE_AES_SYNC) {
  364. mask = (PCXHR_SUER_CLOCK_PRESENT_MASK |
  365. PCXHR_SUER_DATA_PRESENT_MASK);
  366. reg = PCXHR_STAT_FREQ_SYNC_MASK;
  367. } else if (clock_type == HR22_CLOCK_TYPE_AES_1 && mgr->board_has_aes1) {
  368. mask = (PCXHR_SUER1_CLOCK_PRESENT_MASK |
  369. PCXHR_SUER1_DATA_PRESENT_MASK);
  370. reg = PCXHR_STAT_FREQ_UER1_MASK;
  371. } else {
  372. snd_printdd("get_external_clock : type %d not supported\n",
  373. clock_type);
  374. return -EINVAL; /* other clocks not supported */
  375. }
  376. if ((PCXHR_INPB(mgr, PCXHR_XLX_CSUER) & mask) != mask) {
  377. snd_printdd("get_external_clock(%d) = 0 Hz\n", clock_type);
  378. *sample_rate = 0;
  379. return 0; /* no external clock locked */
  380. }
  381. PCXHR_OUTPB(mgr, PCXHR_XLX_STATUS, reg); /* calculate freq */
  382. /* save the measured clock frequency */
  383. reg |= PCXHR_STAT_FREQ_SAVE_MASK;
  384. if (mgr->last_reg_stat != reg) {
  385. udelay(500); /* wait min 2 cycles of lowest freq (8000) */
  386. mgr->last_reg_stat = reg;
  387. }
  388. PCXHR_OUTPB(mgr, PCXHR_XLX_STATUS, reg); /* save */
  389. /* get the frequency */
  390. ticks = (unsigned int)PCXHR_INPB(mgr, PCXHR_XLX_CFG);
  391. ticks = (ticks & 0x03) << 8;
  392. ticks |= (unsigned int)PCXHR_INPB(mgr, PCXHR_DSP_RESET);
  393. if (ticks != 0)
  394. calc_rate = 28224000 / ticks;
  395. /* rounding */
  396. if (calc_rate > 184200)
  397. rate = 192000;
  398. else if (calc_rate > 152200)
  399. rate = 176400;
  400. else if (calc_rate > 112000)
  401. rate = 128000;
  402. else if (calc_rate > 92100)
  403. rate = 96000;
  404. else if (calc_rate > 76100)
  405. rate = 88200;
  406. else if (calc_rate > 56000)
  407. rate = 64000;
  408. else if (calc_rate > 46050)
  409. rate = 48000;
  410. else if (calc_rate > 38050)
  411. rate = 44100;
  412. else if (calc_rate > 28000)
  413. rate = 32000;
  414. else if (calc_rate > 23025)
  415. rate = 24000;
  416. else if (calc_rate > 19025)
  417. rate = 22050;
  418. else if (calc_rate > 14000)
  419. rate = 16000;
  420. else if (calc_rate > 11512)
  421. rate = 12000;
  422. else if (calc_rate > 9512)
  423. rate = 11025;
  424. else if (calc_rate > 7000)
  425. rate = 8000;
  426. else
  427. rate = 0;
  428. snd_printdd("External clock is at %d Hz (measured %d Hz)\n",
  429. rate, calc_rate);
  430. *sample_rate = rate;
  431. return 0;
  432. }
  433. int hr222_update_analog_audio_level(struct snd_pcxhr *chip,
  434. int is_capture, int channel)
  435. {
  436. snd_printdd("hr222_update_analog_audio_level(%s chan=%d)\n",
  437. is_capture ? "capture" : "playback", channel);
  438. if (is_capture) {
  439. int level_l, level_r, level_mic;
  440. /* we have to update all levels */
  441. if (chip->analog_capture_active) {
  442. level_l = chip->analog_capture_volume[0];
  443. level_r = chip->analog_capture_volume[1];
  444. } else {
  445. level_l = HR222_LINE_CAPTURE_LEVEL_MIN;
  446. level_r = HR222_LINE_CAPTURE_LEVEL_MIN;
  447. }
  448. if (chip->mic_active)
  449. level_mic = chip->mic_volume;
  450. else
  451. level_mic = HR222_MICRO_CAPTURE_LEVEL_MIN;
  452. return hr222_set_hw_capture_level(chip->mgr,
  453. level_l, level_r, level_mic);
  454. } else {
  455. int vol;
  456. if (chip->analog_playback_active[channel])
  457. vol = chip->analog_playback_volume[channel];
  458. else
  459. vol = HR222_LINE_PLAYBACK_LEVEL_MIN;
  460. return hr222_set_hw_playback_level(chip->mgr, channel, vol);
  461. }
  462. }
  463. /*texts[5] = {"Line", "Digital", "Digi+SRC", "Mic", "Line+Mic"}*/
  464. #define SOURCE_LINE 0
  465. #define SOURCE_DIGITAL 1
  466. #define SOURCE_DIGISRC 2
  467. #define SOURCE_MIC 3
  468. #define SOURCE_LINEMIC 4
  469. int hr222_set_audio_source(struct snd_pcxhr *chip)
  470. {
  471. int digital = 0;
  472. /* default analog source */
  473. chip->mgr->xlx_cfg &= ~(PCXHR_CFG_SRC_MASK |
  474. PCXHR_CFG_DATAIN_SEL_MASK |
  475. PCXHR_CFG_DATA_UER1_SEL_MASK);
  476. if (chip->audio_capture_source == SOURCE_DIGISRC) {
  477. chip->mgr->xlx_cfg |= PCXHR_CFG_SRC_MASK;
  478. digital = 1;
  479. } else {
  480. if (chip->audio_capture_source == SOURCE_DIGITAL)
  481. digital = 1;
  482. }
  483. if (digital) {
  484. chip->mgr->xlx_cfg |= PCXHR_CFG_DATAIN_SEL_MASK;
  485. if (chip->mgr->board_has_aes1) {
  486. /* get data from the AES1 plug */
  487. chip->mgr->xlx_cfg |= PCXHR_CFG_DATA_UER1_SEL_MASK;
  488. }
  489. /* chip->mic_active = 0; */
  490. /* chip->analog_capture_active = 0; */
  491. } else {
  492. int update_lvl = 0;
  493. chip->analog_capture_active = 0;
  494. chip->mic_active = 0;
  495. if (chip->audio_capture_source == SOURCE_LINE ||
  496. chip->audio_capture_source == SOURCE_LINEMIC) {
  497. if (chip->analog_capture_active == 0)
  498. update_lvl = 1;
  499. chip->analog_capture_active = 1;
  500. }
  501. if (chip->audio_capture_source == SOURCE_MIC ||
  502. chip->audio_capture_source == SOURCE_LINEMIC) {
  503. if (chip->mic_active == 0)
  504. update_lvl = 1;
  505. chip->mic_active = 1;
  506. }
  507. if (update_lvl) {
  508. /* capture: update all 3 mutes/unmutes with one call */
  509. hr222_update_analog_audio_level(chip, 1, 0);
  510. }
  511. }
  512. /* set the source infos (max 3 bits modified) */
  513. PCXHR_OUTPB(chip->mgr, PCXHR_XLX_CFG, chip->mgr->xlx_cfg);
  514. return 0;
  515. }
  516. int hr222_iec958_capture_byte(struct snd_pcxhr *chip,
  517. int aes_idx, unsigned char *aes_bits)
  518. {
  519. unsigned char idx = (unsigned char)(aes_idx * 8);
  520. unsigned char temp = 0;
  521. unsigned char mask = chip->mgr->board_has_aes1 ?
  522. PCXHR_SUER1_BIT_C_READ_MASK : PCXHR_SUER_BIT_C_READ_MASK;
  523. int i;
  524. for (i = 0; i < 8; i++) {
  525. PCXHR_OUTPB(chip->mgr, PCXHR_XLX_RUER, idx++); /* idx < 192 */
  526. temp <<= 1;
  527. if (PCXHR_INPB(chip->mgr, PCXHR_XLX_CSUER) & mask)
  528. temp |= 1;
  529. }
  530. snd_printdd("read iec958 AES %d byte %d = 0x%x\n",
  531. chip->chip_idx, aes_idx, temp);
  532. *aes_bits = temp;
  533. return 0;
  534. }
  535. int hr222_iec958_update_byte(struct snd_pcxhr *chip,
  536. int aes_idx, unsigned char aes_bits)
  537. {
  538. int i;
  539. unsigned char new_bits = aes_bits;
  540. unsigned char old_bits = chip->aes_bits[aes_idx];
  541. unsigned char idx = (unsigned char)(aes_idx * 8);
  542. for (i = 0; i < 8; i++) {
  543. if ((old_bits & 0x01) != (new_bits & 0x01)) {
  544. /* idx < 192 */
  545. PCXHR_OUTPB(chip->mgr, PCXHR_XLX_RUER, idx);
  546. /* write C and U bit */
  547. PCXHR_OUTPB(chip->mgr, PCXHR_XLX_CSUER, new_bits&0x01 ?
  548. PCXHR_SUER_BIT_C_WRITE_MASK : 0);
  549. }
  550. idx++;
  551. old_bits >>= 1;
  552. new_bits >>= 1;
  553. }
  554. chip->aes_bits[aes_idx] = aes_bits;
  555. return 0;
  556. }
  557. static void hr222_micro_boost(struct pcxhr_mgr *mgr, int level)
  558. {
  559. unsigned char boost_mask;
  560. boost_mask = (unsigned char) (level << PCXHR_SELMIC_PREAMPLI_OFFSET);
  561. if (boost_mask & (~PCXHR_SELMIC_PREAMPLI_MASK))
  562. return; /* only values form 0 to 3 accepted */
  563. mgr->xlx_selmic &= ~PCXHR_SELMIC_PREAMPLI_MASK;
  564. mgr->xlx_selmic |= boost_mask;
  565. PCXHR_OUTPB(mgr, PCXHR_XLX_SELMIC, mgr->xlx_selmic);
  566. snd_printdd("hr222_micro_boost : set %x\n", boost_mask);
  567. }
  568. static void hr222_phantom_power(struct pcxhr_mgr *mgr, int power)
  569. {
  570. if (power)
  571. mgr->xlx_selmic |= PCXHR_SELMIC_PHANTOM_ALIM;
  572. else
  573. mgr->xlx_selmic &= ~PCXHR_SELMIC_PHANTOM_ALIM;
  574. PCXHR_OUTPB(mgr, PCXHR_XLX_SELMIC, mgr->xlx_selmic);
  575. snd_printdd("hr222_phantom_power : set %d\n", power);
  576. }
  577. /* mic level */
  578. static const DECLARE_TLV_DB_SCALE(db_scale_mic_hr222, -9850, 50, 650);
  579. static int hr222_mic_vol_info(struct snd_kcontrol *kcontrol,
  580. struct snd_ctl_elem_info *uinfo)
  581. {
  582. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  583. uinfo->count = 1;
  584. uinfo->value.integer.min = HR222_MICRO_CAPTURE_LEVEL_MIN; /* -98 dB */
  585. /* gains from 9 dB to 31.5 dB not recommended; use micboost instead */
  586. uinfo->value.integer.max = HR222_MICRO_CAPTURE_LEVEL_MAX; /* +7 dB */
  587. return 0;
  588. }
  589. static int hr222_mic_vol_get(struct snd_kcontrol *kcontrol,
  590. struct snd_ctl_elem_value *ucontrol)
  591. {
  592. struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
  593. mutex_lock(&chip->mgr->mixer_mutex);
  594. ucontrol->value.integer.value[0] = chip->mic_volume;
  595. mutex_unlock(&chip->mgr->mixer_mutex);
  596. return 0;
  597. }
  598. static int hr222_mic_vol_put(struct snd_kcontrol *kcontrol,
  599. struct snd_ctl_elem_value *ucontrol)
  600. {
  601. struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
  602. int changed = 0;
  603. mutex_lock(&chip->mgr->mixer_mutex);
  604. if (chip->mic_volume != ucontrol->value.integer.value[0]) {
  605. changed = 1;
  606. chip->mic_volume = ucontrol->value.integer.value[0];
  607. hr222_update_analog_audio_level(chip, 1, 0);
  608. }
  609. mutex_unlock(&chip->mgr->mixer_mutex);
  610. return changed;
  611. }
  612. static struct snd_kcontrol_new hr222_control_mic_level = {
  613. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  614. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  615. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  616. .name = "Mic Capture Volume",
  617. .info = hr222_mic_vol_info,
  618. .get = hr222_mic_vol_get,
  619. .put = hr222_mic_vol_put,
  620. .tlv = { .p = db_scale_mic_hr222 },
  621. };
  622. /* mic boost level */
  623. static const DECLARE_TLV_DB_SCALE(db_scale_micboost_hr222, 0, 1800, 5400);
  624. static int hr222_mic_boost_info(struct snd_kcontrol *kcontrol,
  625. struct snd_ctl_elem_info *uinfo)
  626. {
  627. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  628. uinfo->count = 1;
  629. uinfo->value.integer.min = 0; /* 0 dB */
  630. uinfo->value.integer.max = 3; /* 54 dB */
  631. return 0;
  632. }
  633. static int hr222_mic_boost_get(struct snd_kcontrol *kcontrol,
  634. struct snd_ctl_elem_value *ucontrol)
  635. {
  636. struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
  637. mutex_lock(&chip->mgr->mixer_mutex);
  638. ucontrol->value.integer.value[0] = chip->mic_boost;
  639. mutex_unlock(&chip->mgr->mixer_mutex);
  640. return 0;
  641. }
  642. static int hr222_mic_boost_put(struct snd_kcontrol *kcontrol,
  643. struct snd_ctl_elem_value *ucontrol)
  644. {
  645. struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
  646. int changed = 0;
  647. mutex_lock(&chip->mgr->mixer_mutex);
  648. if (chip->mic_boost != ucontrol->value.integer.value[0]) {
  649. changed = 1;
  650. chip->mic_boost = ucontrol->value.integer.value[0];
  651. hr222_micro_boost(chip->mgr, chip->mic_boost);
  652. }
  653. mutex_unlock(&chip->mgr->mixer_mutex);
  654. return changed;
  655. }
  656. static struct snd_kcontrol_new hr222_control_mic_boost = {
  657. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  658. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  659. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  660. .name = "MicBoost Capture Volume",
  661. .info = hr222_mic_boost_info,
  662. .get = hr222_mic_boost_get,
  663. .put = hr222_mic_boost_put,
  664. .tlv = { .p = db_scale_micboost_hr222 },
  665. };
  666. /******************* Phantom power switch *******************/
  667. #define hr222_phantom_power_info snd_ctl_boolean_mono_info
  668. static int hr222_phantom_power_get(struct snd_kcontrol *kcontrol,
  669. struct snd_ctl_elem_value *ucontrol)
  670. {
  671. struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
  672. mutex_lock(&chip->mgr->mixer_mutex);
  673. ucontrol->value.integer.value[0] = chip->phantom_power;
  674. mutex_unlock(&chip->mgr->mixer_mutex);
  675. return 0;
  676. }
  677. static int hr222_phantom_power_put(struct snd_kcontrol *kcontrol,
  678. struct snd_ctl_elem_value *ucontrol)
  679. {
  680. struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
  681. int power, changed = 0;
  682. mutex_lock(&chip->mgr->mixer_mutex);
  683. power = !!ucontrol->value.integer.value[0];
  684. if (chip->phantom_power != power) {
  685. hr222_phantom_power(chip->mgr, power);
  686. chip->phantom_power = power;
  687. changed = 1;
  688. }
  689. mutex_unlock(&chip->mgr->mixer_mutex);
  690. return changed;
  691. }
  692. static struct snd_kcontrol_new hr222_phantom_power_switch = {
  693. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  694. .name = "Phantom Power Switch",
  695. .info = hr222_phantom_power_info,
  696. .get = hr222_phantom_power_get,
  697. .put = hr222_phantom_power_put,
  698. };
  699. int hr222_add_mic_controls(struct snd_pcxhr *chip)
  700. {
  701. int err;
  702. if (!chip->mgr->board_has_mic)
  703. return 0;
  704. /* controls */
  705. err = snd_ctl_add(chip->card, snd_ctl_new1(&hr222_control_mic_level,
  706. chip));
  707. if (err < 0)
  708. return err;
  709. err = snd_ctl_add(chip->card, snd_ctl_new1(&hr222_control_mic_boost,
  710. chip));
  711. if (err < 0)
  712. return err;
  713. err = snd_ctl_add(chip->card, snd_ctl_new1(&hr222_phantom_power_switch,
  714. chip));
  715. return err;
  716. }