gus_dma.c 7.0 KB

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  1. /*
  2. * Routines for GF1 DMA control
  3. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  4. *
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. #include <asm/dma.h>
  22. #include <linux/slab.h>
  23. #include <sound/core.h>
  24. #include <sound/gus.h>
  25. static void snd_gf1_dma_ack(struct snd_gus_card * gus)
  26. {
  27. unsigned long flags;
  28. spin_lock_irqsave(&gus->reg_lock, flags);
  29. snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL, 0x00);
  30. snd_gf1_look8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL);
  31. spin_unlock_irqrestore(&gus->reg_lock, flags);
  32. }
  33. static void snd_gf1_dma_program(struct snd_gus_card * gus,
  34. unsigned int addr,
  35. unsigned long buf_addr,
  36. unsigned int count,
  37. unsigned int cmd)
  38. {
  39. unsigned long flags;
  40. unsigned int address;
  41. unsigned char dma_cmd;
  42. unsigned int address_high;
  43. // snd_printk("dma_transfer: addr=0x%x, buf=0x%lx, count=0x%x\n", addr, (long) buf, count);
  44. if (gus->gf1.dma1 > 3) {
  45. if (gus->gf1.enh_mode) {
  46. address = addr >> 1;
  47. } else {
  48. if (addr & 0x1f) {
  49. snd_printd("snd_gf1_dma_transfer: unaligned address (0x%x)?\n", addr);
  50. return;
  51. }
  52. address = (addr & 0x000c0000) | ((addr & 0x0003ffff) >> 1);
  53. }
  54. } else {
  55. address = addr;
  56. }
  57. dma_cmd = SNDRV_GF1_DMA_ENABLE | (unsigned short) cmd;
  58. #if 0
  59. dma_cmd |= 0x08;
  60. #endif
  61. if (dma_cmd & SNDRV_GF1_DMA_16BIT) {
  62. count++;
  63. count &= ~1; /* align */
  64. }
  65. if (gus->gf1.dma1 > 3) {
  66. dma_cmd |= SNDRV_GF1_DMA_WIDTH16;
  67. count++;
  68. count &= ~1; /* align */
  69. }
  70. snd_gf1_dma_ack(gus);
  71. snd_dma_program(gus->gf1.dma1, buf_addr, count, dma_cmd & SNDRV_GF1_DMA_READ ? DMA_MODE_READ : DMA_MODE_WRITE);
  72. #if 0
  73. snd_printk("address = 0x%x, count = 0x%x, dma_cmd = 0x%x\n", address << 1, count, dma_cmd);
  74. #endif
  75. spin_lock_irqsave(&gus->reg_lock, flags);
  76. if (gus->gf1.enh_mode) {
  77. address_high = ((address >> 16) & 0x000000f0) | (address & 0x0000000f);
  78. snd_gf1_write16(gus, SNDRV_GF1_GW_DRAM_DMA_LOW, (unsigned short) (address >> 4));
  79. snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_HIGH, (unsigned char) address_high);
  80. } else
  81. snd_gf1_write16(gus, SNDRV_GF1_GW_DRAM_DMA_LOW, (unsigned short) (address >> 4));
  82. snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL, dma_cmd);
  83. spin_unlock_irqrestore(&gus->reg_lock, flags);
  84. }
  85. static struct snd_gf1_dma_block *snd_gf1_dma_next_block(struct snd_gus_card * gus)
  86. {
  87. struct snd_gf1_dma_block *block;
  88. /* PCM block have bigger priority than synthesizer one */
  89. if (gus->gf1.dma_data_pcm) {
  90. block = gus->gf1.dma_data_pcm;
  91. if (gus->gf1.dma_data_pcm_last == block) {
  92. gus->gf1.dma_data_pcm =
  93. gus->gf1.dma_data_pcm_last = NULL;
  94. } else {
  95. gus->gf1.dma_data_pcm = block->next;
  96. }
  97. } else if (gus->gf1.dma_data_synth) {
  98. block = gus->gf1.dma_data_synth;
  99. if (gus->gf1.dma_data_synth_last == block) {
  100. gus->gf1.dma_data_synth =
  101. gus->gf1.dma_data_synth_last = NULL;
  102. } else {
  103. gus->gf1.dma_data_synth = block->next;
  104. }
  105. } else {
  106. block = NULL;
  107. }
  108. if (block) {
  109. gus->gf1.dma_ack = block->ack;
  110. gus->gf1.dma_private_data = block->private_data;
  111. }
  112. return block;
  113. }
  114. static void snd_gf1_dma_interrupt(struct snd_gus_card * gus)
  115. {
  116. struct snd_gf1_dma_block *block;
  117. snd_gf1_dma_ack(gus);
  118. if (gus->gf1.dma_ack)
  119. gus->gf1.dma_ack(gus, gus->gf1.dma_private_data);
  120. spin_lock(&gus->dma_lock);
  121. if (gus->gf1.dma_data_pcm == NULL &&
  122. gus->gf1.dma_data_synth == NULL) {
  123. gus->gf1.dma_ack = NULL;
  124. gus->gf1.dma_flags &= ~SNDRV_GF1_DMA_TRIGGER;
  125. spin_unlock(&gus->dma_lock);
  126. return;
  127. }
  128. block = snd_gf1_dma_next_block(gus);
  129. spin_unlock(&gus->dma_lock);
  130. snd_gf1_dma_program(gus, block->addr, block->buf_addr, block->count, (unsigned short) block->cmd);
  131. kfree(block);
  132. #if 0
  133. printk("program dma (IRQ) - addr = 0x%x, buffer = 0x%lx, count = 0x%x, cmd = 0x%x\n", addr, (long) buffer, count, cmd);
  134. #endif
  135. }
  136. int snd_gf1_dma_init(struct snd_gus_card * gus)
  137. {
  138. mutex_lock(&gus->dma_mutex);
  139. gus->gf1.dma_shared++;
  140. if (gus->gf1.dma_shared > 1) {
  141. mutex_unlock(&gus->dma_mutex);
  142. return 0;
  143. }
  144. gus->gf1.interrupt_handler_dma_write = snd_gf1_dma_interrupt;
  145. gus->gf1.dma_data_pcm =
  146. gus->gf1.dma_data_pcm_last =
  147. gus->gf1.dma_data_synth =
  148. gus->gf1.dma_data_synth_last = NULL;
  149. mutex_unlock(&gus->dma_mutex);
  150. return 0;
  151. }
  152. int snd_gf1_dma_done(struct snd_gus_card * gus)
  153. {
  154. struct snd_gf1_dma_block *block;
  155. mutex_lock(&gus->dma_mutex);
  156. gus->gf1.dma_shared--;
  157. if (!gus->gf1.dma_shared) {
  158. snd_dma_disable(gus->gf1.dma1);
  159. snd_gf1_set_default_handlers(gus, SNDRV_GF1_HANDLER_DMA_WRITE);
  160. snd_gf1_dma_ack(gus);
  161. while ((block = gus->gf1.dma_data_pcm)) {
  162. gus->gf1.dma_data_pcm = block->next;
  163. kfree(block);
  164. }
  165. while ((block = gus->gf1.dma_data_synth)) {
  166. gus->gf1.dma_data_synth = block->next;
  167. kfree(block);
  168. }
  169. gus->gf1.dma_data_pcm_last =
  170. gus->gf1.dma_data_synth_last = NULL;
  171. }
  172. mutex_unlock(&gus->dma_mutex);
  173. return 0;
  174. }
  175. int snd_gf1_dma_transfer_block(struct snd_gus_card * gus,
  176. struct snd_gf1_dma_block * __block,
  177. int atomic,
  178. int synth)
  179. {
  180. unsigned long flags;
  181. struct snd_gf1_dma_block *block;
  182. block = kmalloc(sizeof(*block), atomic ? GFP_ATOMIC : GFP_KERNEL);
  183. if (block == NULL) {
  184. snd_printk(KERN_ERR "gf1: DMA transfer failure; not enough memory\n");
  185. return -ENOMEM;
  186. }
  187. *block = *__block;
  188. block->next = NULL;
  189. #if 0
  190. printk("addr = 0x%x, buffer = 0x%lx, count = 0x%x, cmd = 0x%x\n", block->addr, (long) block->buffer, block->count, block->cmd);
  191. #endif
  192. #if 0
  193. printk("gus->gf1.dma_data_pcm_last = 0x%lx\n", (long)gus->gf1.dma_data_pcm_last);
  194. printk("gus->gf1.dma_data_pcm = 0x%lx\n", (long)gus->gf1.dma_data_pcm);
  195. #endif
  196. spin_lock_irqsave(&gus->dma_lock, flags);
  197. if (synth) {
  198. if (gus->gf1.dma_data_synth_last) {
  199. gus->gf1.dma_data_synth_last->next = block;
  200. gus->gf1.dma_data_synth_last = block;
  201. } else {
  202. gus->gf1.dma_data_synth =
  203. gus->gf1.dma_data_synth_last = block;
  204. }
  205. } else {
  206. if (gus->gf1.dma_data_pcm_last) {
  207. gus->gf1.dma_data_pcm_last->next = block;
  208. gus->gf1.dma_data_pcm_last = block;
  209. } else {
  210. gus->gf1.dma_data_pcm =
  211. gus->gf1.dma_data_pcm_last = block;
  212. }
  213. }
  214. if (!(gus->gf1.dma_flags & SNDRV_GF1_DMA_TRIGGER)) {
  215. gus->gf1.dma_flags |= SNDRV_GF1_DMA_TRIGGER;
  216. block = snd_gf1_dma_next_block(gus);
  217. spin_unlock_irqrestore(&gus->dma_lock, flags);
  218. if (block == NULL)
  219. return 0;
  220. snd_gf1_dma_program(gus, block->addr, block->buf_addr, block->count, (unsigned short) block->cmd);
  221. kfree(block);
  222. return 0;
  223. }
  224. spin_unlock_irqrestore(&gus->dma_lock, flags);
  225. return 0;
  226. }