iTCO_vendor_support.c 8.5 KB

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  1. /*
  2. * intel TCO vendor specific watchdog driver support
  3. *
  4. * (c) Copyright 2006-2008 Wim Van Sebroeck <wim@iguana.be>.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. *
  11. * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
  12. * provide warranty for any of this software. This material is
  13. * provided "AS-IS" and at no charge.
  14. */
  15. /*
  16. * Includes, defines, variables, module parameters, ...
  17. */
  18. /* Module and version information */
  19. #define DRV_NAME "iTCO_vendor_support"
  20. #define DRV_VERSION "1.02"
  21. #define PFX DRV_NAME ": "
  22. /* Includes */
  23. #include <linux/module.h> /* For module specific items */
  24. #include <linux/moduleparam.h> /* For new moduleparam's */
  25. #include <linux/types.h> /* For standard types (like size_t) */
  26. #include <linux/errno.h> /* For the -ENODEV/... values */
  27. #include <linux/kernel.h> /* For printk/panic/... */
  28. #include <linux/init.h> /* For __init/__exit/... */
  29. #include <linux/ioport.h> /* For io-port access */
  30. #include <linux/io.h> /* For inb/outb/... */
  31. #include "iTCO_vendor.h"
  32. /* iTCO defines */
  33. #define SMI_EN acpibase + 0x30 /* SMI Control and Enable Register */
  34. #define TCOBASE acpibase + 0x60 /* TCO base address */
  35. #define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */
  36. /* List of vendor support modes */
  37. /* SuperMicro Pentium 3 Era 370SSE+-OEM1/P3TSSE */
  38. #define SUPERMICRO_OLD_BOARD 1
  39. /* SuperMicro Pentium 4 / Xeon 4 / EMT64T Era Systems */
  40. #define SUPERMICRO_NEW_BOARD 2
  41. static int vendorsupport;
  42. module_param(vendorsupport, int, 0);
  43. MODULE_PARM_DESC(vendorsupport, "iTCO vendor specific support mode, default=0 (none), 1=SuperMicro Pent3, 2=SuperMicro Pent4+");
  44. /*
  45. * Vendor Specific Support
  46. */
  47. /*
  48. * Vendor Support: 1
  49. * Board: Super Micro Computer Inc. 370SSE+-OEM1/P3TSSE
  50. * iTCO chipset: ICH2
  51. *
  52. * Code contributed by: R. Seretny <lkpatches@paypc.com>
  53. * Documentation obtained by R. Seretny from SuperMicro Technical Support
  54. *
  55. * To enable Watchdog function:
  56. * BIOS setup -> Power -> TCO Logic SMI Enable -> Within5Minutes
  57. * This setting enables SMI to clear the watchdog expired flag.
  58. * If BIOS or CPU fail which may cause SMI hang, then system will
  59. * reboot. When application starts to use watchdog function,
  60. * application has to take over the control from SMI.
  61. *
  62. * For P3TSSE, J36 jumper needs to be removed to enable the Watchdog
  63. * function.
  64. *
  65. * Note: The system will reboot when Expire Flag is set TWICE.
  66. * So, if the watchdog timer is 20 seconds, then the maximum hang
  67. * time is about 40 seconds, and the minimum hang time is about
  68. * 20.6 seconds.
  69. */
  70. static void supermicro_old_pre_keepalive(unsigned long acpibase)
  71. {
  72. /* Reload TCO Timer (done in iTCO_wdt_keepalive) + */
  73. /* Clear "Expire Flag" (Bit 3 of TC01_STS register) */
  74. outb(0x08, TCO1_STS);
  75. }
  76. /*
  77. * Vendor Support: 2
  78. * Board: Super Micro Computer Inc. P4SBx, P4DPx
  79. * iTCO chipset: ICH4
  80. *
  81. * Code contributed by: R. Seretny <lkpatches@paypc.com>
  82. * Documentation obtained by R. Seretny from SuperMicro Technical Support
  83. *
  84. * To enable Watchdog function:
  85. * 1. BIOS
  86. * For P4SBx:
  87. * BIOS setup -> Advanced -> Integrated Peripherals -> Watch Dog Feature
  88. * For P4DPx:
  89. * BIOS setup -> Advanced -> I/O Device Configuration -> Watch Dog
  90. * This setting enables or disables Watchdog function. When enabled, the
  91. * default watchdog timer is set to be 5 minutes (about 4m35s). It is
  92. * enough to load and run the OS. The application (service or driver) has
  93. * to take over the control once OS is running up and before watchdog
  94. * expires.
  95. *
  96. * 2. JUMPER
  97. * For P4SBx: JP39
  98. * For P4DPx: JP37
  99. * This jumper is used for safety. Closed is enabled. This jumper
  100. * prevents user enables watchdog in BIOS by accident.
  101. *
  102. * To enable Watch Dog function, both BIOS and JUMPER must be enabled.
  103. *
  104. * The documentation lists motherboards P4SBx and P4DPx series as of
  105. * 20-March-2002. However, this code works flawlessly with much newer
  106. * motherboards, such as my X6DHR-8G2 (SuperServer 6014H-82).
  107. *
  108. * The original iTCO driver as written does not actually reset the
  109. * watchdog timer on these machines, as a result they reboot after five
  110. * minutes.
  111. *
  112. * NOTE: You may leave the Watchdog function disabled in the SuperMicro
  113. * BIOS to avoid a "boot-race"... This driver will enable watchdog
  114. * functionality even if it's disabled in the BIOS once the /dev/watchdog
  115. * file is opened.
  116. */
  117. /* I/O Port's */
  118. #define SM_REGINDEX 0x2e /* SuperMicro ICH4+ Register Index */
  119. #define SM_DATAIO 0x2f /* SuperMicro ICH4+ Register Data I/O */
  120. /* Control Register's */
  121. #define SM_CTLPAGESW 0x07 /* SuperMicro ICH4+ Control Page Switch */
  122. #define SM_CTLPAGE 0x08 /* SuperMicro ICH4+ Control Page Num */
  123. #define SM_WATCHENABLE 0x30 /* Watchdog enable: Bit 0: 0=off, 1=on */
  124. #define SM_WATCHPAGE 0x87 /* Watchdog unlock control page */
  125. #define SM_ENDWATCH 0xAA /* Watchdog lock control page */
  126. #define SM_COUNTMODE 0xf5 /* Watchdog count mode select */
  127. /* (Bit 3: 0 = seconds, 1 = minutes */
  128. #define SM_WATCHTIMER 0xf6 /* 8-bits, Watchdog timer counter (RW) */
  129. #define SM_RESETCONTROL 0xf7 /* Watchdog reset control */
  130. /* Bit 6: timer is reset by kbd interrupt */
  131. /* Bit 7: timer is reset by mouse interrupt */
  132. static void supermicro_new_unlock_watchdog(void)
  133. {
  134. /* Write 0x87 to port 0x2e twice */
  135. outb(SM_WATCHPAGE, SM_REGINDEX);
  136. outb(SM_WATCHPAGE, SM_REGINDEX);
  137. /* Switch to watchdog control page */
  138. outb(SM_CTLPAGESW, SM_REGINDEX);
  139. outb(SM_CTLPAGE, SM_DATAIO);
  140. }
  141. static void supermicro_new_lock_watchdog(void)
  142. {
  143. outb(SM_ENDWATCH, SM_REGINDEX);
  144. }
  145. static void supermicro_new_pre_start(unsigned int heartbeat)
  146. {
  147. unsigned int val;
  148. supermicro_new_unlock_watchdog();
  149. /* Watchdog timer setting needs to be in seconds*/
  150. outb(SM_COUNTMODE, SM_REGINDEX);
  151. val = inb(SM_DATAIO);
  152. val &= 0xF7;
  153. outb(val, SM_DATAIO);
  154. /* Write heartbeat interval to WDOG */
  155. outb(SM_WATCHTIMER, SM_REGINDEX);
  156. outb((heartbeat & 255), SM_DATAIO);
  157. /* Make sure keyboard/mouse interrupts don't interfere */
  158. outb(SM_RESETCONTROL, SM_REGINDEX);
  159. val = inb(SM_DATAIO);
  160. val &= 0x3f;
  161. outb(val, SM_DATAIO);
  162. /* enable watchdog by setting bit 0 of Watchdog Enable to 1 */
  163. outb(SM_WATCHENABLE, SM_REGINDEX);
  164. val = inb(SM_DATAIO);
  165. val |= 0x01;
  166. outb(val, SM_DATAIO);
  167. supermicro_new_lock_watchdog();
  168. }
  169. static void supermicro_new_pre_stop(void)
  170. {
  171. unsigned int val;
  172. supermicro_new_unlock_watchdog();
  173. /* disable watchdog by setting bit 0 of Watchdog Enable to 0 */
  174. outb(SM_WATCHENABLE, SM_REGINDEX);
  175. val = inb(SM_DATAIO);
  176. val &= 0xFE;
  177. outb(val, SM_DATAIO);
  178. supermicro_new_lock_watchdog();
  179. }
  180. static void supermicro_new_pre_set_heartbeat(unsigned int heartbeat)
  181. {
  182. supermicro_new_unlock_watchdog();
  183. /* reset watchdog timeout to heartveat value */
  184. outb(SM_WATCHTIMER, SM_REGINDEX);
  185. outb((heartbeat & 255), SM_DATAIO);
  186. supermicro_new_lock_watchdog();
  187. }
  188. /*
  189. * Generic Support Functions
  190. */
  191. void iTCO_vendor_pre_start(unsigned long acpibase,
  192. unsigned int heartbeat)
  193. {
  194. if (vendorsupport == SUPERMICRO_NEW_BOARD)
  195. supermicro_new_pre_start(heartbeat);
  196. }
  197. EXPORT_SYMBOL(iTCO_vendor_pre_start);
  198. void iTCO_vendor_pre_stop(unsigned long acpibase)
  199. {
  200. if (vendorsupport == SUPERMICRO_NEW_BOARD)
  201. supermicro_new_pre_stop();
  202. }
  203. EXPORT_SYMBOL(iTCO_vendor_pre_stop);
  204. void iTCO_vendor_pre_keepalive(unsigned long acpibase, unsigned int heartbeat)
  205. {
  206. if (vendorsupport == SUPERMICRO_OLD_BOARD)
  207. supermicro_old_pre_keepalive(acpibase);
  208. else if (vendorsupport == SUPERMICRO_NEW_BOARD)
  209. supermicro_new_pre_set_heartbeat(heartbeat);
  210. }
  211. EXPORT_SYMBOL(iTCO_vendor_pre_keepalive);
  212. void iTCO_vendor_pre_set_heartbeat(unsigned int heartbeat)
  213. {
  214. if (vendorsupport == SUPERMICRO_NEW_BOARD)
  215. supermicro_new_pre_set_heartbeat(heartbeat);
  216. }
  217. EXPORT_SYMBOL(iTCO_vendor_pre_set_heartbeat);
  218. int iTCO_vendor_check_noreboot_on(void)
  219. {
  220. switch (vendorsupport) {
  221. case SUPERMICRO_OLD_BOARD:
  222. return 0;
  223. default:
  224. return 1;
  225. }
  226. }
  227. EXPORT_SYMBOL(iTCO_vendor_check_noreboot_on);
  228. static int __init iTCO_vendor_init_module(void)
  229. {
  230. printk(KERN_INFO PFX "vendor-support=%d\n", vendorsupport);
  231. return 0;
  232. }
  233. static void __exit iTCO_vendor_exit_module(void)
  234. {
  235. printk(KERN_INFO PFX "Module Unloaded\n");
  236. }
  237. module_init(iTCO_vendor_init_module);
  238. module_exit(iTCO_vendor_exit_module);
  239. MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>, R. Seretny <lkpatches@paypc.com>");
  240. MODULE_DESCRIPTION("Intel TCO Vendor Specific WatchDog Timer Driver Support");
  241. MODULE_VERSION(DRV_VERSION);
  242. MODULE_LICENSE("GPL");