mpc52xx_uart.c 34 KB

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  1. /*
  2. * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
  3. *
  4. * FIXME According to the usermanual the status bits in the status register
  5. * are only updated when the peripherals access the FIFO and not when the
  6. * CPU access them. So since we use this bits to know when we stop writing
  7. * and reading, they may not be updated in-time and a race condition may
  8. * exists. But I haven't be able to prove this and I don't care. But if
  9. * any problem arises, it might worth checking. The TX/RX FIFO Stats
  10. * registers should be used in addition.
  11. * Update: Actually, they seem updated ... At least the bits we use.
  12. *
  13. *
  14. * Maintainer : Sylvain Munaut <tnt@246tNt.com>
  15. *
  16. * Some of the code has been inspired/copied from the 2.4 code written
  17. * by Dale Farnsworth <dfarnsworth@mvista.com>.
  18. *
  19. * Copyright (C) 2008 Freescale Semiconductor Inc.
  20. * John Rigby <jrigby@gmail.com>
  21. * Added support for MPC5121
  22. * Copyright (C) 2006 Secret Lab Technologies Ltd.
  23. * Grant Likely <grant.likely@secretlab.ca>
  24. * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com>
  25. * Copyright (C) 2003 MontaVista, Software, Inc.
  26. *
  27. * This file is licensed under the terms of the GNU General Public License
  28. * version 2. This program is licensed "as is" without any warranty of any
  29. * kind, whether express or implied.
  30. */
  31. /* Platform device Usage :
  32. *
  33. * Since PSCs can have multiple function, the correct driver for each one
  34. * is selected by calling mpc52xx_match_psc_function(...). The function
  35. * handled by this driver is "uart".
  36. *
  37. * The driver init all necessary registers to place the PSC in uart mode without
  38. * DCD. However, the pin multiplexing aren't changed and should be set either
  39. * by the bootloader or in the platform init code.
  40. *
  41. * The idx field must be equal to the PSC index (e.g. 0 for PSC1, 1 for PSC2,
  42. * and so on). So the PSC1 is mapped to /dev/ttyPSC0, PSC2 to /dev/ttyPSC1 and
  43. * so on. But be warned, it's an ABSOLUTE REQUIREMENT ! This is needed mainly
  44. * fpr the console code : without this 1:1 mapping, at early boot time, when we
  45. * are parsing the kernel args console=ttyPSC?, we wouldn't know which PSC it
  46. * will be mapped to.
  47. */
  48. /* OF Platform device Usage :
  49. *
  50. * This driver is only used for PSCs configured in uart mode. The device
  51. * tree will have a node for each PSC in uart mode w/ device_type = "serial"
  52. * and "mpc52xx-psc-uart" in the compatible string
  53. *
  54. * By default, PSC devices are enumerated in the order they are found. However
  55. * a particular PSC number can be forces by adding 'device_no = <port#>'
  56. * to the device node.
  57. *
  58. * The driver init all necessary registers to place the PSC in uart mode without
  59. * DCD. However, the pin multiplexing aren't changed and should be set either
  60. * by the bootloader or in the platform init code.
  61. */
  62. #undef DEBUG
  63. #include <linux/device.h>
  64. #include <linux/module.h>
  65. #include <linux/tty.h>
  66. #include <linux/serial.h>
  67. #include <linux/sysrq.h>
  68. #include <linux/console.h>
  69. #include <linux/delay.h>
  70. #include <linux/io.h>
  71. #include <linux/of.h>
  72. #include <linux/of_platform.h>
  73. #include <asm/mpc52xx.h>
  74. #include <asm/mpc512x.h>
  75. #include <asm/mpc52xx_psc.h>
  76. #if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  77. #define SUPPORT_SYSRQ
  78. #endif
  79. #include <linux/serial_core.h>
  80. /* We've been assigned a range on the "Low-density serial ports" major */
  81. #define SERIAL_PSC_MAJOR 204
  82. #define SERIAL_PSC_MINOR 148
  83. #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */
  84. static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
  85. /* Rem: - We use the read_status_mask as a shadow of
  86. * psc->mpc52xx_psc_imr
  87. * - It's important that is array is all zero on start as we
  88. * use it to know if it's initialized or not ! If it's not sure
  89. * it's cleared, then a memset(...,0,...) should be added to
  90. * the console_init
  91. */
  92. /* lookup table for matching device nodes to index numbers */
  93. static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM];
  94. static void mpc52xx_uart_of_enumerate(void);
  95. #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
  96. /* Forward declaration of the interruption handling routine */
  97. static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id);
  98. /* Simple macro to test if a port is console or not. This one is taken
  99. * for serial_core.c and maybe should be moved to serial_core.h ? */
  100. #ifdef CONFIG_SERIAL_CORE_CONSOLE
  101. #define uart_console(port) \
  102. ((port)->cons && (port)->cons->index == (port)->line)
  103. #else
  104. #define uart_console(port) (0)
  105. #endif
  106. /* ======================================================================== */
  107. /* PSC fifo operations for isolating differences between 52xx and 512x */
  108. /* ======================================================================== */
  109. struct psc_ops {
  110. void (*fifo_init)(struct uart_port *port);
  111. int (*raw_rx_rdy)(struct uart_port *port);
  112. int (*raw_tx_rdy)(struct uart_port *port);
  113. int (*rx_rdy)(struct uart_port *port);
  114. int (*tx_rdy)(struct uart_port *port);
  115. int (*tx_empty)(struct uart_port *port);
  116. void (*stop_rx)(struct uart_port *port);
  117. void (*start_tx)(struct uart_port *port);
  118. void (*stop_tx)(struct uart_port *port);
  119. void (*rx_clr_irq)(struct uart_port *port);
  120. void (*tx_clr_irq)(struct uart_port *port);
  121. void (*write_char)(struct uart_port *port, unsigned char c);
  122. unsigned char (*read_char)(struct uart_port *port);
  123. void (*cw_disable_ints)(struct uart_port *port);
  124. void (*cw_restore_ints)(struct uart_port *port);
  125. unsigned long (*getuartclk)(void *p);
  126. };
  127. #ifdef CONFIG_PPC_MPC52xx
  128. #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
  129. static void mpc52xx_psc_fifo_init(struct uart_port *port)
  130. {
  131. struct mpc52xx_psc __iomem *psc = PSC(port);
  132. struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
  133. /* /32 prescaler */
  134. out_be16(&psc->mpc52xx_psc_clock_select, 0xdd00);
  135. out_8(&fifo->rfcntl, 0x00);
  136. out_be16(&fifo->rfalarm, 0x1ff);
  137. out_8(&fifo->tfcntl, 0x07);
  138. out_be16(&fifo->tfalarm, 0x80);
  139. port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
  140. out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
  141. }
  142. static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port)
  143. {
  144. return in_be16(&PSC(port)->mpc52xx_psc_status)
  145. & MPC52xx_PSC_SR_RXRDY;
  146. }
  147. static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port)
  148. {
  149. return in_be16(&PSC(port)->mpc52xx_psc_status)
  150. & MPC52xx_PSC_SR_TXRDY;
  151. }
  152. static int mpc52xx_psc_rx_rdy(struct uart_port *port)
  153. {
  154. return in_be16(&PSC(port)->mpc52xx_psc_isr)
  155. & port->read_status_mask
  156. & MPC52xx_PSC_IMR_RXRDY;
  157. }
  158. static int mpc52xx_psc_tx_rdy(struct uart_port *port)
  159. {
  160. return in_be16(&PSC(port)->mpc52xx_psc_isr)
  161. & port->read_status_mask
  162. & MPC52xx_PSC_IMR_TXRDY;
  163. }
  164. static int mpc52xx_psc_tx_empty(struct uart_port *port)
  165. {
  166. return in_be16(&PSC(port)->mpc52xx_psc_status)
  167. & MPC52xx_PSC_SR_TXEMP;
  168. }
  169. static void mpc52xx_psc_start_tx(struct uart_port *port)
  170. {
  171. port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
  172. out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
  173. }
  174. static void mpc52xx_psc_stop_tx(struct uart_port *port)
  175. {
  176. port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
  177. out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
  178. }
  179. static void mpc52xx_psc_stop_rx(struct uart_port *port)
  180. {
  181. port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
  182. out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
  183. }
  184. static void mpc52xx_psc_rx_clr_irq(struct uart_port *port)
  185. {
  186. }
  187. static void mpc52xx_psc_tx_clr_irq(struct uart_port *port)
  188. {
  189. }
  190. static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c)
  191. {
  192. out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
  193. }
  194. static unsigned char mpc52xx_psc_read_char(struct uart_port *port)
  195. {
  196. return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
  197. }
  198. static void mpc52xx_psc_cw_disable_ints(struct uart_port *port)
  199. {
  200. out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
  201. }
  202. static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
  203. {
  204. out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
  205. }
  206. /* Search for bus-frequency property in this node or a parent */
  207. static unsigned long mpc52xx_getuartclk(void *p)
  208. {
  209. /*
  210. * 5200 UARTs have a / 32 prescaler
  211. * but the generic serial code assumes 16
  212. * so return ipb freq / 2
  213. */
  214. return mpc52xx_find_ipb_freq(p) / 2;
  215. }
  216. static struct psc_ops mpc52xx_psc_ops = {
  217. .fifo_init = mpc52xx_psc_fifo_init,
  218. .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
  219. .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
  220. .rx_rdy = mpc52xx_psc_rx_rdy,
  221. .tx_rdy = mpc52xx_psc_tx_rdy,
  222. .tx_empty = mpc52xx_psc_tx_empty,
  223. .stop_rx = mpc52xx_psc_stop_rx,
  224. .start_tx = mpc52xx_psc_start_tx,
  225. .stop_tx = mpc52xx_psc_stop_tx,
  226. .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
  227. .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
  228. .write_char = mpc52xx_psc_write_char,
  229. .read_char = mpc52xx_psc_read_char,
  230. .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
  231. .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
  232. .getuartclk = mpc52xx_getuartclk,
  233. };
  234. #endif /* CONFIG_MPC52xx */
  235. #ifdef CONFIG_PPC_MPC512x
  236. #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
  237. static void mpc512x_psc_fifo_init(struct uart_port *port)
  238. {
  239. out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
  240. out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
  241. out_be32(&FIFO_512x(port)->txalarm, 1);
  242. out_be32(&FIFO_512x(port)->tximr, 0);
  243. out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
  244. out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
  245. out_be32(&FIFO_512x(port)->rxalarm, 1);
  246. out_be32(&FIFO_512x(port)->rximr, 0);
  247. out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);
  248. out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);
  249. }
  250. static int mpc512x_psc_raw_rx_rdy(struct uart_port *port)
  251. {
  252. return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
  253. }
  254. static int mpc512x_psc_raw_tx_rdy(struct uart_port *port)
  255. {
  256. return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);
  257. }
  258. static int mpc512x_psc_rx_rdy(struct uart_port *port)
  259. {
  260. return in_be32(&FIFO_512x(port)->rxsr)
  261. & in_be32(&FIFO_512x(port)->rximr)
  262. & MPC512x_PSC_FIFO_ALARM;
  263. }
  264. static int mpc512x_psc_tx_rdy(struct uart_port *port)
  265. {
  266. return in_be32(&FIFO_512x(port)->txsr)
  267. & in_be32(&FIFO_512x(port)->tximr)
  268. & MPC512x_PSC_FIFO_ALARM;
  269. }
  270. static int mpc512x_psc_tx_empty(struct uart_port *port)
  271. {
  272. return in_be32(&FIFO_512x(port)->txsr)
  273. & MPC512x_PSC_FIFO_EMPTY;
  274. }
  275. static void mpc512x_psc_stop_rx(struct uart_port *port)
  276. {
  277. unsigned long rx_fifo_imr;
  278. rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);
  279. rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
  280. out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);
  281. }
  282. static void mpc512x_psc_start_tx(struct uart_port *port)
  283. {
  284. unsigned long tx_fifo_imr;
  285. tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
  286. tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
  287. out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
  288. }
  289. static void mpc512x_psc_stop_tx(struct uart_port *port)
  290. {
  291. unsigned long tx_fifo_imr;
  292. tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
  293. tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
  294. out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
  295. }
  296. static void mpc512x_psc_rx_clr_irq(struct uart_port *port)
  297. {
  298. out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));
  299. }
  300. static void mpc512x_psc_tx_clr_irq(struct uart_port *port)
  301. {
  302. out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));
  303. }
  304. static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c)
  305. {
  306. out_8(&FIFO_512x(port)->txdata_8, c);
  307. }
  308. static unsigned char mpc512x_psc_read_char(struct uart_port *port)
  309. {
  310. return in_8(&FIFO_512x(port)->rxdata_8);
  311. }
  312. static void mpc512x_psc_cw_disable_ints(struct uart_port *port)
  313. {
  314. port->read_status_mask =
  315. in_be32(&FIFO_512x(port)->tximr) << 16 |
  316. in_be32(&FIFO_512x(port)->rximr);
  317. out_be32(&FIFO_512x(port)->tximr, 0);
  318. out_be32(&FIFO_512x(port)->rximr, 0);
  319. }
  320. static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
  321. {
  322. out_be32(&FIFO_512x(port)->tximr,
  323. (port->read_status_mask >> 16) & 0x7f);
  324. out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
  325. }
  326. static unsigned long mpc512x_getuartclk(void *p)
  327. {
  328. return mpc512x_find_ips_freq(p);
  329. }
  330. static struct psc_ops mpc512x_psc_ops = {
  331. .fifo_init = mpc512x_psc_fifo_init,
  332. .raw_rx_rdy = mpc512x_psc_raw_rx_rdy,
  333. .raw_tx_rdy = mpc512x_psc_raw_tx_rdy,
  334. .rx_rdy = mpc512x_psc_rx_rdy,
  335. .tx_rdy = mpc512x_psc_tx_rdy,
  336. .tx_empty = mpc512x_psc_tx_empty,
  337. .stop_rx = mpc512x_psc_stop_rx,
  338. .start_tx = mpc512x_psc_start_tx,
  339. .stop_tx = mpc512x_psc_stop_tx,
  340. .rx_clr_irq = mpc512x_psc_rx_clr_irq,
  341. .tx_clr_irq = mpc512x_psc_tx_clr_irq,
  342. .write_char = mpc512x_psc_write_char,
  343. .read_char = mpc512x_psc_read_char,
  344. .cw_disable_ints = mpc512x_psc_cw_disable_ints,
  345. .cw_restore_ints = mpc512x_psc_cw_restore_ints,
  346. .getuartclk = mpc512x_getuartclk,
  347. };
  348. #endif
  349. static struct psc_ops *psc_ops;
  350. /* ======================================================================== */
  351. /* UART operations */
  352. /* ======================================================================== */
  353. static unsigned int
  354. mpc52xx_uart_tx_empty(struct uart_port *port)
  355. {
  356. return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0;
  357. }
  358. static void
  359. mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
  360. {
  361. if (mctrl & TIOCM_RTS)
  362. out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
  363. else
  364. out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
  365. }
  366. static unsigned int
  367. mpc52xx_uart_get_mctrl(struct uart_port *port)
  368. {
  369. unsigned int ret = TIOCM_DSR;
  370. u8 status = in_8(&PSC(port)->mpc52xx_psc_ipcr);
  371. if (!(status & MPC52xx_PSC_CTS))
  372. ret |= TIOCM_CTS;
  373. if (!(status & MPC52xx_PSC_DCD))
  374. ret |= TIOCM_CAR;
  375. return ret;
  376. }
  377. static void
  378. mpc52xx_uart_stop_tx(struct uart_port *port)
  379. {
  380. /* port->lock taken by caller */
  381. psc_ops->stop_tx(port);
  382. }
  383. static void
  384. mpc52xx_uart_start_tx(struct uart_port *port)
  385. {
  386. /* port->lock taken by caller */
  387. psc_ops->start_tx(port);
  388. }
  389. static void
  390. mpc52xx_uart_send_xchar(struct uart_port *port, char ch)
  391. {
  392. unsigned long flags;
  393. spin_lock_irqsave(&port->lock, flags);
  394. port->x_char = ch;
  395. if (ch) {
  396. /* Make sure tx interrupts are on */
  397. /* Truly necessary ??? They should be anyway */
  398. psc_ops->start_tx(port);
  399. }
  400. spin_unlock_irqrestore(&port->lock, flags);
  401. }
  402. static void
  403. mpc52xx_uart_stop_rx(struct uart_port *port)
  404. {
  405. /* port->lock taken by caller */
  406. psc_ops->stop_rx(port);
  407. }
  408. static void
  409. mpc52xx_uart_enable_ms(struct uart_port *port)
  410. {
  411. struct mpc52xx_psc __iomem *psc = PSC(port);
  412. /* clear D_*-bits by reading them */
  413. in_8(&psc->mpc52xx_psc_ipcr);
  414. /* enable CTS and DCD as IPC interrupts */
  415. out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
  416. port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
  417. out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
  418. }
  419. static void
  420. mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
  421. {
  422. unsigned long flags;
  423. spin_lock_irqsave(&port->lock, flags);
  424. if (ctl == -1)
  425. out_8(&PSC(port)->command, MPC52xx_PSC_START_BRK);
  426. else
  427. out_8(&PSC(port)->command, MPC52xx_PSC_STOP_BRK);
  428. spin_unlock_irqrestore(&port->lock, flags);
  429. }
  430. static int
  431. mpc52xx_uart_startup(struct uart_port *port)
  432. {
  433. struct mpc52xx_psc __iomem *psc = PSC(port);
  434. int ret;
  435. /* Request IRQ */
  436. ret = request_irq(port->irq, mpc52xx_uart_int,
  437. IRQF_DISABLED | IRQF_SAMPLE_RANDOM | IRQF_SHARED,
  438. "mpc52xx_psc_uart", port);
  439. if (ret)
  440. return ret;
  441. /* Reset/activate the port, clear and enable interrupts */
  442. out_8(&psc->command, MPC52xx_PSC_RST_RX);
  443. out_8(&psc->command, MPC52xx_PSC_RST_TX);
  444. out_be32(&psc->sicr, 0); /* UART mode DCD ignored */
  445. psc_ops->fifo_init(port);
  446. out_8(&psc->command, MPC52xx_PSC_TX_ENABLE);
  447. out_8(&psc->command, MPC52xx_PSC_RX_ENABLE);
  448. return 0;
  449. }
  450. static void
  451. mpc52xx_uart_shutdown(struct uart_port *port)
  452. {
  453. struct mpc52xx_psc __iomem *psc = PSC(port);
  454. /* Shut down the port. Leave TX active if on a console port */
  455. out_8(&psc->command, MPC52xx_PSC_RST_RX);
  456. if (!uart_console(port))
  457. out_8(&psc->command, MPC52xx_PSC_RST_TX);
  458. port->read_status_mask = 0;
  459. out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
  460. /* Release interrupt */
  461. free_irq(port->irq, port);
  462. }
  463. static void
  464. mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
  465. struct ktermios *old)
  466. {
  467. struct mpc52xx_psc __iomem *psc = PSC(port);
  468. unsigned long flags;
  469. unsigned char mr1, mr2;
  470. unsigned short ctr;
  471. unsigned int j, baud, quot;
  472. /* Prepare what we're gonna write */
  473. mr1 = 0;
  474. switch (new->c_cflag & CSIZE) {
  475. case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS;
  476. break;
  477. case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS;
  478. break;
  479. case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS;
  480. break;
  481. case CS8:
  482. default: mr1 |= MPC52xx_PSC_MODE_8_BITS;
  483. }
  484. if (new->c_cflag & PARENB) {
  485. mr1 |= (new->c_cflag & PARODD) ?
  486. MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
  487. } else
  488. mr1 |= MPC52xx_PSC_MODE_PARNONE;
  489. mr2 = 0;
  490. if (new->c_cflag & CSTOPB)
  491. mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
  492. else
  493. mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
  494. MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
  495. MPC52xx_PSC_MODE_ONE_STOP;
  496. if (new->c_cflag & CRTSCTS) {
  497. mr1 |= MPC52xx_PSC_MODE_RXRTS;
  498. mr2 |= MPC52xx_PSC_MODE_TXCTS;
  499. }
  500. baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16);
  501. quot = uart_get_divisor(port, baud);
  502. ctr = quot & 0xffff;
  503. /* Get the lock */
  504. spin_lock_irqsave(&port->lock, flags);
  505. /* Update the per-port timeout */
  506. uart_update_timeout(port, new->c_cflag, baud);
  507. /* Do our best to flush TX & RX, so we don't lose anything */
  508. /* But we don't wait indefinitely ! */
  509. j = 5000000; /* Maximum wait */
  510. /* FIXME Can't receive chars since set_termios might be called at early
  511. * boot for the console, all stuff is not yet ready to receive at that
  512. * time and that just makes the kernel oops */
  513. /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
  514. while (!mpc52xx_uart_tx_empty(port) && --j)
  515. udelay(1);
  516. if (!j)
  517. printk(KERN_ERR "mpc52xx_uart.c: "
  518. "Unable to flush RX & TX fifos in-time in set_termios."
  519. "Some chars may have been lost.\n");
  520. /* Reset the TX & RX */
  521. out_8(&psc->command, MPC52xx_PSC_RST_RX);
  522. out_8(&psc->command, MPC52xx_PSC_RST_TX);
  523. /* Send new mode settings */
  524. out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
  525. out_8(&psc->mode, mr1);
  526. out_8(&psc->mode, mr2);
  527. out_8(&psc->ctur, ctr >> 8);
  528. out_8(&psc->ctlr, ctr & 0xff);
  529. if (UART_ENABLE_MS(port, new->c_cflag))
  530. mpc52xx_uart_enable_ms(port);
  531. /* Reenable TX & RX */
  532. out_8(&psc->command, MPC52xx_PSC_TX_ENABLE);
  533. out_8(&psc->command, MPC52xx_PSC_RX_ENABLE);
  534. /* We're all set, release the lock */
  535. spin_unlock_irqrestore(&port->lock, flags);
  536. }
  537. static const char *
  538. mpc52xx_uart_type(struct uart_port *port)
  539. {
  540. return port->type == PORT_MPC52xx ? "MPC52xx PSC" : NULL;
  541. }
  542. static void
  543. mpc52xx_uart_release_port(struct uart_port *port)
  544. {
  545. /* remapped by us ? */
  546. if (port->flags & UPF_IOREMAP) {
  547. iounmap(port->membase);
  548. port->membase = NULL;
  549. }
  550. release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
  551. }
  552. static int
  553. mpc52xx_uart_request_port(struct uart_port *port)
  554. {
  555. int err;
  556. if (port->flags & UPF_IOREMAP) /* Need to remap ? */
  557. port->membase = ioremap(port->mapbase,
  558. sizeof(struct mpc52xx_psc));
  559. if (!port->membase)
  560. return -EINVAL;
  561. err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
  562. "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
  563. if (err && (port->flags & UPF_IOREMAP)) {
  564. iounmap(port->membase);
  565. port->membase = NULL;
  566. }
  567. return err;
  568. }
  569. static void
  570. mpc52xx_uart_config_port(struct uart_port *port, int flags)
  571. {
  572. if ((flags & UART_CONFIG_TYPE)
  573. && (mpc52xx_uart_request_port(port) == 0))
  574. port->type = PORT_MPC52xx;
  575. }
  576. static int
  577. mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
  578. {
  579. if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx)
  580. return -EINVAL;
  581. if ((ser->irq != port->irq) ||
  582. (ser->io_type != SERIAL_IO_MEM) ||
  583. (ser->baud_base != port->uartclk) ||
  584. (ser->iomem_base != (void *)port->mapbase) ||
  585. (ser->hub6 != 0))
  586. return -EINVAL;
  587. return 0;
  588. }
  589. static struct uart_ops mpc52xx_uart_ops = {
  590. .tx_empty = mpc52xx_uart_tx_empty,
  591. .set_mctrl = mpc52xx_uart_set_mctrl,
  592. .get_mctrl = mpc52xx_uart_get_mctrl,
  593. .stop_tx = mpc52xx_uart_stop_tx,
  594. .start_tx = mpc52xx_uart_start_tx,
  595. .send_xchar = mpc52xx_uart_send_xchar,
  596. .stop_rx = mpc52xx_uart_stop_rx,
  597. .enable_ms = mpc52xx_uart_enable_ms,
  598. .break_ctl = mpc52xx_uart_break_ctl,
  599. .startup = mpc52xx_uart_startup,
  600. .shutdown = mpc52xx_uart_shutdown,
  601. .set_termios = mpc52xx_uart_set_termios,
  602. /* .pm = mpc52xx_uart_pm, Not supported yet */
  603. /* .set_wake = mpc52xx_uart_set_wake, Not supported yet */
  604. .type = mpc52xx_uart_type,
  605. .release_port = mpc52xx_uart_release_port,
  606. .request_port = mpc52xx_uart_request_port,
  607. .config_port = mpc52xx_uart_config_port,
  608. .verify_port = mpc52xx_uart_verify_port
  609. };
  610. /* ======================================================================== */
  611. /* Interrupt handling */
  612. /* ======================================================================== */
  613. static inline int
  614. mpc52xx_uart_int_rx_chars(struct uart_port *port)
  615. {
  616. struct tty_struct *tty = port->info->port.tty;
  617. unsigned char ch, flag;
  618. unsigned short status;
  619. /* While we can read, do so ! */
  620. while (psc_ops->raw_rx_rdy(port)) {
  621. /* Get the char */
  622. ch = psc_ops->read_char(port);
  623. /* Handle sysreq char */
  624. #ifdef SUPPORT_SYSRQ
  625. if (uart_handle_sysrq_char(port, ch)) {
  626. port->sysrq = 0;
  627. continue;
  628. }
  629. #endif
  630. /* Store it */
  631. flag = TTY_NORMAL;
  632. port->icount.rx++;
  633. status = in_be16(&PSC(port)->mpc52xx_psc_status);
  634. if (status & (MPC52xx_PSC_SR_PE |
  635. MPC52xx_PSC_SR_FE |
  636. MPC52xx_PSC_SR_RB)) {
  637. if (status & MPC52xx_PSC_SR_RB) {
  638. flag = TTY_BREAK;
  639. uart_handle_break(port);
  640. port->icount.brk++;
  641. } else if (status & MPC52xx_PSC_SR_PE) {
  642. flag = TTY_PARITY;
  643. port->icount.parity++;
  644. }
  645. else if (status & MPC52xx_PSC_SR_FE) {
  646. flag = TTY_FRAME;
  647. port->icount.frame++;
  648. }
  649. /* Clear error condition */
  650. out_8(&PSC(port)->command, MPC52xx_PSC_RST_ERR_STAT);
  651. }
  652. tty_insert_flip_char(tty, ch, flag);
  653. if (status & MPC52xx_PSC_SR_OE) {
  654. /*
  655. * Overrun is special, since it's
  656. * reported immediately, and doesn't
  657. * affect the current character
  658. */
  659. tty_insert_flip_char(tty, 0, TTY_OVERRUN);
  660. port->icount.overrun++;
  661. }
  662. }
  663. spin_unlock(&port->lock);
  664. tty_flip_buffer_push(tty);
  665. spin_lock(&port->lock);
  666. return psc_ops->raw_rx_rdy(port);
  667. }
  668. static inline int
  669. mpc52xx_uart_int_tx_chars(struct uart_port *port)
  670. {
  671. struct circ_buf *xmit = &port->info->xmit;
  672. /* Process out of band chars */
  673. if (port->x_char) {
  674. psc_ops->write_char(port, port->x_char);
  675. port->icount.tx++;
  676. port->x_char = 0;
  677. return 1;
  678. }
  679. /* Nothing to do ? */
  680. if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
  681. mpc52xx_uart_stop_tx(port);
  682. return 0;
  683. }
  684. /* Send chars */
  685. while (psc_ops->raw_tx_rdy(port)) {
  686. psc_ops->write_char(port, xmit->buf[xmit->tail]);
  687. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  688. port->icount.tx++;
  689. if (uart_circ_empty(xmit))
  690. break;
  691. }
  692. /* Wake up */
  693. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  694. uart_write_wakeup(port);
  695. /* Maybe we're done after all */
  696. if (uart_circ_empty(xmit)) {
  697. mpc52xx_uart_stop_tx(port);
  698. return 0;
  699. }
  700. return 1;
  701. }
  702. static irqreturn_t
  703. mpc52xx_uart_int(int irq, void *dev_id)
  704. {
  705. struct uart_port *port = dev_id;
  706. unsigned long pass = ISR_PASS_LIMIT;
  707. unsigned int keepgoing;
  708. u8 status;
  709. spin_lock(&port->lock);
  710. /* While we have stuff to do, we continue */
  711. do {
  712. /* If we don't find anything to do, we stop */
  713. keepgoing = 0;
  714. psc_ops->rx_clr_irq(port);
  715. if (psc_ops->rx_rdy(port))
  716. keepgoing |= mpc52xx_uart_int_rx_chars(port);
  717. psc_ops->tx_clr_irq(port);
  718. if (psc_ops->tx_rdy(port))
  719. keepgoing |= mpc52xx_uart_int_tx_chars(port);
  720. status = in_8(&PSC(port)->mpc52xx_psc_ipcr);
  721. if (status & MPC52xx_PSC_D_DCD)
  722. uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD));
  723. if (status & MPC52xx_PSC_D_CTS)
  724. uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS));
  725. /* Limit number of iteration */
  726. if (!(--pass))
  727. keepgoing = 0;
  728. } while (keepgoing);
  729. spin_unlock(&port->lock);
  730. return IRQ_HANDLED;
  731. }
  732. /* ======================================================================== */
  733. /* Console ( if applicable ) */
  734. /* ======================================================================== */
  735. #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
  736. static void __init
  737. mpc52xx_console_get_options(struct uart_port *port,
  738. int *baud, int *parity, int *bits, int *flow)
  739. {
  740. struct mpc52xx_psc __iomem *psc = PSC(port);
  741. unsigned char mr1;
  742. pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
  743. /* Read the mode registers */
  744. out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
  745. mr1 = in_8(&psc->mode);
  746. /* CT{U,L}R are write-only ! */
  747. *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
  748. /* Parse them */
  749. switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
  750. case MPC52xx_PSC_MODE_5_BITS:
  751. *bits = 5;
  752. break;
  753. case MPC52xx_PSC_MODE_6_BITS:
  754. *bits = 6;
  755. break;
  756. case MPC52xx_PSC_MODE_7_BITS:
  757. *bits = 7;
  758. break;
  759. case MPC52xx_PSC_MODE_8_BITS:
  760. default:
  761. *bits = 8;
  762. }
  763. if (mr1 & MPC52xx_PSC_MODE_PARNONE)
  764. *parity = 'n';
  765. else
  766. *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
  767. }
  768. static void
  769. mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
  770. {
  771. struct uart_port *port = &mpc52xx_uart_ports[co->index];
  772. unsigned int i, j;
  773. /* Disable interrupts */
  774. psc_ops->cw_disable_ints(port);
  775. /* Wait the TX buffer to be empty */
  776. j = 5000000; /* Maximum wait */
  777. while (!mpc52xx_uart_tx_empty(port) && --j)
  778. udelay(1);
  779. /* Write all the chars */
  780. for (i = 0; i < count; i++, s++) {
  781. /* Line return handling */
  782. if (*s == '\n')
  783. psc_ops->write_char(port, '\r');
  784. /* Send the char */
  785. psc_ops->write_char(port, *s);
  786. /* Wait the TX buffer to be empty */
  787. j = 20000; /* Maximum wait */
  788. while (!mpc52xx_uart_tx_empty(port) && --j)
  789. udelay(1);
  790. }
  791. /* Restore interrupt state */
  792. psc_ops->cw_restore_ints(port);
  793. }
  794. static int __init
  795. mpc52xx_console_setup(struct console *co, char *options)
  796. {
  797. struct uart_port *port = &mpc52xx_uart_ports[co->index];
  798. struct device_node *np = mpc52xx_uart_nodes[co->index];
  799. unsigned int uartclk;
  800. struct resource res;
  801. int ret;
  802. int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
  803. int bits = 8;
  804. int parity = 'n';
  805. int flow = 'n';
  806. pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n",
  807. co, co->index, options);
  808. if ((co->index < 0) || (co->index > MPC52xx_PSC_MAXNUM)) {
  809. pr_debug("PSC%x out of range\n", co->index);
  810. return -EINVAL;
  811. }
  812. if (!np) {
  813. pr_debug("PSC%x not found in device tree\n", co->index);
  814. return -EINVAL;
  815. }
  816. pr_debug("Console on ttyPSC%x is %s\n",
  817. co->index, mpc52xx_uart_nodes[co->index]->full_name);
  818. /* Fetch register locations */
  819. ret = of_address_to_resource(np, 0, &res);
  820. if (ret) {
  821. pr_debug("Could not get resources for PSC%x\n", co->index);
  822. return ret;
  823. }
  824. uartclk = psc_ops->getuartclk(np);
  825. if (uartclk == 0) {
  826. pr_debug("Could not find uart clock frequency!\n");
  827. return -EINVAL;
  828. }
  829. /* Basic port init. Needed since we use some uart_??? func before
  830. * real init for early access */
  831. spin_lock_init(&port->lock);
  832. port->uartclk = uartclk;
  833. port->ops = &mpc52xx_uart_ops;
  834. port->mapbase = res.start;
  835. port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc));
  836. port->irq = irq_of_parse_and_map(np, 0);
  837. if (port->membase == NULL)
  838. return -EINVAL;
  839. pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n",
  840. (void *)port->mapbase, port->membase,
  841. port->irq, port->uartclk);
  842. /* Setup the port parameters accoding to options */
  843. if (options)
  844. uart_parse_options(options, &baud, &parity, &bits, &flow);
  845. else
  846. mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
  847. pr_debug("Setting console parameters: %i %i%c1 flow=%c\n",
  848. baud, bits, parity, flow);
  849. return uart_set_options(port, co, baud, parity, bits, flow);
  850. }
  851. static struct uart_driver mpc52xx_uart_driver;
  852. static struct console mpc52xx_console = {
  853. .name = "ttyPSC",
  854. .write = mpc52xx_console_write,
  855. .device = uart_console_device,
  856. .setup = mpc52xx_console_setup,
  857. .flags = CON_PRINTBUFFER,
  858. .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */
  859. .data = &mpc52xx_uart_driver,
  860. };
  861. static int __init
  862. mpc52xx_console_init(void)
  863. {
  864. mpc52xx_uart_of_enumerate();
  865. register_console(&mpc52xx_console);
  866. return 0;
  867. }
  868. console_initcall(mpc52xx_console_init);
  869. #define MPC52xx_PSC_CONSOLE &mpc52xx_console
  870. #else
  871. #define MPC52xx_PSC_CONSOLE NULL
  872. #endif
  873. /* ======================================================================== */
  874. /* UART Driver */
  875. /* ======================================================================== */
  876. static struct uart_driver mpc52xx_uart_driver = {
  877. .driver_name = "mpc52xx_psc_uart",
  878. .dev_name = "ttyPSC",
  879. .major = SERIAL_PSC_MAJOR,
  880. .minor = SERIAL_PSC_MINOR,
  881. .nr = MPC52xx_PSC_MAXNUM,
  882. .cons = MPC52xx_PSC_CONSOLE,
  883. };
  884. /* ======================================================================== */
  885. /* OF Platform Driver */
  886. /* ======================================================================== */
  887. static struct of_device_id mpc52xx_uart_of_match[] = {
  888. #ifdef CONFIG_PPC_MPC52xx
  889. { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
  890. /* binding used by old lite5200 device trees: */
  891. { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
  892. /* binding used by efika: */
  893. { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, },
  894. #endif
  895. #ifdef CONFIG_PPC_MPC512x
  896. { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
  897. #endif
  898. {},
  899. };
  900. static int __devinit
  901. mpc52xx_uart_of_probe(struct of_device *op, const struct of_device_id *match)
  902. {
  903. int idx = -1;
  904. unsigned int uartclk;
  905. struct uart_port *port = NULL;
  906. struct resource res;
  907. int ret;
  908. dev_dbg(&op->dev, "mpc52xx_uart_probe(op=%p, match=%p)\n", op, match);
  909. /* Check validity & presence */
  910. for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++)
  911. if (mpc52xx_uart_nodes[idx] == op->node)
  912. break;
  913. if (idx >= MPC52xx_PSC_MAXNUM)
  914. return -EINVAL;
  915. pr_debug("Found %s assigned to ttyPSC%x\n",
  916. mpc52xx_uart_nodes[idx]->full_name, idx);
  917. uartclk = psc_ops->getuartclk(op->node);
  918. if (uartclk == 0) {
  919. dev_dbg(&op->dev, "Could not find uart clock frequency!\n");
  920. return -EINVAL;
  921. }
  922. /* Init the port structure */
  923. port = &mpc52xx_uart_ports[idx];
  924. spin_lock_init(&port->lock);
  925. port->uartclk = uartclk;
  926. port->fifosize = 512;
  927. port->iotype = UPIO_MEM;
  928. port->flags = UPF_BOOT_AUTOCONF |
  929. (uart_console(port) ? 0 : UPF_IOREMAP);
  930. port->line = idx;
  931. port->ops = &mpc52xx_uart_ops;
  932. port->dev = &op->dev;
  933. /* Search for IRQ and mapbase */
  934. ret = of_address_to_resource(op->node, 0, &res);
  935. if (ret)
  936. return ret;
  937. port->mapbase = res.start;
  938. if (!port->mapbase) {
  939. dev_dbg(&op->dev, "Could not allocate resources for PSC\n");
  940. return -EINVAL;
  941. }
  942. port->irq = irq_of_parse_and_map(op->node, 0);
  943. if (port->irq == NO_IRQ) {
  944. dev_dbg(&op->dev, "Could not get irq\n");
  945. return -EINVAL;
  946. }
  947. dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n",
  948. (void *)port->mapbase, port->irq, port->uartclk);
  949. /* Add the port to the uart sub-system */
  950. ret = uart_add_one_port(&mpc52xx_uart_driver, port);
  951. if (ret) {
  952. irq_dispose_mapping(port->irq);
  953. return ret;
  954. }
  955. dev_set_drvdata(&op->dev, (void *)port);
  956. return 0;
  957. }
  958. static int
  959. mpc52xx_uart_of_remove(struct of_device *op)
  960. {
  961. struct uart_port *port = dev_get_drvdata(&op->dev);
  962. dev_set_drvdata(&op->dev, NULL);
  963. if (port) {
  964. uart_remove_one_port(&mpc52xx_uart_driver, port);
  965. irq_dispose_mapping(port->irq);
  966. }
  967. return 0;
  968. }
  969. #ifdef CONFIG_PM
  970. static int
  971. mpc52xx_uart_of_suspend(struct of_device *op, pm_message_t state)
  972. {
  973. struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev);
  974. if (port)
  975. uart_suspend_port(&mpc52xx_uart_driver, port);
  976. return 0;
  977. }
  978. static int
  979. mpc52xx_uart_of_resume(struct of_device *op)
  980. {
  981. struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev);
  982. if (port)
  983. uart_resume_port(&mpc52xx_uart_driver, port);
  984. return 0;
  985. }
  986. #endif
  987. static void
  988. mpc52xx_uart_of_assign(struct device_node *np, int idx)
  989. {
  990. int free_idx = -1;
  991. int i;
  992. /* Find the first free node */
  993. for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
  994. if (mpc52xx_uart_nodes[i] == NULL) {
  995. free_idx = i;
  996. break;
  997. }
  998. }
  999. if ((idx < 0) || (idx >= MPC52xx_PSC_MAXNUM))
  1000. idx = free_idx;
  1001. if (idx < 0)
  1002. return; /* No free slot; abort */
  1003. of_node_get(np);
  1004. /* If the slot is already occupied, then swap slots */
  1005. if (mpc52xx_uart_nodes[idx] && (free_idx != -1))
  1006. mpc52xx_uart_nodes[free_idx] = mpc52xx_uart_nodes[idx];
  1007. mpc52xx_uart_nodes[idx] = np;
  1008. }
  1009. static void
  1010. mpc52xx_uart_of_enumerate(void)
  1011. {
  1012. static int enum_done;
  1013. struct device_node *np;
  1014. const unsigned int *devno;
  1015. const struct of_device_id *match;
  1016. int i;
  1017. if (enum_done)
  1018. return;
  1019. for_each_node_by_type(np, "serial") {
  1020. match = of_match_node(mpc52xx_uart_of_match, np);
  1021. if (!match)
  1022. continue;
  1023. psc_ops = match->data;
  1024. /* Is a particular device number requested? */
  1025. devno = of_get_property(np, "port-number", NULL);
  1026. mpc52xx_uart_of_assign(np, devno ? *devno : -1);
  1027. }
  1028. enum_done = 1;
  1029. for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
  1030. if (mpc52xx_uart_nodes[i])
  1031. pr_debug("%s assigned to ttyPSC%x\n",
  1032. mpc52xx_uart_nodes[i]->full_name, i);
  1033. }
  1034. }
  1035. MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match);
  1036. static struct of_platform_driver mpc52xx_uart_of_driver = {
  1037. .match_table = mpc52xx_uart_of_match,
  1038. .probe = mpc52xx_uart_of_probe,
  1039. .remove = mpc52xx_uart_of_remove,
  1040. #ifdef CONFIG_PM
  1041. .suspend = mpc52xx_uart_of_suspend,
  1042. .resume = mpc52xx_uart_of_resume,
  1043. #endif
  1044. .driver = {
  1045. .name = "mpc52xx-psc-uart",
  1046. },
  1047. };
  1048. /* ======================================================================== */
  1049. /* Module */
  1050. /* ======================================================================== */
  1051. static int __init
  1052. mpc52xx_uart_init(void)
  1053. {
  1054. int ret;
  1055. printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n");
  1056. ret = uart_register_driver(&mpc52xx_uart_driver);
  1057. if (ret) {
  1058. printk(KERN_ERR "%s: uart_register_driver failed (%i)\n",
  1059. __FILE__, ret);
  1060. return ret;
  1061. }
  1062. mpc52xx_uart_of_enumerate();
  1063. ret = of_register_platform_driver(&mpc52xx_uart_of_driver);
  1064. if (ret) {
  1065. printk(KERN_ERR "%s: of_register_platform_driver failed (%i)\n",
  1066. __FILE__, ret);
  1067. uart_unregister_driver(&mpc52xx_uart_driver);
  1068. return ret;
  1069. }
  1070. return 0;
  1071. }
  1072. static void __exit
  1073. mpc52xx_uart_exit(void)
  1074. {
  1075. of_unregister_platform_driver(&mpc52xx_uart_of_driver);
  1076. uart_unregister_driver(&mpc52xx_uart_driver);
  1077. }
  1078. module_init(mpc52xx_uart_init);
  1079. module_exit(mpc52xx_uart_exit);
  1080. MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
  1081. MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
  1082. MODULE_LICENSE("GPL");