arcmsr_hba.c 67 KB

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  1. /*
  2. *******************************************************************************
  3. ** O.S : Linux
  4. ** FILE NAME : arcmsr_hba.c
  5. ** BY : Erich Chen
  6. ** Description: SCSI RAID Device Driver for
  7. ** ARECA RAID Host adapter
  8. *******************************************************************************
  9. ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved
  10. **
  11. ** Web site: www.areca.com.tw
  12. ** E-mail: support@areca.com.tw
  13. **
  14. ** This program is free software; you can redistribute it and/or modify
  15. ** it under the terms of the GNU General Public License version 2 as
  16. ** published by the Free Software Foundation.
  17. ** This program is distributed in the hope that it will be useful,
  18. ** but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. ** GNU General Public License for more details.
  21. *******************************************************************************
  22. ** Redistribution and use in source and binary forms, with or without
  23. ** modification, are permitted provided that the following conditions
  24. ** are met:
  25. ** 1. Redistributions of source code must retain the above copyright
  26. ** notice, this list of conditions and the following disclaimer.
  27. ** 2. Redistributions in binary form must reproduce the above copyright
  28. ** notice, this list of conditions and the following disclaimer in the
  29. ** documentation and/or other materials provided with the distribution.
  30. ** 3. The name of the author may not be used to endorse or promote products
  31. ** derived from this software without specific prior written permission.
  32. **
  33. ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  34. ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  35. ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  36. ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  37. ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
  38. ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  39. ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
  40. ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  41. ** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
  42. ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  43. *******************************************************************************
  44. ** For history of changes, see Documentation/scsi/ChangeLog.arcmsr
  45. ** Firmware Specification, see Documentation/scsi/arcmsr_spec.txt
  46. *******************************************************************************
  47. */
  48. #include <linux/module.h>
  49. #include <linux/reboot.h>
  50. #include <linux/spinlock.h>
  51. #include <linux/pci_ids.h>
  52. #include <linux/interrupt.h>
  53. #include <linux/moduleparam.h>
  54. #include <linux/errno.h>
  55. #include <linux/types.h>
  56. #include <linux/delay.h>
  57. #include <linux/dma-mapping.h>
  58. #include <linux/timer.h>
  59. #include <linux/pci.h>
  60. #include <linux/aer.h>
  61. #include <asm/dma.h>
  62. #include <asm/io.h>
  63. #include <asm/system.h>
  64. #include <asm/uaccess.h>
  65. #include <scsi/scsi_host.h>
  66. #include <scsi/scsi.h>
  67. #include <scsi/scsi_cmnd.h>
  68. #include <scsi/scsi_tcq.h>
  69. #include <scsi/scsi_device.h>
  70. #include <scsi/scsi_transport.h>
  71. #include <scsi/scsicam.h>
  72. #include "arcmsr.h"
  73. MODULE_AUTHOR("Erich Chen <support@areca.com.tw>");
  74. MODULE_DESCRIPTION("ARECA (ARC11xx/12xx/13xx/16xx) SATA/SAS RAID HOST Adapter");
  75. MODULE_LICENSE("Dual BSD/GPL");
  76. MODULE_VERSION(ARCMSR_DRIVER_VERSION);
  77. static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
  78. struct scsi_cmnd *cmd);
  79. static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
  80. static int arcmsr_abort(struct scsi_cmnd *);
  81. static int arcmsr_bus_reset(struct scsi_cmnd *);
  82. static int arcmsr_bios_param(struct scsi_device *sdev,
  83. struct block_device *bdev, sector_t capacity, int *info);
  84. static int arcmsr_queue_command(struct scsi_cmnd *cmd,
  85. void (*done) (struct scsi_cmnd *));
  86. static int arcmsr_probe(struct pci_dev *pdev,
  87. const struct pci_device_id *id);
  88. static void arcmsr_remove(struct pci_dev *pdev);
  89. static void arcmsr_shutdown(struct pci_dev *pdev);
  90. static void arcmsr_iop_init(struct AdapterControlBlock *acb);
  91. static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
  92. static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
  93. static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
  94. static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb);
  95. static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb);
  96. static const char *arcmsr_info(struct Scsi_Host *);
  97. static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
  98. static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev,
  99. int queue_depth)
  100. {
  101. if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
  102. queue_depth = ARCMSR_MAX_CMD_PERLUN;
  103. scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, queue_depth);
  104. return queue_depth;
  105. }
  106. static struct scsi_host_template arcmsr_scsi_host_template = {
  107. .module = THIS_MODULE,
  108. .name = "ARCMSR ARECA SATA/SAS RAID HOST Adapter"
  109. ARCMSR_DRIVER_VERSION,
  110. .info = arcmsr_info,
  111. .queuecommand = arcmsr_queue_command,
  112. .eh_abort_handler = arcmsr_abort,
  113. .eh_bus_reset_handler = arcmsr_bus_reset,
  114. .bios_param = arcmsr_bios_param,
  115. .change_queue_depth = arcmsr_adjust_disk_queue_depth,
  116. .can_queue = ARCMSR_MAX_OUTSTANDING_CMD,
  117. .this_id = ARCMSR_SCSI_INITIATOR_ID,
  118. .sg_tablesize = ARCMSR_MAX_SG_ENTRIES,
  119. .max_sectors = ARCMSR_MAX_XFER_SECTORS,
  120. .cmd_per_lun = ARCMSR_MAX_CMD_PERLUN,
  121. .use_clustering = ENABLE_CLUSTERING,
  122. .shost_attrs = arcmsr_host_attrs,
  123. };
  124. #ifdef CONFIG_SCSI_ARCMSR_AER
  125. static pci_ers_result_t arcmsr_pci_slot_reset(struct pci_dev *pdev);
  126. static pci_ers_result_t arcmsr_pci_error_detected(struct pci_dev *pdev,
  127. pci_channel_state_t state);
  128. static struct pci_error_handlers arcmsr_pci_error_handlers = {
  129. .error_detected = arcmsr_pci_error_detected,
  130. .slot_reset = arcmsr_pci_slot_reset,
  131. };
  132. #endif
  133. static struct pci_device_id arcmsr_device_id_table[] = {
  134. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110)},
  135. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120)},
  136. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130)},
  137. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160)},
  138. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170)},
  139. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200)},
  140. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201)},
  141. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202)},
  142. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210)},
  143. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220)},
  144. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230)},
  145. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260)},
  146. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270)},
  147. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280)},
  148. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380)},
  149. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381)},
  150. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680)},
  151. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681)},
  152. {0, 0}, /* Terminating entry */
  153. };
  154. MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
  155. static struct pci_driver arcmsr_pci_driver = {
  156. .name = "arcmsr",
  157. .id_table = arcmsr_device_id_table,
  158. .probe = arcmsr_probe,
  159. .remove = arcmsr_remove,
  160. .shutdown = arcmsr_shutdown,
  161. #ifdef CONFIG_SCSI_ARCMSR_AER
  162. .err_handler = &arcmsr_pci_error_handlers,
  163. #endif
  164. };
  165. static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
  166. {
  167. irqreturn_t handle_state;
  168. struct AdapterControlBlock *acb = dev_id;
  169. spin_lock(acb->host->host_lock);
  170. handle_state = arcmsr_interrupt(acb);
  171. spin_unlock(acb->host->host_lock);
  172. return handle_state;
  173. }
  174. static int arcmsr_bios_param(struct scsi_device *sdev,
  175. struct block_device *bdev, sector_t capacity, int *geom)
  176. {
  177. int ret, heads, sectors, cylinders, total_capacity;
  178. unsigned char *buffer;/* return copy of block device's partition table */
  179. buffer = scsi_bios_ptable(bdev);
  180. if (buffer) {
  181. ret = scsi_partsize(buffer, capacity, &geom[2], &geom[0], &geom[1]);
  182. kfree(buffer);
  183. if (ret != -1)
  184. return ret;
  185. }
  186. total_capacity = capacity;
  187. heads = 64;
  188. sectors = 32;
  189. cylinders = total_capacity / (heads * sectors);
  190. if (cylinders > 1024) {
  191. heads = 255;
  192. sectors = 63;
  193. cylinders = total_capacity / (heads * sectors);
  194. }
  195. geom[0] = heads;
  196. geom[1] = sectors;
  197. geom[2] = cylinders;
  198. return 0;
  199. }
  200. static void arcmsr_define_adapter_type(struct AdapterControlBlock *acb)
  201. {
  202. struct pci_dev *pdev = acb->pdev;
  203. u16 dev_id;
  204. pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id);
  205. switch (dev_id) {
  206. case 0x1201 : {
  207. acb->adapter_type = ACB_ADAPTER_TYPE_B;
  208. }
  209. break;
  210. default : acb->adapter_type = ACB_ADAPTER_TYPE_A;
  211. }
  212. }
  213. static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
  214. {
  215. switch (acb->adapter_type) {
  216. case ACB_ADAPTER_TYPE_A: {
  217. struct pci_dev *pdev = acb->pdev;
  218. void *dma_coherent;
  219. dma_addr_t dma_coherent_handle, dma_addr;
  220. struct CommandControlBlock *ccb_tmp;
  221. uint32_t intmask_org;
  222. int i, j;
  223. acb->pmuA = pci_ioremap_bar(pdev, 0);
  224. if (!acb->pmuA) {
  225. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n",
  226. acb->host->host_no);
  227. return -ENOMEM;
  228. }
  229. dma_coherent = dma_alloc_coherent(&pdev->dev,
  230. ARCMSR_MAX_FREECCB_NUM *
  231. sizeof (struct CommandControlBlock) + 0x20,
  232. &dma_coherent_handle, GFP_KERNEL);
  233. if (!dma_coherent) {
  234. iounmap(acb->pmuA);
  235. return -ENOMEM;
  236. }
  237. acb->dma_coherent = dma_coherent;
  238. acb->dma_coherent_handle = dma_coherent_handle;
  239. if (((unsigned long)dma_coherent & 0x1F)) {
  240. dma_coherent = dma_coherent +
  241. (0x20 - ((unsigned long)dma_coherent & 0x1F));
  242. dma_coherent_handle = dma_coherent_handle +
  243. (0x20 - ((unsigned long)dma_coherent_handle & 0x1F));
  244. }
  245. dma_addr = dma_coherent_handle;
  246. ccb_tmp = (struct CommandControlBlock *)dma_coherent;
  247. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  248. ccb_tmp->cdb_shifted_phyaddr = dma_addr >> 5;
  249. ccb_tmp->acb = acb;
  250. acb->pccb_pool[i] = ccb_tmp;
  251. list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
  252. dma_addr = dma_addr + sizeof(struct CommandControlBlock);
  253. ccb_tmp++;
  254. }
  255. acb->vir2phy_offset = (unsigned long)ccb_tmp -(unsigned long)dma_addr;
  256. for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
  257. for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
  258. acb->devstate[i][j] = ARECA_RAID_GONE;
  259. /*
  260. ** here we need to tell iop 331 our ccb_tmp.HighPart
  261. ** if ccb_tmp.HighPart is not zero
  262. */
  263. intmask_org = arcmsr_disable_outbound_ints(acb);
  264. }
  265. break;
  266. case ACB_ADAPTER_TYPE_B: {
  267. struct pci_dev *pdev = acb->pdev;
  268. struct MessageUnit_B *reg;
  269. void __iomem *mem_base0, *mem_base1;
  270. void *dma_coherent;
  271. dma_addr_t dma_coherent_handle, dma_addr;
  272. uint32_t intmask_org;
  273. struct CommandControlBlock *ccb_tmp;
  274. int i, j;
  275. dma_coherent = dma_alloc_coherent(&pdev->dev,
  276. ((ARCMSR_MAX_FREECCB_NUM *
  277. sizeof(struct CommandControlBlock) + 0x20) +
  278. sizeof(struct MessageUnit_B)),
  279. &dma_coherent_handle, GFP_KERNEL);
  280. if (!dma_coherent)
  281. return -ENOMEM;
  282. acb->dma_coherent = dma_coherent;
  283. acb->dma_coherent_handle = dma_coherent_handle;
  284. if (((unsigned long)dma_coherent & 0x1F)) {
  285. dma_coherent = dma_coherent +
  286. (0x20 - ((unsigned long)dma_coherent & 0x1F));
  287. dma_coherent_handle = dma_coherent_handle +
  288. (0x20 - ((unsigned long)dma_coherent_handle & 0x1F));
  289. }
  290. dma_addr = dma_coherent_handle;
  291. ccb_tmp = (struct CommandControlBlock *)dma_coherent;
  292. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  293. ccb_tmp->cdb_shifted_phyaddr = dma_addr >> 5;
  294. ccb_tmp->acb = acb;
  295. acb->pccb_pool[i] = ccb_tmp;
  296. list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
  297. dma_addr = dma_addr + sizeof(struct CommandControlBlock);
  298. ccb_tmp++;
  299. }
  300. reg = (struct MessageUnit_B *)(dma_coherent +
  301. ARCMSR_MAX_FREECCB_NUM * sizeof(struct CommandControlBlock));
  302. acb->pmuB = reg;
  303. mem_base0 = pci_ioremap_bar(pdev, 0);
  304. if (!mem_base0)
  305. goto out;
  306. mem_base1 = pci_ioremap_bar(pdev, 2);
  307. if (!mem_base1) {
  308. iounmap(mem_base0);
  309. goto out;
  310. }
  311. reg->drv2iop_doorbell_reg = mem_base0 + ARCMSR_DRV2IOP_DOORBELL;
  312. reg->drv2iop_doorbell_mask_reg = mem_base0 +
  313. ARCMSR_DRV2IOP_DOORBELL_MASK;
  314. reg->iop2drv_doorbell_reg = mem_base0 + ARCMSR_IOP2DRV_DOORBELL;
  315. reg->iop2drv_doorbell_mask_reg = mem_base0 +
  316. ARCMSR_IOP2DRV_DOORBELL_MASK;
  317. reg->ioctl_wbuffer_reg = mem_base1 + ARCMSR_IOCTL_WBUFFER;
  318. reg->ioctl_rbuffer_reg = mem_base1 + ARCMSR_IOCTL_RBUFFER;
  319. reg->msgcode_rwbuffer_reg = mem_base1 + ARCMSR_MSGCODE_RWBUFFER;
  320. acb->vir2phy_offset = (unsigned long)ccb_tmp -(unsigned long)dma_addr;
  321. for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
  322. for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
  323. acb->devstate[i][j] = ARECA_RAID_GOOD;
  324. /*
  325. ** here we need to tell iop 331 our ccb_tmp.HighPart
  326. ** if ccb_tmp.HighPart is not zero
  327. */
  328. intmask_org = arcmsr_disable_outbound_ints(acb);
  329. }
  330. break;
  331. }
  332. return 0;
  333. out:
  334. dma_free_coherent(&acb->pdev->dev,
  335. (ARCMSR_MAX_FREECCB_NUM * sizeof(struct CommandControlBlock) + 0x20 +
  336. sizeof(struct MessageUnit_B)), acb->dma_coherent, acb->dma_coherent_handle);
  337. return -ENOMEM;
  338. }
  339. static int arcmsr_probe(struct pci_dev *pdev,
  340. const struct pci_device_id *id)
  341. {
  342. struct Scsi_Host *host;
  343. struct AdapterControlBlock *acb;
  344. uint8_t bus, dev_fun;
  345. int error;
  346. error = pci_enable_device(pdev);
  347. if (error)
  348. goto out;
  349. pci_set_master(pdev);
  350. host = scsi_host_alloc(&arcmsr_scsi_host_template,
  351. sizeof(struct AdapterControlBlock));
  352. if (!host) {
  353. error = -ENOMEM;
  354. goto out_disable_device;
  355. }
  356. acb = (struct AdapterControlBlock *)host->hostdata;
  357. memset(acb, 0, sizeof (struct AdapterControlBlock));
  358. error = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  359. if (error) {
  360. error = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  361. if (error) {
  362. printk(KERN_WARNING
  363. "scsi%d: No suitable DMA mask available\n",
  364. host->host_no);
  365. goto out_host_put;
  366. }
  367. }
  368. bus = pdev->bus->number;
  369. dev_fun = pdev->devfn;
  370. acb->host = host;
  371. acb->pdev = pdev;
  372. host->max_sectors = ARCMSR_MAX_XFER_SECTORS;
  373. host->max_lun = ARCMSR_MAX_TARGETLUN;
  374. host->max_id = ARCMSR_MAX_TARGETID;/*16:8*/
  375. host->max_cmd_len = 16; /*this is issue of 64bit LBA, over 2T byte*/
  376. host->sg_tablesize = ARCMSR_MAX_SG_ENTRIES;
  377. host->can_queue = ARCMSR_MAX_FREECCB_NUM; /* max simultaneous cmds */
  378. host->cmd_per_lun = ARCMSR_MAX_CMD_PERLUN;
  379. host->this_id = ARCMSR_SCSI_INITIATOR_ID;
  380. host->unique_id = (bus << 8) | dev_fun;
  381. host->irq = pdev->irq;
  382. error = pci_request_regions(pdev, "arcmsr");
  383. if (error) {
  384. goto out_host_put;
  385. }
  386. arcmsr_define_adapter_type(acb);
  387. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  388. ACB_F_MESSAGE_RQBUFFER_CLEARED |
  389. ACB_F_MESSAGE_WQBUFFER_READED);
  390. acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
  391. INIT_LIST_HEAD(&acb->ccb_free_list);
  392. error = arcmsr_alloc_ccb_pool(acb);
  393. if (error)
  394. goto out_release_regions;
  395. error = request_irq(pdev->irq, arcmsr_do_interrupt,
  396. IRQF_SHARED, "arcmsr", acb);
  397. if (error)
  398. goto out_free_ccb_pool;
  399. arcmsr_iop_init(acb);
  400. pci_set_drvdata(pdev, host);
  401. if (strncmp(acb->firm_version, "V1.42", 5) >= 0)
  402. host->max_sectors= ARCMSR_MAX_XFER_SECTORS_B;
  403. error = scsi_add_host(host, &pdev->dev);
  404. if (error)
  405. goto out_free_irq;
  406. error = arcmsr_alloc_sysfs_attr(acb);
  407. if (error)
  408. goto out_free_sysfs;
  409. scsi_scan_host(host);
  410. #ifdef CONFIG_SCSI_ARCMSR_AER
  411. pci_enable_pcie_error_reporting(pdev);
  412. #endif
  413. return 0;
  414. out_free_sysfs:
  415. out_free_irq:
  416. free_irq(pdev->irq, acb);
  417. out_free_ccb_pool:
  418. arcmsr_free_ccb_pool(acb);
  419. out_release_regions:
  420. pci_release_regions(pdev);
  421. out_host_put:
  422. scsi_host_put(host);
  423. out_disable_device:
  424. pci_disable_device(pdev);
  425. out:
  426. return error;
  427. }
  428. static uint8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
  429. {
  430. struct MessageUnit_A __iomem *reg = acb->pmuA;
  431. uint32_t Index;
  432. uint8_t Retries = 0x00;
  433. do {
  434. for (Index = 0; Index < 100; Index++) {
  435. if (readl(&reg->outbound_intstatus) &
  436. ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
  437. writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
  438. &reg->outbound_intstatus);
  439. return 0x00;
  440. }
  441. msleep(10);
  442. }/*max 1 seconds*/
  443. } while (Retries++ < 20);/*max 20 sec*/
  444. return 0xff;
  445. }
  446. static uint8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
  447. {
  448. struct MessageUnit_B *reg = acb->pmuB;
  449. uint32_t Index;
  450. uint8_t Retries = 0x00;
  451. do {
  452. for (Index = 0; Index < 100; Index++) {
  453. if (readl(reg->iop2drv_doorbell_reg)
  454. & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
  455. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN
  456. , reg->iop2drv_doorbell_reg);
  457. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell_reg);
  458. return 0x00;
  459. }
  460. msleep(10);
  461. }/*max 1 seconds*/
  462. } while (Retries++ < 20);/*max 20 sec*/
  463. return 0xff;
  464. }
  465. static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
  466. {
  467. struct MessageUnit_A __iomem *reg = acb->pmuA;
  468. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
  469. if (arcmsr_hba_wait_msgint_ready(acb))
  470. printk(KERN_NOTICE
  471. "arcmsr%d: wait 'abort all outstanding command' timeout \n"
  472. , acb->host->host_no);
  473. }
  474. static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
  475. {
  476. struct MessageUnit_B *reg = acb->pmuB;
  477. writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell_reg);
  478. if (arcmsr_hbb_wait_msgint_ready(acb))
  479. printk(KERN_NOTICE
  480. "arcmsr%d: wait 'abort all outstanding command' timeout \n"
  481. , acb->host->host_no);
  482. }
  483. static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
  484. {
  485. switch (acb->adapter_type) {
  486. case ACB_ADAPTER_TYPE_A: {
  487. arcmsr_abort_hba_allcmd(acb);
  488. }
  489. break;
  490. case ACB_ADAPTER_TYPE_B: {
  491. arcmsr_abort_hbb_allcmd(acb);
  492. }
  493. }
  494. }
  495. static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
  496. {
  497. struct scsi_cmnd *pcmd = ccb->pcmd;
  498. scsi_dma_unmap(pcmd);
  499. }
  500. static void arcmsr_ccb_complete(struct CommandControlBlock *ccb, int stand_flag)
  501. {
  502. struct AdapterControlBlock *acb = ccb->acb;
  503. struct scsi_cmnd *pcmd = ccb->pcmd;
  504. arcmsr_pci_unmap_dma(ccb);
  505. if (stand_flag == 1)
  506. atomic_dec(&acb->ccboutstandingcount);
  507. ccb->startdone = ARCMSR_CCB_DONE;
  508. ccb->ccb_flags = 0;
  509. list_add_tail(&ccb->list, &acb->ccb_free_list);
  510. pcmd->scsi_done(pcmd);
  511. }
  512. static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
  513. {
  514. struct MessageUnit_A __iomem *reg = acb->pmuA;
  515. int retry_count = 30;
  516. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
  517. do {
  518. if (!arcmsr_hba_wait_msgint_ready(acb))
  519. break;
  520. else {
  521. retry_count--;
  522. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  523. timeout, retry count down = %d \n", acb->host->host_no, retry_count);
  524. }
  525. } while (retry_count != 0);
  526. }
  527. static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
  528. {
  529. struct MessageUnit_B *reg = acb->pmuB;
  530. int retry_count = 30;
  531. writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell_reg);
  532. do {
  533. if (!arcmsr_hbb_wait_msgint_ready(acb))
  534. break;
  535. else {
  536. retry_count--;
  537. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  538. timeout,retry count down = %d \n", acb->host->host_no, retry_count);
  539. }
  540. } while (retry_count != 0);
  541. }
  542. static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
  543. {
  544. switch (acb->adapter_type) {
  545. case ACB_ADAPTER_TYPE_A: {
  546. arcmsr_flush_hba_cache(acb);
  547. }
  548. break;
  549. case ACB_ADAPTER_TYPE_B: {
  550. arcmsr_flush_hbb_cache(acb);
  551. }
  552. }
  553. }
  554. static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
  555. {
  556. struct scsi_cmnd *pcmd = ccb->pcmd;
  557. struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
  558. pcmd->result = DID_OK << 16;
  559. if (sensebuffer) {
  560. int sense_data_length =
  561. sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE
  562. ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE;
  563. memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE);
  564. memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length);
  565. sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
  566. sensebuffer->Valid = 1;
  567. }
  568. }
  569. static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
  570. {
  571. u32 orig_mask = 0;
  572. switch (acb->adapter_type) {
  573. case ACB_ADAPTER_TYPE_A : {
  574. struct MessageUnit_A __iomem *reg = acb->pmuA;
  575. orig_mask = readl(&reg->outbound_intmask)|\
  576. ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE;
  577. writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
  578. &reg->outbound_intmask);
  579. }
  580. break;
  581. case ACB_ADAPTER_TYPE_B : {
  582. struct MessageUnit_B *reg = acb->pmuB;
  583. orig_mask = readl(reg->iop2drv_doorbell_mask_reg) & \
  584. (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
  585. writel(0, reg->iop2drv_doorbell_mask_reg);
  586. }
  587. break;
  588. }
  589. return orig_mask;
  590. }
  591. static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb, \
  592. struct CommandControlBlock *ccb, uint32_t flag_ccb)
  593. {
  594. uint8_t id, lun;
  595. id = ccb->pcmd->device->id;
  596. lun = ccb->pcmd->device->lun;
  597. if (!(flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR)) {
  598. if (acb->devstate[id][lun] == ARECA_RAID_GONE)
  599. acb->devstate[id][lun] = ARECA_RAID_GOOD;
  600. ccb->pcmd->result = DID_OK << 16;
  601. arcmsr_ccb_complete(ccb, 1);
  602. } else {
  603. switch (ccb->arcmsr_cdb.DeviceStatus) {
  604. case ARCMSR_DEV_SELECT_TIMEOUT: {
  605. acb->devstate[id][lun] = ARECA_RAID_GONE;
  606. ccb->pcmd->result = DID_NO_CONNECT << 16;
  607. arcmsr_ccb_complete(ccb, 1);
  608. }
  609. break;
  610. case ARCMSR_DEV_ABORTED:
  611. case ARCMSR_DEV_INIT_FAIL: {
  612. acb->devstate[id][lun] = ARECA_RAID_GONE;
  613. ccb->pcmd->result = DID_BAD_TARGET << 16;
  614. arcmsr_ccb_complete(ccb, 1);
  615. }
  616. break;
  617. case ARCMSR_DEV_CHECK_CONDITION: {
  618. acb->devstate[id][lun] = ARECA_RAID_GOOD;
  619. arcmsr_report_sense_info(ccb);
  620. arcmsr_ccb_complete(ccb, 1);
  621. }
  622. break;
  623. default:
  624. printk(KERN_NOTICE
  625. "arcmsr%d: scsi id = %d lun = %d"
  626. " isr get command error done, "
  627. "but got unknown DeviceStatus = 0x%x \n"
  628. , acb->host->host_no
  629. , id
  630. , lun
  631. , ccb->arcmsr_cdb.DeviceStatus);
  632. acb->devstate[id][lun] = ARECA_RAID_GONE;
  633. ccb->pcmd->result = DID_NO_CONNECT << 16;
  634. arcmsr_ccb_complete(ccb, 1);
  635. break;
  636. }
  637. }
  638. }
  639. static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, uint32_t flag_ccb)
  640. {
  641. struct CommandControlBlock *ccb;
  642. ccb = (struct CommandControlBlock *)(acb->vir2phy_offset + (flag_ccb << 5));
  643. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  644. if (ccb->startdone == ARCMSR_CCB_ABORTED) {
  645. struct scsi_cmnd *abortcmd = ccb->pcmd;
  646. if (abortcmd) {
  647. abortcmd->result |= DID_ABORT << 16;
  648. arcmsr_ccb_complete(ccb, 1);
  649. printk(KERN_NOTICE "arcmsr%d: ccb ='0x%p' \
  650. isr got aborted command \n", acb->host->host_no, ccb);
  651. }
  652. }
  653. printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
  654. done acb = '0x%p'"
  655. "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
  656. " ccboutstandingcount = %d \n"
  657. , acb->host->host_no
  658. , acb
  659. , ccb
  660. , ccb->acb
  661. , ccb->startdone
  662. , atomic_read(&acb->ccboutstandingcount));
  663. }
  664. else
  665. arcmsr_report_ccb_state(acb, ccb, flag_ccb);
  666. }
  667. static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
  668. {
  669. int i = 0;
  670. uint32_t flag_ccb;
  671. switch (acb->adapter_type) {
  672. case ACB_ADAPTER_TYPE_A: {
  673. struct MessageUnit_A __iomem *reg = acb->pmuA;
  674. uint32_t outbound_intstatus;
  675. outbound_intstatus = readl(&reg->outbound_intstatus) &
  676. acb->outbound_int_enable;
  677. /*clear and abort all outbound posted Q*/
  678. writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
  679. while (((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF)
  680. && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
  681. arcmsr_drain_donequeue(acb, flag_ccb);
  682. }
  683. }
  684. break;
  685. case ACB_ADAPTER_TYPE_B: {
  686. struct MessageUnit_B *reg = acb->pmuB;
  687. /*clear all outbound posted Q*/
  688. for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
  689. if ((flag_ccb = readl(&reg->done_qbuffer[i])) != 0) {
  690. writel(0, &reg->done_qbuffer[i]);
  691. arcmsr_drain_donequeue(acb, flag_ccb);
  692. }
  693. writel(0, &reg->post_qbuffer[i]);
  694. }
  695. reg->doneq_index = 0;
  696. reg->postq_index = 0;
  697. }
  698. break;
  699. }
  700. }
  701. static void arcmsr_remove(struct pci_dev *pdev)
  702. {
  703. struct Scsi_Host *host = pci_get_drvdata(pdev);
  704. struct AdapterControlBlock *acb =
  705. (struct AdapterControlBlock *) host->hostdata;
  706. int poll_count = 0;
  707. arcmsr_free_sysfs_attr(acb);
  708. scsi_remove_host(host);
  709. arcmsr_stop_adapter_bgrb(acb);
  710. arcmsr_flush_adapter_cache(acb);
  711. arcmsr_disable_outbound_ints(acb);
  712. acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
  713. acb->acb_flags &= ~ACB_F_IOP_INITED;
  714. for (poll_count = 0; poll_count < ARCMSR_MAX_OUTSTANDING_CMD; poll_count++) {
  715. if (!atomic_read(&acb->ccboutstandingcount))
  716. break;
  717. arcmsr_interrupt(acb);/* FIXME: need spinlock */
  718. msleep(25);
  719. }
  720. if (atomic_read(&acb->ccboutstandingcount)) {
  721. int i;
  722. arcmsr_abort_allcmd(acb);
  723. arcmsr_done4abort_postqueue(acb);
  724. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  725. struct CommandControlBlock *ccb = acb->pccb_pool[i];
  726. if (ccb->startdone == ARCMSR_CCB_START) {
  727. ccb->startdone = ARCMSR_CCB_ABORTED;
  728. ccb->pcmd->result = DID_ABORT << 16;
  729. arcmsr_ccb_complete(ccb, 1);
  730. }
  731. }
  732. }
  733. free_irq(pdev->irq, acb);
  734. arcmsr_free_ccb_pool(acb);
  735. pci_release_regions(pdev);
  736. scsi_host_put(host);
  737. pci_disable_device(pdev);
  738. pci_set_drvdata(pdev, NULL);
  739. }
  740. static void arcmsr_shutdown(struct pci_dev *pdev)
  741. {
  742. struct Scsi_Host *host = pci_get_drvdata(pdev);
  743. struct AdapterControlBlock *acb =
  744. (struct AdapterControlBlock *)host->hostdata;
  745. arcmsr_stop_adapter_bgrb(acb);
  746. arcmsr_flush_adapter_cache(acb);
  747. }
  748. static int arcmsr_module_init(void)
  749. {
  750. int error = 0;
  751. error = pci_register_driver(&arcmsr_pci_driver);
  752. return error;
  753. }
  754. static void arcmsr_module_exit(void)
  755. {
  756. pci_unregister_driver(&arcmsr_pci_driver);
  757. }
  758. module_init(arcmsr_module_init);
  759. module_exit(arcmsr_module_exit);
  760. static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb, \
  761. u32 intmask_org)
  762. {
  763. u32 mask;
  764. switch (acb->adapter_type) {
  765. case ACB_ADAPTER_TYPE_A : {
  766. struct MessageUnit_A __iomem *reg = acb->pmuA;
  767. mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
  768. ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE);
  769. writel(mask, &reg->outbound_intmask);
  770. acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
  771. }
  772. break;
  773. case ACB_ADAPTER_TYPE_B : {
  774. struct MessageUnit_B *reg = acb->pmuB;
  775. mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK | \
  776. ARCMSR_IOP2DRV_DATA_READ_OK | ARCMSR_IOP2DRV_CDB_DONE);
  777. writel(mask, reg->iop2drv_doorbell_mask_reg);
  778. acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
  779. }
  780. }
  781. }
  782. static int arcmsr_build_ccb(struct AdapterControlBlock *acb,
  783. struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
  784. {
  785. struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
  786. int8_t *psge = (int8_t *)&arcmsr_cdb->u;
  787. __le32 address_lo, address_hi;
  788. int arccdbsize = 0x30;
  789. int nseg;
  790. ccb->pcmd = pcmd;
  791. memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
  792. arcmsr_cdb->Bus = 0;
  793. arcmsr_cdb->TargetID = pcmd->device->id;
  794. arcmsr_cdb->LUN = pcmd->device->lun;
  795. arcmsr_cdb->Function = 1;
  796. arcmsr_cdb->CdbLength = (uint8_t)pcmd->cmd_len;
  797. arcmsr_cdb->Context = (unsigned long)arcmsr_cdb;
  798. memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
  799. nseg = scsi_dma_map(pcmd);
  800. if (nseg > ARCMSR_MAX_SG_ENTRIES)
  801. return FAILED;
  802. BUG_ON(nseg < 0);
  803. if (nseg) {
  804. __le32 length;
  805. int i, cdb_sgcount = 0;
  806. struct scatterlist *sg;
  807. /* map stor port SG list to our iop SG List. */
  808. scsi_for_each_sg(pcmd, sg, nseg, i) {
  809. /* Get the physical address of the current data pointer */
  810. length = cpu_to_le32(sg_dma_len(sg));
  811. address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
  812. address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
  813. if (address_hi == 0) {
  814. struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
  815. pdma_sg->address = address_lo;
  816. pdma_sg->length = length;
  817. psge += sizeof (struct SG32ENTRY);
  818. arccdbsize += sizeof (struct SG32ENTRY);
  819. } else {
  820. struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
  821. pdma_sg->addresshigh = address_hi;
  822. pdma_sg->address = address_lo;
  823. pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
  824. psge += sizeof (struct SG64ENTRY);
  825. arccdbsize += sizeof (struct SG64ENTRY);
  826. }
  827. cdb_sgcount++;
  828. }
  829. arcmsr_cdb->sgcount = (uint8_t)cdb_sgcount;
  830. arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
  831. if ( arccdbsize > 256)
  832. arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
  833. }
  834. if (pcmd->sc_data_direction == DMA_TO_DEVICE ) {
  835. arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
  836. ccb->ccb_flags |= CCB_FLAG_WRITE;
  837. }
  838. return SUCCESS;
  839. }
  840. static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
  841. {
  842. uint32_t cdb_shifted_phyaddr = ccb->cdb_shifted_phyaddr;
  843. struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
  844. atomic_inc(&acb->ccboutstandingcount);
  845. ccb->startdone = ARCMSR_CCB_START;
  846. switch (acb->adapter_type) {
  847. case ACB_ADAPTER_TYPE_A: {
  848. struct MessageUnit_A __iomem *reg = acb->pmuA;
  849. if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
  850. writel(cdb_shifted_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
  851. &reg->inbound_queueport);
  852. else {
  853. writel(cdb_shifted_phyaddr, &reg->inbound_queueport);
  854. }
  855. }
  856. break;
  857. case ACB_ADAPTER_TYPE_B: {
  858. struct MessageUnit_B *reg = acb->pmuB;
  859. uint32_t ending_index, index = reg->postq_index;
  860. ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
  861. writel(0, &reg->post_qbuffer[ending_index]);
  862. if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
  863. writel(cdb_shifted_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,\
  864. &reg->post_qbuffer[index]);
  865. }
  866. else {
  867. writel(cdb_shifted_phyaddr, &reg->post_qbuffer[index]);
  868. }
  869. index++;
  870. index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */
  871. reg->postq_index = index;
  872. writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell_reg);
  873. }
  874. break;
  875. }
  876. }
  877. static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
  878. {
  879. struct MessageUnit_A __iomem *reg = acb->pmuA;
  880. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  881. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
  882. if (arcmsr_hba_wait_msgint_ready(acb)) {
  883. printk(KERN_NOTICE
  884. "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
  885. , acb->host->host_no);
  886. }
  887. }
  888. static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
  889. {
  890. struct MessageUnit_B *reg = acb->pmuB;
  891. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  892. writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell_reg);
  893. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  894. printk(KERN_NOTICE
  895. "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
  896. , acb->host->host_no);
  897. }
  898. }
  899. static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
  900. {
  901. switch (acb->adapter_type) {
  902. case ACB_ADAPTER_TYPE_A: {
  903. arcmsr_stop_hba_bgrb(acb);
  904. }
  905. break;
  906. case ACB_ADAPTER_TYPE_B: {
  907. arcmsr_stop_hbb_bgrb(acb);
  908. }
  909. break;
  910. }
  911. }
  912. static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
  913. {
  914. switch (acb->adapter_type) {
  915. case ACB_ADAPTER_TYPE_A: {
  916. iounmap(acb->pmuA);
  917. dma_free_coherent(&acb->pdev->dev,
  918. ARCMSR_MAX_FREECCB_NUM * sizeof (struct CommandControlBlock) + 0x20,
  919. acb->dma_coherent,
  920. acb->dma_coherent_handle);
  921. break;
  922. }
  923. case ACB_ADAPTER_TYPE_B: {
  924. struct MessageUnit_B *reg = acb->pmuB;
  925. iounmap(reg->drv2iop_doorbell_reg - ARCMSR_DRV2IOP_DOORBELL);
  926. iounmap(reg->ioctl_wbuffer_reg - ARCMSR_IOCTL_WBUFFER);
  927. dma_free_coherent(&acb->pdev->dev,
  928. (ARCMSR_MAX_FREECCB_NUM * sizeof(struct CommandControlBlock) + 0x20 +
  929. sizeof(struct MessageUnit_B)), acb->dma_coherent, acb->dma_coherent_handle);
  930. }
  931. }
  932. }
  933. void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
  934. {
  935. switch (acb->adapter_type) {
  936. case ACB_ADAPTER_TYPE_A: {
  937. struct MessageUnit_A __iomem *reg = acb->pmuA;
  938. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  939. }
  940. break;
  941. case ACB_ADAPTER_TYPE_B: {
  942. struct MessageUnit_B *reg = acb->pmuB;
  943. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell_reg);
  944. }
  945. break;
  946. }
  947. }
  948. static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
  949. {
  950. switch (acb->adapter_type) {
  951. case ACB_ADAPTER_TYPE_A: {
  952. struct MessageUnit_A __iomem *reg = acb->pmuA;
  953. /*
  954. ** push inbound doorbell tell iop, driver data write ok
  955. ** and wait reply on next hwinterrupt for next Qbuffer post
  956. */
  957. writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &reg->inbound_doorbell);
  958. }
  959. break;
  960. case ACB_ADAPTER_TYPE_B: {
  961. struct MessageUnit_B *reg = acb->pmuB;
  962. /*
  963. ** push inbound doorbell tell iop, driver data write ok
  964. ** and wait reply on next hwinterrupt for next Qbuffer post
  965. */
  966. writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell_reg);
  967. }
  968. break;
  969. }
  970. }
  971. struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
  972. {
  973. struct QBUFFER __iomem *qbuffer = NULL;
  974. switch (acb->adapter_type) {
  975. case ACB_ADAPTER_TYPE_A: {
  976. struct MessageUnit_A __iomem *reg = acb->pmuA;
  977. qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
  978. }
  979. break;
  980. case ACB_ADAPTER_TYPE_B: {
  981. struct MessageUnit_B *reg = acb->pmuB;
  982. qbuffer = (struct QBUFFER __iomem *)reg->ioctl_rbuffer_reg;
  983. }
  984. break;
  985. }
  986. return qbuffer;
  987. }
  988. static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
  989. {
  990. struct QBUFFER __iomem *pqbuffer = NULL;
  991. switch (acb->adapter_type) {
  992. case ACB_ADAPTER_TYPE_A: {
  993. struct MessageUnit_A __iomem *reg = acb->pmuA;
  994. pqbuffer = (struct QBUFFER __iomem *) &reg->message_wbuffer;
  995. }
  996. break;
  997. case ACB_ADAPTER_TYPE_B: {
  998. struct MessageUnit_B *reg = acb->pmuB;
  999. pqbuffer = (struct QBUFFER __iomem *)reg->ioctl_wbuffer_reg;
  1000. }
  1001. break;
  1002. }
  1003. return pqbuffer;
  1004. }
  1005. static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
  1006. {
  1007. struct QBUFFER __iomem *prbuffer;
  1008. struct QBUFFER *pQbuffer;
  1009. uint8_t __iomem *iop_data;
  1010. int32_t my_empty_len, iop_len, rqbuf_firstindex, rqbuf_lastindex;
  1011. rqbuf_lastindex = acb->rqbuf_lastindex;
  1012. rqbuf_firstindex = acb->rqbuf_firstindex;
  1013. prbuffer = arcmsr_get_iop_rqbuffer(acb);
  1014. iop_data = (uint8_t __iomem *)prbuffer->data;
  1015. iop_len = prbuffer->data_len;
  1016. my_empty_len = (rqbuf_firstindex - rqbuf_lastindex -1)&(ARCMSR_MAX_QBUFFER -1);
  1017. if (my_empty_len >= iop_len)
  1018. {
  1019. while (iop_len > 0) {
  1020. pQbuffer = (struct QBUFFER *)&acb->rqbuffer[rqbuf_lastindex];
  1021. memcpy(pQbuffer, iop_data,1);
  1022. rqbuf_lastindex++;
  1023. rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
  1024. iop_data++;
  1025. iop_len--;
  1026. }
  1027. acb->rqbuf_lastindex = rqbuf_lastindex;
  1028. arcmsr_iop_message_read(acb);
  1029. }
  1030. else {
  1031. acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
  1032. }
  1033. }
  1034. static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
  1035. {
  1036. acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
  1037. if (acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
  1038. uint8_t *pQbuffer;
  1039. struct QBUFFER __iomem *pwbuffer;
  1040. uint8_t __iomem *iop_data;
  1041. int32_t allxfer_len = 0;
  1042. acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
  1043. pwbuffer = arcmsr_get_iop_wqbuffer(acb);
  1044. iop_data = (uint8_t __iomem *)pwbuffer->data;
  1045. while ((acb->wqbuf_firstindex != acb->wqbuf_lastindex) && \
  1046. (allxfer_len < 124)) {
  1047. pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
  1048. memcpy(iop_data, pQbuffer, 1);
  1049. acb->wqbuf_firstindex++;
  1050. acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
  1051. iop_data++;
  1052. allxfer_len++;
  1053. }
  1054. pwbuffer->data_len = allxfer_len;
  1055. arcmsr_iop_message_wrote(acb);
  1056. }
  1057. if (acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
  1058. acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
  1059. }
  1060. }
  1061. static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
  1062. {
  1063. uint32_t outbound_doorbell;
  1064. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1065. outbound_doorbell = readl(&reg->outbound_doorbell);
  1066. writel(outbound_doorbell, &reg->outbound_doorbell);
  1067. if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
  1068. arcmsr_iop2drv_data_wrote_handle(acb);
  1069. }
  1070. if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
  1071. arcmsr_iop2drv_data_read_handle(acb);
  1072. }
  1073. }
  1074. static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
  1075. {
  1076. uint32_t flag_ccb;
  1077. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1078. while ((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF) {
  1079. arcmsr_drain_donequeue(acb, flag_ccb);
  1080. }
  1081. }
  1082. static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
  1083. {
  1084. uint32_t index;
  1085. uint32_t flag_ccb;
  1086. struct MessageUnit_B *reg = acb->pmuB;
  1087. index = reg->doneq_index;
  1088. while ((flag_ccb = readl(&reg->done_qbuffer[index])) != 0) {
  1089. writel(0, &reg->done_qbuffer[index]);
  1090. arcmsr_drain_donequeue(acb, flag_ccb);
  1091. index++;
  1092. index %= ARCMSR_MAX_HBB_POSTQUEUE;
  1093. reg->doneq_index = index;
  1094. }
  1095. }
  1096. static int arcmsr_handle_hba_isr(struct AdapterControlBlock *acb)
  1097. {
  1098. uint32_t outbound_intstatus;
  1099. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1100. outbound_intstatus = readl(&reg->outbound_intstatus) & \
  1101. acb->outbound_int_enable;
  1102. if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT)) {
  1103. return 1;
  1104. }
  1105. writel(outbound_intstatus, &reg->outbound_intstatus);
  1106. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
  1107. arcmsr_hba_doorbell_isr(acb);
  1108. }
  1109. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
  1110. arcmsr_hba_postqueue_isr(acb);
  1111. }
  1112. return 0;
  1113. }
  1114. static int arcmsr_handle_hbb_isr(struct AdapterControlBlock *acb)
  1115. {
  1116. uint32_t outbound_doorbell;
  1117. struct MessageUnit_B *reg = acb->pmuB;
  1118. outbound_doorbell = readl(reg->iop2drv_doorbell_reg) & \
  1119. acb->outbound_int_enable;
  1120. if (!outbound_doorbell)
  1121. return 1;
  1122. writel(~outbound_doorbell, reg->iop2drv_doorbell_reg);
  1123. /*in case the last action of doorbell interrupt clearance is cached, this action can push HW to write down the clear bit*/
  1124. readl(reg->iop2drv_doorbell_reg);
  1125. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell_reg);
  1126. if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
  1127. arcmsr_iop2drv_data_wrote_handle(acb);
  1128. }
  1129. if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
  1130. arcmsr_iop2drv_data_read_handle(acb);
  1131. }
  1132. if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
  1133. arcmsr_hbb_postqueue_isr(acb);
  1134. }
  1135. return 0;
  1136. }
  1137. static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
  1138. {
  1139. switch (acb->adapter_type) {
  1140. case ACB_ADAPTER_TYPE_A: {
  1141. if (arcmsr_handle_hba_isr(acb)) {
  1142. return IRQ_NONE;
  1143. }
  1144. }
  1145. break;
  1146. case ACB_ADAPTER_TYPE_B: {
  1147. if (arcmsr_handle_hbb_isr(acb)) {
  1148. return IRQ_NONE;
  1149. }
  1150. }
  1151. break;
  1152. }
  1153. return IRQ_HANDLED;
  1154. }
  1155. static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
  1156. {
  1157. if (acb) {
  1158. /* stop adapter background rebuild */
  1159. if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
  1160. uint32_t intmask_org;
  1161. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1162. intmask_org = arcmsr_disable_outbound_ints(acb);
  1163. arcmsr_stop_adapter_bgrb(acb);
  1164. arcmsr_flush_adapter_cache(acb);
  1165. arcmsr_enable_outbound_ints(acb, intmask_org);
  1166. }
  1167. }
  1168. }
  1169. void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *acb)
  1170. {
  1171. int32_t wqbuf_firstindex, wqbuf_lastindex;
  1172. uint8_t *pQbuffer;
  1173. struct QBUFFER __iomem *pwbuffer;
  1174. uint8_t __iomem *iop_data;
  1175. int32_t allxfer_len = 0;
  1176. pwbuffer = arcmsr_get_iop_wqbuffer(acb);
  1177. iop_data = (uint8_t __iomem *)pwbuffer->data;
  1178. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
  1179. acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
  1180. wqbuf_firstindex = acb->wqbuf_firstindex;
  1181. wqbuf_lastindex = acb->wqbuf_lastindex;
  1182. while ((wqbuf_firstindex != wqbuf_lastindex) && (allxfer_len < 124)) {
  1183. pQbuffer = &acb->wqbuffer[wqbuf_firstindex];
  1184. memcpy(iop_data, pQbuffer, 1);
  1185. wqbuf_firstindex++;
  1186. wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
  1187. iop_data++;
  1188. allxfer_len++;
  1189. }
  1190. acb->wqbuf_firstindex = wqbuf_firstindex;
  1191. pwbuffer->data_len = allxfer_len;
  1192. arcmsr_iop_message_wrote(acb);
  1193. }
  1194. }
  1195. static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, \
  1196. struct scsi_cmnd *cmd)
  1197. {
  1198. struct CMD_MESSAGE_FIELD *pcmdmessagefld;
  1199. int retvalue = 0, transfer_len = 0;
  1200. char *buffer;
  1201. struct scatterlist *sg;
  1202. uint32_t controlcode = (uint32_t ) cmd->cmnd[5] << 24 |
  1203. (uint32_t ) cmd->cmnd[6] << 16 |
  1204. (uint32_t ) cmd->cmnd[7] << 8 |
  1205. (uint32_t ) cmd->cmnd[8];
  1206. /* 4 bytes: Areca io control code */
  1207. sg = scsi_sglist(cmd);
  1208. buffer = kmap_atomic(sg_page(sg), KM_IRQ0) + sg->offset;
  1209. if (scsi_sg_count(cmd) > 1) {
  1210. retvalue = ARCMSR_MESSAGE_FAIL;
  1211. goto message_out;
  1212. }
  1213. transfer_len += sg->length;
  1214. if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
  1215. retvalue = ARCMSR_MESSAGE_FAIL;
  1216. goto message_out;
  1217. }
  1218. pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
  1219. switch(controlcode) {
  1220. case ARCMSR_MESSAGE_READ_RQBUFFER: {
  1221. unsigned char *ver_addr;
  1222. uint8_t *pQbuffer, *ptmpQbuffer;
  1223. int32_t allxfer_len = 0;
  1224. ver_addr = kmalloc(1032, GFP_ATOMIC);
  1225. if (!ver_addr) {
  1226. retvalue = ARCMSR_MESSAGE_FAIL;
  1227. goto message_out;
  1228. }
  1229. ptmpQbuffer = ver_addr;
  1230. while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
  1231. && (allxfer_len < 1031)) {
  1232. pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
  1233. memcpy(ptmpQbuffer, pQbuffer, 1);
  1234. acb->rqbuf_firstindex++;
  1235. acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
  1236. ptmpQbuffer++;
  1237. allxfer_len++;
  1238. }
  1239. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1240. struct QBUFFER __iomem *prbuffer;
  1241. uint8_t __iomem *iop_data;
  1242. int32_t iop_len;
  1243. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1244. prbuffer = arcmsr_get_iop_rqbuffer(acb);
  1245. iop_data = prbuffer->data;
  1246. iop_len = readl(&prbuffer->data_len);
  1247. while (iop_len > 0) {
  1248. acb->rqbuffer[acb->rqbuf_lastindex] = readb(iop_data);
  1249. acb->rqbuf_lastindex++;
  1250. acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
  1251. iop_data++;
  1252. iop_len--;
  1253. }
  1254. arcmsr_iop_message_read(acb);
  1255. }
  1256. memcpy(pcmdmessagefld->messagedatabuffer, ver_addr, allxfer_len);
  1257. pcmdmessagefld->cmdmessage.Length = allxfer_len;
  1258. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
  1259. kfree(ver_addr);
  1260. }
  1261. break;
  1262. case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
  1263. unsigned char *ver_addr;
  1264. int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
  1265. uint8_t *pQbuffer, *ptmpuserbuffer;
  1266. ver_addr = kmalloc(1032, GFP_ATOMIC);
  1267. if (!ver_addr) {
  1268. retvalue = ARCMSR_MESSAGE_FAIL;
  1269. goto message_out;
  1270. }
  1271. ptmpuserbuffer = ver_addr;
  1272. user_len = pcmdmessagefld->cmdmessage.Length;
  1273. memcpy(ptmpuserbuffer, pcmdmessagefld->messagedatabuffer, user_len);
  1274. wqbuf_lastindex = acb->wqbuf_lastindex;
  1275. wqbuf_firstindex = acb->wqbuf_firstindex;
  1276. if (wqbuf_lastindex != wqbuf_firstindex) {
  1277. struct SENSE_DATA *sensebuffer =
  1278. (struct SENSE_DATA *)cmd->sense_buffer;
  1279. arcmsr_post_ioctldata2iop(acb);
  1280. /* has error report sensedata */
  1281. sensebuffer->ErrorCode = 0x70;
  1282. sensebuffer->SenseKey = ILLEGAL_REQUEST;
  1283. sensebuffer->AdditionalSenseLength = 0x0A;
  1284. sensebuffer->AdditionalSenseCode = 0x20;
  1285. sensebuffer->Valid = 1;
  1286. retvalue = ARCMSR_MESSAGE_FAIL;
  1287. } else {
  1288. my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
  1289. &(ARCMSR_MAX_QBUFFER - 1);
  1290. if (my_empty_len >= user_len) {
  1291. while (user_len > 0) {
  1292. pQbuffer =
  1293. &acb->wqbuffer[acb->wqbuf_lastindex];
  1294. memcpy(pQbuffer, ptmpuserbuffer, 1);
  1295. acb->wqbuf_lastindex++;
  1296. acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
  1297. ptmpuserbuffer++;
  1298. user_len--;
  1299. }
  1300. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
  1301. acb->acb_flags &=
  1302. ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
  1303. arcmsr_post_ioctldata2iop(acb);
  1304. }
  1305. } else {
  1306. /* has error report sensedata */
  1307. struct SENSE_DATA *sensebuffer =
  1308. (struct SENSE_DATA *)cmd->sense_buffer;
  1309. sensebuffer->ErrorCode = 0x70;
  1310. sensebuffer->SenseKey = ILLEGAL_REQUEST;
  1311. sensebuffer->AdditionalSenseLength = 0x0A;
  1312. sensebuffer->AdditionalSenseCode = 0x20;
  1313. sensebuffer->Valid = 1;
  1314. retvalue = ARCMSR_MESSAGE_FAIL;
  1315. }
  1316. }
  1317. kfree(ver_addr);
  1318. }
  1319. break;
  1320. case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
  1321. uint8_t *pQbuffer = acb->rqbuffer;
  1322. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1323. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1324. arcmsr_iop_message_read(acb);
  1325. }
  1326. acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
  1327. acb->rqbuf_firstindex = 0;
  1328. acb->rqbuf_lastindex = 0;
  1329. memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
  1330. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
  1331. }
  1332. break;
  1333. case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
  1334. uint8_t *pQbuffer = acb->wqbuffer;
  1335. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1336. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1337. arcmsr_iop_message_read(acb);
  1338. }
  1339. acb->acb_flags |=
  1340. (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  1341. ACB_F_MESSAGE_WQBUFFER_READED);
  1342. acb->wqbuf_firstindex = 0;
  1343. acb->wqbuf_lastindex = 0;
  1344. memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
  1345. pcmdmessagefld->cmdmessage.ReturnCode =
  1346. ARCMSR_MESSAGE_RETURNCODE_OK;
  1347. }
  1348. break;
  1349. case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
  1350. uint8_t *pQbuffer;
  1351. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1352. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1353. arcmsr_iop_message_read(acb);
  1354. }
  1355. acb->acb_flags |=
  1356. (ACB_F_MESSAGE_WQBUFFER_CLEARED
  1357. | ACB_F_MESSAGE_RQBUFFER_CLEARED
  1358. | ACB_F_MESSAGE_WQBUFFER_READED);
  1359. acb->rqbuf_firstindex = 0;
  1360. acb->rqbuf_lastindex = 0;
  1361. acb->wqbuf_firstindex = 0;
  1362. acb->wqbuf_lastindex = 0;
  1363. pQbuffer = acb->rqbuffer;
  1364. memset(pQbuffer, 0, sizeof(struct QBUFFER));
  1365. pQbuffer = acb->wqbuffer;
  1366. memset(pQbuffer, 0, sizeof(struct QBUFFER));
  1367. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
  1368. }
  1369. break;
  1370. case ARCMSR_MESSAGE_RETURN_CODE_3F: {
  1371. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
  1372. }
  1373. break;
  1374. case ARCMSR_MESSAGE_SAY_HELLO: {
  1375. int8_t *hello_string = "Hello! I am ARCMSR";
  1376. memcpy(pcmdmessagefld->messagedatabuffer, hello_string
  1377. , (int16_t)strlen(hello_string));
  1378. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
  1379. }
  1380. break;
  1381. case ARCMSR_MESSAGE_SAY_GOODBYE:
  1382. arcmsr_iop_parking(acb);
  1383. break;
  1384. case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
  1385. arcmsr_flush_adapter_cache(acb);
  1386. break;
  1387. default:
  1388. retvalue = ARCMSR_MESSAGE_FAIL;
  1389. }
  1390. message_out:
  1391. sg = scsi_sglist(cmd);
  1392. kunmap_atomic(buffer - sg->offset, KM_IRQ0);
  1393. return retvalue;
  1394. }
  1395. static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
  1396. {
  1397. struct list_head *head = &acb->ccb_free_list;
  1398. struct CommandControlBlock *ccb = NULL;
  1399. if (!list_empty(head)) {
  1400. ccb = list_entry(head->next, struct CommandControlBlock, list);
  1401. list_del(head->next);
  1402. }
  1403. return ccb;
  1404. }
  1405. static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
  1406. struct scsi_cmnd *cmd)
  1407. {
  1408. switch (cmd->cmnd[0]) {
  1409. case INQUIRY: {
  1410. unsigned char inqdata[36];
  1411. char *buffer;
  1412. struct scatterlist *sg;
  1413. if (cmd->device->lun) {
  1414. cmd->result = (DID_TIME_OUT << 16);
  1415. cmd->scsi_done(cmd);
  1416. return;
  1417. }
  1418. inqdata[0] = TYPE_PROCESSOR;
  1419. /* Periph Qualifier & Periph Dev Type */
  1420. inqdata[1] = 0;
  1421. /* rem media bit & Dev Type Modifier */
  1422. inqdata[2] = 0;
  1423. /* ISO, ECMA, & ANSI versions */
  1424. inqdata[4] = 31;
  1425. /* length of additional data */
  1426. strncpy(&inqdata[8], "Areca ", 8);
  1427. /* Vendor Identification */
  1428. strncpy(&inqdata[16], "RAID controller ", 16);
  1429. /* Product Identification */
  1430. strncpy(&inqdata[32], "R001", 4); /* Product Revision */
  1431. sg = scsi_sglist(cmd);
  1432. buffer = kmap_atomic(sg_page(sg), KM_IRQ0) + sg->offset;
  1433. memcpy(buffer, inqdata, sizeof(inqdata));
  1434. sg = scsi_sglist(cmd);
  1435. kunmap_atomic(buffer - sg->offset, KM_IRQ0);
  1436. cmd->scsi_done(cmd);
  1437. }
  1438. break;
  1439. case WRITE_BUFFER:
  1440. case READ_BUFFER: {
  1441. if (arcmsr_iop_message_xfer(acb, cmd))
  1442. cmd->result = (DID_ERROR << 16);
  1443. cmd->scsi_done(cmd);
  1444. }
  1445. break;
  1446. default:
  1447. cmd->scsi_done(cmd);
  1448. }
  1449. }
  1450. static int arcmsr_queue_command(struct scsi_cmnd *cmd,
  1451. void (* done)(struct scsi_cmnd *))
  1452. {
  1453. struct Scsi_Host *host = cmd->device->host;
  1454. struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
  1455. struct CommandControlBlock *ccb;
  1456. int target = cmd->device->id;
  1457. int lun = cmd->device->lun;
  1458. cmd->scsi_done = done;
  1459. cmd->host_scribble = NULL;
  1460. cmd->result = 0;
  1461. if (acb->acb_flags & ACB_F_BUS_RESET) {
  1462. printk(KERN_NOTICE "arcmsr%d: bus reset"
  1463. " and return busy \n"
  1464. , acb->host->host_no);
  1465. return SCSI_MLQUEUE_HOST_BUSY;
  1466. }
  1467. if (target == 16) {
  1468. /* virtual device for iop message transfer */
  1469. arcmsr_handle_virtual_command(acb, cmd);
  1470. return 0;
  1471. }
  1472. if (acb->devstate[target][lun] == ARECA_RAID_GONE) {
  1473. uint8_t block_cmd;
  1474. block_cmd = cmd->cmnd[0] & 0x0f;
  1475. if (block_cmd == 0x08 || block_cmd == 0x0a) {
  1476. printk(KERN_NOTICE
  1477. "arcmsr%d: block 'read/write'"
  1478. "command with gone raid volume"
  1479. " Cmd = %2x, TargetId = %d, Lun = %d \n"
  1480. , acb->host->host_no
  1481. , cmd->cmnd[0]
  1482. , target, lun);
  1483. cmd->result = (DID_NO_CONNECT << 16);
  1484. cmd->scsi_done(cmd);
  1485. return 0;
  1486. }
  1487. }
  1488. if (atomic_read(&acb->ccboutstandingcount) >=
  1489. ARCMSR_MAX_OUTSTANDING_CMD)
  1490. return SCSI_MLQUEUE_HOST_BUSY;
  1491. ccb = arcmsr_get_freeccb(acb);
  1492. if (!ccb)
  1493. return SCSI_MLQUEUE_HOST_BUSY;
  1494. if ( arcmsr_build_ccb( acb, ccb, cmd ) == FAILED ) {
  1495. cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1);
  1496. cmd->scsi_done(cmd);
  1497. return 0;
  1498. }
  1499. arcmsr_post_ccb(acb, ccb);
  1500. return 0;
  1501. }
  1502. static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)
  1503. {
  1504. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1505. char *acb_firm_model = acb->firm_model;
  1506. char *acb_firm_version = acb->firm_version;
  1507. char __iomem *iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]);
  1508. char __iomem *iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]);
  1509. int count;
  1510. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  1511. if (arcmsr_hba_wait_msgint_ready(acb)) {
  1512. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  1513. miscellaneous data' timeout \n", acb->host->host_no);
  1514. }
  1515. count = 8;
  1516. while (count) {
  1517. *acb_firm_model = readb(iop_firm_model);
  1518. acb_firm_model++;
  1519. iop_firm_model++;
  1520. count--;
  1521. }
  1522. count = 16;
  1523. while (count) {
  1524. *acb_firm_version = readb(iop_firm_version);
  1525. acb_firm_version++;
  1526. iop_firm_version++;
  1527. count--;
  1528. }
  1529. printk(KERN_INFO "ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n"
  1530. , acb->host->host_no
  1531. , acb->firm_version);
  1532. acb->firm_request_len = readl(&reg->message_rwbuffer[1]);
  1533. acb->firm_numbers_queue = readl(&reg->message_rwbuffer[2]);
  1534. acb->firm_sdram_size = readl(&reg->message_rwbuffer[3]);
  1535. acb->firm_hd_channels = readl(&reg->message_rwbuffer[4]);
  1536. }
  1537. static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
  1538. {
  1539. struct MessageUnit_B *reg = acb->pmuB;
  1540. uint32_t __iomem *lrwbuffer = reg->msgcode_rwbuffer_reg;
  1541. char *acb_firm_model = acb->firm_model;
  1542. char *acb_firm_version = acb->firm_version;
  1543. char __iomem *iop_firm_model = (char __iomem *)(&lrwbuffer[15]);
  1544. /*firm_model,15,60-67*/
  1545. char __iomem *iop_firm_version = (char __iomem *)(&lrwbuffer[17]);
  1546. /*firm_version,17,68-83*/
  1547. int count;
  1548. writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell_reg);
  1549. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  1550. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  1551. miscellaneous data' timeout \n", acb->host->host_no);
  1552. }
  1553. count = 8;
  1554. while (count)
  1555. {
  1556. *acb_firm_model = readb(iop_firm_model);
  1557. acb_firm_model++;
  1558. iop_firm_model++;
  1559. count--;
  1560. }
  1561. count = 16;
  1562. while (count)
  1563. {
  1564. *acb_firm_version = readb(iop_firm_version);
  1565. acb_firm_version++;
  1566. iop_firm_version++;
  1567. count--;
  1568. }
  1569. printk(KERN_INFO "ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n",
  1570. acb->host->host_no,
  1571. acb->firm_version);
  1572. lrwbuffer++;
  1573. acb->firm_request_len = readl(lrwbuffer++);
  1574. /*firm_request_len,1,04-07*/
  1575. acb->firm_numbers_queue = readl(lrwbuffer++);
  1576. /*firm_numbers_queue,2,08-11*/
  1577. acb->firm_sdram_size = readl(lrwbuffer++);
  1578. /*firm_sdram_size,3,12-15*/
  1579. acb->firm_hd_channels = readl(lrwbuffer);
  1580. /*firm_ide_channels,4,16-19*/
  1581. }
  1582. static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
  1583. {
  1584. switch (acb->adapter_type) {
  1585. case ACB_ADAPTER_TYPE_A: {
  1586. arcmsr_get_hba_config(acb);
  1587. }
  1588. break;
  1589. case ACB_ADAPTER_TYPE_B: {
  1590. arcmsr_get_hbb_config(acb);
  1591. }
  1592. break;
  1593. }
  1594. }
  1595. static void arcmsr_polling_hba_ccbdone(struct AdapterControlBlock *acb,
  1596. struct CommandControlBlock *poll_ccb)
  1597. {
  1598. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1599. struct CommandControlBlock *ccb;
  1600. uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
  1601. polling_hba_ccb_retry:
  1602. poll_count++;
  1603. outbound_intstatus = readl(&reg->outbound_intstatus) & acb->outbound_int_enable;
  1604. writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
  1605. while (1) {
  1606. if ((flag_ccb = readl(&reg->outbound_queueport)) == 0xFFFFFFFF) {
  1607. if (poll_ccb_done)
  1608. break;
  1609. else {
  1610. msleep(25);
  1611. if (poll_count > 100)
  1612. break;
  1613. goto polling_hba_ccb_retry;
  1614. }
  1615. }
  1616. ccb = (struct CommandControlBlock *)(acb->vir2phy_offset + (flag_ccb << 5));
  1617. poll_ccb_done = (ccb == poll_ccb) ? 1:0;
  1618. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  1619. if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
  1620. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  1621. " poll command abort successfully \n"
  1622. , acb->host->host_no
  1623. , ccb->pcmd->device->id
  1624. , ccb->pcmd->device->lun
  1625. , ccb);
  1626. ccb->pcmd->result = DID_ABORT << 16;
  1627. arcmsr_ccb_complete(ccb, 1);
  1628. poll_ccb_done = 1;
  1629. continue;
  1630. }
  1631. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  1632. " command done ccb = '0x%p'"
  1633. "ccboutstandingcount = %d \n"
  1634. , acb->host->host_no
  1635. , ccb
  1636. , atomic_read(&acb->ccboutstandingcount));
  1637. continue;
  1638. }
  1639. arcmsr_report_ccb_state(acb, ccb, flag_ccb);
  1640. }
  1641. }
  1642. static void arcmsr_polling_hbb_ccbdone(struct AdapterControlBlock *acb,
  1643. struct CommandControlBlock *poll_ccb)
  1644. {
  1645. struct MessageUnit_B *reg = acb->pmuB;
  1646. struct CommandControlBlock *ccb;
  1647. uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
  1648. int index;
  1649. polling_hbb_ccb_retry:
  1650. poll_count++;
  1651. /* clear doorbell interrupt */
  1652. writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell_reg);
  1653. while (1) {
  1654. index = reg->doneq_index;
  1655. if ((flag_ccb = readl(&reg->done_qbuffer[index])) == 0) {
  1656. if (poll_ccb_done)
  1657. break;
  1658. else {
  1659. msleep(25);
  1660. if (poll_count > 100)
  1661. break;
  1662. goto polling_hbb_ccb_retry;
  1663. }
  1664. }
  1665. writel(0, &reg->done_qbuffer[index]);
  1666. index++;
  1667. /*if last index number set it to 0 */
  1668. index %= ARCMSR_MAX_HBB_POSTQUEUE;
  1669. reg->doneq_index = index;
  1670. /* check ifcommand done with no error*/
  1671. ccb = (struct CommandControlBlock *)\
  1672. (acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
  1673. poll_ccb_done = (ccb == poll_ccb) ? 1:0;
  1674. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  1675. if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
  1676. printk(KERN_NOTICE "arcmsr%d: \
  1677. scsi id = %d lun = %d ccb = '0x%p' poll command abort successfully \n"
  1678. ,acb->host->host_no
  1679. ,ccb->pcmd->device->id
  1680. ,ccb->pcmd->device->lun
  1681. ,ccb);
  1682. ccb->pcmd->result = DID_ABORT << 16;
  1683. arcmsr_ccb_complete(ccb, 1);
  1684. continue;
  1685. }
  1686. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  1687. " command done ccb = '0x%p'"
  1688. "ccboutstandingcount = %d \n"
  1689. , acb->host->host_no
  1690. , ccb
  1691. , atomic_read(&acb->ccboutstandingcount));
  1692. continue;
  1693. }
  1694. arcmsr_report_ccb_state(acb, ccb, flag_ccb);
  1695. } /*drain reply FIFO*/
  1696. }
  1697. static void arcmsr_polling_ccbdone(struct AdapterControlBlock *acb,
  1698. struct CommandControlBlock *poll_ccb)
  1699. {
  1700. switch (acb->adapter_type) {
  1701. case ACB_ADAPTER_TYPE_A: {
  1702. arcmsr_polling_hba_ccbdone(acb,poll_ccb);
  1703. }
  1704. break;
  1705. case ACB_ADAPTER_TYPE_B: {
  1706. arcmsr_polling_hbb_ccbdone(acb,poll_ccb);
  1707. }
  1708. }
  1709. }
  1710. static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
  1711. {
  1712. uint32_t cdb_phyaddr, ccb_phyaddr_hi32;
  1713. dma_addr_t dma_coherent_handle;
  1714. /*
  1715. ********************************************************************
  1716. ** here we need to tell iop 331 our freeccb.HighPart
  1717. ** if freeccb.HighPart is not zero
  1718. ********************************************************************
  1719. */
  1720. dma_coherent_handle = acb->dma_coherent_handle;
  1721. cdb_phyaddr = (uint32_t)(dma_coherent_handle);
  1722. ccb_phyaddr_hi32 = (uint32_t)((cdb_phyaddr >> 16) >> 16);
  1723. /*
  1724. ***********************************************************************
  1725. ** if adapter type B, set window of "post command Q"
  1726. ***********************************************************************
  1727. */
  1728. switch (acb->adapter_type) {
  1729. case ACB_ADAPTER_TYPE_A: {
  1730. if (ccb_phyaddr_hi32 != 0) {
  1731. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1732. uint32_t intmask_org;
  1733. intmask_org = arcmsr_disable_outbound_ints(acb);
  1734. writel(ARCMSR_SIGNATURE_SET_CONFIG, \
  1735. &reg->message_rwbuffer[0]);
  1736. writel(ccb_phyaddr_hi32, &reg->message_rwbuffer[1]);
  1737. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
  1738. &reg->inbound_msgaddr0);
  1739. if (arcmsr_hba_wait_msgint_ready(acb)) {
  1740. printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
  1741. part physical address timeout\n",
  1742. acb->host->host_no);
  1743. return 1;
  1744. }
  1745. arcmsr_enable_outbound_ints(acb, intmask_org);
  1746. }
  1747. }
  1748. break;
  1749. case ACB_ADAPTER_TYPE_B: {
  1750. unsigned long post_queue_phyaddr;
  1751. uint32_t __iomem *rwbuffer;
  1752. struct MessageUnit_B *reg = acb->pmuB;
  1753. uint32_t intmask_org;
  1754. intmask_org = arcmsr_disable_outbound_ints(acb);
  1755. reg->postq_index = 0;
  1756. reg->doneq_index = 0;
  1757. writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell_reg);
  1758. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  1759. printk(KERN_NOTICE "arcmsr%d:can not set diver mode\n", \
  1760. acb->host->host_no);
  1761. return 1;
  1762. }
  1763. post_queue_phyaddr = cdb_phyaddr + ARCMSR_MAX_FREECCB_NUM * \
  1764. sizeof(struct CommandControlBlock) + offsetof(struct MessageUnit_B, post_qbuffer) ;
  1765. rwbuffer = reg->msgcode_rwbuffer_reg;
  1766. /* driver "set config" signature */
  1767. writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
  1768. /* normal should be zero */
  1769. writel(ccb_phyaddr_hi32, rwbuffer++);
  1770. /* postQ size (256 + 8)*4 */
  1771. writel(post_queue_phyaddr, rwbuffer++);
  1772. /* doneQ size (256 + 8)*4 */
  1773. writel(post_queue_phyaddr + 1056, rwbuffer++);
  1774. /* ccb maxQ size must be --> [(256 + 8)*4]*/
  1775. writel(1056, rwbuffer);
  1776. writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell_reg);
  1777. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  1778. printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
  1779. timeout \n",acb->host->host_no);
  1780. return 1;
  1781. }
  1782. writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell_reg);
  1783. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  1784. printk(KERN_NOTICE "arcmsr%d: 'can not set diver mode \n"\
  1785. ,acb->host->host_no);
  1786. return 1;
  1787. }
  1788. arcmsr_enable_outbound_ints(acb, intmask_org);
  1789. }
  1790. break;
  1791. }
  1792. return 0;
  1793. }
  1794. static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
  1795. {
  1796. uint32_t firmware_state = 0;
  1797. switch (acb->adapter_type) {
  1798. case ACB_ADAPTER_TYPE_A: {
  1799. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1800. do {
  1801. firmware_state = readl(&reg->outbound_msgaddr1);
  1802. } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
  1803. }
  1804. break;
  1805. case ACB_ADAPTER_TYPE_B: {
  1806. struct MessageUnit_B *reg = acb->pmuB;
  1807. do {
  1808. firmware_state = readl(reg->iop2drv_doorbell_reg);
  1809. } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
  1810. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell_reg);
  1811. }
  1812. break;
  1813. }
  1814. }
  1815. static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
  1816. {
  1817. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1818. acb->acb_flags |= ACB_F_MSG_START_BGRB;
  1819. writel(ARCMSR_INBOUND_MESG0_START_BGRB, &reg->inbound_msgaddr0);
  1820. if (arcmsr_hba_wait_msgint_ready(acb)) {
  1821. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  1822. rebulid' timeout \n", acb->host->host_no);
  1823. }
  1824. }
  1825. static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
  1826. {
  1827. struct MessageUnit_B *reg = acb->pmuB;
  1828. acb->acb_flags |= ACB_F_MSG_START_BGRB;
  1829. writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell_reg);
  1830. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  1831. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  1832. rebulid' timeout \n",acb->host->host_no);
  1833. }
  1834. }
  1835. static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
  1836. {
  1837. switch (acb->adapter_type) {
  1838. case ACB_ADAPTER_TYPE_A:
  1839. arcmsr_start_hba_bgrb(acb);
  1840. break;
  1841. case ACB_ADAPTER_TYPE_B:
  1842. arcmsr_start_hbb_bgrb(acb);
  1843. break;
  1844. }
  1845. }
  1846. static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
  1847. {
  1848. switch (acb->adapter_type) {
  1849. case ACB_ADAPTER_TYPE_A: {
  1850. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1851. uint32_t outbound_doorbell;
  1852. /* empty doorbell Qbuffer if door bell ringed */
  1853. outbound_doorbell = readl(&reg->outbound_doorbell);
  1854. /*clear doorbell interrupt */
  1855. writel(outbound_doorbell, &reg->outbound_doorbell);
  1856. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  1857. }
  1858. break;
  1859. case ACB_ADAPTER_TYPE_B: {
  1860. struct MessageUnit_B *reg = acb->pmuB;
  1861. /*clear interrupt and message state*/
  1862. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell_reg);
  1863. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell_reg);
  1864. /* let IOP know data has been read */
  1865. }
  1866. break;
  1867. }
  1868. }
  1869. static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
  1870. {
  1871. switch (acb->adapter_type) {
  1872. case ACB_ADAPTER_TYPE_A:
  1873. return;
  1874. case ACB_ADAPTER_TYPE_B:
  1875. {
  1876. struct MessageUnit_B *reg = acb->pmuB;
  1877. writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell_reg);
  1878. if(arcmsr_hbb_wait_msgint_ready(acb)) {
  1879. printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT");
  1880. return;
  1881. }
  1882. }
  1883. break;
  1884. }
  1885. return;
  1886. }
  1887. static void arcmsr_iop_init(struct AdapterControlBlock *acb)
  1888. {
  1889. uint32_t intmask_org;
  1890. /* disable all outbound interrupt */
  1891. intmask_org = arcmsr_disable_outbound_ints(acb);
  1892. arcmsr_wait_firmware_ready(acb);
  1893. arcmsr_iop_confirm(acb);
  1894. arcmsr_get_firmware_spec(acb);
  1895. /*start background rebuild*/
  1896. arcmsr_start_adapter_bgrb(acb);
  1897. /* empty doorbell Qbuffer if door bell ringed */
  1898. arcmsr_clear_doorbell_queue_buffer(acb);
  1899. arcmsr_enable_eoi_mode(acb);
  1900. /* enable outbound Post Queue,outbound doorbell Interrupt */
  1901. arcmsr_enable_outbound_ints(acb, intmask_org);
  1902. acb->acb_flags |= ACB_F_IOP_INITED;
  1903. }
  1904. static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
  1905. {
  1906. struct CommandControlBlock *ccb;
  1907. uint32_t intmask_org;
  1908. int i = 0;
  1909. if (atomic_read(&acb->ccboutstandingcount) != 0) {
  1910. /* talk to iop 331 outstanding command aborted */
  1911. arcmsr_abort_allcmd(acb);
  1912. /* wait for 3 sec for all command aborted*/
  1913. ssleep(3);
  1914. /* disable all outbound interrupt */
  1915. intmask_org = arcmsr_disable_outbound_ints(acb);
  1916. /* clear all outbound posted Q */
  1917. arcmsr_done4abort_postqueue(acb);
  1918. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  1919. ccb = acb->pccb_pool[i];
  1920. if (ccb->startdone == ARCMSR_CCB_START) {
  1921. ccb->startdone = ARCMSR_CCB_ABORTED;
  1922. arcmsr_ccb_complete(ccb, 1);
  1923. }
  1924. }
  1925. /* enable all outbound interrupt */
  1926. arcmsr_enable_outbound_ints(acb, intmask_org);
  1927. }
  1928. }
  1929. static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
  1930. {
  1931. struct AdapterControlBlock *acb =
  1932. (struct AdapterControlBlock *)cmd->device->host->hostdata;
  1933. int i;
  1934. acb->num_resets++;
  1935. acb->acb_flags |= ACB_F_BUS_RESET;
  1936. for (i = 0; i < 400; i++) {
  1937. if (!atomic_read(&acb->ccboutstandingcount))
  1938. break;
  1939. arcmsr_interrupt(acb);/* FIXME: need spinlock */
  1940. msleep(25);
  1941. }
  1942. arcmsr_iop_reset(acb);
  1943. acb->acb_flags &= ~ACB_F_BUS_RESET;
  1944. return SUCCESS;
  1945. }
  1946. static void arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
  1947. struct CommandControlBlock *ccb)
  1948. {
  1949. u32 intmask;
  1950. ccb->startdone = ARCMSR_CCB_ABORTED;
  1951. /*
  1952. ** Wait for 3 sec for all command done.
  1953. */
  1954. ssleep(3);
  1955. intmask = arcmsr_disable_outbound_ints(acb);
  1956. arcmsr_polling_ccbdone(acb, ccb);
  1957. arcmsr_enable_outbound_ints(acb, intmask);
  1958. }
  1959. static int arcmsr_abort(struct scsi_cmnd *cmd)
  1960. {
  1961. struct AdapterControlBlock *acb =
  1962. (struct AdapterControlBlock *)cmd->device->host->hostdata;
  1963. int i = 0;
  1964. printk(KERN_NOTICE
  1965. "arcmsr%d: abort device command of scsi id = %d lun = %d \n",
  1966. acb->host->host_no, cmd->device->id, cmd->device->lun);
  1967. acb->num_aborts++;
  1968. /*
  1969. ************************************************
  1970. ** the all interrupt service routine is locked
  1971. ** we need to handle it as soon as possible and exit
  1972. ************************************************
  1973. */
  1974. if (!atomic_read(&acb->ccboutstandingcount))
  1975. return SUCCESS;
  1976. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  1977. struct CommandControlBlock *ccb = acb->pccb_pool[i];
  1978. if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
  1979. arcmsr_abort_one_cmd(acb, ccb);
  1980. break;
  1981. }
  1982. }
  1983. return SUCCESS;
  1984. }
  1985. static const char *arcmsr_info(struct Scsi_Host *host)
  1986. {
  1987. struct AdapterControlBlock *acb =
  1988. (struct AdapterControlBlock *) host->hostdata;
  1989. static char buf[256];
  1990. char *type;
  1991. int raid6 = 1;
  1992. switch (acb->pdev->device) {
  1993. case PCI_DEVICE_ID_ARECA_1110:
  1994. case PCI_DEVICE_ID_ARECA_1200:
  1995. case PCI_DEVICE_ID_ARECA_1202:
  1996. case PCI_DEVICE_ID_ARECA_1210:
  1997. raid6 = 0;
  1998. /*FALLTHRU*/
  1999. case PCI_DEVICE_ID_ARECA_1120:
  2000. case PCI_DEVICE_ID_ARECA_1130:
  2001. case PCI_DEVICE_ID_ARECA_1160:
  2002. case PCI_DEVICE_ID_ARECA_1170:
  2003. case PCI_DEVICE_ID_ARECA_1201:
  2004. case PCI_DEVICE_ID_ARECA_1220:
  2005. case PCI_DEVICE_ID_ARECA_1230:
  2006. case PCI_DEVICE_ID_ARECA_1260:
  2007. case PCI_DEVICE_ID_ARECA_1270:
  2008. case PCI_DEVICE_ID_ARECA_1280:
  2009. type = "SATA";
  2010. break;
  2011. case PCI_DEVICE_ID_ARECA_1380:
  2012. case PCI_DEVICE_ID_ARECA_1381:
  2013. case PCI_DEVICE_ID_ARECA_1680:
  2014. case PCI_DEVICE_ID_ARECA_1681:
  2015. type = "SAS";
  2016. break;
  2017. default:
  2018. type = "X-TYPE";
  2019. break;
  2020. }
  2021. sprintf(buf, "Areca %s Host Adapter RAID Controller%s\n %s",
  2022. type, raid6 ? "( RAID6 capable)" : "",
  2023. ARCMSR_DRIVER_VERSION);
  2024. return buf;
  2025. }
  2026. #ifdef CONFIG_SCSI_ARCMSR_AER
  2027. static pci_ers_result_t arcmsr_pci_slot_reset(struct pci_dev *pdev)
  2028. {
  2029. struct Scsi_Host *host = pci_get_drvdata(pdev);
  2030. struct AdapterControlBlock *acb =
  2031. (struct AdapterControlBlock *) host->hostdata;
  2032. uint32_t intmask_org;
  2033. int i, j;
  2034. if (pci_enable_device(pdev)) {
  2035. return PCI_ERS_RESULT_DISCONNECT;
  2036. }
  2037. pci_set_master(pdev);
  2038. intmask_org = arcmsr_disable_outbound_ints(acb);
  2039. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  2040. ACB_F_MESSAGE_RQBUFFER_CLEARED |
  2041. ACB_F_MESSAGE_WQBUFFER_READED);
  2042. acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
  2043. for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
  2044. for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
  2045. acb->devstate[i][j] = ARECA_RAID_GONE;
  2046. arcmsr_wait_firmware_ready(acb);
  2047. arcmsr_iop_confirm(acb);
  2048. /* disable all outbound interrupt */
  2049. arcmsr_get_firmware_spec(acb);
  2050. /*start background rebuild*/
  2051. arcmsr_start_adapter_bgrb(acb);
  2052. /* empty doorbell Qbuffer if door bell ringed */
  2053. arcmsr_clear_doorbell_queue_buffer(acb);
  2054. arcmsr_enable_eoi_mode(acb);
  2055. /* enable outbound Post Queue,outbound doorbell Interrupt */
  2056. arcmsr_enable_outbound_ints(acb, intmask_org);
  2057. acb->acb_flags |= ACB_F_IOP_INITED;
  2058. pci_enable_pcie_error_reporting(pdev);
  2059. return PCI_ERS_RESULT_RECOVERED;
  2060. }
  2061. static void arcmsr_pci_ers_need_reset_forepart(struct pci_dev *pdev)
  2062. {
  2063. struct Scsi_Host *host = pci_get_drvdata(pdev);
  2064. struct AdapterControlBlock *acb = (struct AdapterControlBlock *)host->hostdata;
  2065. struct CommandControlBlock *ccb;
  2066. uint32_t intmask_org;
  2067. int i = 0;
  2068. if (atomic_read(&acb->ccboutstandingcount) != 0) {
  2069. /* talk to iop 331 outstanding command aborted */
  2070. arcmsr_abort_allcmd(acb);
  2071. /* wait for 3 sec for all command aborted*/
  2072. ssleep(3);
  2073. /* disable all outbound interrupt */
  2074. intmask_org = arcmsr_disable_outbound_ints(acb);
  2075. /* clear all outbound posted Q */
  2076. arcmsr_done4abort_postqueue(acb);
  2077. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  2078. ccb = acb->pccb_pool[i];
  2079. if (ccb->startdone == ARCMSR_CCB_START) {
  2080. ccb->startdone = ARCMSR_CCB_ABORTED;
  2081. arcmsr_ccb_complete(ccb, 1);
  2082. }
  2083. }
  2084. /* enable all outbound interrupt */
  2085. arcmsr_enable_outbound_ints(acb, intmask_org);
  2086. }
  2087. pci_disable_device(pdev);
  2088. }
  2089. static void arcmsr_pci_ers_disconnect_forepart(struct pci_dev *pdev)
  2090. {
  2091. struct Scsi_Host *host = pci_get_drvdata(pdev);
  2092. struct AdapterControlBlock *acb = \
  2093. (struct AdapterControlBlock *)host->hostdata;
  2094. arcmsr_stop_adapter_bgrb(acb);
  2095. arcmsr_flush_adapter_cache(acb);
  2096. }
  2097. static pci_ers_result_t arcmsr_pci_error_detected(struct pci_dev *pdev,
  2098. pci_channel_state_t state)
  2099. {
  2100. switch (state) {
  2101. case pci_channel_io_frozen:
  2102. arcmsr_pci_ers_need_reset_forepart(pdev);
  2103. return PCI_ERS_RESULT_NEED_RESET;
  2104. case pci_channel_io_perm_failure:
  2105. arcmsr_pci_ers_disconnect_forepart(pdev);
  2106. return PCI_ERS_RESULT_DISCONNECT;
  2107. break;
  2108. default:
  2109. return PCI_ERS_RESULT_NEED_RESET;
  2110. }
  2111. }
  2112. #endif