aerdrv.h 3.1 KB

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  1. /*
  2. * Copyright (C) 2006 Intel Corp.
  3. * Tom Long Nguyen (tom.l.nguyen@intel.com)
  4. * Zhang Yanmin (yanmin.zhang@intel.com)
  5. *
  6. */
  7. #ifndef _AERDRV_H_
  8. #define _AERDRV_H_
  9. #include <linux/workqueue.h>
  10. #include <linux/pcieport_if.h>
  11. #include <linux/aer.h>
  12. #define AER_NONFATAL 0
  13. #define AER_FATAL 1
  14. #define AER_CORRECTABLE 2
  15. #define AER_UNCORRECTABLE 4
  16. #define AER_ERROR_MASK 0x001fffff
  17. #define AER_ERROR(d) (d & AER_ERROR_MASK)
  18. /* Root Error Status Register Bits */
  19. #define ROOT_ERR_STATUS_MASKS 0x0f
  20. #define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
  21. PCI_EXP_RTCTL_SENFEE| \
  22. PCI_EXP_RTCTL_SEFEE)
  23. #define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
  24. PCI_ERR_ROOT_CMD_NONFATAL_EN| \
  25. PCI_ERR_ROOT_CMD_FATAL_EN)
  26. #define ERR_COR_ID(d) (d & 0xffff)
  27. #define ERR_UNCOR_ID(d) (d >> 16)
  28. #define AER_SUCCESS 0
  29. #define AER_UNSUCCESS 1
  30. #define AER_ERROR_SOURCES_MAX 100
  31. #define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
  32. PCI_ERR_UNC_ECRC| \
  33. PCI_ERR_UNC_UNSUP| \
  34. PCI_ERR_UNC_COMP_ABORT| \
  35. PCI_ERR_UNC_UNX_COMP| \
  36. PCI_ERR_UNC_MALF_TLP)
  37. /* AER Error Info Flags */
  38. #define AER_TLP_HEADER_VALID_FLAG 0x00000001
  39. #define AER_MULTI_ERROR_VALID_FLAG 0x00000002
  40. #define ERR_CORRECTABLE_ERROR_MASK 0x000031c1
  41. #define ERR_UNCORRECTABLE_ERROR_MASK 0x001ff010
  42. struct header_log_regs {
  43. unsigned int dw0;
  44. unsigned int dw1;
  45. unsigned int dw2;
  46. unsigned int dw3;
  47. };
  48. struct aer_err_info {
  49. int severity; /* 0:NONFATAL | 1:FATAL | 2:COR */
  50. int flags;
  51. unsigned int status; /* COR/UNCOR Error Status */
  52. struct header_log_regs tlp; /* TLP Header */
  53. };
  54. struct aer_err_source {
  55. unsigned int status;
  56. unsigned int id;
  57. };
  58. struct aer_rpc {
  59. struct pcie_device *rpd; /* Root Port device */
  60. struct work_struct dpc_handler;
  61. struct aer_err_source e_sources[AER_ERROR_SOURCES_MAX];
  62. unsigned short prod_idx; /* Error Producer Index */
  63. unsigned short cons_idx; /* Error Consumer Index */
  64. int isr;
  65. spinlock_t e_lock; /*
  66. * Lock access to Error Status/ID Regs
  67. * and error producer/consumer index
  68. */
  69. struct mutex rpc_mutex; /*
  70. * only one thread could do
  71. * recovery on the same
  72. * root port hierarchy
  73. */
  74. wait_queue_head_t wait_release;
  75. };
  76. struct aer_broadcast_data {
  77. enum pci_channel_state state;
  78. enum pci_ers_result result;
  79. };
  80. static inline pci_ers_result_t merge_result(enum pci_ers_result orig,
  81. enum pci_ers_result new)
  82. {
  83. switch (orig) {
  84. case PCI_ERS_RESULT_CAN_RECOVER:
  85. case PCI_ERS_RESULT_RECOVERED:
  86. orig = new;
  87. break;
  88. case PCI_ERS_RESULT_DISCONNECT:
  89. if (new == PCI_ERS_RESULT_NEED_RESET)
  90. orig = new;
  91. break;
  92. default:
  93. break;
  94. }
  95. return orig;
  96. }
  97. extern struct bus_type pcie_port_bus_type;
  98. extern void aer_enable_rootport(struct aer_rpc *rpc);
  99. extern void aer_delete_rootport(struct aer_rpc *rpc);
  100. extern int aer_init(struct pcie_device *dev);
  101. extern void aer_isr(struct work_struct *work);
  102. extern void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
  103. #ifdef CONFIG_ACPI
  104. extern int aer_osc_setup(struct pcie_device *pciedev);
  105. #else
  106. static inline int aer_osc_setup(struct pcie_device *pciedev)
  107. {
  108. return 0;
  109. }
  110. #endif
  111. #endif //_AERDRV_H_