zd_rf_al2230.c 12 KB

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  1. /* ZD1211 USB-WLAN driver for Linux
  2. *
  3. * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
  4. * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. */
  20. #include <linux/kernel.h>
  21. #include "zd_rf.h"
  22. #include "zd_usb.h"
  23. #include "zd_chip.h"
  24. #define IS_AL2230S(chip) ((chip)->al2230s_bit || (chip)->rf.type == AL2230S_RF)
  25. static const u32 zd1211_al2230_table[][3] = {
  26. RF_CHANNEL( 1) = { 0x03f790, 0x033331, 0x00000d, },
  27. RF_CHANNEL( 2) = { 0x03f790, 0x0b3331, 0x00000d, },
  28. RF_CHANNEL( 3) = { 0x03e790, 0x033331, 0x00000d, },
  29. RF_CHANNEL( 4) = { 0x03e790, 0x0b3331, 0x00000d, },
  30. RF_CHANNEL( 5) = { 0x03f7a0, 0x033331, 0x00000d, },
  31. RF_CHANNEL( 6) = { 0x03f7a0, 0x0b3331, 0x00000d, },
  32. RF_CHANNEL( 7) = { 0x03e7a0, 0x033331, 0x00000d, },
  33. RF_CHANNEL( 8) = { 0x03e7a0, 0x0b3331, 0x00000d, },
  34. RF_CHANNEL( 9) = { 0x03f7b0, 0x033331, 0x00000d, },
  35. RF_CHANNEL(10) = { 0x03f7b0, 0x0b3331, 0x00000d, },
  36. RF_CHANNEL(11) = { 0x03e7b0, 0x033331, 0x00000d, },
  37. RF_CHANNEL(12) = { 0x03e7b0, 0x0b3331, 0x00000d, },
  38. RF_CHANNEL(13) = { 0x03f7c0, 0x033331, 0x00000d, },
  39. RF_CHANNEL(14) = { 0x03e7c0, 0x066661, 0x00000d, },
  40. };
  41. static const u32 zd1211b_al2230_table[][3] = {
  42. RF_CHANNEL( 1) = { 0x09efc0, 0x8cccc0, 0xb00000, },
  43. RF_CHANNEL( 2) = { 0x09efc0, 0x8cccd0, 0xb00000, },
  44. RF_CHANNEL( 3) = { 0x09e7c0, 0x8cccc0, 0xb00000, },
  45. RF_CHANNEL( 4) = { 0x09e7c0, 0x8cccd0, 0xb00000, },
  46. RF_CHANNEL( 5) = { 0x05efc0, 0x8cccc0, 0xb00000, },
  47. RF_CHANNEL( 6) = { 0x05efc0, 0x8cccd0, 0xb00000, },
  48. RF_CHANNEL( 7) = { 0x05e7c0, 0x8cccc0, 0xb00000, },
  49. RF_CHANNEL( 8) = { 0x05e7c0, 0x8cccd0, 0xb00000, },
  50. RF_CHANNEL( 9) = { 0x0defc0, 0x8cccc0, 0xb00000, },
  51. RF_CHANNEL(10) = { 0x0defc0, 0x8cccd0, 0xb00000, },
  52. RF_CHANNEL(11) = { 0x0de7c0, 0x8cccc0, 0xb00000, },
  53. RF_CHANNEL(12) = { 0x0de7c0, 0x8cccd0, 0xb00000, },
  54. RF_CHANNEL(13) = { 0x03efc0, 0x8cccc0, 0xb00000, },
  55. RF_CHANNEL(14) = { 0x03e7c0, 0x866660, 0xb00000, },
  56. };
  57. static const struct zd_ioreq16 zd1211b_ioreqs_shared_1[] = {
  58. { CR240, 0x57 }, { CR9, 0xe0 },
  59. };
  60. static const struct zd_ioreq16 ioreqs_init_al2230s[] = {
  61. { CR47, 0x1e }, /* MARK_002 */
  62. { CR106, 0x22 },
  63. { CR107, 0x2a }, /* MARK_002 */
  64. { CR109, 0x13 }, /* MARK_002 */
  65. { CR118, 0xf8 }, /* MARK_002 */
  66. { CR119, 0x12 }, { CR122, 0xe0 },
  67. { CR128, 0x10 }, /* MARK_001 from 0xe->0x10 */
  68. { CR129, 0x0e }, /* MARK_001 from 0xd->0x0e */
  69. { CR130, 0x10 }, /* MARK_001 from 0xb->0x0d */
  70. };
  71. static int zd1211b_al2230_finalize_rf(struct zd_chip *chip)
  72. {
  73. int r;
  74. static const struct zd_ioreq16 ioreqs[] = {
  75. { CR80, 0x30 }, { CR81, 0x30 }, { CR79, 0x58 },
  76. { CR12, 0xf0 }, { CR77, 0x1b }, { CR78, 0x58 },
  77. { CR203, 0x06 },
  78. { },
  79. { CR240, 0x80 },
  80. };
  81. r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  82. if (r)
  83. return r;
  84. /* related to antenna selection? */
  85. if (chip->new_phy_layout) {
  86. r = zd_iowrite16_locked(chip, 0xe1, CR9);
  87. if (r)
  88. return r;
  89. }
  90. return zd_iowrite16_locked(chip, 0x06, CR203);
  91. }
  92. static int zd1211_al2230_init_hw(struct zd_rf *rf)
  93. {
  94. int r;
  95. struct zd_chip *chip = zd_rf_to_chip(rf);
  96. static const struct zd_ioreq16 ioreqs_init[] = {
  97. { CR15, 0x20 }, { CR23, 0x40 }, { CR24, 0x20 },
  98. { CR26, 0x11 }, { CR28, 0x3e }, { CR29, 0x00 },
  99. { CR44, 0x33 }, { CR106, 0x2a }, { CR107, 0x1a },
  100. { CR109, 0x09 }, { CR110, 0x27 }, { CR111, 0x2b },
  101. { CR112, 0x2b }, { CR119, 0x0a }, { CR10, 0x89 },
  102. /* for newest (3rd cut) AL2300 */
  103. { CR17, 0x28 },
  104. { CR26, 0x93 }, { CR34, 0x30 },
  105. /* for newest (3rd cut) AL2300 */
  106. { CR35, 0x3e },
  107. { CR41, 0x24 }, { CR44, 0x32 },
  108. /* for newest (3rd cut) AL2300 */
  109. { CR46, 0x96 },
  110. { CR47, 0x1e }, { CR79, 0x58 }, { CR80, 0x30 },
  111. { CR81, 0x30 }, { CR87, 0x0a }, { CR89, 0x04 },
  112. { CR92, 0x0a }, { CR99, 0x28 }, { CR100, 0x00 },
  113. { CR101, 0x13 }, { CR102, 0x27 }, { CR106, 0x24 },
  114. { CR107, 0x2a }, { CR109, 0x09 }, { CR110, 0x13 },
  115. { CR111, 0x1f }, { CR112, 0x1f }, { CR113, 0x27 },
  116. { CR114, 0x27 },
  117. /* for newest (3rd cut) AL2300 */
  118. { CR115, 0x24 },
  119. { CR116, 0x24 }, { CR117, 0xf4 }, { CR118, 0xfc },
  120. { CR119, 0x10 }, { CR120, 0x4f }, { CR121, 0x77 },
  121. { CR122, 0xe0 }, { CR137, 0x88 }, { CR252, 0xff },
  122. { CR253, 0xff },
  123. };
  124. static const struct zd_ioreq16 ioreqs_pll[] = {
  125. /* shdnb(PLL_ON)=0 */
  126. { CR251, 0x2f },
  127. /* shdnb(PLL_ON)=1 */
  128. { CR251, 0x3f },
  129. { CR138, 0x28 }, { CR203, 0x06 },
  130. };
  131. static const u32 rv1[] = {
  132. /* Channel 1 */
  133. 0x03f790,
  134. 0x033331,
  135. 0x00000d,
  136. 0x0b3331,
  137. 0x03b812,
  138. 0x00fff3,
  139. };
  140. static const u32 rv2[] = {
  141. 0x000da4,
  142. 0x0f4dc5, /* fix freq shift, 0x04edc5 */
  143. 0x0805b6,
  144. 0x011687,
  145. 0x000688,
  146. 0x0403b9, /* external control TX power (CR31) */
  147. 0x00dbba,
  148. 0x00099b,
  149. 0x0bdffc,
  150. 0x00000d,
  151. 0x00500f,
  152. };
  153. static const u32 rv3[] = {
  154. 0x00d00f,
  155. 0x004c0f,
  156. 0x00540f,
  157. 0x00700f,
  158. 0x00500f,
  159. };
  160. r = zd_iowrite16a_locked(chip, ioreqs_init, ARRAY_SIZE(ioreqs_init));
  161. if (r)
  162. return r;
  163. if (IS_AL2230S(chip)) {
  164. r = zd_iowrite16a_locked(chip, ioreqs_init_al2230s,
  165. ARRAY_SIZE(ioreqs_init_al2230s));
  166. if (r)
  167. return r;
  168. }
  169. r = zd_rfwritev_locked(chip, rv1, ARRAY_SIZE(rv1), RF_RV_BITS);
  170. if (r)
  171. return r;
  172. /* improve band edge for AL2230S */
  173. if (IS_AL2230S(chip))
  174. r = zd_rfwrite_locked(chip, 0x000824, RF_RV_BITS);
  175. else
  176. r = zd_rfwrite_locked(chip, 0x0005a4, RF_RV_BITS);
  177. if (r)
  178. return r;
  179. r = zd_rfwritev_locked(chip, rv2, ARRAY_SIZE(rv2), RF_RV_BITS);
  180. if (r)
  181. return r;
  182. r = zd_iowrite16a_locked(chip, ioreqs_pll, ARRAY_SIZE(ioreqs_pll));
  183. if (r)
  184. return r;
  185. r = zd_rfwritev_locked(chip, rv3, ARRAY_SIZE(rv3), RF_RV_BITS);
  186. if (r)
  187. return r;
  188. return 0;
  189. }
  190. static int zd1211b_al2230_init_hw(struct zd_rf *rf)
  191. {
  192. int r;
  193. struct zd_chip *chip = zd_rf_to_chip(rf);
  194. static const struct zd_ioreq16 ioreqs1[] = {
  195. { CR10, 0x89 }, { CR15, 0x20 },
  196. { CR17, 0x2B }, /* for newest(3rd cut) AL2230 */
  197. { CR23, 0x40 }, { CR24, 0x20 }, { CR26, 0x93 },
  198. { CR28, 0x3e }, { CR29, 0x00 },
  199. { CR33, 0x28 }, /* 5621 */
  200. { CR34, 0x30 },
  201. { CR35, 0x3e }, /* for newest(3rd cut) AL2230 */
  202. { CR41, 0x24 }, { CR44, 0x32 },
  203. { CR46, 0x99 }, /* for newest(3rd cut) AL2230 */
  204. { CR47, 0x1e },
  205. /* ZD1211B 05.06.10 */
  206. { CR48, 0x06 }, { CR49, 0xf9 }, { CR51, 0x01 },
  207. { CR52, 0x80 }, { CR53, 0x7e }, { CR65, 0x00 },
  208. { CR66, 0x00 }, { CR67, 0x00 }, { CR68, 0x00 },
  209. { CR69, 0x28 },
  210. { CR79, 0x58 }, { CR80, 0x30 }, { CR81, 0x30 },
  211. { CR87, 0x0a }, { CR89, 0x04 },
  212. { CR91, 0x00 }, /* 5621 */
  213. { CR92, 0x0a },
  214. { CR98, 0x8d }, /* 4804, for 1212 new algorithm */
  215. { CR99, 0x00 }, /* 5621 */
  216. { CR101, 0x13 }, { CR102, 0x27 },
  217. { CR106, 0x24 }, /* for newest(3rd cut) AL2230 */
  218. { CR107, 0x2a },
  219. { CR109, 0x13 }, /* 4804, for 1212 new algorithm */
  220. { CR110, 0x1f }, /* 4804, for 1212 new algorithm */
  221. { CR111, 0x1f }, { CR112, 0x1f }, { CR113, 0x27 },
  222. { CR114, 0x27 },
  223. { CR115, 0x26 }, /* 24->26 at 4902 for newest(3rd cut) AL2230 */
  224. { CR116, 0x24 },
  225. { CR117, 0xfa }, /* for 1211b */
  226. { CR118, 0xfa }, /* for 1211b */
  227. { CR119, 0x10 },
  228. { CR120, 0x4f },
  229. { CR121, 0x6c }, /* for 1211b */
  230. { CR122, 0xfc }, /* E0->FC at 4902 */
  231. { CR123, 0x57 }, /* 5623 */
  232. { CR125, 0xad }, /* 4804, for 1212 new algorithm */
  233. { CR126, 0x6c }, /* 5614 */
  234. { CR127, 0x03 }, /* 4804, for 1212 new algorithm */
  235. { CR137, 0x50 }, /* 5614 */
  236. { CR138, 0xa8 },
  237. { CR144, 0xac }, /* 5621 */
  238. { CR150, 0x0d }, { CR252, 0x34 }, { CR253, 0x34 },
  239. };
  240. static const u32 rv1[] = {
  241. 0x8cccd0,
  242. 0x481dc0,
  243. 0xcfff00,
  244. 0x25a000,
  245. };
  246. static const u32 rv2[] = {
  247. /* To improve AL2230 yield, improve phase noise, 4713 */
  248. 0x25a000,
  249. 0xa3b2f0,
  250. 0x6da010, /* Reg6 update for MP versio */
  251. 0xe36280, /* Modified by jxiao for Bor-Chin on 2004/08/02 */
  252. 0x116000,
  253. 0x9dc020, /* External control TX power (CR31) */
  254. 0x5ddb00, /* RegA update for MP version */
  255. 0xd99000, /* RegB update for MP version */
  256. 0x3ffbd0, /* RegC update for MP version */
  257. 0xb00000, /* RegD update for MP version */
  258. /* improve phase noise and remove phase calibration,4713 */
  259. 0xf01a00,
  260. };
  261. static const struct zd_ioreq16 ioreqs2[] = {
  262. { CR251, 0x2f }, /* shdnb(PLL_ON)=0 */
  263. { CR251, 0x7f }, /* shdnb(PLL_ON)=1 */
  264. };
  265. static const u32 rv3[] = {
  266. /* To improve AL2230 yield, 4713 */
  267. 0xf01b00,
  268. 0xf01e00,
  269. 0xf01a00,
  270. };
  271. static const struct zd_ioreq16 ioreqs3[] = {
  272. /* related to 6M band edge patching, happens unconditionally */
  273. { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
  274. };
  275. r = zd_iowrite16a_locked(chip, zd1211b_ioreqs_shared_1,
  276. ARRAY_SIZE(zd1211b_ioreqs_shared_1));
  277. if (r)
  278. return r;
  279. r = zd_iowrite16a_locked(chip, ioreqs1, ARRAY_SIZE(ioreqs1));
  280. if (r)
  281. return r;
  282. if (IS_AL2230S(chip)) {
  283. r = zd_iowrite16a_locked(chip, ioreqs_init_al2230s,
  284. ARRAY_SIZE(ioreqs_init_al2230s));
  285. if (r)
  286. return r;
  287. }
  288. r = zd_rfwritev_cr_locked(chip, zd1211b_al2230_table[0], 3);
  289. if (r)
  290. return r;
  291. r = zd_rfwritev_cr_locked(chip, rv1, ARRAY_SIZE(rv1));
  292. if (r)
  293. return r;
  294. if (IS_AL2230S(chip))
  295. r = zd_rfwrite_locked(chip, 0x241000, RF_RV_BITS);
  296. else
  297. r = zd_rfwrite_locked(chip, 0x25a000, RF_RV_BITS);
  298. if (r)
  299. return r;
  300. r = zd_rfwritev_cr_locked(chip, rv2, ARRAY_SIZE(rv2));
  301. if (r)
  302. return r;
  303. r = zd_iowrite16a_locked(chip, ioreqs2, ARRAY_SIZE(ioreqs2));
  304. if (r)
  305. return r;
  306. r = zd_rfwritev_cr_locked(chip, rv3, ARRAY_SIZE(rv3));
  307. if (r)
  308. return r;
  309. r = zd_iowrite16a_locked(chip, ioreqs3, ARRAY_SIZE(ioreqs3));
  310. if (r)
  311. return r;
  312. return zd1211b_al2230_finalize_rf(chip);
  313. }
  314. static int zd1211_al2230_set_channel(struct zd_rf *rf, u8 channel)
  315. {
  316. int r;
  317. const u32 *rv = zd1211_al2230_table[channel-1];
  318. struct zd_chip *chip = zd_rf_to_chip(rf);
  319. static const struct zd_ioreq16 ioreqs[] = {
  320. { CR138, 0x28 },
  321. { CR203, 0x06 },
  322. };
  323. r = zd_rfwritev_locked(chip, rv, 3, RF_RV_BITS);
  324. if (r)
  325. return r;
  326. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  327. }
  328. static int zd1211b_al2230_set_channel(struct zd_rf *rf, u8 channel)
  329. {
  330. int r;
  331. const u32 *rv = zd1211b_al2230_table[channel-1];
  332. struct zd_chip *chip = zd_rf_to_chip(rf);
  333. r = zd_iowrite16a_locked(chip, zd1211b_ioreqs_shared_1,
  334. ARRAY_SIZE(zd1211b_ioreqs_shared_1));
  335. if (r)
  336. return r;
  337. r = zd_rfwritev_cr_locked(chip, rv, 3);
  338. if (r)
  339. return r;
  340. return zd1211b_al2230_finalize_rf(chip);
  341. }
  342. static int zd1211_al2230_switch_radio_on(struct zd_rf *rf)
  343. {
  344. struct zd_chip *chip = zd_rf_to_chip(rf);
  345. static const struct zd_ioreq16 ioreqs[] = {
  346. { CR11, 0x00 },
  347. { CR251, 0x3f },
  348. };
  349. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  350. }
  351. static int zd1211b_al2230_switch_radio_on(struct zd_rf *rf)
  352. {
  353. struct zd_chip *chip = zd_rf_to_chip(rf);
  354. static const struct zd_ioreq16 ioreqs[] = {
  355. { CR11, 0x00 },
  356. { CR251, 0x7f },
  357. };
  358. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  359. }
  360. static int al2230_switch_radio_off(struct zd_rf *rf)
  361. {
  362. struct zd_chip *chip = zd_rf_to_chip(rf);
  363. static const struct zd_ioreq16 ioreqs[] = {
  364. { CR11, 0x04 },
  365. { CR251, 0x2f },
  366. };
  367. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  368. }
  369. int zd_rf_init_al2230(struct zd_rf *rf)
  370. {
  371. struct zd_chip *chip = zd_rf_to_chip(rf);
  372. rf->switch_radio_off = al2230_switch_radio_off;
  373. if (zd_chip_is_zd1211b(chip)) {
  374. rf->init_hw = zd1211b_al2230_init_hw;
  375. rf->set_channel = zd1211b_al2230_set_channel;
  376. rf->switch_radio_on = zd1211b_al2230_switch_radio_on;
  377. } else {
  378. rf->init_hw = zd1211_al2230_init_hw;
  379. rf->set_channel = zd1211_al2230_set_channel;
  380. rf->switch_radio_on = zd1211_al2230_switch_radio_on;
  381. }
  382. rf->patch_6m_band_edge = zd_rf_generic_patch_6m;
  383. rf->patch_cck_gain = 1;
  384. return 0;
  385. }