p54pci.c 16 KB

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  1. /*
  2. * Linux device driver for PCI based Prism54
  3. *
  4. * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
  5. * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
  6. *
  7. * Based on the islsm (softmac prism54) driver, which is:
  8. * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/pci.h>
  16. #include <linux/firmware.h>
  17. #include <linux/etherdevice.h>
  18. #include <linux/delay.h>
  19. #include <linux/completion.h>
  20. #include <net/mac80211.h>
  21. #include "p54.h"
  22. #include "p54pci.h"
  23. MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  24. MODULE_DESCRIPTION("Prism54 PCI wireless driver");
  25. MODULE_LICENSE("GPL");
  26. MODULE_ALIAS("prism54pci");
  27. MODULE_FIRMWARE("isl3886pci");
  28. static struct pci_device_id p54p_table[] __devinitdata = {
  29. /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
  30. { PCI_DEVICE(0x1260, 0x3890) },
  31. /* 3COM 3CRWE154G72 Wireless LAN adapter */
  32. { PCI_DEVICE(0x10b7, 0x6001) },
  33. /* Intersil PRISM Indigo Wireless LAN adapter */
  34. { PCI_DEVICE(0x1260, 0x3877) },
  35. /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
  36. { PCI_DEVICE(0x1260, 0x3886) },
  37. { },
  38. };
  39. MODULE_DEVICE_TABLE(pci, p54p_table);
  40. static int p54p_upload_firmware(struct ieee80211_hw *dev)
  41. {
  42. struct p54p_priv *priv = dev->priv;
  43. __le32 reg;
  44. int err;
  45. __le32 *data;
  46. u32 remains, left, device_addr;
  47. P54P_WRITE(int_enable, cpu_to_le32(0));
  48. P54P_READ(int_enable);
  49. udelay(10);
  50. reg = P54P_READ(ctrl_stat);
  51. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  52. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
  53. P54P_WRITE(ctrl_stat, reg);
  54. P54P_READ(ctrl_stat);
  55. udelay(10);
  56. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  57. P54P_WRITE(ctrl_stat, reg);
  58. wmb();
  59. udelay(10);
  60. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  61. P54P_WRITE(ctrl_stat, reg);
  62. wmb();
  63. /* wait for the firmware to reset properly */
  64. mdelay(10);
  65. err = p54_parse_firmware(dev, priv->firmware);
  66. if (err)
  67. return err;
  68. data = (__le32 *) priv->firmware->data;
  69. remains = priv->firmware->size;
  70. device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
  71. while (remains) {
  72. u32 i = 0;
  73. left = min((u32)0x1000, remains);
  74. P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
  75. P54P_READ(int_enable);
  76. device_addr += 0x1000;
  77. while (i < left) {
  78. P54P_WRITE(direct_mem_win[i], *data++);
  79. i += sizeof(u32);
  80. }
  81. remains -= left;
  82. P54P_READ(int_enable);
  83. }
  84. reg = P54P_READ(ctrl_stat);
  85. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
  86. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  87. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
  88. P54P_WRITE(ctrl_stat, reg);
  89. P54P_READ(ctrl_stat);
  90. udelay(10);
  91. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  92. P54P_WRITE(ctrl_stat, reg);
  93. wmb();
  94. udelay(10);
  95. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  96. P54P_WRITE(ctrl_stat, reg);
  97. wmb();
  98. udelay(10);
  99. /* wait for the firmware to boot properly */
  100. mdelay(100);
  101. return 0;
  102. }
  103. static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
  104. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  105. struct sk_buff **rx_buf)
  106. {
  107. struct p54p_priv *priv = dev->priv;
  108. struct p54p_ring_control *ring_control = priv->ring_control;
  109. u32 limit, idx, i;
  110. idx = le32_to_cpu(ring_control->host_idx[ring_index]);
  111. limit = idx;
  112. limit -= le32_to_cpu(ring_control->device_idx[ring_index]);
  113. limit = ring_limit - limit;
  114. i = idx % ring_limit;
  115. while (limit-- > 1) {
  116. struct p54p_desc *desc = &ring[i];
  117. if (!desc->host_addr) {
  118. struct sk_buff *skb;
  119. dma_addr_t mapping;
  120. skb = dev_alloc_skb(priv->common.rx_mtu + 32);
  121. if (!skb)
  122. break;
  123. mapping = pci_map_single(priv->pdev,
  124. skb_tail_pointer(skb),
  125. priv->common.rx_mtu + 32,
  126. PCI_DMA_FROMDEVICE);
  127. desc->host_addr = cpu_to_le32(mapping);
  128. desc->device_addr = 0; // FIXME: necessary?
  129. desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
  130. desc->flags = 0;
  131. rx_buf[i] = skb;
  132. }
  133. i++;
  134. idx++;
  135. i %= ring_limit;
  136. }
  137. wmb();
  138. ring_control->host_idx[ring_index] = cpu_to_le32(idx);
  139. }
  140. static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
  141. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  142. struct sk_buff **rx_buf)
  143. {
  144. struct p54p_priv *priv = dev->priv;
  145. struct p54p_ring_control *ring_control = priv->ring_control;
  146. struct p54p_desc *desc;
  147. u32 idx, i;
  148. i = (*index) % ring_limit;
  149. (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
  150. idx %= ring_limit;
  151. while (i != idx) {
  152. u16 len;
  153. struct sk_buff *skb;
  154. desc = &ring[i];
  155. len = le16_to_cpu(desc->len);
  156. skb = rx_buf[i];
  157. if (!skb) {
  158. i++;
  159. i %= ring_limit;
  160. continue;
  161. }
  162. skb_put(skb, len);
  163. if (p54_rx(dev, skb)) {
  164. pci_unmap_single(priv->pdev,
  165. le32_to_cpu(desc->host_addr),
  166. priv->common.rx_mtu + 32,
  167. PCI_DMA_FROMDEVICE);
  168. rx_buf[i] = NULL;
  169. desc->host_addr = 0;
  170. } else {
  171. skb_trim(skb, 0);
  172. desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
  173. }
  174. i++;
  175. i %= ring_limit;
  176. }
  177. p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf);
  178. }
  179. /* caller must hold priv->lock */
  180. static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
  181. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  182. void **tx_buf)
  183. {
  184. struct p54p_priv *priv = dev->priv;
  185. struct p54p_ring_control *ring_control = priv->ring_control;
  186. struct p54p_desc *desc;
  187. u32 idx, i;
  188. i = (*index) % ring_limit;
  189. (*index) = idx = le32_to_cpu(ring_control->device_idx[1]);
  190. idx %= ring_limit;
  191. while (i != idx) {
  192. desc = &ring[i];
  193. if (tx_buf[i])
  194. if (FREE_AFTER_TX((struct sk_buff *) tx_buf[i]))
  195. p54_free_skb(dev, tx_buf[i]);
  196. tx_buf[i] = NULL;
  197. pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
  198. le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
  199. desc->host_addr = 0;
  200. desc->device_addr = 0;
  201. desc->len = 0;
  202. desc->flags = 0;
  203. i++;
  204. i %= ring_limit;
  205. }
  206. }
  207. static void p54p_rx_tasklet(unsigned long dev_id)
  208. {
  209. struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
  210. struct p54p_priv *priv = dev->priv;
  211. struct p54p_ring_control *ring_control = priv->ring_control;
  212. p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
  213. ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
  214. p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
  215. ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
  216. wmb();
  217. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  218. }
  219. static irqreturn_t p54p_interrupt(int irq, void *dev_id)
  220. {
  221. struct ieee80211_hw *dev = dev_id;
  222. struct p54p_priv *priv = dev->priv;
  223. struct p54p_ring_control *ring_control = priv->ring_control;
  224. __le32 reg;
  225. spin_lock(&priv->lock);
  226. reg = P54P_READ(int_ident);
  227. if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
  228. spin_unlock(&priv->lock);
  229. return IRQ_HANDLED;
  230. }
  231. P54P_WRITE(int_ack, reg);
  232. reg &= P54P_READ(int_enable);
  233. if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)) {
  234. p54p_check_tx_ring(dev, &priv->tx_idx_mgmt,
  235. 3, ring_control->tx_mgmt,
  236. ARRAY_SIZE(ring_control->tx_mgmt),
  237. priv->tx_buf_mgmt);
  238. p54p_check_tx_ring(dev, &priv->tx_idx_data,
  239. 1, ring_control->tx_data,
  240. ARRAY_SIZE(ring_control->tx_data),
  241. priv->tx_buf_data);
  242. tasklet_schedule(&priv->rx_tasklet);
  243. } else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
  244. complete(&priv->boot_comp);
  245. spin_unlock(&priv->lock);
  246. return reg ? IRQ_HANDLED : IRQ_NONE;
  247. }
  248. static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
  249. {
  250. struct p54p_priv *priv = dev->priv;
  251. struct p54p_ring_control *ring_control = priv->ring_control;
  252. unsigned long flags;
  253. struct p54p_desc *desc;
  254. dma_addr_t mapping;
  255. u32 device_idx, idx, i;
  256. spin_lock_irqsave(&priv->lock, flags);
  257. device_idx = le32_to_cpu(ring_control->device_idx[1]);
  258. idx = le32_to_cpu(ring_control->host_idx[1]);
  259. i = idx % ARRAY_SIZE(ring_control->tx_data);
  260. priv->tx_buf_data[i] = skb;
  261. mapping = pci_map_single(priv->pdev, skb->data, skb->len,
  262. PCI_DMA_TODEVICE);
  263. desc = &ring_control->tx_data[i];
  264. desc->host_addr = cpu_to_le32(mapping);
  265. desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
  266. desc->len = cpu_to_le16(skb->len);
  267. desc->flags = 0;
  268. wmb();
  269. ring_control->host_idx[1] = cpu_to_le32(idx + 1);
  270. spin_unlock_irqrestore(&priv->lock, flags);
  271. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  272. P54P_READ(dev_int);
  273. }
  274. static void p54p_stop(struct ieee80211_hw *dev)
  275. {
  276. struct p54p_priv *priv = dev->priv;
  277. struct p54p_ring_control *ring_control = priv->ring_control;
  278. unsigned int i;
  279. struct p54p_desc *desc;
  280. tasklet_kill(&priv->rx_tasklet);
  281. P54P_WRITE(int_enable, cpu_to_le32(0));
  282. P54P_READ(int_enable);
  283. udelay(10);
  284. free_irq(priv->pdev->irq, dev);
  285. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  286. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
  287. desc = &ring_control->rx_data[i];
  288. if (desc->host_addr)
  289. pci_unmap_single(priv->pdev,
  290. le32_to_cpu(desc->host_addr),
  291. priv->common.rx_mtu + 32,
  292. PCI_DMA_FROMDEVICE);
  293. kfree_skb(priv->rx_buf_data[i]);
  294. priv->rx_buf_data[i] = NULL;
  295. }
  296. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
  297. desc = &ring_control->rx_mgmt[i];
  298. if (desc->host_addr)
  299. pci_unmap_single(priv->pdev,
  300. le32_to_cpu(desc->host_addr),
  301. priv->common.rx_mtu + 32,
  302. PCI_DMA_FROMDEVICE);
  303. kfree_skb(priv->rx_buf_mgmt[i]);
  304. priv->rx_buf_mgmt[i] = NULL;
  305. }
  306. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
  307. desc = &ring_control->tx_data[i];
  308. if (desc->host_addr)
  309. pci_unmap_single(priv->pdev,
  310. le32_to_cpu(desc->host_addr),
  311. le16_to_cpu(desc->len),
  312. PCI_DMA_TODEVICE);
  313. p54_free_skb(dev, priv->tx_buf_data[i]);
  314. priv->tx_buf_data[i] = NULL;
  315. }
  316. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
  317. desc = &ring_control->tx_mgmt[i];
  318. if (desc->host_addr)
  319. pci_unmap_single(priv->pdev,
  320. le32_to_cpu(desc->host_addr),
  321. le16_to_cpu(desc->len),
  322. PCI_DMA_TODEVICE);
  323. p54_free_skb(dev, priv->tx_buf_mgmt[i]);
  324. priv->tx_buf_mgmt[i] = NULL;
  325. }
  326. memset(ring_control, 0, sizeof(*ring_control));
  327. }
  328. static int p54p_open(struct ieee80211_hw *dev)
  329. {
  330. struct p54p_priv *priv = dev->priv;
  331. int err;
  332. init_completion(&priv->boot_comp);
  333. err = request_irq(priv->pdev->irq, &p54p_interrupt,
  334. IRQF_SHARED, "p54pci", dev);
  335. if (err) {
  336. printk(KERN_ERR "%s: failed to register IRQ handler\n",
  337. wiphy_name(dev->wiphy));
  338. return err;
  339. }
  340. memset(priv->ring_control, 0, sizeof(*priv->ring_control));
  341. err = p54p_upload_firmware(dev);
  342. if (err) {
  343. free_irq(priv->pdev->irq, dev);
  344. return err;
  345. }
  346. priv->rx_idx_data = priv->tx_idx_data = 0;
  347. priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
  348. p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
  349. ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data);
  350. p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
  351. ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt);
  352. P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
  353. P54P_READ(ring_control_base);
  354. wmb();
  355. udelay(10);
  356. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
  357. P54P_READ(int_enable);
  358. wmb();
  359. udelay(10);
  360. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  361. P54P_READ(dev_int);
  362. if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
  363. printk(KERN_ERR "%s: Cannot boot firmware!\n",
  364. wiphy_name(dev->wiphy));
  365. p54p_stop(dev);
  366. return -ETIMEDOUT;
  367. }
  368. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
  369. P54P_READ(int_enable);
  370. wmb();
  371. udelay(10);
  372. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  373. P54P_READ(dev_int);
  374. wmb();
  375. udelay(10);
  376. return 0;
  377. }
  378. static int __devinit p54p_probe(struct pci_dev *pdev,
  379. const struct pci_device_id *id)
  380. {
  381. struct p54p_priv *priv;
  382. struct ieee80211_hw *dev;
  383. unsigned long mem_addr, mem_len;
  384. int err;
  385. err = pci_enable_device(pdev);
  386. if (err) {
  387. printk(KERN_ERR "%s (p54pci): Cannot enable new PCI device\n",
  388. pci_name(pdev));
  389. return err;
  390. }
  391. mem_addr = pci_resource_start(pdev, 0);
  392. mem_len = pci_resource_len(pdev, 0);
  393. if (mem_len < sizeof(struct p54p_csr)) {
  394. printk(KERN_ERR "%s (p54pci): Too short PCI resources\n",
  395. pci_name(pdev));
  396. goto err_disable_dev;
  397. }
  398. err = pci_request_regions(pdev, "p54pci");
  399. if (err) {
  400. printk(KERN_ERR "%s (p54pci): Cannot obtain PCI resources\n",
  401. pci_name(pdev));
  402. goto err_disable_dev;
  403. }
  404. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) ||
  405. pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
  406. printk(KERN_ERR "%s (p54pci): No suitable DMA available\n",
  407. pci_name(pdev));
  408. goto err_free_reg;
  409. }
  410. pci_set_master(pdev);
  411. pci_try_set_mwi(pdev);
  412. pci_write_config_byte(pdev, 0x40, 0);
  413. pci_write_config_byte(pdev, 0x41, 0);
  414. dev = p54_init_common(sizeof(*priv));
  415. if (!dev) {
  416. printk(KERN_ERR "%s (p54pci): ieee80211 alloc failed\n",
  417. pci_name(pdev));
  418. err = -ENOMEM;
  419. goto err_free_reg;
  420. }
  421. priv = dev->priv;
  422. priv->pdev = pdev;
  423. SET_IEEE80211_DEV(dev, &pdev->dev);
  424. pci_set_drvdata(pdev, dev);
  425. priv->map = ioremap(mem_addr, mem_len);
  426. if (!priv->map) {
  427. printk(KERN_ERR "%s (p54pci): Cannot map device memory\n",
  428. pci_name(pdev));
  429. err = -EINVAL; // TODO: use a better error code?
  430. goto err_free_dev;
  431. }
  432. priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
  433. &priv->ring_control_dma);
  434. if (!priv->ring_control) {
  435. printk(KERN_ERR "%s (p54pci): Cannot allocate rings\n",
  436. pci_name(pdev));
  437. err = -ENOMEM;
  438. goto err_iounmap;
  439. }
  440. priv->common.open = p54p_open;
  441. priv->common.stop = p54p_stop;
  442. priv->common.tx = p54p_tx;
  443. spin_lock_init(&priv->lock);
  444. tasklet_init(&priv->rx_tasklet, p54p_rx_tasklet, (unsigned long)dev);
  445. err = request_firmware(&priv->firmware, "isl3886pci",
  446. &priv->pdev->dev);
  447. if (err) {
  448. printk(KERN_ERR "%s (p54pci): cannot find firmware "
  449. "(isl3886pci)\n", pci_name(priv->pdev));
  450. err = request_firmware(&priv->firmware, "isl3886",
  451. &priv->pdev->dev);
  452. if (err)
  453. goto err_free_common;
  454. }
  455. err = p54p_open(dev);
  456. if (err)
  457. goto err_free_common;
  458. err = p54_read_eeprom(dev);
  459. p54p_stop(dev);
  460. if (err)
  461. goto err_free_common;
  462. err = ieee80211_register_hw(dev);
  463. if (err) {
  464. printk(KERN_ERR "%s (p54pci): Cannot register netdevice\n",
  465. pci_name(pdev));
  466. goto err_free_common;
  467. }
  468. return 0;
  469. err_free_common:
  470. release_firmware(priv->firmware);
  471. p54_free_common(dev);
  472. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  473. priv->ring_control, priv->ring_control_dma);
  474. err_iounmap:
  475. iounmap(priv->map);
  476. err_free_dev:
  477. pci_set_drvdata(pdev, NULL);
  478. ieee80211_free_hw(dev);
  479. err_free_reg:
  480. pci_release_regions(pdev);
  481. err_disable_dev:
  482. pci_disable_device(pdev);
  483. return err;
  484. }
  485. static void __devexit p54p_remove(struct pci_dev *pdev)
  486. {
  487. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  488. struct p54p_priv *priv;
  489. if (!dev)
  490. return;
  491. ieee80211_unregister_hw(dev);
  492. priv = dev->priv;
  493. release_firmware(priv->firmware);
  494. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  495. priv->ring_control, priv->ring_control_dma);
  496. p54_free_common(dev);
  497. iounmap(priv->map);
  498. pci_release_regions(pdev);
  499. pci_disable_device(pdev);
  500. ieee80211_free_hw(dev);
  501. }
  502. #ifdef CONFIG_PM
  503. static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
  504. {
  505. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  506. struct p54p_priv *priv = dev->priv;
  507. if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
  508. ieee80211_stop_queues(dev);
  509. p54p_stop(dev);
  510. }
  511. pci_save_state(pdev);
  512. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  513. return 0;
  514. }
  515. static int p54p_resume(struct pci_dev *pdev)
  516. {
  517. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  518. struct p54p_priv *priv = dev->priv;
  519. pci_set_power_state(pdev, PCI_D0);
  520. pci_restore_state(pdev);
  521. if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
  522. p54p_open(dev);
  523. ieee80211_wake_queues(dev);
  524. }
  525. return 0;
  526. }
  527. #endif /* CONFIG_PM */
  528. static struct pci_driver p54p_driver = {
  529. .name = "p54pci",
  530. .id_table = p54p_table,
  531. .probe = p54p_probe,
  532. .remove = __devexit_p(p54p_remove),
  533. #ifdef CONFIG_PM
  534. .suspend = p54p_suspend,
  535. .resume = p54p_resume,
  536. #endif /* CONFIG_PM */
  537. };
  538. static int __init p54p_init(void)
  539. {
  540. return pci_register_driver(&p54p_driver);
  541. }
  542. static void __exit p54p_exit(void)
  543. {
  544. pci_unregister_driver(&p54p_driver);
  545. }
  546. module_init(p54p_init);
  547. module_exit(p54p_exit);