iwl3945-base.c 234 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167416841694170417141724173417441754176417741784179418041814182418341844185418641874188418941904191419241934194419541964197419841994200420142024203420442054206420742084209421042114212421342144215421642174218421942204221422242234224422542264227422842294230423142324233423442354236423742384239424042414242424342444245424642474248424942504251425242534254425542564257425842594260426142624263426442654266426742684269427042714272427342744275427642774278427942804281428242834284428542864287428842894290429142924293429442954296429742984299430043014302430343044305430643074308430943104311431243134314431543164317431843194320432143224323432443254326432743284329433043314332433343344335433643374338433943404341434243434344434543464347434843494350435143524353435443554356435743584359436043614362436343644365436643674368436943704371437243734374437543764377437843794380438143824383438443854386438743884389439043914392439343944395439643974398439944004401440244034404440544064407440844094410441144124413441444154416441744184419442044214422442344244425442644274428442944304431443244334434443544364437443844394440444144424443444444454446444744484449445044514452445344544455445644574458445944604461446244634464446544664467446844694470447144724473447444754476447744784479448044814482448344844485448644874488448944904491449244934494449544964497449844994500450145024503450445054506450745084509451045114512451345144515451645174518451945204521452245234524452545264527452845294530453145324533453445354536453745384539454045414542454345444545454645474548454945504551455245534554455545564557455845594560456145624563456445654566456745684569457045714572457345744575457645774578457945804581458245834584458545864587458845894590459145924593459445954596459745984599460046014602460346044605460646074608460946104611461246134614461546164617461846194620462146224623462446254626462746284629463046314632463346344635463646374638463946404641464246434644464546464647464846494650465146524653465446554656465746584659466046614662466346644665466646674668466946704671467246734674467546764677467846794680468146824683468446854686468746884689469046914692469346944695469646974698469947004701470247034704470547064707470847094710471147124713471447154716471747184719472047214722472347244725472647274728472947304731473247334734473547364737473847394740474147424743474447454746474747484749475047514752475347544755475647574758475947604761476247634764476547664767476847694770477147724773477447754776477747784779478047814782478347844785478647874788478947904791479247934794479547964797479847994800480148024803480448054806480748084809481048114812481348144815481648174818481948204821482248234824482548264827482848294830483148324833483448354836483748384839484048414842484348444845484648474848484948504851485248534854485548564857485848594860486148624863486448654866486748684869487048714872487348744875487648774878487948804881488248834884488548864887488848894890489148924893489448954896489748984899490049014902490349044905490649074908490949104911491249134914491549164917491849194920492149224923492449254926492749284929493049314932493349344935493649374938493949404941494249434944494549464947494849494950495149524953495449554956495749584959496049614962496349644965496649674968496949704971497249734974497549764977497849794980498149824983498449854986498749884989499049914992499349944995499649974998499950005001500250035004500550065007500850095010501150125013501450155016501750185019502050215022502350245025502650275028502950305031503250335034503550365037503850395040504150425043504450455046504750485049505050515052505350545055505650575058505950605061506250635064506550665067506850695070507150725073507450755076507750785079508050815082508350845085508650875088508950905091509250935094509550965097509850995100510151025103510451055106510751085109511051115112511351145115511651175118511951205121512251235124512551265127512851295130513151325133513451355136513751385139514051415142514351445145514651475148514951505151515251535154515551565157515851595160516151625163516451655166516751685169517051715172517351745175517651775178517951805181518251835184518551865187518851895190519151925193519451955196519751985199520052015202520352045205520652075208520952105211521252135214521552165217521852195220522152225223522452255226522752285229523052315232523352345235523652375238523952405241524252435244524552465247524852495250525152525253525452555256525752585259526052615262526352645265526652675268526952705271527252735274527552765277527852795280528152825283528452855286528752885289529052915292529352945295529652975298529953005301530253035304530553065307530853095310531153125313531453155316531753185319532053215322532353245325532653275328532953305331533253335334533553365337533853395340534153425343534453455346534753485349535053515352535353545355535653575358535953605361536253635364536553665367536853695370537153725373537453755376537753785379538053815382538353845385538653875388538953905391539253935394539553965397539853995400540154025403540454055406540754085409541054115412541354145415541654175418541954205421542254235424542554265427542854295430543154325433543454355436543754385439544054415442544354445445544654475448544954505451545254535454545554565457545854595460546154625463546454655466546754685469547054715472547354745475547654775478547954805481548254835484548554865487548854895490549154925493549454955496549754985499550055015502550355045505550655075508550955105511551255135514551555165517551855195520552155225523552455255526552755285529553055315532553355345535553655375538553955405541554255435544554555465547554855495550555155525553555455555556555755585559556055615562556355645565556655675568556955705571557255735574557555765577557855795580558155825583558455855586558755885589559055915592559355945595559655975598559956005601560256035604560556065607560856095610561156125613561456155616561756185619562056215622562356245625562656275628562956305631563256335634563556365637563856395640564156425643564456455646564756485649565056515652565356545655565656575658565956605661566256635664566556665667566856695670567156725673567456755676567756785679568056815682568356845685568656875688568956905691569256935694569556965697569856995700570157025703570457055706570757085709571057115712571357145715571657175718571957205721572257235724572557265727572857295730573157325733573457355736573757385739574057415742574357445745574657475748574957505751575257535754575557565757575857595760576157625763576457655766576757685769577057715772577357745775577657775778577957805781578257835784578557865787578857895790579157925793579457955796579757985799580058015802580358045805580658075808580958105811581258135814581558165817581858195820582158225823582458255826582758285829583058315832583358345835583658375838583958405841584258435844584558465847584858495850585158525853585458555856585758585859586058615862586358645865586658675868586958705871587258735874587558765877587858795880588158825883588458855886588758885889589058915892589358945895589658975898589959005901590259035904590559065907590859095910591159125913591459155916591759185919592059215922592359245925592659275928592959305931593259335934593559365937593859395940594159425943594459455946594759485949595059515952595359545955595659575958595959605961596259635964596559665967596859695970597159725973597459755976597759785979598059815982598359845985598659875988598959905991599259935994599559965997599859996000600160026003600460056006600760086009601060116012601360146015601660176018601960206021602260236024602560266027602860296030603160326033603460356036603760386039604060416042604360446045604660476048604960506051605260536054605560566057605860596060606160626063606460656066606760686069607060716072607360746075607660776078607960806081608260836084608560866087608860896090609160926093609460956096609760986099610061016102610361046105610661076108610961106111611261136114611561166117611861196120612161226123612461256126612761286129613061316132613361346135613661376138613961406141614261436144614561466147614861496150615161526153615461556156615761586159616061616162616361646165616661676168616961706171617261736174617561766177617861796180618161826183618461856186618761886189619061916192619361946195619661976198619962006201620262036204620562066207620862096210621162126213621462156216621762186219622062216222622362246225622662276228622962306231623262336234623562366237623862396240624162426243624462456246624762486249625062516252625362546255625662576258625962606261626262636264626562666267626862696270627162726273627462756276627762786279628062816282628362846285628662876288628962906291629262936294629562966297629862996300630163026303630463056306630763086309631063116312631363146315631663176318631963206321632263236324632563266327632863296330633163326333633463356336633763386339634063416342634363446345634663476348634963506351635263536354635563566357635863596360636163626363636463656366636763686369637063716372637363746375637663776378637963806381638263836384638563866387638863896390639163926393639463956396639763986399640064016402640364046405640664076408640964106411641264136414641564166417641864196420642164226423642464256426642764286429643064316432643364346435643664376438643964406441644264436444644564466447644864496450645164526453645464556456645764586459646064616462646364646465646664676468646964706471647264736474647564766477647864796480648164826483648464856486648764886489649064916492649364946495649664976498649965006501650265036504650565066507650865096510651165126513651465156516651765186519652065216522652365246525652665276528652965306531653265336534653565366537653865396540654165426543654465456546654765486549655065516552655365546555655665576558655965606561656265636564656565666567656865696570657165726573657465756576657765786579658065816582658365846585658665876588658965906591659265936594659565966597659865996600660166026603660466056606660766086609661066116612661366146615661666176618661966206621662266236624662566266627662866296630663166326633663466356636663766386639664066416642664366446645664666476648664966506651665266536654665566566657665866596660666166626663666466656666666766686669667066716672667366746675667666776678667966806681668266836684668566866687668866896690669166926693669466956696669766986699670067016702670367046705670667076708670967106711671267136714671567166717671867196720672167226723672467256726672767286729673067316732673367346735673667376738673967406741674267436744674567466747674867496750675167526753675467556756675767586759676067616762676367646765676667676768676967706771677267736774677567766777677867796780678167826783678467856786678767886789679067916792679367946795679667976798679968006801680268036804680568066807680868096810681168126813681468156816681768186819682068216822682368246825682668276828682968306831683268336834683568366837683868396840684168426843684468456846684768486849685068516852685368546855685668576858685968606861686268636864686568666867686868696870687168726873687468756876687768786879688068816882688368846885688668876888688968906891689268936894689568966897689868996900690169026903690469056906690769086909691069116912691369146915691669176918691969206921692269236924692569266927692869296930693169326933693469356936693769386939694069416942694369446945694669476948694969506951695269536954695569566957695869596960696169626963696469656966696769686969697069716972697369746975697669776978697969806981698269836984698569866987698869896990699169926993699469956996699769986999700070017002700370047005700670077008700970107011701270137014701570167017701870197020702170227023702470257026702770287029703070317032703370347035703670377038703970407041704270437044704570467047704870497050705170527053705470557056705770587059706070617062706370647065706670677068706970707071707270737074707570767077707870797080708170827083708470857086708770887089709070917092709370947095709670977098709971007101710271037104710571067107710871097110711171127113711471157116711771187119712071217122712371247125712671277128712971307131713271337134713571367137713871397140714171427143714471457146714771487149715071517152715371547155715671577158715971607161716271637164716571667167716871697170717171727173717471757176717771787179718071817182718371847185718671877188718971907191719271937194719571967197719871997200720172027203720472057206720772087209721072117212721372147215721672177218721972207221722272237224722572267227722872297230723172327233723472357236723772387239724072417242724372447245724672477248724972507251725272537254725572567257725872597260726172627263726472657266726772687269727072717272727372747275727672777278727972807281728272837284728572867287728872897290729172927293729472957296729772987299730073017302730373047305730673077308730973107311731273137314731573167317731873197320732173227323732473257326732773287329733073317332733373347335733673377338733973407341734273437344734573467347734873497350735173527353735473557356735773587359736073617362736373647365736673677368736973707371737273737374737573767377737873797380738173827383738473857386738773887389739073917392739373947395739673977398739974007401740274037404740574067407740874097410741174127413741474157416741774187419742074217422742374247425742674277428742974307431743274337434743574367437743874397440744174427443744474457446744774487449745074517452745374547455745674577458745974607461746274637464746574667467746874697470747174727473747474757476747774787479748074817482748374847485748674877488748974907491749274937494749574967497749874997500750175027503750475057506750775087509751075117512751375147515751675177518751975207521752275237524752575267527752875297530753175327533753475357536753775387539754075417542754375447545754675477548754975507551755275537554755575567557755875597560756175627563756475657566756775687569757075717572757375747575757675777578757975807581758275837584758575867587758875897590759175927593759475957596759775987599760076017602760376047605760676077608760976107611761276137614761576167617761876197620762176227623762476257626762776287629763076317632763376347635763676377638763976407641764276437644764576467647764876497650765176527653765476557656765776587659766076617662766376647665766676677668766976707671767276737674767576767677767876797680768176827683768476857686768776887689769076917692769376947695769676977698769977007701770277037704770577067707770877097710771177127713771477157716771777187719772077217722772377247725772677277728772977307731773277337734773577367737773877397740774177427743774477457746774777487749775077517752775377547755775677577758775977607761776277637764776577667767776877697770777177727773777477757776777777787779778077817782778377847785778677877788778977907791779277937794779577967797779877997800780178027803780478057806780778087809781078117812781378147815781678177818781978207821782278237824782578267827782878297830783178327833783478357836783778387839784078417842784378447845784678477848784978507851785278537854785578567857785878597860786178627863786478657866786778687869787078717872787378747875787678777878787978807881788278837884788578867887788878897890789178927893789478957896789778987899790079017902790379047905790679077908790979107911791279137914791579167917791879197920792179227923792479257926792779287929793079317932793379347935793679377938793979407941794279437944794579467947794879497950795179527953795479557956795779587959796079617962796379647965796679677968796979707971797279737974797579767977797879797980798179827983798479857986798779887989799079917992799379947995799679977998799980008001800280038004800580068007800880098010801180128013801480158016801780188019802080218022802380248025802680278028802980308031803280338034803580368037803880398040804180428043804480458046804780488049805080518052805380548055805680578058805980608061806280638064806580668067806880698070807180728073807480758076807780788079808080818082808380848085808680878088808980908091809280938094809580968097809880998100810181028103810481058106810781088109811081118112811381148115811681178118811981208121812281238124812581268127812881298130813181328133813481358136813781388139814081418142814381448145814681478148814981508151815281538154815581568157815881598160816181628163816481658166816781688169817081718172817381748175817681778178817981808181818281838184818581868187818881898190819181928193819481958196819781988199820082018202820382048205820682078208820982108211821282138214821582168217821882198220822182228223822482258226822782288229823082318232823382348235823682378238823982408241824282438244824582468247824882498250825182528253825482558256825782588259826082618262826382648265826682678268826982708271827282738274827582768277827882798280828182828283828482858286828782888289829082918292829382948295829682978298829983008301830283038304830583068307830883098310831183128313831483158316831783188319832083218322832383248325832683278328832983308331833283338334833583368337833883398340834183428343834483458346834783488349835083518352835383548355
  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/ieee80211_radiotap.h>
  42. #include <net/lib80211.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #include "iwl-3945-core.h"
  46. #include "iwl-3945.h"
  47. #include "iwl-helpers.h"
  48. #ifdef CONFIG_IWL3945_DEBUG
  49. u32 iwl3945_debug_level;
  50. #endif
  51. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  52. struct iwl3945_tx_queue *txq);
  53. /******************************************************************************
  54. *
  55. * module boiler plate
  56. *
  57. ******************************************************************************/
  58. /* module parameters */
  59. static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
  60. static u32 iwl3945_param_debug; /* def: 0 = minimal debug log messages */
  61. static int iwl3945_param_disable; /* def: 0 = enable radio */
  62. static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
  63. int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
  64. int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
  65. /*
  66. * module name, copyright, version, etc.
  67. * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
  68. */
  69. #define DRV_DESCRIPTION \
  70. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  71. #ifdef CONFIG_IWL3945_DEBUG
  72. #define VD "d"
  73. #else
  74. #define VD
  75. #endif
  76. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  77. #define VS "s"
  78. #else
  79. #define VS
  80. #endif
  81. #define IWLWIFI_VERSION "1.2.26k" VD VS
  82. #define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
  83. #define DRV_AUTHOR "<ilw@linux.intel.com>"
  84. #define DRV_VERSION IWLWIFI_VERSION
  85. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  86. MODULE_VERSION(DRV_VERSION);
  87. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  88. MODULE_LICENSE("GPL");
  89. static const struct ieee80211_supported_band *iwl3945_get_band(
  90. struct iwl3945_priv *priv, enum ieee80211_band band)
  91. {
  92. return priv->hw->wiphy->bands[band];
  93. }
  94. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  95. * DMA services
  96. *
  97. * Theory of operation
  98. *
  99. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  100. * of buffer descriptors, each of which points to one or more data buffers for
  101. * the device to read from or fill. Driver and device exchange status of each
  102. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  103. * entries in each circular buffer, to protect against confusing empty and full
  104. * queue states.
  105. *
  106. * The device reads or writes the data in the queues via the device's several
  107. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  108. *
  109. * For Tx queue, there are low mark and high mark limits. If, after queuing
  110. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  111. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  112. * Tx queue resumed.
  113. *
  114. * The 3945 operates with six queues: One receive queue, one transmit queue
  115. * (#4) for sending commands to the device firmware, and four transmit queues
  116. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  117. ***************************************************/
  118. int iwl3945_queue_space(const struct iwl3945_queue *q)
  119. {
  120. int s = q->read_ptr - q->write_ptr;
  121. if (q->read_ptr > q->write_ptr)
  122. s -= q->n_bd;
  123. if (s <= 0)
  124. s += q->n_window;
  125. /* keep some reserve to not confuse empty and full situations */
  126. s -= 2;
  127. if (s < 0)
  128. s = 0;
  129. return s;
  130. }
  131. int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
  132. {
  133. return q->write_ptr > q->read_ptr ?
  134. (i >= q->read_ptr && i < q->write_ptr) :
  135. !(i < q->read_ptr && i >= q->write_ptr);
  136. }
  137. static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
  138. {
  139. /* This is for scan command, the big buffer at end of command array */
  140. if (is_huge)
  141. return q->n_window; /* must be power of 2 */
  142. /* Otherwise, use normal size buffers */
  143. return index & (q->n_window - 1);
  144. }
  145. /**
  146. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  147. */
  148. static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
  149. int count, int slots_num, u32 id)
  150. {
  151. q->n_bd = count;
  152. q->n_window = slots_num;
  153. q->id = id;
  154. /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
  155. * and iwl_queue_dec_wrap are broken. */
  156. BUG_ON(!is_power_of_2(count));
  157. /* slots_num must be power-of-two size, otherwise
  158. * get_cmd_index is broken. */
  159. BUG_ON(!is_power_of_2(slots_num));
  160. q->low_mark = q->n_window / 4;
  161. if (q->low_mark < 4)
  162. q->low_mark = 4;
  163. q->high_mark = q->n_window / 8;
  164. if (q->high_mark < 2)
  165. q->high_mark = 2;
  166. q->write_ptr = q->read_ptr = 0;
  167. return 0;
  168. }
  169. /**
  170. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  171. */
  172. static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
  173. struct iwl3945_tx_queue *txq, u32 id)
  174. {
  175. struct pci_dev *dev = priv->pci_dev;
  176. /* Driver private data, only for Tx (not command) queues,
  177. * not shared with device. */
  178. if (id != IWL_CMD_QUEUE_NUM) {
  179. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  180. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  181. if (!txq->txb) {
  182. IWL_ERROR("kmalloc for auxiliary BD "
  183. "structures failed\n");
  184. goto error;
  185. }
  186. } else
  187. txq->txb = NULL;
  188. /* Circular buffer of transmit frame descriptors (TFDs),
  189. * shared with device */
  190. txq->bd = pci_alloc_consistent(dev,
  191. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  192. &txq->q.dma_addr);
  193. if (!txq->bd) {
  194. IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
  195. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  196. goto error;
  197. }
  198. txq->q.id = id;
  199. return 0;
  200. error:
  201. kfree(txq->txb);
  202. txq->txb = NULL;
  203. return -ENOMEM;
  204. }
  205. /**
  206. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  207. */
  208. int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
  209. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  210. {
  211. struct pci_dev *dev = priv->pci_dev;
  212. int len;
  213. int rc = 0;
  214. /*
  215. * Alloc buffer array for commands (Tx or other types of commands).
  216. * For the command queue (#4), allocate command space + one big
  217. * command for scan, since scan command is very huge; the system will
  218. * not have two scans at the same time, so only one is needed.
  219. * For data Tx queues (all other queues), no super-size command
  220. * space is needed.
  221. */
  222. len = sizeof(struct iwl3945_cmd) * slots_num;
  223. if (txq_id == IWL_CMD_QUEUE_NUM)
  224. len += IWL_MAX_SCAN_SIZE;
  225. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  226. if (!txq->cmd)
  227. return -ENOMEM;
  228. /* Alloc driver data array and TFD circular buffer */
  229. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  230. if (rc) {
  231. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  232. return -ENOMEM;
  233. }
  234. txq->need_update = 0;
  235. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  236. * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
  237. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  238. /* Initialize queue high/low-water, head/tail indexes */
  239. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  240. /* Tell device where to find queue, enable DMA channel. */
  241. iwl3945_hw_tx_queue_init(priv, txq);
  242. return 0;
  243. }
  244. /**
  245. * iwl3945_tx_queue_free - Deallocate DMA queue.
  246. * @txq: Transmit queue to deallocate.
  247. *
  248. * Empty queue by removing and destroying all BD's.
  249. * Free all buffers.
  250. * 0-fill, but do not free "txq" descriptor structure.
  251. */
  252. void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
  253. {
  254. struct iwl3945_queue *q = &txq->q;
  255. struct pci_dev *dev = priv->pci_dev;
  256. int len;
  257. if (q->n_bd == 0)
  258. return;
  259. /* first, empty all BD's */
  260. for (; q->write_ptr != q->read_ptr;
  261. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
  262. iwl3945_hw_txq_free_tfd(priv, txq);
  263. len = sizeof(struct iwl3945_cmd) * q->n_window;
  264. if (q->id == IWL_CMD_QUEUE_NUM)
  265. len += IWL_MAX_SCAN_SIZE;
  266. /* De-alloc array of command/tx buffers */
  267. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  268. /* De-alloc circular buffer of TFDs */
  269. if (txq->q.n_bd)
  270. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  271. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  272. /* De-alloc array of per-TFD driver data */
  273. kfree(txq->txb);
  274. txq->txb = NULL;
  275. /* 0-fill queue descriptor structure */
  276. memset(txq, 0, sizeof(*txq));
  277. }
  278. const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  279. /*************** STATION TABLE MANAGEMENT ****
  280. * mac80211 should be examined to determine if sta_info is duplicating
  281. * the functionality provided here
  282. */
  283. /**************************************************************/
  284. #if 0 /* temporary disable till we add real remove station */
  285. /**
  286. * iwl3945_remove_station - Remove driver's knowledge of station.
  287. *
  288. * NOTE: This does not remove station from device's station table.
  289. */
  290. static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
  291. {
  292. int index = IWL_INVALID_STATION;
  293. int i;
  294. unsigned long flags;
  295. spin_lock_irqsave(&priv->sta_lock, flags);
  296. if (is_ap)
  297. index = IWL_AP_ID;
  298. else if (is_broadcast_ether_addr(addr))
  299. index = priv->hw_setting.bcast_sta_id;
  300. else
  301. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
  302. if (priv->stations[i].used &&
  303. !compare_ether_addr(priv->stations[i].sta.sta.addr,
  304. addr)) {
  305. index = i;
  306. break;
  307. }
  308. if (unlikely(index == IWL_INVALID_STATION))
  309. goto out;
  310. if (priv->stations[index].used) {
  311. priv->stations[index].used = 0;
  312. priv->num_stations--;
  313. }
  314. BUG_ON(priv->num_stations < 0);
  315. out:
  316. spin_unlock_irqrestore(&priv->sta_lock, flags);
  317. return 0;
  318. }
  319. #endif
  320. /**
  321. * iwl3945_clear_stations_table - Clear the driver's station table
  322. *
  323. * NOTE: This does not clear or otherwise alter the device's station table.
  324. */
  325. static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
  326. {
  327. unsigned long flags;
  328. spin_lock_irqsave(&priv->sta_lock, flags);
  329. priv->num_stations = 0;
  330. memset(priv->stations, 0, sizeof(priv->stations));
  331. spin_unlock_irqrestore(&priv->sta_lock, flags);
  332. }
  333. /**
  334. * iwl3945_add_station - Add station to station tables in driver and device
  335. */
  336. u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
  337. {
  338. int i;
  339. int index = IWL_INVALID_STATION;
  340. struct iwl3945_station_entry *station;
  341. unsigned long flags_spin;
  342. u8 rate;
  343. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  344. if (is_ap)
  345. index = IWL_AP_ID;
  346. else if (is_broadcast_ether_addr(addr))
  347. index = priv->hw_setting.bcast_sta_id;
  348. else
  349. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
  350. if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
  351. addr)) {
  352. index = i;
  353. break;
  354. }
  355. if (!priv->stations[i].used &&
  356. index == IWL_INVALID_STATION)
  357. index = i;
  358. }
  359. /* These two conditions has the same outcome but keep them separate
  360. since they have different meaning */
  361. if (unlikely(index == IWL_INVALID_STATION)) {
  362. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  363. return index;
  364. }
  365. if (priv->stations[index].used &&
  366. !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
  367. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  368. return index;
  369. }
  370. IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
  371. station = &priv->stations[index];
  372. station->used = 1;
  373. priv->num_stations++;
  374. /* Set up the REPLY_ADD_STA command to send to device */
  375. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  376. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  377. station->sta.mode = 0;
  378. station->sta.sta.sta_id = index;
  379. station->sta.station_flags = 0;
  380. if (priv->band == IEEE80211_BAND_5GHZ)
  381. rate = IWL_RATE_6M_PLCP;
  382. else
  383. rate = IWL_RATE_1M_PLCP;
  384. /* Turn on both antennas for the station... */
  385. station->sta.rate_n_flags =
  386. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  387. station->current_rate.rate_n_flags =
  388. le16_to_cpu(station->sta.rate_n_flags);
  389. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  390. /* Add station to device's station table */
  391. iwl3945_send_add_station(priv, &station->sta, flags);
  392. return index;
  393. }
  394. /*************** DRIVER STATUS FUNCTIONS *****/
  395. static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
  396. {
  397. /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
  398. * set but EXIT_PENDING is not */
  399. return test_bit(STATUS_READY, &priv->status) &&
  400. test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
  401. !test_bit(STATUS_EXIT_PENDING, &priv->status);
  402. }
  403. static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
  404. {
  405. return test_bit(STATUS_ALIVE, &priv->status);
  406. }
  407. static inline int iwl3945_is_init(struct iwl3945_priv *priv)
  408. {
  409. return test_bit(STATUS_INIT, &priv->status);
  410. }
  411. static inline int iwl3945_is_rfkill_sw(struct iwl3945_priv *priv)
  412. {
  413. return test_bit(STATUS_RF_KILL_SW, &priv->status);
  414. }
  415. static inline int iwl3945_is_rfkill_hw(struct iwl3945_priv *priv)
  416. {
  417. return test_bit(STATUS_RF_KILL_HW, &priv->status);
  418. }
  419. static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
  420. {
  421. return iwl3945_is_rfkill_hw(priv) ||
  422. iwl3945_is_rfkill_sw(priv);
  423. }
  424. static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
  425. {
  426. if (iwl3945_is_rfkill(priv))
  427. return 0;
  428. return iwl3945_is_ready(priv);
  429. }
  430. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  431. #define IWL_CMD(x) case x: return #x
  432. static const char *get_cmd_string(u8 cmd)
  433. {
  434. switch (cmd) {
  435. IWL_CMD(REPLY_ALIVE);
  436. IWL_CMD(REPLY_ERROR);
  437. IWL_CMD(REPLY_RXON);
  438. IWL_CMD(REPLY_RXON_ASSOC);
  439. IWL_CMD(REPLY_QOS_PARAM);
  440. IWL_CMD(REPLY_RXON_TIMING);
  441. IWL_CMD(REPLY_ADD_STA);
  442. IWL_CMD(REPLY_REMOVE_STA);
  443. IWL_CMD(REPLY_REMOVE_ALL_STA);
  444. IWL_CMD(REPLY_3945_RX);
  445. IWL_CMD(REPLY_TX);
  446. IWL_CMD(REPLY_RATE_SCALE);
  447. IWL_CMD(REPLY_LEDS_CMD);
  448. IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
  449. IWL_CMD(RADAR_NOTIFICATION);
  450. IWL_CMD(REPLY_QUIET_CMD);
  451. IWL_CMD(REPLY_CHANNEL_SWITCH);
  452. IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
  453. IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
  454. IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
  455. IWL_CMD(POWER_TABLE_CMD);
  456. IWL_CMD(PM_SLEEP_NOTIFICATION);
  457. IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
  458. IWL_CMD(REPLY_SCAN_CMD);
  459. IWL_CMD(REPLY_SCAN_ABORT_CMD);
  460. IWL_CMD(SCAN_START_NOTIFICATION);
  461. IWL_CMD(SCAN_RESULTS_NOTIFICATION);
  462. IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
  463. IWL_CMD(BEACON_NOTIFICATION);
  464. IWL_CMD(REPLY_TX_BEACON);
  465. IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
  466. IWL_CMD(QUIET_NOTIFICATION);
  467. IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
  468. IWL_CMD(MEASURE_ABORT_NOTIFICATION);
  469. IWL_CMD(REPLY_BT_CONFIG);
  470. IWL_CMD(REPLY_STATISTICS_CMD);
  471. IWL_CMD(STATISTICS_NOTIFICATION);
  472. IWL_CMD(REPLY_CARD_STATE_CMD);
  473. IWL_CMD(CARD_STATE_NOTIFICATION);
  474. IWL_CMD(MISSED_BEACONS_NOTIFICATION);
  475. default:
  476. return "UNKNOWN";
  477. }
  478. }
  479. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  480. /**
  481. * iwl3945_enqueue_hcmd - enqueue a uCode command
  482. * @priv: device private data point
  483. * @cmd: a point to the ucode command structure
  484. *
  485. * The function returns < 0 values to indicate the operation is
  486. * failed. On success, it turns the index (> 0) of command in the
  487. * command queue.
  488. */
  489. static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  490. {
  491. struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  492. struct iwl3945_queue *q = &txq->q;
  493. struct iwl3945_tfd_frame *tfd;
  494. u32 *control_flags;
  495. struct iwl3945_cmd *out_cmd;
  496. u32 idx;
  497. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  498. dma_addr_t phys_addr;
  499. int pad;
  500. u16 count;
  501. int ret;
  502. unsigned long flags;
  503. /* If any of the command structures end up being larger than
  504. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  505. * we will need to increase the size of the TFD entries */
  506. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  507. !(cmd->meta.flags & CMD_SIZE_HUGE));
  508. if (iwl3945_is_rfkill(priv)) {
  509. IWL_DEBUG_INFO("Not sending command - RF KILL");
  510. return -EIO;
  511. }
  512. if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  513. IWL_ERROR("No space for Tx\n");
  514. return -ENOSPC;
  515. }
  516. spin_lock_irqsave(&priv->hcmd_lock, flags);
  517. tfd = &txq->bd[q->write_ptr];
  518. memset(tfd, 0, sizeof(*tfd));
  519. control_flags = (u32 *) tfd;
  520. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  521. out_cmd = &txq->cmd[idx];
  522. out_cmd->hdr.cmd = cmd->id;
  523. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  524. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  525. /* At this point, the out_cmd now has all of the incoming cmd
  526. * information */
  527. out_cmd->hdr.flags = 0;
  528. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  529. INDEX_TO_SEQ(q->write_ptr));
  530. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  531. out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
  532. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  533. offsetof(struct iwl3945_cmd, hdr);
  534. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  535. pad = U32_PAD(cmd->len);
  536. count = TFD_CTL_COUNT_GET(*control_flags);
  537. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  538. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  539. "%d bytes at %d[%d]:%d\n",
  540. get_cmd_string(out_cmd->hdr.cmd),
  541. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  542. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  543. txq->need_update = 1;
  544. /* Increment and update queue's write index */
  545. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  546. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  547. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  548. return ret ? ret : idx;
  549. }
  550. static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  551. {
  552. int ret;
  553. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  554. /* An asynchronous command can not expect an SKB to be set. */
  555. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  556. /* An asynchronous command MUST have a callback. */
  557. BUG_ON(!cmd->meta.u.callback);
  558. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  559. return -EBUSY;
  560. ret = iwl3945_enqueue_hcmd(priv, cmd);
  561. if (ret < 0) {
  562. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  563. get_cmd_string(cmd->id), ret);
  564. return ret;
  565. }
  566. return 0;
  567. }
  568. static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  569. {
  570. int cmd_idx;
  571. int ret;
  572. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  573. /* A synchronous command can not have a callback set. */
  574. BUG_ON(cmd->meta.u.callback != NULL);
  575. if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
  576. IWL_ERROR("Error sending %s: Already sending a host command\n",
  577. get_cmd_string(cmd->id));
  578. ret = -EBUSY;
  579. goto out;
  580. }
  581. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  582. if (cmd->meta.flags & CMD_WANT_SKB)
  583. cmd->meta.source = &cmd->meta;
  584. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  585. if (cmd_idx < 0) {
  586. ret = cmd_idx;
  587. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  588. get_cmd_string(cmd->id), ret);
  589. goto out;
  590. }
  591. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  592. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  593. HOST_COMPLETE_TIMEOUT);
  594. if (!ret) {
  595. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  596. IWL_ERROR("Error sending %s: time out after %dms.\n",
  597. get_cmd_string(cmd->id),
  598. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  599. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  600. ret = -ETIMEDOUT;
  601. goto cancel;
  602. }
  603. }
  604. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  605. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  606. get_cmd_string(cmd->id));
  607. ret = -ECANCELED;
  608. goto fail;
  609. }
  610. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  611. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  612. get_cmd_string(cmd->id));
  613. ret = -EIO;
  614. goto fail;
  615. }
  616. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  617. IWL_ERROR("Error: Response NULL in '%s'\n",
  618. get_cmd_string(cmd->id));
  619. ret = -EIO;
  620. goto out;
  621. }
  622. ret = 0;
  623. goto out;
  624. cancel:
  625. if (cmd->meta.flags & CMD_WANT_SKB) {
  626. struct iwl3945_cmd *qcmd;
  627. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  628. * TX cmd queue. Otherwise in case the cmd comes
  629. * in later, it will possibly set an invalid
  630. * address (cmd->meta.source). */
  631. qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  632. qcmd->meta.flags &= ~CMD_WANT_SKB;
  633. }
  634. fail:
  635. if (cmd->meta.u.skb) {
  636. dev_kfree_skb_any(cmd->meta.u.skb);
  637. cmd->meta.u.skb = NULL;
  638. }
  639. out:
  640. clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
  641. return ret;
  642. }
  643. int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  644. {
  645. if (cmd->meta.flags & CMD_ASYNC)
  646. return iwl3945_send_cmd_async(priv, cmd);
  647. return iwl3945_send_cmd_sync(priv, cmd);
  648. }
  649. int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
  650. {
  651. struct iwl3945_host_cmd cmd = {
  652. .id = id,
  653. .len = len,
  654. .data = data,
  655. };
  656. return iwl3945_send_cmd_sync(priv, &cmd);
  657. }
  658. static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
  659. {
  660. struct iwl3945_host_cmd cmd = {
  661. .id = id,
  662. .len = sizeof(val),
  663. .data = &val,
  664. };
  665. return iwl3945_send_cmd_sync(priv, &cmd);
  666. }
  667. int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
  668. {
  669. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  670. }
  671. /**
  672. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  673. * @band: 2.4 or 5 GHz band
  674. * @channel: Any channel valid for the requested band
  675. * In addition to setting the staging RXON, priv->band is also set.
  676. *
  677. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  678. * in the staging RXON flag structure based on the band
  679. */
  680. static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
  681. enum ieee80211_band band,
  682. u16 channel)
  683. {
  684. if (!iwl3945_get_channel_info(priv, band, channel)) {
  685. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  686. channel, band);
  687. return -EINVAL;
  688. }
  689. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  690. (priv->band == band))
  691. return 0;
  692. priv->staging_rxon.channel = cpu_to_le16(channel);
  693. if (band == IEEE80211_BAND_5GHZ)
  694. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  695. else
  696. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  697. priv->band = band;
  698. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  699. return 0;
  700. }
  701. /**
  702. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  703. *
  704. * NOTE: This is really only useful during development and can eventually
  705. * be #ifdef'd out once the driver is stable and folks aren't actively
  706. * making changes
  707. */
  708. static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
  709. {
  710. int error = 0;
  711. int counter = 1;
  712. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  713. error |= le32_to_cpu(rxon->flags &
  714. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  715. RXON_FLG_RADAR_DETECT_MSK));
  716. if (error)
  717. IWL_WARNING("check 24G fields %d | %d\n",
  718. counter++, error);
  719. } else {
  720. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  721. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  722. if (error)
  723. IWL_WARNING("check 52 fields %d | %d\n",
  724. counter++, error);
  725. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  726. if (error)
  727. IWL_WARNING("check 52 CCK %d | %d\n",
  728. counter++, error);
  729. }
  730. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  731. if (error)
  732. IWL_WARNING("check mac addr %d | %d\n", counter++, error);
  733. /* make sure basic rates 6Mbps and 1Mbps are supported */
  734. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  735. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  736. if (error)
  737. IWL_WARNING("check basic rate %d | %d\n", counter++, error);
  738. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  739. if (error)
  740. IWL_WARNING("check assoc id %d | %d\n", counter++, error);
  741. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  742. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  743. if (error)
  744. IWL_WARNING("check CCK and short slot %d | %d\n",
  745. counter++, error);
  746. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  747. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  748. if (error)
  749. IWL_WARNING("check CCK & auto detect %d | %d\n",
  750. counter++, error);
  751. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  752. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  753. if (error)
  754. IWL_WARNING("check TGG and auto detect %d | %d\n",
  755. counter++, error);
  756. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  757. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  758. RXON_FLG_ANT_A_MSK)) == 0);
  759. if (error)
  760. IWL_WARNING("check antenna %d %d\n", counter++, error);
  761. if (error)
  762. IWL_WARNING("Tuning to channel %d\n",
  763. le16_to_cpu(rxon->channel));
  764. if (error) {
  765. IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
  766. return -1;
  767. }
  768. return 0;
  769. }
  770. /**
  771. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  772. * @priv: staging_rxon is compared to active_rxon
  773. *
  774. * If the RXON structure is changing enough to require a new tune,
  775. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  776. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  777. */
  778. static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
  779. {
  780. /* These items are only settable from the full RXON command */
  781. if (!(iwl3945_is_associated(priv)) ||
  782. compare_ether_addr(priv->staging_rxon.bssid_addr,
  783. priv->active_rxon.bssid_addr) ||
  784. compare_ether_addr(priv->staging_rxon.node_addr,
  785. priv->active_rxon.node_addr) ||
  786. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  787. priv->active_rxon.wlap_bssid_addr) ||
  788. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  789. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  790. (priv->staging_rxon.air_propagation !=
  791. priv->active_rxon.air_propagation) ||
  792. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  793. return 1;
  794. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  795. * be updated with the RXON_ASSOC command -- however only some
  796. * flag transitions are allowed using RXON_ASSOC */
  797. /* Check if we are not switching bands */
  798. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  799. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  800. return 1;
  801. /* Check if we are switching association toggle */
  802. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  803. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  804. return 1;
  805. return 0;
  806. }
  807. static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
  808. {
  809. int rc = 0;
  810. struct iwl3945_rx_packet *res = NULL;
  811. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  812. struct iwl3945_host_cmd cmd = {
  813. .id = REPLY_RXON_ASSOC,
  814. .len = sizeof(rxon_assoc),
  815. .meta.flags = CMD_WANT_SKB,
  816. .data = &rxon_assoc,
  817. };
  818. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
  819. const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
  820. if ((rxon1->flags == rxon2->flags) &&
  821. (rxon1->filter_flags == rxon2->filter_flags) &&
  822. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  823. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  824. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  825. return 0;
  826. }
  827. rxon_assoc.flags = priv->staging_rxon.flags;
  828. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  829. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  830. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  831. rxon_assoc.reserved = 0;
  832. rc = iwl3945_send_cmd_sync(priv, &cmd);
  833. if (rc)
  834. return rc;
  835. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  836. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  837. IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
  838. rc = -EIO;
  839. }
  840. priv->alloc_rxb_skb--;
  841. dev_kfree_skb_any(cmd.meta.u.skb);
  842. return rc;
  843. }
  844. /**
  845. * iwl3945_commit_rxon - commit staging_rxon to hardware
  846. *
  847. * The RXON command in staging_rxon is committed to the hardware and
  848. * the active_rxon structure is updated with the new data. This
  849. * function correctly transitions out of the RXON_ASSOC_MSK state if
  850. * a HW tune is required based on the RXON structure changes.
  851. */
  852. static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
  853. {
  854. /* cast away the const for active_rxon in this function */
  855. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  856. int rc = 0;
  857. if (!iwl3945_is_alive(priv))
  858. return -1;
  859. /* always get timestamp with Rx frame */
  860. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  861. /* select antenna */
  862. priv->staging_rxon.flags &=
  863. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  864. priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
  865. rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
  866. if (rc) {
  867. IWL_ERROR("Invalid RXON configuration. Not committing.\n");
  868. return -EINVAL;
  869. }
  870. /* If we don't need to send a full RXON, we can use
  871. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  872. * and other flags for the current radio configuration. */
  873. if (!iwl3945_full_rxon_required(priv)) {
  874. rc = iwl3945_send_rxon_assoc(priv);
  875. if (rc) {
  876. IWL_ERROR("Error setting RXON_ASSOC "
  877. "configuration (%d).\n", rc);
  878. return rc;
  879. }
  880. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  881. return 0;
  882. }
  883. /* If we are currently associated and the new config requires
  884. * an RXON_ASSOC and the new config wants the associated mask enabled,
  885. * we must clear the associated from the active configuration
  886. * before we apply the new config */
  887. if (iwl3945_is_associated(priv) &&
  888. (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  889. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  890. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  891. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  892. sizeof(struct iwl3945_rxon_cmd),
  893. &priv->active_rxon);
  894. /* If the mask clearing failed then we set
  895. * active_rxon back to what it was previously */
  896. if (rc) {
  897. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  898. IWL_ERROR("Error clearing ASSOC_MSK on current "
  899. "configuration (%d).\n", rc);
  900. return rc;
  901. }
  902. }
  903. IWL_DEBUG_INFO("Sending RXON\n"
  904. "* with%s RXON_FILTER_ASSOC_MSK\n"
  905. "* channel = %d\n"
  906. "* bssid = %pM\n",
  907. ((priv->staging_rxon.filter_flags &
  908. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  909. le16_to_cpu(priv->staging_rxon.channel),
  910. priv->staging_rxon.bssid_addr);
  911. /* Apply the new configuration */
  912. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  913. sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
  914. if (rc) {
  915. IWL_ERROR("Error setting new configuration (%d).\n", rc);
  916. return rc;
  917. }
  918. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  919. iwl3945_clear_stations_table(priv);
  920. /* If we issue a new RXON command which required a tune then we must
  921. * send a new TXPOWER command or we won't be able to Tx any frames */
  922. rc = iwl3945_hw_reg_send_txpower(priv);
  923. if (rc) {
  924. IWL_ERROR("Error setting Tx power (%d).\n", rc);
  925. return rc;
  926. }
  927. /* Add the broadcast address so we can send broadcast frames */
  928. if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
  929. IWL_INVALID_STATION) {
  930. IWL_ERROR("Error adding BROADCAST address for transmit.\n");
  931. return -EIO;
  932. }
  933. /* If we have set the ASSOC_MSK and we are in BSS mode then
  934. * add the IWL_AP_ID to the station rate table */
  935. if (iwl3945_is_associated(priv) &&
  936. (priv->iw_mode == NL80211_IFTYPE_STATION))
  937. if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
  938. == IWL_INVALID_STATION) {
  939. IWL_ERROR("Error adding AP address for transmit.\n");
  940. return -EIO;
  941. }
  942. /* Init the hardware's rate fallback order based on the band */
  943. rc = iwl3945_init_hw_rate_table(priv);
  944. if (rc) {
  945. IWL_ERROR("Error setting HW rate table: %02X\n", rc);
  946. return -EIO;
  947. }
  948. return 0;
  949. }
  950. static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
  951. {
  952. struct iwl3945_bt_cmd bt_cmd = {
  953. .flags = 3,
  954. .lead_time = 0xAA,
  955. .max_kill = 1,
  956. .kill_ack_mask = 0,
  957. .kill_cts_mask = 0,
  958. };
  959. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  960. sizeof(struct iwl3945_bt_cmd), &bt_cmd);
  961. }
  962. static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
  963. {
  964. int rc = 0;
  965. struct iwl3945_rx_packet *res;
  966. struct iwl3945_host_cmd cmd = {
  967. .id = REPLY_SCAN_ABORT_CMD,
  968. .meta.flags = CMD_WANT_SKB,
  969. };
  970. /* If there isn't a scan actively going on in the hardware
  971. * then we are in between scan bands and not actually
  972. * actively scanning, so don't send the abort command */
  973. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  974. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  975. return 0;
  976. }
  977. rc = iwl3945_send_cmd_sync(priv, &cmd);
  978. if (rc) {
  979. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  980. return rc;
  981. }
  982. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  983. if (res->u.status != CAN_ABORT_STATUS) {
  984. /* The scan abort will return 1 for success or
  985. * 2 for "failure". A failure condition can be
  986. * due to simply not being in an active scan which
  987. * can occur if we send the scan abort before we
  988. * the microcode has notified us that a scan is
  989. * completed. */
  990. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  991. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  992. clear_bit(STATUS_SCAN_HW, &priv->status);
  993. }
  994. dev_kfree_skb_any(cmd.meta.u.skb);
  995. return rc;
  996. }
  997. static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
  998. struct iwl3945_cmd *cmd,
  999. struct sk_buff *skb)
  1000. {
  1001. return 1;
  1002. }
  1003. /*
  1004. * CARD_STATE_CMD
  1005. *
  1006. * Use: Sets the device's internal card state to enable, disable, or halt
  1007. *
  1008. * When in the 'enable' state the card operates as normal.
  1009. * When in the 'disable' state, the card enters into a low power mode.
  1010. * When in the 'halt' state, the card is shut down and must be fully
  1011. * restarted to come back on.
  1012. */
  1013. static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
  1014. {
  1015. struct iwl3945_host_cmd cmd = {
  1016. .id = REPLY_CARD_STATE_CMD,
  1017. .len = sizeof(u32),
  1018. .data = &flags,
  1019. .meta.flags = meta_flag,
  1020. };
  1021. if (meta_flag & CMD_ASYNC)
  1022. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  1023. return iwl3945_send_cmd(priv, &cmd);
  1024. }
  1025. static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
  1026. struct iwl3945_cmd *cmd, struct sk_buff *skb)
  1027. {
  1028. struct iwl3945_rx_packet *res = NULL;
  1029. if (!skb) {
  1030. IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
  1031. return 1;
  1032. }
  1033. res = (struct iwl3945_rx_packet *)skb->data;
  1034. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1035. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1036. res->hdr.flags);
  1037. return 1;
  1038. }
  1039. switch (res->u.add_sta.status) {
  1040. case ADD_STA_SUCCESS_MSK:
  1041. break;
  1042. default:
  1043. break;
  1044. }
  1045. /* We didn't cache the SKB; let the caller free it */
  1046. return 1;
  1047. }
  1048. int iwl3945_send_add_station(struct iwl3945_priv *priv,
  1049. struct iwl3945_addsta_cmd *sta, u8 flags)
  1050. {
  1051. struct iwl3945_rx_packet *res = NULL;
  1052. int rc = 0;
  1053. struct iwl3945_host_cmd cmd = {
  1054. .id = REPLY_ADD_STA,
  1055. .len = sizeof(struct iwl3945_addsta_cmd),
  1056. .meta.flags = flags,
  1057. .data = sta,
  1058. };
  1059. if (flags & CMD_ASYNC)
  1060. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  1061. else
  1062. cmd.meta.flags |= CMD_WANT_SKB;
  1063. rc = iwl3945_send_cmd(priv, &cmd);
  1064. if (rc || (flags & CMD_ASYNC))
  1065. return rc;
  1066. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1067. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1068. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1069. res->hdr.flags);
  1070. rc = -EIO;
  1071. }
  1072. if (rc == 0) {
  1073. switch (res->u.add_sta.status) {
  1074. case ADD_STA_SUCCESS_MSK:
  1075. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  1076. break;
  1077. default:
  1078. rc = -EIO;
  1079. IWL_WARNING("REPLY_ADD_STA failed\n");
  1080. break;
  1081. }
  1082. }
  1083. priv->alloc_rxb_skb--;
  1084. dev_kfree_skb_any(cmd.meta.u.skb);
  1085. return rc;
  1086. }
  1087. static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
  1088. struct ieee80211_key_conf *keyconf,
  1089. u8 sta_id)
  1090. {
  1091. unsigned long flags;
  1092. __le16 key_flags = 0;
  1093. switch (keyconf->alg) {
  1094. case ALG_CCMP:
  1095. key_flags |= STA_KEY_FLG_CCMP;
  1096. key_flags |= cpu_to_le16(
  1097. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  1098. key_flags &= ~STA_KEY_FLG_INVALID;
  1099. break;
  1100. case ALG_TKIP:
  1101. case ALG_WEP:
  1102. default:
  1103. return -EINVAL;
  1104. }
  1105. spin_lock_irqsave(&priv->sta_lock, flags);
  1106. priv->stations[sta_id].keyinfo.alg = keyconf->alg;
  1107. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  1108. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  1109. keyconf->keylen);
  1110. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  1111. keyconf->keylen);
  1112. priv->stations[sta_id].sta.key.key_flags = key_flags;
  1113. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1114. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1115. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1116. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1117. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1118. return 0;
  1119. }
  1120. static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
  1121. {
  1122. unsigned long flags;
  1123. spin_lock_irqsave(&priv->sta_lock, flags);
  1124. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1125. memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
  1126. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1127. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1128. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1129. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1130. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1131. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1132. return 0;
  1133. }
  1134. static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
  1135. {
  1136. struct list_head *element;
  1137. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1138. priv->frames_count);
  1139. while (!list_empty(&priv->free_frames)) {
  1140. element = priv->free_frames.next;
  1141. list_del(element);
  1142. kfree(list_entry(element, struct iwl3945_frame, list));
  1143. priv->frames_count--;
  1144. }
  1145. if (priv->frames_count) {
  1146. IWL_WARNING("%d frames still in use. Did we lose one?\n",
  1147. priv->frames_count);
  1148. priv->frames_count = 0;
  1149. }
  1150. }
  1151. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
  1152. {
  1153. struct iwl3945_frame *frame;
  1154. struct list_head *element;
  1155. if (list_empty(&priv->free_frames)) {
  1156. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1157. if (!frame) {
  1158. IWL_ERROR("Could not allocate frame!\n");
  1159. return NULL;
  1160. }
  1161. priv->frames_count++;
  1162. return frame;
  1163. }
  1164. element = priv->free_frames.next;
  1165. list_del(element);
  1166. return list_entry(element, struct iwl3945_frame, list);
  1167. }
  1168. static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
  1169. {
  1170. memset(frame, 0, sizeof(*frame));
  1171. list_add(&frame->list, &priv->free_frames);
  1172. }
  1173. unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
  1174. struct ieee80211_hdr *hdr,
  1175. int left)
  1176. {
  1177. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1178. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  1179. (priv->iw_mode != NL80211_IFTYPE_AP)))
  1180. return 0;
  1181. if (priv->ibss_beacon->len > left)
  1182. return 0;
  1183. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1184. return priv->ibss_beacon->len;
  1185. }
  1186. static u8 iwl3945_rate_get_lowest_plcp(struct iwl3945_priv *priv)
  1187. {
  1188. u8 i;
  1189. int rate_mask;
  1190. /* Set rate mask*/
  1191. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1192. rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
  1193. else
  1194. rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
  1195. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1196. i = iwl3945_rates[i].next_ieee) {
  1197. if (rate_mask & (1 << i))
  1198. return iwl3945_rates[i].plcp;
  1199. }
  1200. /* No valid rate was found. Assign the lowest one */
  1201. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1202. return IWL_RATE_1M_PLCP;
  1203. else
  1204. return IWL_RATE_6M_PLCP;
  1205. }
  1206. static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
  1207. {
  1208. struct iwl3945_frame *frame;
  1209. unsigned int frame_size;
  1210. int rc;
  1211. u8 rate;
  1212. frame = iwl3945_get_free_frame(priv);
  1213. if (!frame) {
  1214. IWL_ERROR("Could not obtain free frame buffer for beacon "
  1215. "command.\n");
  1216. return -ENOMEM;
  1217. }
  1218. rate = iwl3945_rate_get_lowest_plcp(priv);
  1219. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1220. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1221. &frame->u.cmd[0]);
  1222. iwl3945_free_frame(priv, frame);
  1223. return rc;
  1224. }
  1225. /******************************************************************************
  1226. *
  1227. * EEPROM related functions
  1228. *
  1229. ******************************************************************************/
  1230. static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
  1231. {
  1232. memcpy(mac, priv->eeprom.mac_address, 6);
  1233. }
  1234. /*
  1235. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1236. * embedded controller) as EEPROM reader; each read is a series of pulses
  1237. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1238. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1239. * simply claims ownership, which should be safe when this function is called
  1240. * (i.e. before loading uCode!).
  1241. */
  1242. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
  1243. {
  1244. _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1245. return 0;
  1246. }
  1247. /**
  1248. * iwl3945_eeprom_init - read EEPROM contents
  1249. *
  1250. * Load the EEPROM contents from adapter into priv->eeprom
  1251. *
  1252. * NOTE: This routine uses the non-debug IO access functions.
  1253. */
  1254. int iwl3945_eeprom_init(struct iwl3945_priv *priv)
  1255. {
  1256. u16 *e = (u16 *)&priv->eeprom;
  1257. u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
  1258. int sz = sizeof(priv->eeprom);
  1259. int ret;
  1260. u16 addr;
  1261. /* The EEPROM structure has several padding buffers within it
  1262. * and when adding new EEPROM maps is subject to programmer errors
  1263. * which may be very difficult to identify without explicitly
  1264. * checking the resulting size of the eeprom map. */
  1265. BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
  1266. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1267. IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
  1268. return -ENOENT;
  1269. }
  1270. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1271. ret = iwl3945_eeprom_acquire_semaphore(priv);
  1272. if (ret < 0) {
  1273. IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
  1274. return -ENOENT;
  1275. }
  1276. /* eeprom is an array of 16bit values */
  1277. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1278. u32 r;
  1279. _iwl3945_write32(priv, CSR_EEPROM_REG,
  1280. CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
  1281. _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1282. ret = iwl3945_poll_direct_bit(priv, CSR_EEPROM_REG,
  1283. CSR_EEPROM_REG_READ_VALID_MSK,
  1284. IWL_EEPROM_ACCESS_TIMEOUT);
  1285. if (ret < 0) {
  1286. IWL_ERROR("Time out reading EEPROM[%d]\n", addr);
  1287. return ret;
  1288. }
  1289. r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
  1290. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1291. }
  1292. return 0;
  1293. }
  1294. static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
  1295. {
  1296. if (priv->hw_setting.shared_virt)
  1297. pci_free_consistent(priv->pci_dev,
  1298. sizeof(struct iwl3945_shared),
  1299. priv->hw_setting.shared_virt,
  1300. priv->hw_setting.shared_phys);
  1301. }
  1302. /**
  1303. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1304. *
  1305. * return : set the bit for each supported rate insert in ie
  1306. */
  1307. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1308. u16 basic_rate, int *left)
  1309. {
  1310. u16 ret_rates = 0, bit;
  1311. int i;
  1312. u8 *cnt = ie;
  1313. u8 *rates = ie + 1;
  1314. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1315. if (bit & supported_rate) {
  1316. ret_rates |= bit;
  1317. rates[*cnt] = iwl3945_rates[i].ieee |
  1318. ((bit & basic_rate) ? 0x80 : 0x00);
  1319. (*cnt)++;
  1320. (*left)--;
  1321. if ((*left <= 0) ||
  1322. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1323. break;
  1324. }
  1325. }
  1326. return ret_rates;
  1327. }
  1328. /**
  1329. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1330. */
  1331. static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
  1332. struct ieee80211_mgmt *frame,
  1333. int left)
  1334. {
  1335. int len = 0;
  1336. u8 *pos = NULL;
  1337. u16 active_rates, ret_rates, cck_rates;
  1338. /* Make sure there is enough space for the probe request,
  1339. * two mandatory IEs and the data */
  1340. left -= 24;
  1341. if (left < 0)
  1342. return 0;
  1343. len += 24;
  1344. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1345. memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
  1346. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1347. memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
  1348. frame->seq_ctrl = 0;
  1349. /* fill in our indirect SSID IE */
  1350. /* ...next IE... */
  1351. left -= 2;
  1352. if (left < 0)
  1353. return 0;
  1354. len += 2;
  1355. pos = &(frame->u.probe_req.variable[0]);
  1356. *pos++ = WLAN_EID_SSID;
  1357. *pos++ = 0;
  1358. /* fill in supported rate */
  1359. /* ...next IE... */
  1360. left -= 2;
  1361. if (left < 0)
  1362. return 0;
  1363. /* ... fill it in... */
  1364. *pos++ = WLAN_EID_SUPP_RATES;
  1365. *pos = 0;
  1366. priv->active_rate = priv->rates_mask;
  1367. active_rates = priv->active_rate;
  1368. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1369. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1370. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1371. priv->active_rate_basic, &left);
  1372. active_rates &= ~ret_rates;
  1373. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1374. priv->active_rate_basic, &left);
  1375. active_rates &= ~ret_rates;
  1376. len += 2 + *pos;
  1377. pos += (*pos) + 1;
  1378. if (active_rates == 0)
  1379. goto fill_end;
  1380. /* fill in supported extended rate */
  1381. /* ...next IE... */
  1382. left -= 2;
  1383. if (left < 0)
  1384. return 0;
  1385. /* ... fill it in... */
  1386. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1387. *pos = 0;
  1388. iwl3945_supported_rate_to_ie(pos, active_rates,
  1389. priv->active_rate_basic, &left);
  1390. if (*pos > 0)
  1391. len += 2 + *pos;
  1392. fill_end:
  1393. return (u16)len;
  1394. }
  1395. /*
  1396. * QoS support
  1397. */
  1398. static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
  1399. struct iwl3945_qosparam_cmd *qos)
  1400. {
  1401. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1402. sizeof(struct iwl3945_qosparam_cmd), qos);
  1403. }
  1404. static void iwl3945_reset_qos(struct iwl3945_priv *priv)
  1405. {
  1406. u16 cw_min = 15;
  1407. u16 cw_max = 1023;
  1408. u8 aifs = 2;
  1409. u8 is_legacy = 0;
  1410. unsigned long flags;
  1411. int i;
  1412. spin_lock_irqsave(&priv->lock, flags);
  1413. priv->qos_data.qos_active = 0;
  1414. /* QoS always active in AP and ADHOC mode
  1415. * In STA mode wait for association
  1416. */
  1417. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  1418. priv->iw_mode == NL80211_IFTYPE_AP)
  1419. priv->qos_data.qos_active = 1;
  1420. else
  1421. priv->qos_data.qos_active = 0;
  1422. /* check for legacy mode */
  1423. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  1424. (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
  1425. (priv->iw_mode == NL80211_IFTYPE_STATION &&
  1426. (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
  1427. cw_min = 31;
  1428. is_legacy = 1;
  1429. }
  1430. if (priv->qos_data.qos_active)
  1431. aifs = 3;
  1432. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  1433. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  1434. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  1435. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  1436. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  1437. if (priv->qos_data.qos_active) {
  1438. i = 1;
  1439. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  1440. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  1441. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  1442. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1443. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1444. i = 2;
  1445. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1446. cpu_to_le16((cw_min + 1) / 2 - 1);
  1447. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1448. cpu_to_le16(cw_max);
  1449. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1450. if (is_legacy)
  1451. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1452. cpu_to_le16(6016);
  1453. else
  1454. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1455. cpu_to_le16(3008);
  1456. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1457. i = 3;
  1458. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1459. cpu_to_le16((cw_min + 1) / 4 - 1);
  1460. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1461. cpu_to_le16((cw_max + 1) / 2 - 1);
  1462. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1463. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1464. if (is_legacy)
  1465. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1466. cpu_to_le16(3264);
  1467. else
  1468. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1469. cpu_to_le16(1504);
  1470. } else {
  1471. for (i = 1; i < 4; i++) {
  1472. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1473. cpu_to_le16(cw_min);
  1474. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1475. cpu_to_le16(cw_max);
  1476. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  1477. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1478. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1479. }
  1480. }
  1481. IWL_DEBUG_QOS("set QoS to default \n");
  1482. spin_unlock_irqrestore(&priv->lock, flags);
  1483. }
  1484. static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
  1485. {
  1486. unsigned long flags;
  1487. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1488. return;
  1489. spin_lock_irqsave(&priv->lock, flags);
  1490. priv->qos_data.def_qos_parm.qos_flags = 0;
  1491. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1492. !priv->qos_data.qos_cap.q_AP.txop_request)
  1493. priv->qos_data.def_qos_parm.qos_flags |=
  1494. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1495. if (priv->qos_data.qos_active)
  1496. priv->qos_data.def_qos_parm.qos_flags |=
  1497. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1498. spin_unlock_irqrestore(&priv->lock, flags);
  1499. if (force || iwl3945_is_associated(priv)) {
  1500. IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n",
  1501. priv->qos_data.qos_active);
  1502. iwl3945_send_qos_params_command(priv,
  1503. &(priv->qos_data.def_qos_parm));
  1504. }
  1505. }
  1506. /*
  1507. * Power management (not Tx power!) functions
  1508. */
  1509. #define MSEC_TO_USEC 1024
  1510. #define NOSLP __constant_cpu_to_le32(0)
  1511. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
  1512. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1513. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1514. __constant_cpu_to_le32(X1), \
  1515. __constant_cpu_to_le32(X2), \
  1516. __constant_cpu_to_le32(X3), \
  1517. __constant_cpu_to_le32(X4)}
  1518. /* default power management (not Tx power) table values */
  1519. /* for TIM 0-10 */
  1520. static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
  1521. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1522. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1523. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1524. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1525. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1526. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1527. };
  1528. /* for TIM > 10 */
  1529. static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
  1530. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1531. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1532. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1533. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1534. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1535. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1536. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1537. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1538. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1539. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1540. };
  1541. int iwl3945_power_init_handle(struct iwl3945_priv *priv)
  1542. {
  1543. int rc = 0, i;
  1544. struct iwl3945_power_mgr *pow_data;
  1545. int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
  1546. u16 pci_pm;
  1547. IWL_DEBUG_POWER("Initialize power \n");
  1548. pow_data = &(priv->power_data);
  1549. memset(pow_data, 0, sizeof(*pow_data));
  1550. pow_data->active_index = IWL_POWER_RANGE_0;
  1551. pow_data->dtim_val = 0xffff;
  1552. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1553. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1554. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1555. if (rc != 0)
  1556. return 0;
  1557. else {
  1558. struct iwl3945_powertable_cmd *cmd;
  1559. IWL_DEBUG_POWER("adjust power command flags\n");
  1560. for (i = 0; i < IWL_POWER_AC; i++) {
  1561. cmd = &pow_data->pwr_range_0[i].cmd;
  1562. if (pci_pm & 0x1)
  1563. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1564. else
  1565. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1566. }
  1567. }
  1568. return rc;
  1569. }
  1570. static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
  1571. struct iwl3945_powertable_cmd *cmd, u32 mode)
  1572. {
  1573. int rc = 0, i;
  1574. u8 skip;
  1575. u32 max_sleep = 0;
  1576. struct iwl3945_power_vec_entry *range;
  1577. u8 period = 0;
  1578. struct iwl3945_power_mgr *pow_data;
  1579. if (mode > IWL_POWER_INDEX_5) {
  1580. IWL_DEBUG_POWER("Error invalid power mode \n");
  1581. return -1;
  1582. }
  1583. pow_data = &(priv->power_data);
  1584. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1585. range = &pow_data->pwr_range_0[0];
  1586. else
  1587. range = &pow_data->pwr_range_1[1];
  1588. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1589. #ifdef IWL_MAC80211_DISABLE
  1590. if (priv->assoc_network != NULL) {
  1591. unsigned long flags;
  1592. period = priv->assoc_network->tim.tim_period;
  1593. }
  1594. #endif /*IWL_MAC80211_DISABLE */
  1595. skip = range[mode].no_dtim;
  1596. if (period == 0) {
  1597. period = 1;
  1598. skip = 0;
  1599. }
  1600. if (skip == 0) {
  1601. max_sleep = period;
  1602. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1603. } else {
  1604. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1605. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1606. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1607. }
  1608. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1609. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1610. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1611. }
  1612. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1613. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1614. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1615. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1616. le32_to_cpu(cmd->sleep_interval[0]),
  1617. le32_to_cpu(cmd->sleep_interval[1]),
  1618. le32_to_cpu(cmd->sleep_interval[2]),
  1619. le32_to_cpu(cmd->sleep_interval[3]),
  1620. le32_to_cpu(cmd->sleep_interval[4]));
  1621. return rc;
  1622. }
  1623. static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
  1624. {
  1625. u32 uninitialized_var(final_mode);
  1626. int rc;
  1627. struct iwl3945_powertable_cmd cmd;
  1628. /* If on battery, set to 3,
  1629. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1630. * else user level */
  1631. switch (mode) {
  1632. case IWL_POWER_BATTERY:
  1633. final_mode = IWL_POWER_INDEX_3;
  1634. break;
  1635. case IWL_POWER_AC:
  1636. final_mode = IWL_POWER_MODE_CAM;
  1637. break;
  1638. default:
  1639. final_mode = mode;
  1640. break;
  1641. }
  1642. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1643. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
  1644. if (final_mode == IWL_POWER_MODE_CAM)
  1645. clear_bit(STATUS_POWER_PMI, &priv->status);
  1646. else
  1647. set_bit(STATUS_POWER_PMI, &priv->status);
  1648. return rc;
  1649. }
  1650. /**
  1651. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1652. *
  1653. * NOTE: priv->mutex is not required before calling this function
  1654. */
  1655. static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
  1656. {
  1657. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1658. clear_bit(STATUS_SCANNING, &priv->status);
  1659. return 0;
  1660. }
  1661. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1662. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1663. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1664. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1665. queue_work(priv->workqueue, &priv->abort_scan);
  1666. } else
  1667. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1668. return test_bit(STATUS_SCANNING, &priv->status);
  1669. }
  1670. return 0;
  1671. }
  1672. /**
  1673. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1674. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1675. *
  1676. * NOTE: priv->mutex must be held before calling this function
  1677. */
  1678. static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
  1679. {
  1680. unsigned long now = jiffies;
  1681. int ret;
  1682. ret = iwl3945_scan_cancel(priv);
  1683. if (ret && ms) {
  1684. mutex_unlock(&priv->mutex);
  1685. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1686. test_bit(STATUS_SCANNING, &priv->status))
  1687. msleep(1);
  1688. mutex_lock(&priv->mutex);
  1689. return test_bit(STATUS_SCANNING, &priv->status);
  1690. }
  1691. return ret;
  1692. }
  1693. #define MAX_UCODE_BEACON_INTERVAL 1024
  1694. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1695. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1696. {
  1697. u16 new_val = 0;
  1698. u16 beacon_factor = 0;
  1699. beacon_factor =
  1700. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1701. / MAX_UCODE_BEACON_INTERVAL;
  1702. new_val = beacon_val / beacon_factor;
  1703. return cpu_to_le16(new_val);
  1704. }
  1705. static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
  1706. {
  1707. u64 interval_tm_unit;
  1708. u64 tsf, result;
  1709. unsigned long flags;
  1710. struct ieee80211_conf *conf = NULL;
  1711. u16 beacon_int = 0;
  1712. conf = ieee80211_get_hw_conf(priv->hw);
  1713. spin_lock_irqsave(&priv->lock, flags);
  1714. priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
  1715. priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
  1716. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1717. tsf = priv->timestamp1;
  1718. tsf = ((tsf << 32) | priv->timestamp0);
  1719. beacon_int = priv->beacon_int;
  1720. spin_unlock_irqrestore(&priv->lock, flags);
  1721. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  1722. if (beacon_int == 0) {
  1723. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1724. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1725. } else {
  1726. priv->rxon_timing.beacon_interval =
  1727. cpu_to_le16(beacon_int);
  1728. priv->rxon_timing.beacon_interval =
  1729. iwl3945_adjust_beacon_interval(
  1730. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1731. }
  1732. priv->rxon_timing.atim_window = 0;
  1733. } else {
  1734. priv->rxon_timing.beacon_interval =
  1735. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1736. /* TODO: we need to get atim_window from upper stack
  1737. * for now we set to 0 */
  1738. priv->rxon_timing.atim_window = 0;
  1739. }
  1740. interval_tm_unit =
  1741. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1742. result = do_div(tsf, interval_tm_unit);
  1743. priv->rxon_timing.beacon_init_val =
  1744. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1745. IWL_DEBUG_ASSOC
  1746. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1747. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1748. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1749. le16_to_cpu(priv->rxon_timing.atim_window));
  1750. }
  1751. static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
  1752. {
  1753. if (!iwl3945_is_ready_rf(priv)) {
  1754. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1755. return -EIO;
  1756. }
  1757. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1758. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1759. return -EAGAIN;
  1760. }
  1761. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1762. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1763. "Queuing.\n");
  1764. return -EAGAIN;
  1765. }
  1766. IWL_DEBUG_INFO("Starting scan...\n");
  1767. if (priv->cfg->sku & IWL_SKU_G)
  1768. priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
  1769. if (priv->cfg->sku & IWL_SKU_A)
  1770. priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
  1771. set_bit(STATUS_SCANNING, &priv->status);
  1772. priv->scan_start = jiffies;
  1773. priv->scan_pass_start = priv->scan_start;
  1774. queue_work(priv->workqueue, &priv->request_scan);
  1775. return 0;
  1776. }
  1777. static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
  1778. {
  1779. struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
  1780. if (hw_decrypt)
  1781. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1782. else
  1783. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1784. return 0;
  1785. }
  1786. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
  1787. enum ieee80211_band band)
  1788. {
  1789. if (band == IEEE80211_BAND_5GHZ) {
  1790. priv->staging_rxon.flags &=
  1791. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1792. | RXON_FLG_CCK_MSK);
  1793. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1794. } else {
  1795. /* Copied from iwl3945_bg_post_associate() */
  1796. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1797. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1798. else
  1799. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1800. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1801. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1802. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1803. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1804. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1805. }
  1806. }
  1807. /*
  1808. * initialize rxon structure with default values from eeprom
  1809. */
  1810. static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv,
  1811. int mode)
  1812. {
  1813. const struct iwl3945_channel_info *ch_info;
  1814. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  1815. switch (mode) {
  1816. case NL80211_IFTYPE_AP:
  1817. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  1818. break;
  1819. case NL80211_IFTYPE_STATION:
  1820. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1821. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1822. break;
  1823. case NL80211_IFTYPE_ADHOC:
  1824. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1825. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1826. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1827. RXON_FILTER_ACCEPT_GRP_MSK;
  1828. break;
  1829. case NL80211_IFTYPE_MONITOR:
  1830. priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1831. priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1832. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1833. break;
  1834. default:
  1835. IWL_ERROR("Unsupported interface type %d\n", mode);
  1836. break;
  1837. }
  1838. #if 0
  1839. /* TODO: Figure out when short_preamble would be set and cache from
  1840. * that */
  1841. if (!hw_to_local(priv->hw)->short_preamble)
  1842. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1843. else
  1844. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1845. #endif
  1846. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1847. le16_to_cpu(priv->active_rxon.channel));
  1848. if (!ch_info)
  1849. ch_info = &priv->channel_info[0];
  1850. /*
  1851. * in some case A channels are all non IBSS
  1852. * in this case force B/G channel
  1853. */
  1854. if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info)))
  1855. ch_info = &priv->channel_info[0];
  1856. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  1857. if (is_channel_a_band(ch_info))
  1858. priv->band = IEEE80211_BAND_5GHZ;
  1859. else
  1860. priv->band = IEEE80211_BAND_2GHZ;
  1861. iwl3945_set_flags_for_phymode(priv, priv->band);
  1862. priv->staging_rxon.ofdm_basic_rates =
  1863. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1864. priv->staging_rxon.cck_basic_rates =
  1865. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1866. }
  1867. static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
  1868. {
  1869. if (mode == NL80211_IFTYPE_ADHOC) {
  1870. const struct iwl3945_channel_info *ch_info;
  1871. ch_info = iwl3945_get_channel_info(priv,
  1872. priv->band,
  1873. le16_to_cpu(priv->staging_rxon.channel));
  1874. if (!ch_info || !is_channel_ibss(ch_info)) {
  1875. IWL_ERROR("channel %d not IBSS channel\n",
  1876. le16_to_cpu(priv->staging_rxon.channel));
  1877. return -EINVAL;
  1878. }
  1879. }
  1880. iwl3945_connection_init_rx_config(priv, mode);
  1881. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1882. iwl3945_clear_stations_table(priv);
  1883. /* don't commit rxon if rf-kill is on*/
  1884. if (!iwl3945_is_ready_rf(priv))
  1885. return -EAGAIN;
  1886. cancel_delayed_work(&priv->scan_check);
  1887. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  1888. IWL_WARNING("Aborted scan still in progress after 100ms\n");
  1889. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  1890. return -EAGAIN;
  1891. }
  1892. iwl3945_commit_rxon(priv);
  1893. return 0;
  1894. }
  1895. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
  1896. struct ieee80211_tx_info *info,
  1897. struct iwl3945_cmd *cmd,
  1898. struct sk_buff *skb_frag,
  1899. int last_frag)
  1900. {
  1901. struct iwl3945_hw_key *keyinfo =
  1902. &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
  1903. switch (keyinfo->alg) {
  1904. case ALG_CCMP:
  1905. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  1906. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  1907. IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
  1908. break;
  1909. case ALG_TKIP:
  1910. #if 0
  1911. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  1912. if (last_frag)
  1913. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  1914. 8);
  1915. else
  1916. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  1917. #endif
  1918. break;
  1919. case ALG_WEP:
  1920. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  1921. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  1922. if (keyinfo->keylen == 13)
  1923. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  1924. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  1925. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  1926. "with key %d\n", info->control.hw_key->hw_key_idx);
  1927. break;
  1928. default:
  1929. printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
  1930. break;
  1931. }
  1932. }
  1933. /*
  1934. * handle build REPLY_TX command notification.
  1935. */
  1936. static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
  1937. struct iwl3945_cmd *cmd,
  1938. struct ieee80211_tx_info *info,
  1939. struct ieee80211_hdr *hdr,
  1940. int is_unicast, u8 std_id)
  1941. {
  1942. __le16 fc = hdr->frame_control;
  1943. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  1944. u8 rc_flags = info->control.rates[0].flags;
  1945. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1946. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  1947. tx_flags |= TX_CMD_FLG_ACK_MSK;
  1948. if (ieee80211_is_mgmt(fc))
  1949. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1950. if (ieee80211_is_probe_resp(fc) &&
  1951. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  1952. tx_flags |= TX_CMD_FLG_TSF_MSK;
  1953. } else {
  1954. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  1955. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1956. }
  1957. cmd->cmd.tx.sta_id = std_id;
  1958. if (ieee80211_has_morefrags(fc))
  1959. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  1960. if (ieee80211_is_data_qos(fc)) {
  1961. u8 *qc = ieee80211_get_qos_ctl(hdr);
  1962. cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
  1963. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  1964. } else {
  1965. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1966. }
  1967. if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  1968. tx_flags |= TX_CMD_FLG_RTS_MSK;
  1969. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  1970. } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  1971. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  1972. tx_flags |= TX_CMD_FLG_CTS_MSK;
  1973. }
  1974. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  1975. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  1976. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  1977. if (ieee80211_is_mgmt(fc)) {
  1978. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  1979. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  1980. else
  1981. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  1982. } else {
  1983. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  1984. #ifdef CONFIG_IWL3945_LEDS
  1985. priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
  1986. #endif
  1987. }
  1988. cmd->cmd.tx.driver_txop = 0;
  1989. cmd->cmd.tx.tx_flags = tx_flags;
  1990. cmd->cmd.tx.next_frame_len = 0;
  1991. }
  1992. /**
  1993. * iwl3945_get_sta_id - Find station's index within station table
  1994. */
  1995. static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
  1996. {
  1997. int sta_id;
  1998. u16 fc = le16_to_cpu(hdr->frame_control);
  1999. /* If this frame is broadcast or management, use broadcast station id */
  2000. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  2001. is_multicast_ether_addr(hdr->addr1))
  2002. return priv->hw_setting.bcast_sta_id;
  2003. switch (priv->iw_mode) {
  2004. /* If we are a client station in a BSS network, use the special
  2005. * AP station entry (that's the only station we communicate with) */
  2006. case NL80211_IFTYPE_STATION:
  2007. return IWL_AP_ID;
  2008. /* If we are an AP, then find the station, or use BCAST */
  2009. case NL80211_IFTYPE_AP:
  2010. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2011. if (sta_id != IWL_INVALID_STATION)
  2012. return sta_id;
  2013. return priv->hw_setting.bcast_sta_id;
  2014. /* If this frame is going out to an IBSS network, find the station,
  2015. * or create a new station table entry */
  2016. case NL80211_IFTYPE_ADHOC: {
  2017. /* Create new station table entry */
  2018. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2019. if (sta_id != IWL_INVALID_STATION)
  2020. return sta_id;
  2021. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  2022. if (sta_id != IWL_INVALID_STATION)
  2023. return sta_id;
  2024. IWL_DEBUG_DROP("Station %pM not in station map. "
  2025. "Defaulting to broadcast...\n",
  2026. hdr->addr1);
  2027. iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  2028. return priv->hw_setting.bcast_sta_id;
  2029. }
  2030. /* If we are in monitor mode, use BCAST. This is required for
  2031. * packet injection. */
  2032. case NL80211_IFTYPE_MONITOR:
  2033. return priv->hw_setting.bcast_sta_id;
  2034. default:
  2035. IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode);
  2036. return priv->hw_setting.bcast_sta_id;
  2037. }
  2038. }
  2039. /*
  2040. * start REPLY_TX command process
  2041. */
  2042. static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
  2043. {
  2044. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  2045. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  2046. struct iwl3945_tfd_frame *tfd;
  2047. u32 *control_flags;
  2048. int txq_id = skb_get_queue_mapping(skb);
  2049. struct iwl3945_tx_queue *txq = NULL;
  2050. struct iwl3945_queue *q = NULL;
  2051. dma_addr_t phys_addr;
  2052. dma_addr_t txcmd_phys;
  2053. struct iwl3945_cmd *out_cmd = NULL;
  2054. u16 len, idx, len_org, hdr_len;
  2055. u8 id;
  2056. u8 unicast;
  2057. u8 sta_id;
  2058. u8 tid = 0;
  2059. u16 seq_number = 0;
  2060. __le16 fc;
  2061. u8 wait_write_ptr = 0;
  2062. u8 *qc = NULL;
  2063. unsigned long flags;
  2064. int rc;
  2065. spin_lock_irqsave(&priv->lock, flags);
  2066. if (iwl3945_is_rfkill(priv)) {
  2067. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  2068. goto drop_unlock;
  2069. }
  2070. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  2071. IWL_ERROR("ERROR: No TX rate available.\n");
  2072. goto drop_unlock;
  2073. }
  2074. unicast = !is_multicast_ether_addr(hdr->addr1);
  2075. id = 0;
  2076. fc = hdr->frame_control;
  2077. #ifdef CONFIG_IWL3945_DEBUG
  2078. if (ieee80211_is_auth(fc))
  2079. IWL_DEBUG_TX("Sending AUTH frame\n");
  2080. else if (ieee80211_is_assoc_req(fc))
  2081. IWL_DEBUG_TX("Sending ASSOC frame\n");
  2082. else if (ieee80211_is_reassoc_req(fc))
  2083. IWL_DEBUG_TX("Sending REASSOC frame\n");
  2084. #endif
  2085. /* drop all data frame if we are not associated */
  2086. if (ieee80211_is_data(fc) &&
  2087. (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
  2088. (!iwl3945_is_associated(priv) ||
  2089. ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
  2090. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  2091. goto drop_unlock;
  2092. }
  2093. spin_unlock_irqrestore(&priv->lock, flags);
  2094. hdr_len = ieee80211_hdrlen(fc);
  2095. /* Find (or create) index into station table for destination station */
  2096. sta_id = iwl3945_get_sta_id(priv, hdr);
  2097. if (sta_id == IWL_INVALID_STATION) {
  2098. IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
  2099. hdr->addr1);
  2100. goto drop;
  2101. }
  2102. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  2103. if (ieee80211_is_data_qos(fc)) {
  2104. qc = ieee80211_get_qos_ctl(hdr);
  2105. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  2106. seq_number = priv->stations[sta_id].tid[tid].seq_number &
  2107. IEEE80211_SCTL_SEQ;
  2108. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  2109. (hdr->seq_ctrl &
  2110. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  2111. seq_number += 0x10;
  2112. }
  2113. /* Descriptor for chosen Tx queue */
  2114. txq = &priv->txq[txq_id];
  2115. q = &txq->q;
  2116. spin_lock_irqsave(&priv->lock, flags);
  2117. /* Set up first empty TFD within this queue's circular TFD buffer */
  2118. tfd = &txq->bd[q->write_ptr];
  2119. memset(tfd, 0, sizeof(*tfd));
  2120. control_flags = (u32 *) tfd;
  2121. idx = get_cmd_index(q, q->write_ptr, 0);
  2122. /* Set up driver data for this TFD */
  2123. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  2124. txq->txb[q->write_ptr].skb[0] = skb;
  2125. /* Init first empty entry in queue's array of Tx/cmd buffers */
  2126. out_cmd = &txq->cmd[idx];
  2127. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  2128. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  2129. /*
  2130. * Set up the Tx-command (not MAC!) header.
  2131. * Store the chosen Tx queue and TFD index within the sequence field;
  2132. * after Tx, uCode's Tx response will return this value so driver can
  2133. * locate the frame within the tx queue and do post-tx processing.
  2134. */
  2135. out_cmd->hdr.cmd = REPLY_TX;
  2136. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  2137. INDEX_TO_SEQ(q->write_ptr)));
  2138. /* Copy MAC header from skb into command buffer */
  2139. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  2140. /*
  2141. * Use the first empty entry in this queue's command buffer array
  2142. * to contain the Tx command and MAC header concatenated together
  2143. * (payload data will be in another buffer).
  2144. * Size of this varies, due to varying MAC header length.
  2145. * If end is not dword aligned, we'll have 2 extra bytes at the end
  2146. * of the MAC header (device reads on dword boundaries).
  2147. * We'll tell device about this padding later.
  2148. */
  2149. len = priv->hw_setting.tx_cmd_len +
  2150. sizeof(struct iwl3945_cmd_header) + hdr_len;
  2151. len_org = len;
  2152. len = (len + 3) & ~3;
  2153. if (len_org != len)
  2154. len_org = 1;
  2155. else
  2156. len_org = 0;
  2157. /* Physical address of this Tx command's header (not MAC header!),
  2158. * within command buffer array. */
  2159. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
  2160. offsetof(struct iwl3945_cmd, hdr);
  2161. /* Add buffer containing Tx command and MAC(!) header to TFD's
  2162. * first entry */
  2163. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  2164. if (info->control.hw_key)
  2165. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
  2166. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  2167. * if any (802.11 null frames have no payload). */
  2168. len = skb->len - hdr_len;
  2169. if (len) {
  2170. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  2171. len, PCI_DMA_TODEVICE);
  2172. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  2173. }
  2174. if (!len)
  2175. /* If there is no payload, then we use only one Tx buffer */
  2176. *control_flags = TFD_CTL_COUNT_SET(1);
  2177. else
  2178. /* Else use 2 buffers.
  2179. * Tell 3945 about any padding after MAC header */
  2180. *control_flags = TFD_CTL_COUNT_SET(2) |
  2181. TFD_CTL_PAD_SET(U32_PAD(len));
  2182. /* Total # bytes to be transmitted */
  2183. len = (u16)skb->len;
  2184. out_cmd->cmd.tx.len = cpu_to_le16(len);
  2185. /* TODO need this for burst mode later on */
  2186. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
  2187. /* set is_hcca to 0; it probably will never be implemented */
  2188. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  2189. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  2190. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2191. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  2192. txq->need_update = 1;
  2193. if (qc)
  2194. priv->stations[sta_id].tid[tid].seq_number = seq_number;
  2195. } else {
  2196. wait_write_ptr = 1;
  2197. txq->need_update = 0;
  2198. }
  2199. iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
  2200. sizeof(out_cmd->cmd.tx));
  2201. iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2202. ieee80211_hdrlen(fc));
  2203. /* Tell device the write index *just past* this latest filled TFD */
  2204. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  2205. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2206. spin_unlock_irqrestore(&priv->lock, flags);
  2207. if (rc)
  2208. return rc;
  2209. if ((iwl3945_queue_space(q) < q->high_mark)
  2210. && priv->mac80211_registered) {
  2211. if (wait_write_ptr) {
  2212. spin_lock_irqsave(&priv->lock, flags);
  2213. txq->need_update = 1;
  2214. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2215. spin_unlock_irqrestore(&priv->lock, flags);
  2216. }
  2217. ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
  2218. }
  2219. return 0;
  2220. drop_unlock:
  2221. spin_unlock_irqrestore(&priv->lock, flags);
  2222. drop:
  2223. return -1;
  2224. }
  2225. static void iwl3945_set_rate(struct iwl3945_priv *priv)
  2226. {
  2227. const struct ieee80211_supported_band *sband = NULL;
  2228. struct ieee80211_rate *rate;
  2229. int i;
  2230. sband = iwl3945_get_band(priv, priv->band);
  2231. if (!sband) {
  2232. IWL_ERROR("Failed to set rate: unable to get hw mode\n");
  2233. return;
  2234. }
  2235. priv->active_rate = 0;
  2236. priv->active_rate_basic = 0;
  2237. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2238. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2239. for (i = 0; i < sband->n_bitrates; i++) {
  2240. rate = &sband->bitrates[i];
  2241. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2242. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2243. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2244. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2245. priv->active_rate |= (1 << rate->hw_value);
  2246. }
  2247. }
  2248. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2249. priv->active_rate, priv->active_rate_basic);
  2250. /*
  2251. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2252. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2253. * OFDM
  2254. */
  2255. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2256. priv->staging_rxon.cck_basic_rates =
  2257. ((priv->active_rate_basic &
  2258. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2259. else
  2260. priv->staging_rxon.cck_basic_rates =
  2261. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2262. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2263. priv->staging_rxon.ofdm_basic_rates =
  2264. ((priv->active_rate_basic &
  2265. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2266. IWL_FIRST_OFDM_RATE) & 0xFF;
  2267. else
  2268. priv->staging_rxon.ofdm_basic_rates =
  2269. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2270. }
  2271. static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
  2272. {
  2273. unsigned long flags;
  2274. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2275. return;
  2276. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2277. disable_radio ? "OFF" : "ON");
  2278. if (disable_radio) {
  2279. iwl3945_scan_cancel(priv);
  2280. /* FIXME: This is a workaround for AP */
  2281. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  2282. spin_lock_irqsave(&priv->lock, flags);
  2283. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2284. CSR_UCODE_SW_BIT_RFKILL);
  2285. spin_unlock_irqrestore(&priv->lock, flags);
  2286. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2287. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2288. }
  2289. return;
  2290. }
  2291. spin_lock_irqsave(&priv->lock, flags);
  2292. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2293. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2294. spin_unlock_irqrestore(&priv->lock, flags);
  2295. /* wake up ucode */
  2296. msleep(10);
  2297. spin_lock_irqsave(&priv->lock, flags);
  2298. iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2299. if (!iwl3945_grab_nic_access(priv))
  2300. iwl3945_release_nic_access(priv);
  2301. spin_unlock_irqrestore(&priv->lock, flags);
  2302. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2303. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2304. "disabled by HW switch\n");
  2305. return;
  2306. }
  2307. if (priv->is_open)
  2308. queue_work(priv->workqueue, &priv->restart);
  2309. return;
  2310. }
  2311. void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
  2312. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2313. {
  2314. u16 fc =
  2315. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2316. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2317. return;
  2318. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2319. return;
  2320. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2321. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2322. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2323. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2324. RX_RES_STATUS_BAD_ICV_MIC)
  2325. stats->flag |= RX_FLAG_MMIC_ERROR;
  2326. case RX_RES_STATUS_SEC_TYPE_WEP:
  2327. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2328. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2329. RX_RES_STATUS_DECRYPT_OK) {
  2330. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2331. stats->flag |= RX_FLAG_DECRYPTED;
  2332. }
  2333. break;
  2334. default:
  2335. break;
  2336. }
  2337. }
  2338. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2339. #include "iwl-spectrum.h"
  2340. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2341. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2342. #define TIME_UNIT 1024
  2343. /*
  2344. * extended beacon time format
  2345. * time in usec will be changed into a 32-bit value in 8:24 format
  2346. * the high 1 byte is the beacon counts
  2347. * the lower 3 bytes is the time in usec within one beacon interval
  2348. */
  2349. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2350. {
  2351. u32 quot;
  2352. u32 rem;
  2353. u32 interval = beacon_interval * 1024;
  2354. if (!interval || !usec)
  2355. return 0;
  2356. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2357. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2358. return (quot << 24) + rem;
  2359. }
  2360. /* base is usually what we get from ucode with each received frame,
  2361. * the same as HW timer counter counting down
  2362. */
  2363. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2364. {
  2365. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2366. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2367. u32 interval = beacon_interval * TIME_UNIT;
  2368. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2369. (addon & BEACON_TIME_MASK_HIGH);
  2370. if (base_low > addon_low)
  2371. res += base_low - addon_low;
  2372. else if (base_low < addon_low) {
  2373. res += interval + base_low - addon_low;
  2374. res += (1 << 24);
  2375. } else
  2376. res += (1 << 24);
  2377. return cpu_to_le32(res);
  2378. }
  2379. static int iwl3945_get_measurement(struct iwl3945_priv *priv,
  2380. struct ieee80211_measurement_params *params,
  2381. u8 type)
  2382. {
  2383. struct iwl3945_spectrum_cmd spectrum;
  2384. struct iwl3945_rx_packet *res;
  2385. struct iwl3945_host_cmd cmd = {
  2386. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2387. .data = (void *)&spectrum,
  2388. .meta.flags = CMD_WANT_SKB,
  2389. };
  2390. u32 add_time = le64_to_cpu(params->start_time);
  2391. int rc;
  2392. int spectrum_resp_status;
  2393. int duration = le16_to_cpu(params->duration);
  2394. if (iwl3945_is_associated(priv))
  2395. add_time =
  2396. iwl3945_usecs_to_beacons(
  2397. le64_to_cpu(params->start_time) - priv->last_tsf,
  2398. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2399. memset(&spectrum, 0, sizeof(spectrum));
  2400. spectrum.channel_count = cpu_to_le16(1);
  2401. spectrum.flags =
  2402. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2403. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2404. cmd.len = sizeof(spectrum);
  2405. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2406. if (iwl3945_is_associated(priv))
  2407. spectrum.start_time =
  2408. iwl3945_add_beacon_time(priv->last_beacon_time,
  2409. add_time,
  2410. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2411. else
  2412. spectrum.start_time = 0;
  2413. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2414. spectrum.channels[0].channel = params->channel;
  2415. spectrum.channels[0].type = type;
  2416. if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2417. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2418. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2419. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2420. if (rc)
  2421. return rc;
  2422. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  2423. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2424. IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
  2425. rc = -EIO;
  2426. }
  2427. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2428. switch (spectrum_resp_status) {
  2429. case 0: /* Command will be handled */
  2430. if (res->u.spectrum.id != 0xff) {
  2431. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2432. res->u.spectrum.id);
  2433. priv->measurement_status &= ~MEASUREMENT_READY;
  2434. }
  2435. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2436. rc = 0;
  2437. break;
  2438. case 1: /* Command will not be handled */
  2439. rc = -EAGAIN;
  2440. break;
  2441. }
  2442. dev_kfree_skb_any(cmd.meta.u.skb);
  2443. return rc;
  2444. }
  2445. #endif
  2446. static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
  2447. struct iwl3945_rx_mem_buffer *rxb)
  2448. {
  2449. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2450. struct iwl3945_alive_resp *palive;
  2451. struct delayed_work *pwork;
  2452. palive = &pkt->u.alive_frame;
  2453. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2454. "0x%01X 0x%01X\n",
  2455. palive->is_valid, palive->ver_type,
  2456. palive->ver_subtype);
  2457. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2458. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2459. memcpy(&priv->card_alive_init,
  2460. &pkt->u.alive_frame,
  2461. sizeof(struct iwl3945_init_alive_resp));
  2462. pwork = &priv->init_alive_start;
  2463. } else {
  2464. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2465. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2466. sizeof(struct iwl3945_alive_resp));
  2467. pwork = &priv->alive_start;
  2468. iwl3945_disable_events(priv);
  2469. }
  2470. /* We delay the ALIVE response by 5ms to
  2471. * give the HW RF Kill time to activate... */
  2472. if (palive->is_valid == UCODE_VALID_OK)
  2473. queue_delayed_work(priv->workqueue, pwork,
  2474. msecs_to_jiffies(5));
  2475. else
  2476. IWL_WARNING("uCode did not respond OK.\n");
  2477. }
  2478. static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
  2479. struct iwl3945_rx_mem_buffer *rxb)
  2480. {
  2481. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2482. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2483. return;
  2484. }
  2485. static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
  2486. struct iwl3945_rx_mem_buffer *rxb)
  2487. {
  2488. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2489. IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
  2490. "seq 0x%04X ser 0x%08X\n",
  2491. le32_to_cpu(pkt->u.err_resp.error_type),
  2492. get_cmd_string(pkt->u.err_resp.cmd_id),
  2493. pkt->u.err_resp.cmd_id,
  2494. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2495. le32_to_cpu(pkt->u.err_resp.error_info));
  2496. }
  2497. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2498. static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
  2499. {
  2500. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2501. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
  2502. struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
  2503. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2504. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2505. rxon->channel = csa->channel;
  2506. priv->staging_rxon.channel = csa->channel;
  2507. }
  2508. static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
  2509. struct iwl3945_rx_mem_buffer *rxb)
  2510. {
  2511. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2512. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2513. struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2514. if (!report->state) {
  2515. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2516. "Spectrum Measure Notification: Start\n");
  2517. return;
  2518. }
  2519. memcpy(&priv->measure_report, report, sizeof(*report));
  2520. priv->measurement_status |= MEASUREMENT_READY;
  2521. #endif
  2522. }
  2523. static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
  2524. struct iwl3945_rx_mem_buffer *rxb)
  2525. {
  2526. #ifdef CONFIG_IWL3945_DEBUG
  2527. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2528. struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2529. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2530. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2531. #endif
  2532. }
  2533. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
  2534. struct iwl3945_rx_mem_buffer *rxb)
  2535. {
  2536. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2537. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2538. "notification for %s:\n",
  2539. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2540. iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
  2541. }
  2542. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2543. {
  2544. struct iwl3945_priv *priv =
  2545. container_of(work, struct iwl3945_priv, beacon_update);
  2546. struct sk_buff *beacon;
  2547. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2548. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  2549. if (!beacon) {
  2550. IWL_ERROR("update beacon failed\n");
  2551. return;
  2552. }
  2553. mutex_lock(&priv->mutex);
  2554. /* new beacon skb is allocated every time; dispose previous.*/
  2555. if (priv->ibss_beacon)
  2556. dev_kfree_skb(priv->ibss_beacon);
  2557. priv->ibss_beacon = beacon;
  2558. mutex_unlock(&priv->mutex);
  2559. iwl3945_send_beacon_cmd(priv);
  2560. }
  2561. static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
  2562. struct iwl3945_rx_mem_buffer *rxb)
  2563. {
  2564. #ifdef CONFIG_IWL3945_DEBUG
  2565. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2566. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2567. u8 rate = beacon->beacon_notify_hdr.rate;
  2568. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2569. "tsf %d %d rate %d\n",
  2570. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2571. beacon->beacon_notify_hdr.failure_frame,
  2572. le32_to_cpu(beacon->ibss_mgr_status),
  2573. le32_to_cpu(beacon->high_tsf),
  2574. le32_to_cpu(beacon->low_tsf), rate);
  2575. #endif
  2576. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  2577. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2578. queue_work(priv->workqueue, &priv->beacon_update);
  2579. }
  2580. /* Service response to REPLY_SCAN_CMD (0x80) */
  2581. static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
  2582. struct iwl3945_rx_mem_buffer *rxb)
  2583. {
  2584. #ifdef CONFIG_IWL3945_DEBUG
  2585. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2586. struct iwl3945_scanreq_notification *notif =
  2587. (struct iwl3945_scanreq_notification *)pkt->u.raw;
  2588. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  2589. #endif
  2590. }
  2591. /* Service SCAN_START_NOTIFICATION (0x82) */
  2592. static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
  2593. struct iwl3945_rx_mem_buffer *rxb)
  2594. {
  2595. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2596. struct iwl3945_scanstart_notification *notif =
  2597. (struct iwl3945_scanstart_notification *)pkt->u.raw;
  2598. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2599. IWL_DEBUG_SCAN("Scan start: "
  2600. "%d [802.11%s] "
  2601. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2602. notif->channel,
  2603. notif->band ? "bg" : "a",
  2604. notif->tsf_high,
  2605. notif->tsf_low, notif->status, notif->beacon_timer);
  2606. }
  2607. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2608. static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
  2609. struct iwl3945_rx_mem_buffer *rxb)
  2610. {
  2611. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2612. struct iwl3945_scanresults_notification *notif =
  2613. (struct iwl3945_scanresults_notification *)pkt->u.raw;
  2614. IWL_DEBUG_SCAN("Scan ch.res: "
  2615. "%d [802.11%s] "
  2616. "(TSF: 0x%08X:%08X) - %d "
  2617. "elapsed=%lu usec (%dms since last)\n",
  2618. notif->channel,
  2619. notif->band ? "bg" : "a",
  2620. le32_to_cpu(notif->tsf_high),
  2621. le32_to_cpu(notif->tsf_low),
  2622. le32_to_cpu(notif->statistics[0]),
  2623. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2624. jiffies_to_msecs(elapsed_jiffies
  2625. (priv->last_scan_jiffies, jiffies)));
  2626. priv->last_scan_jiffies = jiffies;
  2627. priv->next_scan_jiffies = 0;
  2628. }
  2629. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2630. static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
  2631. struct iwl3945_rx_mem_buffer *rxb)
  2632. {
  2633. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2634. struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2635. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2636. scan_notif->scanned_channels,
  2637. scan_notif->tsf_low,
  2638. scan_notif->tsf_high, scan_notif->status);
  2639. /* The HW is no longer scanning */
  2640. clear_bit(STATUS_SCAN_HW, &priv->status);
  2641. /* The scan completion notification came in, so kill that timer... */
  2642. cancel_delayed_work(&priv->scan_check);
  2643. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2644. (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
  2645. "2.4" : "5.2",
  2646. jiffies_to_msecs(elapsed_jiffies
  2647. (priv->scan_pass_start, jiffies)));
  2648. /* Remove this scanned band from the list of pending
  2649. * bands to scan, band G precedes A in order of scanning
  2650. * as seen in iwl3945_bg_request_scan */
  2651. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
  2652. priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
  2653. else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
  2654. priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
  2655. /* If a request to abort was given, or the scan did not succeed
  2656. * then we reset the scan state machine and terminate,
  2657. * re-queuing another scan if one has been requested */
  2658. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2659. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2660. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2661. } else {
  2662. /* If there are more bands on this scan pass reschedule */
  2663. if (priv->scan_bands > 0)
  2664. goto reschedule;
  2665. }
  2666. priv->last_scan_jiffies = jiffies;
  2667. priv->next_scan_jiffies = 0;
  2668. IWL_DEBUG_INFO("Setting scan to off\n");
  2669. clear_bit(STATUS_SCANNING, &priv->status);
  2670. IWL_DEBUG_INFO("Scan took %dms\n",
  2671. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2672. queue_work(priv->workqueue, &priv->scan_completed);
  2673. return;
  2674. reschedule:
  2675. priv->scan_pass_start = jiffies;
  2676. queue_work(priv->workqueue, &priv->request_scan);
  2677. }
  2678. /* Handle notification from uCode that card's power state is changing
  2679. * due to software, hardware, or critical temperature RFKILL */
  2680. static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
  2681. struct iwl3945_rx_mem_buffer *rxb)
  2682. {
  2683. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2684. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2685. unsigned long status = priv->status;
  2686. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2687. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2688. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2689. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2690. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2691. if (flags & HW_CARD_DISABLED)
  2692. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2693. else
  2694. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2695. if (flags & SW_CARD_DISABLED)
  2696. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2697. else
  2698. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2699. iwl3945_scan_cancel(priv);
  2700. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2701. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2702. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2703. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2704. queue_work(priv->workqueue, &priv->rf_kill);
  2705. else
  2706. wake_up_interruptible(&priv->wait_command_queue);
  2707. }
  2708. /**
  2709. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2710. *
  2711. * Setup the RX handlers for each of the reply types sent from the uCode
  2712. * to the host.
  2713. *
  2714. * This function chains into the hardware specific files for them to setup
  2715. * any hardware specific handlers as well.
  2716. */
  2717. static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
  2718. {
  2719. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  2720. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  2721. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  2722. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  2723. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  2724. iwl3945_rx_spectrum_measure_notif;
  2725. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  2726. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  2727. iwl3945_rx_pm_debug_statistics_notif;
  2728. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  2729. /*
  2730. * The same handler is used for both the REPLY to a discrete
  2731. * statistics request from the host as well as for the periodic
  2732. * statistics notifications (after received beacons) from the uCode.
  2733. */
  2734. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  2735. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  2736. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  2737. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  2738. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  2739. iwl3945_rx_scan_results_notif;
  2740. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  2741. iwl3945_rx_scan_complete_notif;
  2742. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  2743. /* Set up hardware specific Rx handlers */
  2744. iwl3945_hw_rx_handler_setup(priv);
  2745. }
  2746. /**
  2747. * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
  2748. * When FW advances 'R' index, all entries between old and new 'R' index
  2749. * need to be reclaimed.
  2750. */
  2751. static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
  2752. int txq_id, int index)
  2753. {
  2754. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2755. struct iwl3945_queue *q = &txq->q;
  2756. int nfreed = 0;
  2757. if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
  2758. IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
  2759. "is out of range [0-%d] %d %d.\n", txq_id,
  2760. index, q->n_bd, q->write_ptr, q->read_ptr);
  2761. return;
  2762. }
  2763. for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
  2764. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2765. if (nfreed > 1) {
  2766. IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
  2767. q->write_ptr, q->read_ptr);
  2768. queue_work(priv->workqueue, &priv->restart);
  2769. break;
  2770. }
  2771. nfreed++;
  2772. }
  2773. }
  2774. /**
  2775. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2776. * @rxb: Rx buffer to reclaim
  2777. *
  2778. * If an Rx buffer has an async callback associated with it the callback
  2779. * will be executed. The attached skb (if present) will only be freed
  2780. * if the callback returns 1
  2781. */
  2782. static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
  2783. struct iwl3945_rx_mem_buffer *rxb)
  2784. {
  2785. struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  2786. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2787. int txq_id = SEQ_TO_QUEUE(sequence);
  2788. int index = SEQ_TO_INDEX(sequence);
  2789. int huge = sequence & SEQ_HUGE_FRAME;
  2790. int cmd_index;
  2791. struct iwl3945_cmd *cmd;
  2792. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  2793. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  2794. cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  2795. /* Input error checking is done when commands are added to queue. */
  2796. if (cmd->meta.flags & CMD_WANT_SKB) {
  2797. cmd->meta.source->u.skb = rxb->skb;
  2798. rxb->skb = NULL;
  2799. } else if (cmd->meta.u.callback &&
  2800. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  2801. rxb->skb = NULL;
  2802. iwl3945_cmd_queue_reclaim(priv, txq_id, index);
  2803. if (!(cmd->meta.flags & CMD_ASYNC)) {
  2804. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  2805. wake_up_interruptible(&priv->wait_command_queue);
  2806. }
  2807. }
  2808. /************************** RX-FUNCTIONS ****************************/
  2809. /*
  2810. * Rx theory of operation
  2811. *
  2812. * The host allocates 32 DMA target addresses and passes the host address
  2813. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  2814. * 0 to 31
  2815. *
  2816. * Rx Queue Indexes
  2817. * The host/firmware share two index registers for managing the Rx buffers.
  2818. *
  2819. * The READ index maps to the first position that the firmware may be writing
  2820. * to -- the driver can read up to (but not including) this position and get
  2821. * good data.
  2822. * The READ index is managed by the firmware once the card is enabled.
  2823. *
  2824. * The WRITE index maps to the last position the driver has read from -- the
  2825. * position preceding WRITE is the last slot the firmware can place a packet.
  2826. *
  2827. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2828. * WRITE = READ.
  2829. *
  2830. * During initialization, the host sets up the READ queue position to the first
  2831. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  2832. *
  2833. * When the firmware places a packet in a buffer, it will advance the READ index
  2834. * and fire the RX interrupt. The driver can then query the READ index and
  2835. * process as many packets as possible, moving the WRITE index forward as it
  2836. * resets the Rx queue buffers with new memory.
  2837. *
  2838. * The management in the driver is as follows:
  2839. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2840. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2841. * to replenish the iwl->rxq->rx_free.
  2842. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  2843. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  2844. * 'processed' and 'read' driver indexes as well)
  2845. * + A received packet is processed and handed to the kernel network stack,
  2846. * detached from the iwl->rxq. The driver 'processed' index is updated.
  2847. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2848. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2849. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  2850. * were enough free buffers and RX_STALLED is set it is cleared.
  2851. *
  2852. *
  2853. * Driver sequence:
  2854. *
  2855. * iwl3945_rx_queue_alloc() Allocates rx_free
  2856. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2857. * iwl3945_rx_queue_restock
  2858. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  2859. * queue, updates firmware pointers, and updates
  2860. * the WRITE index. If insufficient rx_free buffers
  2861. * are available, schedules iwl3945_rx_replenish
  2862. *
  2863. * -- enable interrupts --
  2864. * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
  2865. * READ INDEX, detaching the SKB from the pool.
  2866. * Moves the packet buffer from queue to rx_used.
  2867. * Calls iwl3945_rx_queue_restock to refill any empty
  2868. * slots.
  2869. * ...
  2870. *
  2871. */
  2872. /**
  2873. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  2874. */
  2875. static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
  2876. {
  2877. int s = q->read - q->write;
  2878. if (s <= 0)
  2879. s += RX_QUEUE_SIZE;
  2880. /* keep some buffer to not confuse full and empty queue */
  2881. s -= 2;
  2882. if (s < 0)
  2883. s = 0;
  2884. return s;
  2885. }
  2886. /**
  2887. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  2888. */
  2889. int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
  2890. {
  2891. u32 reg = 0;
  2892. int rc = 0;
  2893. unsigned long flags;
  2894. spin_lock_irqsave(&q->lock, flags);
  2895. if (q->need_update == 0)
  2896. goto exit_unlock;
  2897. /* If power-saving is in use, make sure device is awake */
  2898. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  2899. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2900. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2901. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  2902. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2903. goto exit_unlock;
  2904. }
  2905. rc = iwl3945_grab_nic_access(priv);
  2906. if (rc)
  2907. goto exit_unlock;
  2908. /* Device expects a multiple of 8 */
  2909. iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
  2910. q->write & ~0x7);
  2911. iwl3945_release_nic_access(priv);
  2912. /* Else device is assumed to be awake */
  2913. } else
  2914. /* Device expects a multiple of 8 */
  2915. iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  2916. q->need_update = 0;
  2917. exit_unlock:
  2918. spin_unlock_irqrestore(&q->lock, flags);
  2919. return rc;
  2920. }
  2921. /**
  2922. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  2923. */
  2924. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
  2925. dma_addr_t dma_addr)
  2926. {
  2927. return cpu_to_le32((u32)dma_addr);
  2928. }
  2929. /**
  2930. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  2931. *
  2932. * If there are slots in the RX queue that need to be restocked,
  2933. * and we have free pre-allocated buffers, fill the ranks as much
  2934. * as we can, pulling from rx_free.
  2935. *
  2936. * This moves the 'write' index forward to catch up with 'processed', and
  2937. * also updates the memory address in the firmware to reference the new
  2938. * target buffer.
  2939. */
  2940. static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
  2941. {
  2942. struct iwl3945_rx_queue *rxq = &priv->rxq;
  2943. struct list_head *element;
  2944. struct iwl3945_rx_mem_buffer *rxb;
  2945. unsigned long flags;
  2946. int write, rc;
  2947. spin_lock_irqsave(&rxq->lock, flags);
  2948. write = rxq->write & ~0x7;
  2949. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  2950. /* Get next free Rx buffer, remove from free list */
  2951. element = rxq->rx_free.next;
  2952. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  2953. list_del(element);
  2954. /* Point to Rx buffer via next RBD in circular buffer */
  2955. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
  2956. rxq->queue[rxq->write] = rxb;
  2957. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  2958. rxq->free_count--;
  2959. }
  2960. spin_unlock_irqrestore(&rxq->lock, flags);
  2961. /* If the pre-allocated buffer pool is dropping low, schedule to
  2962. * refill it */
  2963. if (rxq->free_count <= RX_LOW_WATERMARK)
  2964. queue_work(priv->workqueue, &priv->rx_replenish);
  2965. /* If we've added more space for the firmware to place data, tell it.
  2966. * Increment device's write pointer in multiples of 8. */
  2967. if ((write != (rxq->write & ~0x7))
  2968. || (abs(rxq->write - rxq->read) > 7)) {
  2969. spin_lock_irqsave(&rxq->lock, flags);
  2970. rxq->need_update = 1;
  2971. spin_unlock_irqrestore(&rxq->lock, flags);
  2972. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  2973. if (rc)
  2974. return rc;
  2975. }
  2976. return 0;
  2977. }
  2978. /**
  2979. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  2980. *
  2981. * When moving to rx_free an SKB is allocated for the slot.
  2982. *
  2983. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  2984. * This is called as a scheduled work item (except for during initialization)
  2985. */
  2986. static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
  2987. {
  2988. struct iwl3945_rx_queue *rxq = &priv->rxq;
  2989. struct list_head *element;
  2990. struct iwl3945_rx_mem_buffer *rxb;
  2991. unsigned long flags;
  2992. spin_lock_irqsave(&rxq->lock, flags);
  2993. while (!list_empty(&rxq->rx_used)) {
  2994. element = rxq->rx_used.next;
  2995. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  2996. /* Alloc a new receive buffer */
  2997. rxb->skb =
  2998. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  2999. if (!rxb->skb) {
  3000. if (net_ratelimit())
  3001. printk(KERN_CRIT DRV_NAME
  3002. ": Can not allocate SKB buffers\n");
  3003. /* We don't reschedule replenish work here -- we will
  3004. * call the restock method and if it still needs
  3005. * more buffers it will schedule replenish */
  3006. break;
  3007. }
  3008. /* If radiotap head is required, reserve some headroom here.
  3009. * The physical head count is a variable rx_stats->phy_count.
  3010. * We reserve 4 bytes here. Plus these extra bytes, the
  3011. * headroom of the physical head should be enough for the
  3012. * radiotap head that iwl3945 supported. See iwl3945_rt.
  3013. */
  3014. skb_reserve(rxb->skb, 4);
  3015. priv->alloc_rxb_skb++;
  3016. list_del(element);
  3017. /* Get physical address of RB/SKB */
  3018. rxb->dma_addr =
  3019. pci_map_single(priv->pci_dev, rxb->skb->data,
  3020. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3021. list_add_tail(&rxb->list, &rxq->rx_free);
  3022. rxq->free_count++;
  3023. }
  3024. spin_unlock_irqrestore(&rxq->lock, flags);
  3025. }
  3026. /*
  3027. * this should be called while priv->lock is locked
  3028. */
  3029. static void __iwl3945_rx_replenish(void *data)
  3030. {
  3031. struct iwl3945_priv *priv = data;
  3032. iwl3945_rx_allocate(priv);
  3033. iwl3945_rx_queue_restock(priv);
  3034. }
  3035. void iwl3945_rx_replenish(void *data)
  3036. {
  3037. struct iwl3945_priv *priv = data;
  3038. unsigned long flags;
  3039. iwl3945_rx_allocate(priv);
  3040. spin_lock_irqsave(&priv->lock, flags);
  3041. iwl3945_rx_queue_restock(priv);
  3042. spin_unlock_irqrestore(&priv->lock, flags);
  3043. }
  3044. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  3045. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  3046. * This free routine walks the list of POOL entries and if SKB is set to
  3047. * non NULL it is unmapped and freed
  3048. */
  3049. static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3050. {
  3051. int i;
  3052. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  3053. if (rxq->pool[i].skb != NULL) {
  3054. pci_unmap_single(priv->pci_dev,
  3055. rxq->pool[i].dma_addr,
  3056. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3057. dev_kfree_skb(rxq->pool[i].skb);
  3058. }
  3059. }
  3060. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  3061. rxq->dma_addr);
  3062. rxq->bd = NULL;
  3063. }
  3064. int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
  3065. {
  3066. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3067. struct pci_dev *dev = priv->pci_dev;
  3068. int i;
  3069. spin_lock_init(&rxq->lock);
  3070. INIT_LIST_HEAD(&rxq->rx_free);
  3071. INIT_LIST_HEAD(&rxq->rx_used);
  3072. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  3073. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  3074. if (!rxq->bd)
  3075. return -ENOMEM;
  3076. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3077. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  3078. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3079. /* Set us so that we have processed and used all buffers, but have
  3080. * not restocked the Rx queue with fresh buffers */
  3081. rxq->read = rxq->write = 0;
  3082. rxq->free_count = 0;
  3083. rxq->need_update = 0;
  3084. return 0;
  3085. }
  3086. void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3087. {
  3088. unsigned long flags;
  3089. int i;
  3090. spin_lock_irqsave(&rxq->lock, flags);
  3091. INIT_LIST_HEAD(&rxq->rx_free);
  3092. INIT_LIST_HEAD(&rxq->rx_used);
  3093. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3094. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  3095. /* In the reset function, these buffers may have been allocated
  3096. * to an SKB, so we need to unmap and free potential storage */
  3097. if (rxq->pool[i].skb != NULL) {
  3098. pci_unmap_single(priv->pci_dev,
  3099. rxq->pool[i].dma_addr,
  3100. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3101. priv->alloc_rxb_skb--;
  3102. dev_kfree_skb(rxq->pool[i].skb);
  3103. rxq->pool[i].skb = NULL;
  3104. }
  3105. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3106. }
  3107. /* Set us so that we have processed and used all buffers, but have
  3108. * not restocked the Rx queue with fresh buffers */
  3109. rxq->read = rxq->write = 0;
  3110. rxq->free_count = 0;
  3111. spin_unlock_irqrestore(&rxq->lock, flags);
  3112. }
  3113. /* Convert linear signal-to-noise ratio into dB */
  3114. static u8 ratio2dB[100] = {
  3115. /* 0 1 2 3 4 5 6 7 8 9 */
  3116. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  3117. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  3118. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  3119. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  3120. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  3121. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  3122. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  3123. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  3124. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  3125. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  3126. };
  3127. /* Calculates a relative dB value from a ratio of linear
  3128. * (i.e. not dB) signal levels.
  3129. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  3130. int iwl3945_calc_db_from_ratio(int sig_ratio)
  3131. {
  3132. /* 1000:1 or higher just report as 60 dB */
  3133. if (sig_ratio >= 1000)
  3134. return 60;
  3135. /* 100:1 or higher, divide by 10 and use table,
  3136. * add 20 dB to make up for divide by 10 */
  3137. if (sig_ratio >= 100)
  3138. return 20 + (int)ratio2dB[sig_ratio/10];
  3139. /* We shouldn't see this */
  3140. if (sig_ratio < 1)
  3141. return 0;
  3142. /* Use table for ratios 1:1 - 99:1 */
  3143. return (int)ratio2dB[sig_ratio];
  3144. }
  3145. #define PERFECT_RSSI (-20) /* dBm */
  3146. #define WORST_RSSI (-95) /* dBm */
  3147. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  3148. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  3149. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  3150. * about formulas used below. */
  3151. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  3152. {
  3153. int sig_qual;
  3154. int degradation = PERFECT_RSSI - rssi_dbm;
  3155. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  3156. * as indicator; formula is (signal dbm - noise dbm).
  3157. * SNR at or above 40 is a great signal (100%).
  3158. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  3159. * Weakest usable signal is usually 10 - 15 dB SNR. */
  3160. if (noise_dbm) {
  3161. if (rssi_dbm - noise_dbm >= 40)
  3162. return 100;
  3163. else if (rssi_dbm < noise_dbm)
  3164. return 0;
  3165. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  3166. /* Else use just the signal level.
  3167. * This formula is a least squares fit of data points collected and
  3168. * compared with a reference system that had a percentage (%) display
  3169. * for signal quality. */
  3170. } else
  3171. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  3172. (15 * RSSI_RANGE + 62 * degradation)) /
  3173. (RSSI_RANGE * RSSI_RANGE);
  3174. if (sig_qual > 100)
  3175. sig_qual = 100;
  3176. else if (sig_qual < 1)
  3177. sig_qual = 0;
  3178. return sig_qual;
  3179. }
  3180. /**
  3181. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  3182. *
  3183. * Uses the priv->rx_handlers callback function array to invoke
  3184. * the appropriate handlers, including command responses,
  3185. * frame-received notifications, and other notifications.
  3186. */
  3187. static void iwl3945_rx_handle(struct iwl3945_priv *priv)
  3188. {
  3189. struct iwl3945_rx_mem_buffer *rxb;
  3190. struct iwl3945_rx_packet *pkt;
  3191. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3192. u32 r, i;
  3193. int reclaim;
  3194. unsigned long flags;
  3195. u8 fill_rx = 0;
  3196. u32 count = 8;
  3197. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3198. * buffer that the driver may process (last buffer filled by ucode). */
  3199. r = iwl3945_hw_get_rx_read(priv);
  3200. i = rxq->read;
  3201. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3202. fill_rx = 1;
  3203. /* Rx interrupt, but nothing sent from uCode */
  3204. if (i == r)
  3205. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3206. while (i != r) {
  3207. rxb = rxq->queue[i];
  3208. /* If an RXB doesn't have a Rx queue slot associated with it,
  3209. * then a bug has been introduced in the queue refilling
  3210. * routines -- catch it here */
  3211. BUG_ON(rxb == NULL);
  3212. rxq->queue[i] = NULL;
  3213. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
  3214. IWL_RX_BUF_SIZE,
  3215. PCI_DMA_FROMDEVICE);
  3216. pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3217. /* Reclaim a command buffer only if this packet is a response
  3218. * to a (driver-originated) command.
  3219. * If the packet (e.g. Rx frame) originated from uCode,
  3220. * there is no command buffer to reclaim.
  3221. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3222. * but apparently a few don't get set; catch them here. */
  3223. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3224. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3225. (pkt->hdr.cmd != REPLY_TX);
  3226. /* Based on type of command response or notification,
  3227. * handle those that need handling via function in
  3228. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3229. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3230. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3231. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3232. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3233. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3234. } else {
  3235. /* No handling needed */
  3236. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3237. "r %d i %d No handler needed for %s, 0x%02x\n",
  3238. r, i, get_cmd_string(pkt->hdr.cmd),
  3239. pkt->hdr.cmd);
  3240. }
  3241. if (reclaim) {
  3242. /* Invoke any callbacks, transfer the skb to caller, and
  3243. * fire off the (possibly) blocking iwl3945_send_cmd()
  3244. * as we reclaim the driver command queue */
  3245. if (rxb && rxb->skb)
  3246. iwl3945_tx_cmd_complete(priv, rxb);
  3247. else
  3248. IWL_WARNING("Claim null rxb?\n");
  3249. }
  3250. /* For now we just don't re-use anything. We can tweak this
  3251. * later to try and re-use notification packets and SKBs that
  3252. * fail to Rx correctly */
  3253. if (rxb->skb != NULL) {
  3254. priv->alloc_rxb_skb--;
  3255. dev_kfree_skb_any(rxb->skb);
  3256. rxb->skb = NULL;
  3257. }
  3258. pci_unmap_single(priv->pci_dev, rxb->dma_addr,
  3259. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3260. spin_lock_irqsave(&rxq->lock, flags);
  3261. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3262. spin_unlock_irqrestore(&rxq->lock, flags);
  3263. i = (i + 1) & RX_QUEUE_MASK;
  3264. /* If there are a lot of unused frames,
  3265. * restock the Rx queue so ucode won't assert. */
  3266. if (fill_rx) {
  3267. count++;
  3268. if (count >= 8) {
  3269. priv->rxq.read = i;
  3270. __iwl3945_rx_replenish(priv);
  3271. count = 0;
  3272. }
  3273. }
  3274. }
  3275. /* Backtrack one entry */
  3276. priv->rxq.read = i;
  3277. iwl3945_rx_queue_restock(priv);
  3278. }
  3279. /**
  3280. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3281. */
  3282. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  3283. struct iwl3945_tx_queue *txq)
  3284. {
  3285. u32 reg = 0;
  3286. int rc = 0;
  3287. int txq_id = txq->q.id;
  3288. if (txq->need_update == 0)
  3289. return rc;
  3290. /* if we're trying to save power */
  3291. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3292. /* wake up nic if it's powered down ...
  3293. * uCode will wake up, and interrupt us again, so next
  3294. * time we'll skip this part. */
  3295. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3296. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3297. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3298. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3299. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3300. return rc;
  3301. }
  3302. /* restore this queue's parameters in nic hardware. */
  3303. rc = iwl3945_grab_nic_access(priv);
  3304. if (rc)
  3305. return rc;
  3306. iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
  3307. txq->q.write_ptr | (txq_id << 8));
  3308. iwl3945_release_nic_access(priv);
  3309. /* else not in power-save mode, uCode will never sleep when we're
  3310. * trying to tx (during RFKILL, we're not trying to tx). */
  3311. } else
  3312. iwl3945_write32(priv, HBUS_TARG_WRPTR,
  3313. txq->q.write_ptr | (txq_id << 8));
  3314. txq->need_update = 0;
  3315. return rc;
  3316. }
  3317. #ifdef CONFIG_IWL3945_DEBUG
  3318. static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
  3319. {
  3320. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3321. iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3322. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3323. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3324. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3325. le32_to_cpu(rxon->filter_flags));
  3326. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3327. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3328. rxon->ofdm_basic_rates);
  3329. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3330. IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
  3331. IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  3332. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3333. }
  3334. #endif
  3335. static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
  3336. {
  3337. IWL_DEBUG_ISR("Enabling interrupts\n");
  3338. set_bit(STATUS_INT_ENABLED, &priv->status);
  3339. iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3340. }
  3341. /* call this function to flush any scheduled tasklet */
  3342. static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
  3343. {
  3344. /* wait to make sure we flush pending tasklet*/
  3345. synchronize_irq(priv->pci_dev->irq);
  3346. tasklet_kill(&priv->irq_tasklet);
  3347. }
  3348. static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
  3349. {
  3350. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3351. /* disable interrupts from uCode/NIC to host */
  3352. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3353. /* acknowledge/clear/reset any interrupts still pending
  3354. * from uCode or flow handler (Rx/Tx DMA) */
  3355. iwl3945_write32(priv, CSR_INT, 0xffffffff);
  3356. iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3357. IWL_DEBUG_ISR("Disabled interrupts\n");
  3358. }
  3359. static const char *desc_lookup(int i)
  3360. {
  3361. switch (i) {
  3362. case 1:
  3363. return "FAIL";
  3364. case 2:
  3365. return "BAD_PARAM";
  3366. case 3:
  3367. return "BAD_CHECKSUM";
  3368. case 4:
  3369. return "NMI_INTERRUPT";
  3370. case 5:
  3371. return "SYSASSERT";
  3372. case 6:
  3373. return "FATAL_ERROR";
  3374. }
  3375. return "UNKNOWN";
  3376. }
  3377. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3378. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3379. static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
  3380. {
  3381. u32 i;
  3382. u32 desc, time, count, base, data1;
  3383. u32 blink1, blink2, ilink1, ilink2;
  3384. int rc;
  3385. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3386. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3387. IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
  3388. return;
  3389. }
  3390. rc = iwl3945_grab_nic_access(priv);
  3391. if (rc) {
  3392. IWL_WARNING("Can not read from adapter at this time.\n");
  3393. return;
  3394. }
  3395. count = iwl3945_read_targ_mem(priv, base);
  3396. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3397. IWL_ERROR("Start IWL Error Log Dump:\n");
  3398. IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
  3399. }
  3400. IWL_ERROR("Desc Time asrtPC blink2 "
  3401. "ilink1 nmiPC Line\n");
  3402. for (i = ERROR_START_OFFSET;
  3403. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3404. i += ERROR_ELEM_SIZE) {
  3405. desc = iwl3945_read_targ_mem(priv, base + i);
  3406. time =
  3407. iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3408. blink1 =
  3409. iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3410. blink2 =
  3411. iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3412. ilink1 =
  3413. iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3414. ilink2 =
  3415. iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3416. data1 =
  3417. iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3418. IWL_ERROR
  3419. ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3420. desc_lookup(desc), desc, time, blink1, blink2,
  3421. ilink1, ilink2, data1);
  3422. }
  3423. iwl3945_release_nic_access(priv);
  3424. }
  3425. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3426. /**
  3427. * iwl3945_print_event_log - Dump error event log to syslog
  3428. *
  3429. * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
  3430. */
  3431. static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
  3432. u32 num_events, u32 mode)
  3433. {
  3434. u32 i;
  3435. u32 base; /* SRAM byte address of event log header */
  3436. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3437. u32 ptr; /* SRAM byte address of log data */
  3438. u32 ev, time, data; /* event log data */
  3439. if (num_events == 0)
  3440. return;
  3441. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3442. if (mode == 0)
  3443. event_size = 2 * sizeof(u32);
  3444. else
  3445. event_size = 3 * sizeof(u32);
  3446. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3447. /* "time" is actually "data" for mode 0 (no timestamp).
  3448. * place event id # at far right for easier visual parsing. */
  3449. for (i = 0; i < num_events; i++) {
  3450. ev = iwl3945_read_targ_mem(priv, ptr);
  3451. ptr += sizeof(u32);
  3452. time = iwl3945_read_targ_mem(priv, ptr);
  3453. ptr += sizeof(u32);
  3454. if (mode == 0)
  3455. IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
  3456. else {
  3457. data = iwl3945_read_targ_mem(priv, ptr);
  3458. ptr += sizeof(u32);
  3459. IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
  3460. }
  3461. }
  3462. }
  3463. static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
  3464. {
  3465. int rc;
  3466. u32 base; /* SRAM byte address of event log header */
  3467. u32 capacity; /* event log capacity in # entries */
  3468. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3469. u32 num_wraps; /* # times uCode wrapped to top of log */
  3470. u32 next_entry; /* index of next entry to be written by uCode */
  3471. u32 size; /* # entries that we'll print */
  3472. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3473. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3474. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  3475. return;
  3476. }
  3477. rc = iwl3945_grab_nic_access(priv);
  3478. if (rc) {
  3479. IWL_WARNING("Can not read from adapter at this time.\n");
  3480. return;
  3481. }
  3482. /* event log header */
  3483. capacity = iwl3945_read_targ_mem(priv, base);
  3484. mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3485. num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3486. next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3487. size = num_wraps ? capacity : next_entry;
  3488. /* bail out if nothing in log */
  3489. if (size == 0) {
  3490. IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
  3491. iwl3945_release_nic_access(priv);
  3492. return;
  3493. }
  3494. IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
  3495. size, num_wraps);
  3496. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3497. * i.e the next one that uCode would fill. */
  3498. if (num_wraps)
  3499. iwl3945_print_event_log(priv, next_entry,
  3500. capacity - next_entry, mode);
  3501. /* (then/else) start at top of log */
  3502. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3503. iwl3945_release_nic_access(priv);
  3504. }
  3505. /**
  3506. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3507. */
  3508. static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
  3509. {
  3510. /* Set the FW error flag -- cleared on iwl3945_down */
  3511. set_bit(STATUS_FW_ERROR, &priv->status);
  3512. /* Cancel currently queued command. */
  3513. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3514. #ifdef CONFIG_IWL3945_DEBUG
  3515. if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
  3516. iwl3945_dump_nic_error_log(priv);
  3517. iwl3945_dump_nic_event_log(priv);
  3518. iwl3945_print_rx_config_cmd(&priv->staging_rxon);
  3519. }
  3520. #endif
  3521. wake_up_interruptible(&priv->wait_command_queue);
  3522. /* Keep the restart process from trying to send host
  3523. * commands by clearing the INIT status bit */
  3524. clear_bit(STATUS_READY, &priv->status);
  3525. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3526. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3527. "Restarting adapter due to uCode error.\n");
  3528. if (iwl3945_is_associated(priv)) {
  3529. memcpy(&priv->recovery_rxon, &priv->active_rxon,
  3530. sizeof(priv->recovery_rxon));
  3531. priv->error_recovering = 1;
  3532. }
  3533. queue_work(priv->workqueue, &priv->restart);
  3534. }
  3535. }
  3536. static void iwl3945_error_recovery(struct iwl3945_priv *priv)
  3537. {
  3538. unsigned long flags;
  3539. memcpy(&priv->staging_rxon, &priv->recovery_rxon,
  3540. sizeof(priv->staging_rxon));
  3541. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3542. iwl3945_commit_rxon(priv);
  3543. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3544. spin_lock_irqsave(&priv->lock, flags);
  3545. priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
  3546. priv->error_recovering = 0;
  3547. spin_unlock_irqrestore(&priv->lock, flags);
  3548. }
  3549. static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
  3550. {
  3551. u32 inta, handled = 0;
  3552. u32 inta_fh;
  3553. unsigned long flags;
  3554. #ifdef CONFIG_IWL3945_DEBUG
  3555. u32 inta_mask;
  3556. #endif
  3557. spin_lock_irqsave(&priv->lock, flags);
  3558. /* Ack/clear/reset pending uCode interrupts.
  3559. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3560. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3561. inta = iwl3945_read32(priv, CSR_INT);
  3562. iwl3945_write32(priv, CSR_INT, inta);
  3563. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3564. * Any new interrupts that happen after this, either while we're
  3565. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3566. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3567. iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3568. #ifdef CONFIG_IWL3945_DEBUG
  3569. if (iwl3945_debug_level & IWL_DL_ISR) {
  3570. /* just for debug */
  3571. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3572. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3573. inta, inta_mask, inta_fh);
  3574. }
  3575. #endif
  3576. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3577. * atomic, make sure that inta covers all the interrupts that
  3578. * we've discovered, even if FH interrupt came in just after
  3579. * reading CSR_INT. */
  3580. if (inta_fh & CSR39_FH_INT_RX_MASK)
  3581. inta |= CSR_INT_BIT_FH_RX;
  3582. if (inta_fh & CSR39_FH_INT_TX_MASK)
  3583. inta |= CSR_INT_BIT_FH_TX;
  3584. /* Now service all interrupt bits discovered above. */
  3585. if (inta & CSR_INT_BIT_HW_ERR) {
  3586. IWL_ERROR("Microcode HW error detected. Restarting.\n");
  3587. /* Tell the device to stop sending interrupts */
  3588. iwl3945_disable_interrupts(priv);
  3589. iwl3945_irq_handle_error(priv);
  3590. handled |= CSR_INT_BIT_HW_ERR;
  3591. spin_unlock_irqrestore(&priv->lock, flags);
  3592. return;
  3593. }
  3594. #ifdef CONFIG_IWL3945_DEBUG
  3595. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3596. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3597. if (inta & CSR_INT_BIT_SCD)
  3598. IWL_DEBUG_ISR("Scheduler finished to transmit "
  3599. "the frame/frames.\n");
  3600. /* Alive notification via Rx interrupt will do the real work */
  3601. if (inta & CSR_INT_BIT_ALIVE)
  3602. IWL_DEBUG_ISR("Alive interrupt\n");
  3603. }
  3604. #endif
  3605. /* Safely ignore these bits for debug checks below */
  3606. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  3607. /* Error detected by uCode */
  3608. if (inta & CSR_INT_BIT_SW_ERR) {
  3609. IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
  3610. inta);
  3611. iwl3945_irq_handle_error(priv);
  3612. handled |= CSR_INT_BIT_SW_ERR;
  3613. }
  3614. /* uCode wakes up after power-down sleep */
  3615. if (inta & CSR_INT_BIT_WAKEUP) {
  3616. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3617. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  3618. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  3619. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  3620. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  3621. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  3622. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  3623. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  3624. handled |= CSR_INT_BIT_WAKEUP;
  3625. }
  3626. /* All uCode command responses, including Tx command responses,
  3627. * Rx "responses" (frame-received notification), and other
  3628. * notifications from uCode come through here*/
  3629. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3630. iwl3945_rx_handle(priv);
  3631. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3632. }
  3633. if (inta & CSR_INT_BIT_FH_TX) {
  3634. IWL_DEBUG_ISR("Tx interrupt\n");
  3635. iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3636. if (!iwl3945_grab_nic_access(priv)) {
  3637. iwl3945_write_direct32(priv,
  3638. FH_TCSR_CREDIT
  3639. (ALM_FH_SRVC_CHNL), 0x0);
  3640. iwl3945_release_nic_access(priv);
  3641. }
  3642. handled |= CSR_INT_BIT_FH_TX;
  3643. }
  3644. if (inta & ~handled)
  3645. IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  3646. if (inta & ~CSR_INI_SET_MASK) {
  3647. IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
  3648. inta & ~CSR_INI_SET_MASK);
  3649. IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
  3650. }
  3651. /* Re-enable all interrupts */
  3652. /* only Re-enable if disabled by irq */
  3653. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3654. iwl3945_enable_interrupts(priv);
  3655. #ifdef CONFIG_IWL3945_DEBUG
  3656. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3657. inta = iwl3945_read32(priv, CSR_INT);
  3658. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3659. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3660. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  3661. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  3662. }
  3663. #endif
  3664. spin_unlock_irqrestore(&priv->lock, flags);
  3665. }
  3666. static irqreturn_t iwl3945_isr(int irq, void *data)
  3667. {
  3668. struct iwl3945_priv *priv = data;
  3669. u32 inta, inta_mask;
  3670. u32 inta_fh;
  3671. if (!priv)
  3672. return IRQ_NONE;
  3673. spin_lock(&priv->lock);
  3674. /* Disable (but don't clear!) interrupts here to avoid
  3675. * back-to-back ISRs and sporadic interrupts from our NIC.
  3676. * If we have something to service, the tasklet will re-enable ints.
  3677. * If we *don't* have something, we'll re-enable before leaving here. */
  3678. inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
  3679. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3680. /* Discover which interrupts are active/pending */
  3681. inta = iwl3945_read32(priv, CSR_INT);
  3682. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3683. /* Ignore interrupt if there's nothing in NIC to service.
  3684. * This may be due to IRQ shared with another device,
  3685. * or due to sporadic interrupts thrown from our NIC. */
  3686. if (!inta && !inta_fh) {
  3687. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  3688. goto none;
  3689. }
  3690. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  3691. /* Hardware disappeared */
  3692. IWL_WARNING("HARDWARE GONE?? INTA == 0x%08x\n", inta);
  3693. goto unplugged;
  3694. }
  3695. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3696. inta, inta_mask, inta_fh);
  3697. inta &= ~CSR_INT_BIT_SCD;
  3698. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  3699. if (likely(inta || inta_fh))
  3700. tasklet_schedule(&priv->irq_tasklet);
  3701. unplugged:
  3702. spin_unlock(&priv->lock);
  3703. return IRQ_HANDLED;
  3704. none:
  3705. /* re-enable interrupts here since we don't have anything to service. */
  3706. /* only Re-enable if disabled by irq */
  3707. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3708. iwl3945_enable_interrupts(priv);
  3709. spin_unlock(&priv->lock);
  3710. return IRQ_NONE;
  3711. }
  3712. /************************** EEPROM BANDS ****************************
  3713. *
  3714. * The iwl3945_eeprom_band definitions below provide the mapping from the
  3715. * EEPROM contents to the specific channel number supported for each
  3716. * band.
  3717. *
  3718. * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
  3719. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  3720. * The specific geography and calibration information for that channel
  3721. * is contained in the eeprom map itself.
  3722. *
  3723. * During init, we copy the eeprom information and channel map
  3724. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  3725. *
  3726. * channel_map_24/52 provides the index in the channel_info array for a
  3727. * given channel. We have to have two separate maps as there is channel
  3728. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  3729. * band_2
  3730. *
  3731. * A value of 0xff stored in the channel_map indicates that the channel
  3732. * is not supported by the hardware at all.
  3733. *
  3734. * A value of 0xfe in the channel_map indicates that the channel is not
  3735. * valid for Tx with the current hardware. This means that
  3736. * while the system can tune and receive on a given channel, it may not
  3737. * be able to associate or transmit any frames on that
  3738. * channel. There is no corresponding channel information for that
  3739. * entry.
  3740. *
  3741. *********************************************************************/
  3742. /* 2.4 GHz */
  3743. static const u8 iwl3945_eeprom_band_1[14] = {
  3744. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  3745. };
  3746. /* 5.2 GHz bands */
  3747. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  3748. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  3749. };
  3750. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  3751. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  3752. };
  3753. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  3754. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  3755. };
  3756. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  3757. 145, 149, 153, 157, 161, 165
  3758. };
  3759. static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
  3760. int *eeprom_ch_count,
  3761. const struct iwl3945_eeprom_channel
  3762. **eeprom_ch_info,
  3763. const u8 **eeprom_ch_index)
  3764. {
  3765. switch (band) {
  3766. case 1: /* 2.4GHz band */
  3767. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  3768. *eeprom_ch_info = priv->eeprom.band_1_channels;
  3769. *eeprom_ch_index = iwl3945_eeprom_band_1;
  3770. break;
  3771. case 2: /* 4.9GHz band */
  3772. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  3773. *eeprom_ch_info = priv->eeprom.band_2_channels;
  3774. *eeprom_ch_index = iwl3945_eeprom_band_2;
  3775. break;
  3776. case 3: /* 5.2GHz band */
  3777. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  3778. *eeprom_ch_info = priv->eeprom.band_3_channels;
  3779. *eeprom_ch_index = iwl3945_eeprom_band_3;
  3780. break;
  3781. case 4: /* 5.5GHz band */
  3782. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  3783. *eeprom_ch_info = priv->eeprom.band_4_channels;
  3784. *eeprom_ch_index = iwl3945_eeprom_band_4;
  3785. break;
  3786. case 5: /* 5.7GHz band */
  3787. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  3788. *eeprom_ch_info = priv->eeprom.band_5_channels;
  3789. *eeprom_ch_index = iwl3945_eeprom_band_5;
  3790. break;
  3791. default:
  3792. BUG();
  3793. return;
  3794. }
  3795. }
  3796. /**
  3797. * iwl3945_get_channel_info - Find driver's private channel info
  3798. *
  3799. * Based on band and channel number.
  3800. */
  3801. const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
  3802. enum ieee80211_band band, u16 channel)
  3803. {
  3804. int i;
  3805. switch (band) {
  3806. case IEEE80211_BAND_5GHZ:
  3807. for (i = 14; i < priv->channel_count; i++) {
  3808. if (priv->channel_info[i].channel == channel)
  3809. return &priv->channel_info[i];
  3810. }
  3811. break;
  3812. case IEEE80211_BAND_2GHZ:
  3813. if (channel >= 1 && channel <= 14)
  3814. return &priv->channel_info[channel - 1];
  3815. break;
  3816. case IEEE80211_NUM_BANDS:
  3817. WARN_ON(1);
  3818. }
  3819. return NULL;
  3820. }
  3821. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  3822. ? # x " " : "")
  3823. /**
  3824. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  3825. */
  3826. static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
  3827. {
  3828. int eeprom_ch_count = 0;
  3829. const u8 *eeprom_ch_index = NULL;
  3830. const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
  3831. int band, ch;
  3832. struct iwl3945_channel_info *ch_info;
  3833. if (priv->channel_count) {
  3834. IWL_DEBUG_INFO("Channel map already initialized.\n");
  3835. return 0;
  3836. }
  3837. if (priv->eeprom.version < 0x2f) {
  3838. IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
  3839. priv->eeprom.version);
  3840. return -EINVAL;
  3841. }
  3842. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  3843. priv->channel_count =
  3844. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  3845. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  3846. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  3847. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  3848. ARRAY_SIZE(iwl3945_eeprom_band_5);
  3849. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  3850. priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
  3851. priv->channel_count, GFP_KERNEL);
  3852. if (!priv->channel_info) {
  3853. IWL_ERROR("Could not allocate channel_info\n");
  3854. priv->channel_count = 0;
  3855. return -ENOMEM;
  3856. }
  3857. ch_info = priv->channel_info;
  3858. /* Loop through the 5 EEPROM bands adding them in order to the
  3859. * channel map we maintain (that contains additional information than
  3860. * what just in the EEPROM) */
  3861. for (band = 1; band <= 5; band++) {
  3862. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  3863. &eeprom_ch_info, &eeprom_ch_index);
  3864. /* Loop through each band adding each of the channels */
  3865. for (ch = 0; ch < eeprom_ch_count; ch++) {
  3866. ch_info->channel = eeprom_ch_index[ch];
  3867. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  3868. IEEE80211_BAND_5GHZ;
  3869. /* permanently store EEPROM's channel regulatory flags
  3870. * and max power in channel info database. */
  3871. ch_info->eeprom = eeprom_ch_info[ch];
  3872. /* Copy the run-time flags so they are there even on
  3873. * invalid channels */
  3874. ch_info->flags = eeprom_ch_info[ch].flags;
  3875. if (!(is_channel_valid(ch_info))) {
  3876. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  3877. "No traffic\n",
  3878. ch_info->channel,
  3879. ch_info->flags,
  3880. is_channel_a_band(ch_info) ?
  3881. "5.2" : "2.4");
  3882. ch_info++;
  3883. continue;
  3884. }
  3885. /* Initialize regulatory-based run-time data */
  3886. ch_info->max_power_avg = ch_info->curr_txpow =
  3887. eeprom_ch_info[ch].max_power_avg;
  3888. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  3889. ch_info->min_power = 0;
  3890. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  3891. " %ddBm): Ad-Hoc %ssupported\n",
  3892. ch_info->channel,
  3893. is_channel_a_band(ch_info) ?
  3894. "5.2" : "2.4",
  3895. CHECK_AND_PRINT(VALID),
  3896. CHECK_AND_PRINT(IBSS),
  3897. CHECK_AND_PRINT(ACTIVE),
  3898. CHECK_AND_PRINT(RADAR),
  3899. CHECK_AND_PRINT(WIDE),
  3900. CHECK_AND_PRINT(DFS),
  3901. eeprom_ch_info[ch].flags,
  3902. eeprom_ch_info[ch].max_power_avg,
  3903. ((eeprom_ch_info[ch].
  3904. flags & EEPROM_CHANNEL_IBSS)
  3905. && !(eeprom_ch_info[ch].
  3906. flags & EEPROM_CHANNEL_RADAR))
  3907. ? "" : "not ");
  3908. /* Set the user_txpower_limit to the highest power
  3909. * supported by any channel */
  3910. if (eeprom_ch_info[ch].max_power_avg >
  3911. priv->user_txpower_limit)
  3912. priv->user_txpower_limit =
  3913. eeprom_ch_info[ch].max_power_avg;
  3914. ch_info++;
  3915. }
  3916. }
  3917. /* Set up txpower settings in driver for all channels */
  3918. if (iwl3945_txpower_set_from_eeprom(priv))
  3919. return -EIO;
  3920. return 0;
  3921. }
  3922. /*
  3923. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  3924. */
  3925. static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
  3926. {
  3927. kfree(priv->channel_info);
  3928. priv->channel_count = 0;
  3929. }
  3930. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  3931. * sending probe req. This should be set long enough to hear probe responses
  3932. * from more than one AP. */
  3933. #define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
  3934. #define IWL_ACTIVE_DWELL_TIME_52 (20)
  3935. #define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
  3936. #define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
  3937. /* For faster active scanning, scan will move to the next channel if fewer than
  3938. * PLCP_QUIET_THRESH packets are heard on this channel within
  3939. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  3940. * time if it's a quiet channel (nothing responded to our probe, and there's
  3941. * no other traffic).
  3942. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  3943. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  3944. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
  3945. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  3946. * Must be set longer than active dwell time.
  3947. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  3948. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  3949. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  3950. #define IWL_PASSIVE_DWELL_BASE (100)
  3951. #define IWL_CHANNEL_TUNE_TIME 5
  3952. #define IWL_SCAN_PROBE_MASK(n) (BIT(n) | (BIT(n) - BIT(1)))
  3953. static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
  3954. enum ieee80211_band band,
  3955. u8 n_probes)
  3956. {
  3957. if (band == IEEE80211_BAND_5GHZ)
  3958. return IWL_ACTIVE_DWELL_TIME_52 +
  3959. IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
  3960. else
  3961. return IWL_ACTIVE_DWELL_TIME_24 +
  3962. IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
  3963. }
  3964. static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
  3965. enum ieee80211_band band)
  3966. {
  3967. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  3968. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  3969. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  3970. if (iwl3945_is_associated(priv)) {
  3971. /* If we're associated, we clamp the maximum passive
  3972. * dwell time to be 98% of the beacon interval (minus
  3973. * 2 * channel tune time) */
  3974. passive = priv->beacon_int;
  3975. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  3976. passive = IWL_PASSIVE_DWELL_BASE;
  3977. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  3978. }
  3979. return passive;
  3980. }
  3981. static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
  3982. enum ieee80211_band band,
  3983. u8 is_active, u8 n_probes,
  3984. struct iwl3945_scan_channel *scan_ch)
  3985. {
  3986. const struct ieee80211_channel *channels = NULL;
  3987. const struct ieee80211_supported_band *sband;
  3988. const struct iwl3945_channel_info *ch_info;
  3989. u16 passive_dwell = 0;
  3990. u16 active_dwell = 0;
  3991. int added, i;
  3992. sband = iwl3945_get_band(priv, band);
  3993. if (!sband)
  3994. return 0;
  3995. channels = sband->channels;
  3996. active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
  3997. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  3998. if (passive_dwell <= active_dwell)
  3999. passive_dwell = active_dwell + 1;
  4000. for (i = 0, added = 0; i < sband->n_channels; i++) {
  4001. if (channels[i].flags & IEEE80211_CHAN_DISABLED)
  4002. continue;
  4003. scan_ch->channel = channels[i].hw_value;
  4004. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  4005. if (!is_channel_valid(ch_info)) {
  4006. IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
  4007. scan_ch->channel);
  4008. continue;
  4009. }
  4010. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  4011. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  4012. /* If passive , set up for auto-switch
  4013. * and use long active_dwell time.
  4014. */
  4015. if (!is_active || is_channel_passive(ch_info) ||
  4016. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
  4017. scan_ch->type = 0; /* passive */
  4018. if (IWL_UCODE_API(priv->ucode_ver) == 1)
  4019. scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
  4020. } else {
  4021. scan_ch->type = 1; /* active */
  4022. }
  4023. /* Set direct probe bits. These may be used both for active
  4024. * scan channels (probes gets sent right away),
  4025. * or for passive channels (probes get se sent only after
  4026. * hearing clear Rx packet).*/
  4027. if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
  4028. if (n_probes)
  4029. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  4030. } else {
  4031. /* uCode v1 does not allow setting direct probe bits on
  4032. * passive channel. */
  4033. if ((scan_ch->type & 1) && n_probes)
  4034. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  4035. }
  4036. /* Set txpower levels to defaults */
  4037. scan_ch->tpc.dsp_atten = 110;
  4038. /* scan_pwr_info->tpc.dsp_atten; */
  4039. /*scan_pwr_info->tpc.tx_gain; */
  4040. if (band == IEEE80211_BAND_5GHZ)
  4041. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  4042. else {
  4043. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  4044. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  4045. * power level:
  4046. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  4047. */
  4048. }
  4049. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  4050. scan_ch->channel,
  4051. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  4052. (scan_ch->type & 1) ?
  4053. active_dwell : passive_dwell);
  4054. scan_ch++;
  4055. added++;
  4056. }
  4057. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  4058. return added;
  4059. }
  4060. static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
  4061. struct ieee80211_rate *rates)
  4062. {
  4063. int i;
  4064. for (i = 0; i < IWL_RATE_COUNT; i++) {
  4065. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  4066. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  4067. rates[i].hw_value_short = i;
  4068. rates[i].flags = 0;
  4069. if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  4070. /*
  4071. * If CCK != 1M then set short preamble rate flag.
  4072. */
  4073. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  4074. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  4075. }
  4076. }
  4077. }
  4078. /**
  4079. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  4080. */
  4081. static int iwl3945_init_geos(struct iwl3945_priv *priv)
  4082. {
  4083. struct iwl3945_channel_info *ch;
  4084. struct ieee80211_supported_band *sband;
  4085. struct ieee80211_channel *channels;
  4086. struct ieee80211_channel *geo_ch;
  4087. struct ieee80211_rate *rates;
  4088. int i = 0;
  4089. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  4090. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  4091. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  4092. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4093. return 0;
  4094. }
  4095. channels = kzalloc(sizeof(struct ieee80211_channel) *
  4096. priv->channel_count, GFP_KERNEL);
  4097. if (!channels)
  4098. return -ENOMEM;
  4099. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  4100. GFP_KERNEL);
  4101. if (!rates) {
  4102. kfree(channels);
  4103. return -ENOMEM;
  4104. }
  4105. /* 5.2GHz channels start after the 2.4GHz channels */
  4106. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4107. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  4108. /* just OFDM */
  4109. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  4110. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  4111. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4112. sband->channels = channels;
  4113. /* OFDM & CCK */
  4114. sband->bitrates = rates;
  4115. sband->n_bitrates = IWL_RATE_COUNT;
  4116. priv->ieee_channels = channels;
  4117. priv->ieee_rates = rates;
  4118. iwl3945_init_hw_rates(priv, rates);
  4119. for (i = 0; i < priv->channel_count; i++) {
  4120. ch = &priv->channel_info[i];
  4121. /* FIXME: might be removed if scan is OK*/
  4122. if (!is_channel_valid(ch))
  4123. continue;
  4124. if (is_channel_a_band(ch))
  4125. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4126. else
  4127. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4128. geo_ch = &sband->channels[sband->n_channels++];
  4129. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  4130. geo_ch->max_power = ch->max_power_avg;
  4131. geo_ch->max_antenna_gain = 0xff;
  4132. geo_ch->hw_value = ch->channel;
  4133. if (is_channel_valid(ch)) {
  4134. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  4135. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  4136. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  4137. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  4138. if (ch->flags & EEPROM_CHANNEL_RADAR)
  4139. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  4140. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  4141. priv->max_channel_txpower_limit =
  4142. ch->max_power_avg;
  4143. } else {
  4144. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  4145. }
  4146. /* Save flags for reg domain usage */
  4147. geo_ch->orig_flags = geo_ch->flags;
  4148. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  4149. ch->channel, geo_ch->center_freq,
  4150. is_channel_a_band(ch) ? "5.2" : "2.4",
  4151. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  4152. "restricted" : "valid",
  4153. geo_ch->flags);
  4154. }
  4155. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  4156. priv->cfg->sku & IWL_SKU_A) {
  4157. printk(KERN_INFO DRV_NAME
  4158. ": Incorrectly detected BG card as ABG. Please send "
  4159. "your PCI ID 0x%04X:0x%04X to maintainer.\n",
  4160. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  4161. priv->cfg->sku &= ~IWL_SKU_A;
  4162. }
  4163. printk(KERN_INFO DRV_NAME
  4164. ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  4165. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  4166. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  4167. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  4168. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  4169. &priv->bands[IEEE80211_BAND_2GHZ];
  4170. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  4171. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  4172. &priv->bands[IEEE80211_BAND_5GHZ];
  4173. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4174. return 0;
  4175. }
  4176. /*
  4177. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  4178. */
  4179. static void iwl3945_free_geos(struct iwl3945_priv *priv)
  4180. {
  4181. kfree(priv->ieee_channels);
  4182. kfree(priv->ieee_rates);
  4183. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4184. }
  4185. /******************************************************************************
  4186. *
  4187. * uCode download functions
  4188. *
  4189. ******************************************************************************/
  4190. static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
  4191. {
  4192. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  4193. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  4194. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4195. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  4196. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4197. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4198. }
  4199. /**
  4200. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4201. * looking at all data.
  4202. */
  4203. static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4204. {
  4205. u32 val;
  4206. u32 save_len = len;
  4207. int rc = 0;
  4208. u32 errcnt;
  4209. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4210. rc = iwl3945_grab_nic_access(priv);
  4211. if (rc)
  4212. return rc;
  4213. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
  4214. errcnt = 0;
  4215. for (; len > 0; len -= sizeof(u32), image++) {
  4216. /* read data comes through single port, auto-incr addr */
  4217. /* NOTE: Use the debugless read so we don't flood kernel log
  4218. * if IWL_DL_IO is set */
  4219. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4220. if (val != le32_to_cpu(*image)) {
  4221. IWL_ERROR("uCode INST section is invalid at "
  4222. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4223. save_len - len, val, le32_to_cpu(*image));
  4224. rc = -EIO;
  4225. errcnt++;
  4226. if (errcnt >= 20)
  4227. break;
  4228. }
  4229. }
  4230. iwl3945_release_nic_access(priv);
  4231. if (!errcnt)
  4232. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4233. return rc;
  4234. }
  4235. /**
  4236. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4237. * using sample data 100 bytes apart. If these sample points are good,
  4238. * it's a pretty good bet that everything between them is good, too.
  4239. */
  4240. static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4241. {
  4242. u32 val;
  4243. int rc = 0;
  4244. u32 errcnt = 0;
  4245. u32 i;
  4246. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4247. rc = iwl3945_grab_nic_access(priv);
  4248. if (rc)
  4249. return rc;
  4250. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4251. /* read data comes through single port, auto-incr addr */
  4252. /* NOTE: Use the debugless read so we don't flood kernel log
  4253. * if IWL_DL_IO is set */
  4254. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4255. i + RTC_INST_LOWER_BOUND);
  4256. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4257. if (val != le32_to_cpu(*image)) {
  4258. #if 0 /* Enable this if you want to see details */
  4259. IWL_ERROR("uCode INST section is invalid at "
  4260. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4261. i, val, *image);
  4262. #endif
  4263. rc = -EIO;
  4264. errcnt++;
  4265. if (errcnt >= 3)
  4266. break;
  4267. }
  4268. }
  4269. iwl3945_release_nic_access(priv);
  4270. return rc;
  4271. }
  4272. /**
  4273. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4274. * and verify its contents
  4275. */
  4276. static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
  4277. {
  4278. __le32 *image;
  4279. u32 len;
  4280. int rc = 0;
  4281. /* Try bootstrap */
  4282. image = (__le32 *)priv->ucode_boot.v_addr;
  4283. len = priv->ucode_boot.len;
  4284. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4285. if (rc == 0) {
  4286. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4287. return 0;
  4288. }
  4289. /* Try initialize */
  4290. image = (__le32 *)priv->ucode_init.v_addr;
  4291. len = priv->ucode_init.len;
  4292. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4293. if (rc == 0) {
  4294. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4295. return 0;
  4296. }
  4297. /* Try runtime/protocol */
  4298. image = (__le32 *)priv->ucode_code.v_addr;
  4299. len = priv->ucode_code.len;
  4300. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4301. if (rc == 0) {
  4302. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4303. return 0;
  4304. }
  4305. IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4306. /* Since nothing seems to match, show first several data entries in
  4307. * instruction SRAM, so maybe visual inspection will give a clue.
  4308. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4309. image = (__le32 *)priv->ucode_boot.v_addr;
  4310. len = priv->ucode_boot.len;
  4311. rc = iwl3945_verify_inst_full(priv, image, len);
  4312. return rc;
  4313. }
  4314. /* check contents of special bootstrap uCode SRAM */
  4315. static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
  4316. {
  4317. __le32 *image = priv->ucode_boot.v_addr;
  4318. u32 len = priv->ucode_boot.len;
  4319. u32 reg;
  4320. u32 val;
  4321. IWL_DEBUG_INFO("Begin verify bsm\n");
  4322. /* verify BSM SRAM contents */
  4323. val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
  4324. for (reg = BSM_SRAM_LOWER_BOUND;
  4325. reg < BSM_SRAM_LOWER_BOUND + len;
  4326. reg += sizeof(u32), image++) {
  4327. val = iwl3945_read_prph(priv, reg);
  4328. if (val != le32_to_cpu(*image)) {
  4329. IWL_ERROR("BSM uCode verification failed at "
  4330. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  4331. BSM_SRAM_LOWER_BOUND,
  4332. reg - BSM_SRAM_LOWER_BOUND, len,
  4333. val, le32_to_cpu(*image));
  4334. return -EIO;
  4335. }
  4336. }
  4337. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  4338. return 0;
  4339. }
  4340. /**
  4341. * iwl3945_load_bsm - Load bootstrap instructions
  4342. *
  4343. * BSM operation:
  4344. *
  4345. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  4346. * in special SRAM that does not power down during RFKILL. When powering back
  4347. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  4348. * the bootstrap program into the on-board processor, and starts it.
  4349. *
  4350. * The bootstrap program loads (via DMA) instructions and data for a new
  4351. * program from host DRAM locations indicated by the host driver in the
  4352. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  4353. * automatically.
  4354. *
  4355. * When initializing the NIC, the host driver points the BSM to the
  4356. * "initialize" uCode image. This uCode sets up some internal data, then
  4357. * notifies host via "initialize alive" that it is complete.
  4358. *
  4359. * The host then replaces the BSM_DRAM_* pointer values to point to the
  4360. * normal runtime uCode instructions and a backup uCode data cache buffer
  4361. * (filled initially with starting data values for the on-board processor),
  4362. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  4363. * which begins normal operation.
  4364. *
  4365. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  4366. * the backup data cache in DRAM before SRAM is powered down.
  4367. *
  4368. * When powering back up, the BSM loads the bootstrap program. This reloads
  4369. * the runtime uCode instructions and the backup data cache into SRAM,
  4370. * and re-launches the runtime uCode from where it left off.
  4371. */
  4372. static int iwl3945_load_bsm(struct iwl3945_priv *priv)
  4373. {
  4374. __le32 *image = priv->ucode_boot.v_addr;
  4375. u32 len = priv->ucode_boot.len;
  4376. dma_addr_t pinst;
  4377. dma_addr_t pdata;
  4378. u32 inst_len;
  4379. u32 data_len;
  4380. int rc;
  4381. int i;
  4382. u32 done;
  4383. u32 reg_offset;
  4384. IWL_DEBUG_INFO("Begin load bsm\n");
  4385. /* make sure bootstrap program is no larger than BSM's SRAM size */
  4386. if (len > IWL_MAX_BSM_SIZE)
  4387. return -EINVAL;
  4388. /* Tell bootstrap uCode where to find the "Initialize" uCode
  4389. * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
  4390. * NOTE: iwl3945_initialize_alive_start() will replace these values,
  4391. * after the "initialize" uCode has run, to point to
  4392. * runtime/protocol instructions and backup data cache. */
  4393. pinst = priv->ucode_init.p_addr;
  4394. pdata = priv->ucode_init_data.p_addr;
  4395. inst_len = priv->ucode_init.len;
  4396. data_len = priv->ucode_init_data.len;
  4397. rc = iwl3945_grab_nic_access(priv);
  4398. if (rc)
  4399. return rc;
  4400. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4401. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4402. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  4403. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  4404. /* Fill BSM memory with bootstrap instructions */
  4405. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  4406. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  4407. reg_offset += sizeof(u32), image++)
  4408. _iwl3945_write_prph(priv, reg_offset,
  4409. le32_to_cpu(*image));
  4410. rc = iwl3945_verify_bsm(priv);
  4411. if (rc) {
  4412. iwl3945_release_nic_access(priv);
  4413. return rc;
  4414. }
  4415. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  4416. iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  4417. iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
  4418. RTC_INST_LOWER_BOUND);
  4419. iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  4420. /* Load bootstrap code into instruction SRAM now,
  4421. * to prepare to load "initialize" uCode */
  4422. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4423. BSM_WR_CTRL_REG_BIT_START);
  4424. /* Wait for load of bootstrap uCode to finish */
  4425. for (i = 0; i < 100; i++) {
  4426. done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
  4427. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  4428. break;
  4429. udelay(10);
  4430. }
  4431. if (i < 100)
  4432. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  4433. else {
  4434. IWL_ERROR("BSM write did not complete!\n");
  4435. return -EIO;
  4436. }
  4437. /* Enable future boot loads whenever power management unit triggers it
  4438. * (e.g. when powering back up after power-save shutdown) */
  4439. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4440. BSM_WR_CTRL_REG_BIT_START_EN);
  4441. iwl3945_release_nic_access(priv);
  4442. return 0;
  4443. }
  4444. static void iwl3945_nic_start(struct iwl3945_priv *priv)
  4445. {
  4446. /* Remove all resets to allow NIC to operate */
  4447. iwl3945_write32(priv, CSR_RESET, 0);
  4448. }
  4449. /**
  4450. * iwl3945_read_ucode - Read uCode images from disk file.
  4451. *
  4452. * Copy into buffers for card to fetch via bus-mastering
  4453. */
  4454. static int iwl3945_read_ucode(struct iwl3945_priv *priv)
  4455. {
  4456. struct iwl3945_ucode *ucode;
  4457. int ret = -EINVAL, index;
  4458. const struct firmware *ucode_raw;
  4459. /* firmware file name contains uCode/driver compatibility version */
  4460. const char *name_pre = priv->cfg->fw_name_pre;
  4461. const unsigned int api_max = priv->cfg->ucode_api_max;
  4462. const unsigned int api_min = priv->cfg->ucode_api_min;
  4463. char buf[25];
  4464. u8 *src;
  4465. size_t len;
  4466. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4467. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4468. * request_firmware() is synchronous, file is in memory on return. */
  4469. for (index = api_max; index >= api_min; index--) {
  4470. sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
  4471. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  4472. if (ret < 0) {
  4473. IWL_ERROR("%s firmware file req failed: Reason %d\n",
  4474. buf, ret);
  4475. if (ret == -ENOENT)
  4476. continue;
  4477. else
  4478. goto error;
  4479. } else {
  4480. if (index < api_max)
  4481. IWL_ERROR("Loaded firmware %s, which is deprecated. Please use API v%u instead.\n",
  4482. buf, api_max);
  4483. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4484. buf, ucode_raw->size);
  4485. break;
  4486. }
  4487. }
  4488. if (ret < 0)
  4489. goto error;
  4490. /* Make sure that we got at least our header! */
  4491. if (ucode_raw->size < sizeof(*ucode)) {
  4492. IWL_ERROR("File size way too small!\n");
  4493. ret = -EINVAL;
  4494. goto err_release;
  4495. }
  4496. /* Data from ucode file: header followed by uCode images */
  4497. ucode = (void *)ucode_raw->data;
  4498. priv->ucode_ver = le32_to_cpu(ucode->ver);
  4499. api_ver = IWL_UCODE_API(priv->ucode_ver);
  4500. inst_size = le32_to_cpu(ucode->inst_size);
  4501. data_size = le32_to_cpu(ucode->data_size);
  4502. init_size = le32_to_cpu(ucode->init_size);
  4503. init_data_size = le32_to_cpu(ucode->init_data_size);
  4504. boot_size = le32_to_cpu(ucode->boot_size);
  4505. /* api_ver should match the api version forming part of the
  4506. * firmware filename ... but we don't check for that and only rely
  4507. * on the API version read from firware header from here on forward */
  4508. if (api_ver < api_min || api_ver > api_max) {
  4509. IWL_ERROR("Driver unable to support your firmware API. "
  4510. "Driver supports v%u, firmware is v%u.\n",
  4511. api_max, api_ver);
  4512. priv->ucode_ver = 0;
  4513. ret = -EINVAL;
  4514. goto err_release;
  4515. }
  4516. if (api_ver != api_max)
  4517. IWL_ERROR("Firmware has old API version. Expected %u, "
  4518. "got %u. New firmware can be obtained "
  4519. "from http://www.intellinuxwireless.org.\n",
  4520. api_max, api_ver);
  4521. printk(KERN_INFO DRV_NAME " loaded firmware version %u.%u.%u.%u\n",
  4522. IWL_UCODE_MAJOR(priv->ucode_ver),
  4523. IWL_UCODE_MINOR(priv->ucode_ver),
  4524. IWL_UCODE_API(priv->ucode_ver),
  4525. IWL_UCODE_SERIAL(priv->ucode_ver));
  4526. IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n",
  4527. priv->ucode_ver);
  4528. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4529. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4530. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4531. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4532. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4533. /* Verify size of file vs. image size info in file's header */
  4534. if (ucode_raw->size < sizeof(*ucode) +
  4535. inst_size + data_size + init_size +
  4536. init_data_size + boot_size) {
  4537. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4538. (int)ucode_raw->size);
  4539. ret = -EINVAL;
  4540. goto err_release;
  4541. }
  4542. /* Verify that uCode images will fit in card's SRAM */
  4543. if (inst_size > IWL_MAX_INST_SIZE) {
  4544. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4545. inst_size);
  4546. ret = -EINVAL;
  4547. goto err_release;
  4548. }
  4549. if (data_size > IWL_MAX_DATA_SIZE) {
  4550. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4551. data_size);
  4552. ret = -EINVAL;
  4553. goto err_release;
  4554. }
  4555. if (init_size > IWL_MAX_INST_SIZE) {
  4556. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4557. init_size);
  4558. ret = -EINVAL;
  4559. goto err_release;
  4560. }
  4561. if (init_data_size > IWL_MAX_DATA_SIZE) {
  4562. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4563. init_data_size);
  4564. ret = -EINVAL;
  4565. goto err_release;
  4566. }
  4567. if (boot_size > IWL_MAX_BSM_SIZE) {
  4568. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4569. boot_size);
  4570. ret = -EINVAL;
  4571. goto err_release;
  4572. }
  4573. /* Allocate ucode buffers for card's bus-master loading ... */
  4574. /* Runtime instructions and 2 copies of data:
  4575. * 1) unmodified from disk
  4576. * 2) backup cache for save/restore during power-downs */
  4577. priv->ucode_code.len = inst_size;
  4578. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4579. priv->ucode_data.len = data_size;
  4580. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4581. priv->ucode_data_backup.len = data_size;
  4582. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4583. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4584. !priv->ucode_data_backup.v_addr)
  4585. goto err_pci_alloc;
  4586. /* Initialization instructions and data */
  4587. if (init_size && init_data_size) {
  4588. priv->ucode_init.len = init_size;
  4589. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4590. priv->ucode_init_data.len = init_data_size;
  4591. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4592. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4593. goto err_pci_alloc;
  4594. }
  4595. /* Bootstrap (instructions only, no data) */
  4596. if (boot_size) {
  4597. priv->ucode_boot.len = boot_size;
  4598. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4599. if (!priv->ucode_boot.v_addr)
  4600. goto err_pci_alloc;
  4601. }
  4602. /* Copy images into buffers for card's bus-master reads ... */
  4603. /* Runtime instructions (first block of data in file) */
  4604. src = &ucode->data[0];
  4605. len = priv->ucode_code.len;
  4606. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4607. memcpy(priv->ucode_code.v_addr, src, len);
  4608. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4609. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4610. /* Runtime data (2nd block)
  4611. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4612. src = &ucode->data[inst_size];
  4613. len = priv->ucode_data.len;
  4614. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4615. memcpy(priv->ucode_data.v_addr, src, len);
  4616. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4617. /* Initialization instructions (3rd block) */
  4618. if (init_size) {
  4619. src = &ucode->data[inst_size + data_size];
  4620. len = priv->ucode_init.len;
  4621. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4622. len);
  4623. memcpy(priv->ucode_init.v_addr, src, len);
  4624. }
  4625. /* Initialization data (4th block) */
  4626. if (init_data_size) {
  4627. src = &ucode->data[inst_size + data_size + init_size];
  4628. len = priv->ucode_init_data.len;
  4629. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4630. (int)len);
  4631. memcpy(priv->ucode_init_data.v_addr, src, len);
  4632. }
  4633. /* Bootstrap instructions (5th block) */
  4634. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4635. len = priv->ucode_boot.len;
  4636. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4637. (int)len);
  4638. memcpy(priv->ucode_boot.v_addr, src, len);
  4639. /* We have our copies now, allow OS release its copies */
  4640. release_firmware(ucode_raw);
  4641. return 0;
  4642. err_pci_alloc:
  4643. IWL_ERROR("failed to allocate pci memory\n");
  4644. ret = -ENOMEM;
  4645. iwl3945_dealloc_ucode_pci(priv);
  4646. err_release:
  4647. release_firmware(ucode_raw);
  4648. error:
  4649. return ret;
  4650. }
  4651. /**
  4652. * iwl3945_set_ucode_ptrs - Set uCode address location
  4653. *
  4654. * Tell initialization uCode where to find runtime uCode.
  4655. *
  4656. * BSM registers initially contain pointers to initialization uCode.
  4657. * We need to replace them to load runtime uCode inst and data,
  4658. * and to save runtime data when powering down.
  4659. */
  4660. static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
  4661. {
  4662. dma_addr_t pinst;
  4663. dma_addr_t pdata;
  4664. int rc = 0;
  4665. unsigned long flags;
  4666. /* bits 31:0 for 3945 */
  4667. pinst = priv->ucode_code.p_addr;
  4668. pdata = priv->ucode_data_backup.p_addr;
  4669. spin_lock_irqsave(&priv->lock, flags);
  4670. rc = iwl3945_grab_nic_access(priv);
  4671. if (rc) {
  4672. spin_unlock_irqrestore(&priv->lock, flags);
  4673. return rc;
  4674. }
  4675. /* Tell bootstrap uCode where to find image to load */
  4676. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4677. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4678. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  4679. priv->ucode_data.len);
  4680. /* Inst byte count must be last to set up, bit 31 signals uCode
  4681. * that all new ptr/size info is in place */
  4682. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  4683. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  4684. iwl3945_release_nic_access(priv);
  4685. spin_unlock_irqrestore(&priv->lock, flags);
  4686. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  4687. return rc;
  4688. }
  4689. /**
  4690. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  4691. *
  4692. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  4693. *
  4694. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  4695. */
  4696. static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
  4697. {
  4698. /* Check alive response for "valid" sign from uCode */
  4699. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  4700. /* We had an error bringing up the hardware, so take it
  4701. * all the way back down so we can try again */
  4702. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  4703. goto restart;
  4704. }
  4705. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  4706. * This is a paranoid check, because we would not have gotten the
  4707. * "initialize" alive if code weren't properly loaded. */
  4708. if (iwl3945_verify_ucode(priv)) {
  4709. /* Runtime instruction load was bad;
  4710. * take it all the way back down so we can try again */
  4711. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  4712. goto restart;
  4713. }
  4714. /* Send pointers to protocol/runtime uCode image ... init code will
  4715. * load and launch runtime uCode, which will send us another "Alive"
  4716. * notification. */
  4717. IWL_DEBUG_INFO("Initialization Alive received.\n");
  4718. if (iwl3945_set_ucode_ptrs(priv)) {
  4719. /* Runtime instruction load won't happen;
  4720. * take it all the way back down so we can try again */
  4721. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  4722. goto restart;
  4723. }
  4724. return;
  4725. restart:
  4726. queue_work(priv->workqueue, &priv->restart);
  4727. }
  4728. /* temporary */
  4729. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw,
  4730. struct sk_buff *skb);
  4731. /**
  4732. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  4733. * from protocol/runtime uCode (initialization uCode's
  4734. * Alive gets handled by iwl3945_init_alive_start()).
  4735. */
  4736. static void iwl3945_alive_start(struct iwl3945_priv *priv)
  4737. {
  4738. int rc = 0;
  4739. int thermal_spin = 0;
  4740. u32 rfkill;
  4741. IWL_DEBUG_INFO("Runtime Alive received.\n");
  4742. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  4743. /* We had an error bringing up the hardware, so take it
  4744. * all the way back down so we can try again */
  4745. IWL_DEBUG_INFO("Alive failed.\n");
  4746. goto restart;
  4747. }
  4748. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  4749. * This is a paranoid check, because we would not have gotten the
  4750. * "runtime" alive if code weren't properly loaded. */
  4751. if (iwl3945_verify_ucode(priv)) {
  4752. /* Runtime instruction load was bad;
  4753. * take it all the way back down so we can try again */
  4754. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  4755. goto restart;
  4756. }
  4757. iwl3945_clear_stations_table(priv);
  4758. rc = iwl3945_grab_nic_access(priv);
  4759. if (rc) {
  4760. IWL_WARNING("Can not read RFKILL status from adapter\n");
  4761. return;
  4762. }
  4763. rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
  4764. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  4765. iwl3945_release_nic_access(priv);
  4766. if (rfkill & 0x1) {
  4767. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4768. /* if RFKILL is not on, then wait for thermal
  4769. * sensor in adapter to kick in */
  4770. while (iwl3945_hw_get_temperature(priv) == 0) {
  4771. thermal_spin++;
  4772. udelay(10);
  4773. }
  4774. if (thermal_spin)
  4775. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  4776. thermal_spin * 10);
  4777. } else
  4778. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4779. /* After the ALIVE response, we can send commands to 3945 uCode */
  4780. set_bit(STATUS_ALIVE, &priv->status);
  4781. /* Clear out the uCode error bit if it is set */
  4782. clear_bit(STATUS_FW_ERROR, &priv->status);
  4783. if (iwl3945_is_rfkill(priv))
  4784. return;
  4785. ieee80211_wake_queues(priv->hw);
  4786. priv->active_rate = priv->rates_mask;
  4787. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  4788. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  4789. if (iwl3945_is_associated(priv)) {
  4790. struct iwl3945_rxon_cmd *active_rxon =
  4791. (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
  4792. memcpy(&priv->staging_rxon, &priv->active_rxon,
  4793. sizeof(priv->staging_rxon));
  4794. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4795. } else {
  4796. /* Initialize our rx_config data */
  4797. iwl3945_connection_init_rx_config(priv, priv->iw_mode);
  4798. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  4799. }
  4800. /* Configure Bluetooth device coexistence support */
  4801. iwl3945_send_bt_config(priv);
  4802. /* Configure the adapter for unassociated operation */
  4803. iwl3945_commit_rxon(priv);
  4804. iwl3945_reg_txpower_periodic(priv);
  4805. iwl3945_led_register(priv);
  4806. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  4807. set_bit(STATUS_READY, &priv->status);
  4808. wake_up_interruptible(&priv->wait_command_queue);
  4809. if (priv->error_recovering)
  4810. iwl3945_error_recovery(priv);
  4811. /* reassociate for ADHOC mode */
  4812. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  4813. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  4814. priv->vif);
  4815. if (beacon)
  4816. iwl3945_mac_beacon_update(priv->hw, beacon);
  4817. }
  4818. return;
  4819. restart:
  4820. queue_work(priv->workqueue, &priv->restart);
  4821. }
  4822. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
  4823. static void __iwl3945_down(struct iwl3945_priv *priv)
  4824. {
  4825. unsigned long flags;
  4826. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  4827. struct ieee80211_conf *conf = NULL;
  4828. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  4829. conf = ieee80211_get_hw_conf(priv->hw);
  4830. if (!exit_pending)
  4831. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4832. iwl3945_led_unregister(priv);
  4833. iwl3945_clear_stations_table(priv);
  4834. /* Unblock any waiting calls */
  4835. wake_up_interruptible_all(&priv->wait_command_queue);
  4836. /* Wipe out the EXIT_PENDING status bit if we are not actually
  4837. * exiting the module */
  4838. if (!exit_pending)
  4839. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4840. /* stop and reset the on-board processor */
  4841. iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  4842. /* tell the device to stop sending interrupts */
  4843. spin_lock_irqsave(&priv->lock, flags);
  4844. iwl3945_disable_interrupts(priv);
  4845. spin_unlock_irqrestore(&priv->lock, flags);
  4846. iwl_synchronize_irq(priv);
  4847. if (priv->mac80211_registered)
  4848. ieee80211_stop_queues(priv->hw);
  4849. /* If we have not previously called iwl3945_init() then
  4850. * clear all bits but the RF Kill and SUSPEND bits and return */
  4851. if (!iwl3945_is_init(priv)) {
  4852. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4853. STATUS_RF_KILL_HW |
  4854. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4855. STATUS_RF_KILL_SW |
  4856. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4857. STATUS_GEO_CONFIGURED |
  4858. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4859. STATUS_IN_SUSPEND |
  4860. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4861. STATUS_EXIT_PENDING;
  4862. goto exit;
  4863. }
  4864. /* ...otherwise clear out all the status bits but the RF Kill and
  4865. * SUSPEND bits and continue taking the NIC down. */
  4866. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4867. STATUS_RF_KILL_HW |
  4868. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4869. STATUS_RF_KILL_SW |
  4870. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4871. STATUS_GEO_CONFIGURED |
  4872. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4873. STATUS_IN_SUSPEND |
  4874. test_bit(STATUS_FW_ERROR, &priv->status) <<
  4875. STATUS_FW_ERROR |
  4876. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4877. STATUS_EXIT_PENDING;
  4878. spin_lock_irqsave(&priv->lock, flags);
  4879. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  4880. spin_unlock_irqrestore(&priv->lock, flags);
  4881. iwl3945_hw_txq_ctx_stop(priv);
  4882. iwl3945_hw_rxq_stop(priv);
  4883. spin_lock_irqsave(&priv->lock, flags);
  4884. if (!iwl3945_grab_nic_access(priv)) {
  4885. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  4886. APMG_CLK_VAL_DMA_CLK_RQT);
  4887. iwl3945_release_nic_access(priv);
  4888. }
  4889. spin_unlock_irqrestore(&priv->lock, flags);
  4890. udelay(5);
  4891. iwl3945_hw_nic_stop_master(priv);
  4892. iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  4893. iwl3945_hw_nic_reset(priv);
  4894. exit:
  4895. memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
  4896. if (priv->ibss_beacon)
  4897. dev_kfree_skb(priv->ibss_beacon);
  4898. priv->ibss_beacon = NULL;
  4899. /* clear out any free frames */
  4900. iwl3945_clear_free_frames(priv);
  4901. }
  4902. static void iwl3945_down(struct iwl3945_priv *priv)
  4903. {
  4904. mutex_lock(&priv->mutex);
  4905. __iwl3945_down(priv);
  4906. mutex_unlock(&priv->mutex);
  4907. iwl3945_cancel_deferred_work(priv);
  4908. }
  4909. #define MAX_HW_RESTARTS 5
  4910. static int __iwl3945_up(struct iwl3945_priv *priv)
  4911. {
  4912. int rc, i;
  4913. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4914. IWL_WARNING("Exit pending; will not bring the NIC up\n");
  4915. return -EIO;
  4916. }
  4917. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  4918. IWL_WARNING("Radio disabled by SW RF kill (module "
  4919. "parameter)\n");
  4920. return -ENODEV;
  4921. }
  4922. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  4923. IWL_ERROR("ucode not available for device bring up\n");
  4924. return -EIO;
  4925. }
  4926. /* If platform's RF_KILL switch is NOT set to KILL */
  4927. if (iwl3945_read32(priv, CSR_GP_CNTRL) &
  4928. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  4929. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4930. else {
  4931. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4932. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  4933. IWL_WARNING("Radio disabled by HW RF Kill switch\n");
  4934. return -ENODEV;
  4935. }
  4936. }
  4937. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  4938. rc = iwl3945_hw_nic_init(priv);
  4939. if (rc) {
  4940. IWL_ERROR("Unable to int nic\n");
  4941. return rc;
  4942. }
  4943. /* make sure rfkill handshake bits are cleared */
  4944. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4945. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  4946. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  4947. /* clear (again), then enable host interrupts */
  4948. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  4949. iwl3945_enable_interrupts(priv);
  4950. /* really make sure rfkill handshake bits are cleared */
  4951. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4952. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4953. /* Copy original ucode data image from disk into backup cache.
  4954. * This will be used to initialize the on-board processor's
  4955. * data SRAM for a clean start when the runtime program first loads. */
  4956. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  4957. priv->ucode_data.len);
  4958. /* We return success when we resume from suspend and rf_kill is on. */
  4959. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  4960. return 0;
  4961. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  4962. iwl3945_clear_stations_table(priv);
  4963. /* load bootstrap state machine,
  4964. * load bootstrap program into processor's memory,
  4965. * prepare to load the "initialize" uCode */
  4966. rc = iwl3945_load_bsm(priv);
  4967. if (rc) {
  4968. IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
  4969. continue;
  4970. }
  4971. /* start card; "initialize" will load runtime ucode */
  4972. iwl3945_nic_start(priv);
  4973. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  4974. return 0;
  4975. }
  4976. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4977. __iwl3945_down(priv);
  4978. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4979. /* tried to restart and config the device for as long as our
  4980. * patience could withstand */
  4981. IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
  4982. return -EIO;
  4983. }
  4984. /*****************************************************************************
  4985. *
  4986. * Workqueue callbacks
  4987. *
  4988. *****************************************************************************/
  4989. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  4990. {
  4991. struct iwl3945_priv *priv =
  4992. container_of(data, struct iwl3945_priv, init_alive_start.work);
  4993. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4994. return;
  4995. mutex_lock(&priv->mutex);
  4996. iwl3945_init_alive_start(priv);
  4997. mutex_unlock(&priv->mutex);
  4998. }
  4999. static void iwl3945_bg_alive_start(struct work_struct *data)
  5000. {
  5001. struct iwl3945_priv *priv =
  5002. container_of(data, struct iwl3945_priv, alive_start.work);
  5003. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5004. return;
  5005. mutex_lock(&priv->mutex);
  5006. iwl3945_alive_start(priv);
  5007. mutex_unlock(&priv->mutex);
  5008. }
  5009. static void iwl3945_bg_rf_kill(struct work_struct *work)
  5010. {
  5011. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
  5012. wake_up_interruptible(&priv->wait_command_queue);
  5013. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5014. return;
  5015. mutex_lock(&priv->mutex);
  5016. if (!iwl3945_is_rfkill(priv)) {
  5017. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  5018. "HW and/or SW RF Kill no longer active, restarting "
  5019. "device\n");
  5020. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5021. queue_work(priv->workqueue, &priv->restart);
  5022. } else {
  5023. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  5024. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  5025. "disabled by SW switch\n");
  5026. else
  5027. IWL_WARNING("Radio Frequency Kill Switch is On:\n"
  5028. "Kill switch must be turned off for "
  5029. "wireless networking to work.\n");
  5030. }
  5031. mutex_unlock(&priv->mutex);
  5032. iwl3945_rfkill_set_hw_state(priv);
  5033. }
  5034. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  5035. static void iwl3945_bg_scan_check(struct work_struct *data)
  5036. {
  5037. struct iwl3945_priv *priv =
  5038. container_of(data, struct iwl3945_priv, scan_check.work);
  5039. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5040. return;
  5041. mutex_lock(&priv->mutex);
  5042. if (test_bit(STATUS_SCANNING, &priv->status) ||
  5043. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5044. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  5045. "Scan completion watchdog resetting adapter (%dms)\n",
  5046. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  5047. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5048. iwl3945_send_scan_abort(priv);
  5049. }
  5050. mutex_unlock(&priv->mutex);
  5051. }
  5052. static void iwl3945_bg_request_scan(struct work_struct *data)
  5053. {
  5054. struct iwl3945_priv *priv =
  5055. container_of(data, struct iwl3945_priv, request_scan);
  5056. struct iwl3945_host_cmd cmd = {
  5057. .id = REPLY_SCAN_CMD,
  5058. .len = sizeof(struct iwl3945_scan_cmd),
  5059. .meta.flags = CMD_SIZE_HUGE,
  5060. };
  5061. int rc = 0;
  5062. struct iwl3945_scan_cmd *scan;
  5063. struct ieee80211_conf *conf = NULL;
  5064. u8 n_probes = 2;
  5065. enum ieee80211_band band;
  5066. DECLARE_SSID_BUF(ssid);
  5067. conf = ieee80211_get_hw_conf(priv->hw);
  5068. mutex_lock(&priv->mutex);
  5069. if (!iwl3945_is_ready(priv)) {
  5070. IWL_WARNING("request scan called when driver not ready.\n");
  5071. goto done;
  5072. }
  5073. /* Make sure the scan wasn't canceled before this queued work
  5074. * was given the chance to run... */
  5075. if (!test_bit(STATUS_SCANNING, &priv->status))
  5076. goto done;
  5077. /* This should never be called or scheduled if there is currently
  5078. * a scan active in the hardware. */
  5079. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  5080. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  5081. "Ignoring second request.\n");
  5082. rc = -EIO;
  5083. goto done;
  5084. }
  5085. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5086. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  5087. goto done;
  5088. }
  5089. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5090. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  5091. goto done;
  5092. }
  5093. if (iwl3945_is_rfkill(priv)) {
  5094. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  5095. goto done;
  5096. }
  5097. if (!test_bit(STATUS_READY, &priv->status)) {
  5098. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  5099. goto done;
  5100. }
  5101. if (!priv->scan_bands) {
  5102. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  5103. goto done;
  5104. }
  5105. if (!priv->scan) {
  5106. priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  5107. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  5108. if (!priv->scan) {
  5109. rc = -ENOMEM;
  5110. goto done;
  5111. }
  5112. }
  5113. scan = priv->scan;
  5114. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  5115. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  5116. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  5117. if (iwl3945_is_associated(priv)) {
  5118. u16 interval = 0;
  5119. u32 extra;
  5120. u32 suspend_time = 100;
  5121. u32 scan_suspend_time = 100;
  5122. unsigned long flags;
  5123. IWL_DEBUG_INFO("Scanning while associated...\n");
  5124. spin_lock_irqsave(&priv->lock, flags);
  5125. interval = priv->beacon_int;
  5126. spin_unlock_irqrestore(&priv->lock, flags);
  5127. scan->suspend_time = 0;
  5128. scan->max_out_time = cpu_to_le32(200 * 1024);
  5129. if (!interval)
  5130. interval = suspend_time;
  5131. /*
  5132. * suspend time format:
  5133. * 0-19: beacon interval in usec (time before exec.)
  5134. * 20-23: 0
  5135. * 24-31: number of beacons (suspend between channels)
  5136. */
  5137. extra = (suspend_time / interval) << 24;
  5138. scan_suspend_time = 0xFF0FFFFF &
  5139. (extra | ((suspend_time % interval) * 1024));
  5140. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  5141. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  5142. scan_suspend_time, interval);
  5143. }
  5144. /* We should add the ability for user to lock to PASSIVE ONLY */
  5145. if (priv->one_direct_scan) {
  5146. IWL_DEBUG_SCAN
  5147. ("Kicking off one direct scan for '%s'\n",
  5148. print_ssid(ssid, priv->direct_ssid,
  5149. priv->direct_ssid_len));
  5150. scan->direct_scan[0].id = WLAN_EID_SSID;
  5151. scan->direct_scan[0].len = priv->direct_ssid_len;
  5152. memcpy(scan->direct_scan[0].ssid,
  5153. priv->direct_ssid, priv->direct_ssid_len);
  5154. n_probes++;
  5155. } else
  5156. IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
  5157. /* We don't build a direct scan probe request; the uCode will do
  5158. * that based on the direct_mask added to each channel entry */
  5159. scan->tx_cmd.len = cpu_to_le16(
  5160. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  5161. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  5162. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  5163. scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
  5164. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  5165. /* flags + rate selection */
  5166. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
  5167. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  5168. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  5169. scan->good_CRC_th = 0;
  5170. band = IEEE80211_BAND_2GHZ;
  5171. } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
  5172. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  5173. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  5174. band = IEEE80211_BAND_5GHZ;
  5175. } else {
  5176. IWL_WARNING("Invalid scan band count\n");
  5177. goto done;
  5178. }
  5179. /* select Rx antennas */
  5180. scan->flags |= iwl3945_get_antenna_flags(priv);
  5181. if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
  5182. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  5183. scan->channel_count =
  5184. iwl3945_get_channels_for_scan(priv, band, 1, /* active */
  5185. n_probes,
  5186. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5187. if (scan->channel_count == 0) {
  5188. IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
  5189. goto done;
  5190. }
  5191. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  5192. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  5193. cmd.data = scan;
  5194. scan->len = cpu_to_le16(cmd.len);
  5195. set_bit(STATUS_SCAN_HW, &priv->status);
  5196. rc = iwl3945_send_cmd_sync(priv, &cmd);
  5197. if (rc)
  5198. goto done;
  5199. queue_delayed_work(priv->workqueue, &priv->scan_check,
  5200. IWL_SCAN_CHECK_WATCHDOG);
  5201. mutex_unlock(&priv->mutex);
  5202. return;
  5203. done:
  5204. /* can not perform scan make sure we clear scanning
  5205. * bits from status so next scan request can be performed.
  5206. * if we dont clear scanning status bit here all next scan
  5207. * will fail
  5208. */
  5209. clear_bit(STATUS_SCAN_HW, &priv->status);
  5210. clear_bit(STATUS_SCANNING, &priv->status);
  5211. /* inform mac80211 scan aborted */
  5212. queue_work(priv->workqueue, &priv->scan_completed);
  5213. mutex_unlock(&priv->mutex);
  5214. }
  5215. static void iwl3945_bg_up(struct work_struct *data)
  5216. {
  5217. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
  5218. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5219. return;
  5220. mutex_lock(&priv->mutex);
  5221. __iwl3945_up(priv);
  5222. mutex_unlock(&priv->mutex);
  5223. iwl3945_rfkill_set_hw_state(priv);
  5224. }
  5225. static void iwl3945_bg_restart(struct work_struct *data)
  5226. {
  5227. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
  5228. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5229. return;
  5230. iwl3945_down(priv);
  5231. queue_work(priv->workqueue, &priv->up);
  5232. }
  5233. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  5234. {
  5235. struct iwl3945_priv *priv =
  5236. container_of(data, struct iwl3945_priv, rx_replenish);
  5237. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5238. return;
  5239. mutex_lock(&priv->mutex);
  5240. iwl3945_rx_replenish(priv);
  5241. mutex_unlock(&priv->mutex);
  5242. }
  5243. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  5244. static void iwl3945_post_associate(struct iwl3945_priv *priv)
  5245. {
  5246. int rc = 0;
  5247. struct ieee80211_conf *conf = NULL;
  5248. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  5249. IWL_ERROR("%s Should not be called in AP mode\n", __func__);
  5250. return;
  5251. }
  5252. IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
  5253. priv->assoc_id, priv->active_rxon.bssid_addr);
  5254. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5255. return;
  5256. if (!priv->vif || !priv->is_open)
  5257. return;
  5258. iwl3945_scan_cancel_timeout(priv, 200);
  5259. conf = ieee80211_get_hw_conf(priv->hw);
  5260. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5261. iwl3945_commit_rxon(priv);
  5262. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5263. iwl3945_setup_rxon_timing(priv);
  5264. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5265. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5266. if (rc)
  5267. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5268. "Attempting to continue.\n");
  5269. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5270. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5271. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  5272. priv->assoc_id, priv->beacon_int);
  5273. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5274. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5275. else
  5276. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5277. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5278. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5279. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  5280. else
  5281. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5282. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  5283. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5284. }
  5285. iwl3945_commit_rxon(priv);
  5286. switch (priv->iw_mode) {
  5287. case NL80211_IFTYPE_STATION:
  5288. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  5289. break;
  5290. case NL80211_IFTYPE_ADHOC:
  5291. priv->assoc_id = 1;
  5292. iwl3945_add_station(priv, priv->bssid, 0, 0);
  5293. iwl3945_sync_sta(priv, IWL_STA_ID,
  5294. (priv->band == IEEE80211_BAND_5GHZ) ?
  5295. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  5296. CMD_ASYNC);
  5297. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  5298. iwl3945_send_beacon_cmd(priv);
  5299. break;
  5300. default:
  5301. IWL_ERROR("%s Should not be called in %d mode\n",
  5302. __func__, priv->iw_mode);
  5303. break;
  5304. }
  5305. iwl3945_activate_qos(priv, 0);
  5306. /* we have just associated, don't start scan too early */
  5307. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  5308. }
  5309. static void iwl3945_bg_abort_scan(struct work_struct *work)
  5310. {
  5311. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
  5312. if (!iwl3945_is_ready(priv))
  5313. return;
  5314. mutex_lock(&priv->mutex);
  5315. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  5316. iwl3945_send_scan_abort(priv);
  5317. mutex_unlock(&priv->mutex);
  5318. }
  5319. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
  5320. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5321. {
  5322. struct iwl3945_priv *priv =
  5323. container_of(work, struct iwl3945_priv, scan_completed);
  5324. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5325. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5326. return;
  5327. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  5328. iwl3945_mac_config(priv->hw, 0);
  5329. ieee80211_scan_completed(priv->hw);
  5330. /* Since setting the TXPOWER may have been deferred while
  5331. * performing the scan, fire one off */
  5332. mutex_lock(&priv->mutex);
  5333. iwl3945_hw_reg_send_txpower(priv);
  5334. mutex_unlock(&priv->mutex);
  5335. }
  5336. /*****************************************************************************
  5337. *
  5338. * mac80211 entry point functions
  5339. *
  5340. *****************************************************************************/
  5341. #define UCODE_READY_TIMEOUT (2 * HZ)
  5342. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5343. {
  5344. struct iwl3945_priv *priv = hw->priv;
  5345. int ret;
  5346. IWL_DEBUG_MAC80211("enter\n");
  5347. if (pci_enable_device(priv->pci_dev)) {
  5348. IWL_ERROR("Fail to pci_enable_device\n");
  5349. return -ENODEV;
  5350. }
  5351. pci_restore_state(priv->pci_dev);
  5352. pci_enable_msi(priv->pci_dev);
  5353. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  5354. DRV_NAME, priv);
  5355. if (ret) {
  5356. IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
  5357. goto out_disable_msi;
  5358. }
  5359. /* we should be verifying the device is ready to be opened */
  5360. mutex_lock(&priv->mutex);
  5361. memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  5362. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  5363. * ucode filename and max sizes are card-specific. */
  5364. if (!priv->ucode_code.len) {
  5365. ret = iwl3945_read_ucode(priv);
  5366. if (ret) {
  5367. IWL_ERROR("Could not read microcode: %d\n", ret);
  5368. mutex_unlock(&priv->mutex);
  5369. goto out_release_irq;
  5370. }
  5371. }
  5372. ret = __iwl3945_up(priv);
  5373. mutex_unlock(&priv->mutex);
  5374. iwl3945_rfkill_set_hw_state(priv);
  5375. if (ret)
  5376. goto out_release_irq;
  5377. IWL_DEBUG_INFO("Start UP work.\n");
  5378. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  5379. return 0;
  5380. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  5381. * mac80211 will not be run successfully. */
  5382. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  5383. test_bit(STATUS_READY, &priv->status),
  5384. UCODE_READY_TIMEOUT);
  5385. if (!ret) {
  5386. if (!test_bit(STATUS_READY, &priv->status)) {
  5387. IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
  5388. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  5389. ret = -ETIMEDOUT;
  5390. goto out_release_irq;
  5391. }
  5392. }
  5393. priv->is_open = 1;
  5394. IWL_DEBUG_MAC80211("leave\n");
  5395. return 0;
  5396. out_release_irq:
  5397. free_irq(priv->pci_dev->irq, priv);
  5398. out_disable_msi:
  5399. pci_disable_msi(priv->pci_dev);
  5400. pci_disable_device(priv->pci_dev);
  5401. priv->is_open = 0;
  5402. IWL_DEBUG_MAC80211("leave - failed\n");
  5403. return ret;
  5404. }
  5405. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5406. {
  5407. struct iwl3945_priv *priv = hw->priv;
  5408. IWL_DEBUG_MAC80211("enter\n");
  5409. if (!priv->is_open) {
  5410. IWL_DEBUG_MAC80211("leave - skip\n");
  5411. return;
  5412. }
  5413. priv->is_open = 0;
  5414. if (iwl3945_is_ready_rf(priv)) {
  5415. /* stop mac, cancel any scan request and clear
  5416. * RXON_FILTER_ASSOC_MSK BIT
  5417. */
  5418. mutex_lock(&priv->mutex);
  5419. iwl3945_scan_cancel_timeout(priv, 100);
  5420. mutex_unlock(&priv->mutex);
  5421. }
  5422. iwl3945_down(priv);
  5423. flush_workqueue(priv->workqueue);
  5424. free_irq(priv->pci_dev->irq, priv);
  5425. pci_disable_msi(priv->pci_dev);
  5426. pci_save_state(priv->pci_dev);
  5427. pci_disable_device(priv->pci_dev);
  5428. IWL_DEBUG_MAC80211("leave\n");
  5429. }
  5430. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  5431. {
  5432. struct iwl3945_priv *priv = hw->priv;
  5433. IWL_DEBUG_MAC80211("enter\n");
  5434. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5435. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  5436. if (iwl3945_tx_skb(priv, skb))
  5437. dev_kfree_skb_any(skb);
  5438. IWL_DEBUG_MAC80211("leave\n");
  5439. return 0;
  5440. }
  5441. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5442. struct ieee80211_if_init_conf *conf)
  5443. {
  5444. struct iwl3945_priv *priv = hw->priv;
  5445. unsigned long flags;
  5446. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5447. if (priv->vif) {
  5448. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5449. return -EOPNOTSUPP;
  5450. }
  5451. spin_lock_irqsave(&priv->lock, flags);
  5452. priv->vif = conf->vif;
  5453. priv->iw_mode = conf->type;
  5454. spin_unlock_irqrestore(&priv->lock, flags);
  5455. mutex_lock(&priv->mutex);
  5456. if (conf->mac_addr) {
  5457. IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
  5458. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5459. }
  5460. if (iwl3945_is_ready(priv))
  5461. iwl3945_set_mode(priv, conf->type);
  5462. mutex_unlock(&priv->mutex);
  5463. IWL_DEBUG_MAC80211("leave\n");
  5464. return 0;
  5465. }
  5466. /**
  5467. * iwl3945_mac_config - mac80211 config callback
  5468. *
  5469. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5470. * be set inappropriately and the driver currently sets the hardware up to
  5471. * use it whenever needed.
  5472. */
  5473. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
  5474. {
  5475. struct iwl3945_priv *priv = hw->priv;
  5476. const struct iwl3945_channel_info *ch_info;
  5477. struct ieee80211_conf *conf = &hw->conf;
  5478. unsigned long flags;
  5479. int ret = 0;
  5480. mutex_lock(&priv->mutex);
  5481. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5482. if (!iwl3945_is_ready(priv)) {
  5483. IWL_DEBUG_MAC80211("leave - not ready\n");
  5484. ret = -EIO;
  5485. goto out;
  5486. }
  5487. if (unlikely(!iwl3945_param_disable_hw_scan &&
  5488. test_bit(STATUS_SCANNING, &priv->status))) {
  5489. IWL_DEBUG_MAC80211("leave - scanning\n");
  5490. set_bit(STATUS_CONF_PENDING, &priv->status);
  5491. mutex_unlock(&priv->mutex);
  5492. return 0;
  5493. }
  5494. spin_lock_irqsave(&priv->lock, flags);
  5495. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5496. conf->channel->hw_value);
  5497. if (!is_channel_valid(ch_info)) {
  5498. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
  5499. conf->channel->hw_value, conf->channel->band);
  5500. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5501. spin_unlock_irqrestore(&priv->lock, flags);
  5502. ret = -EINVAL;
  5503. goto out;
  5504. }
  5505. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5506. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5507. /* The list of supported rates and rate mask can be different
  5508. * for each phymode; since the phymode may have changed, reset
  5509. * the rate mask to what mac80211 lists */
  5510. iwl3945_set_rate(priv);
  5511. spin_unlock_irqrestore(&priv->lock, flags);
  5512. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5513. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5514. iwl3945_hw_channel_switch(priv, conf->channel);
  5515. goto out;
  5516. }
  5517. #endif
  5518. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5519. if (!conf->radio_enabled) {
  5520. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5521. goto out;
  5522. }
  5523. if (iwl3945_is_rfkill(priv)) {
  5524. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5525. ret = -EIO;
  5526. goto out;
  5527. }
  5528. iwl3945_set_rate(priv);
  5529. if (memcmp(&priv->active_rxon,
  5530. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  5531. iwl3945_commit_rxon(priv);
  5532. else
  5533. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5534. IWL_DEBUG_MAC80211("leave\n");
  5535. out:
  5536. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5537. mutex_unlock(&priv->mutex);
  5538. return ret;
  5539. }
  5540. static void iwl3945_config_ap(struct iwl3945_priv *priv)
  5541. {
  5542. int rc = 0;
  5543. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5544. return;
  5545. /* The following should be done only at AP bring up */
  5546. if (!(iwl3945_is_associated(priv))) {
  5547. /* RXON - unassoc (to set timing command) */
  5548. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5549. iwl3945_commit_rxon(priv);
  5550. /* RXON Timing */
  5551. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5552. iwl3945_setup_rxon_timing(priv);
  5553. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5554. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5555. if (rc)
  5556. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5557. "Attempting to continue.\n");
  5558. /* FIXME: what should be the assoc_id for AP? */
  5559. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5560. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5561. priv->staging_rxon.flags |=
  5562. RXON_FLG_SHORT_PREAMBLE_MSK;
  5563. else
  5564. priv->staging_rxon.flags &=
  5565. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5566. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5567. if (priv->assoc_capability &
  5568. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5569. priv->staging_rxon.flags |=
  5570. RXON_FLG_SHORT_SLOT_MSK;
  5571. else
  5572. priv->staging_rxon.flags &=
  5573. ~RXON_FLG_SHORT_SLOT_MSK;
  5574. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  5575. priv->staging_rxon.flags &=
  5576. ~RXON_FLG_SHORT_SLOT_MSK;
  5577. }
  5578. /* restore RXON assoc */
  5579. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5580. iwl3945_commit_rxon(priv);
  5581. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5582. }
  5583. iwl3945_send_beacon_cmd(priv);
  5584. /* FIXME - we need to add code here to detect a totally new
  5585. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5586. * clear sta table, add BCAST sta... */
  5587. }
  5588. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5589. struct ieee80211_vif *vif,
  5590. struct ieee80211_if_conf *conf)
  5591. {
  5592. struct iwl3945_priv *priv = hw->priv;
  5593. int rc;
  5594. if (conf == NULL)
  5595. return -EIO;
  5596. if (priv->vif != vif) {
  5597. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5598. return 0;
  5599. }
  5600. /* handle this temporarily here */
  5601. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  5602. conf->changed & IEEE80211_IFCC_BEACON) {
  5603. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  5604. if (!beacon)
  5605. return -ENOMEM;
  5606. mutex_lock(&priv->mutex);
  5607. rc = iwl3945_mac_beacon_update(hw, beacon);
  5608. mutex_unlock(&priv->mutex);
  5609. if (rc)
  5610. return rc;
  5611. }
  5612. if (!iwl3945_is_alive(priv))
  5613. return -EAGAIN;
  5614. mutex_lock(&priv->mutex);
  5615. if (conf->bssid)
  5616. IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
  5617. /*
  5618. * very dubious code was here; the probe filtering flag is never set:
  5619. *
  5620. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5621. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5622. */
  5623. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  5624. if (!conf->bssid) {
  5625. conf->bssid = priv->mac_addr;
  5626. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5627. IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
  5628. conf->bssid);
  5629. }
  5630. if (priv->ibss_beacon)
  5631. dev_kfree_skb(priv->ibss_beacon);
  5632. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  5633. }
  5634. if (iwl3945_is_rfkill(priv))
  5635. goto done;
  5636. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5637. !is_multicast_ether_addr(conf->bssid)) {
  5638. /* If there is currently a HW scan going on in the background
  5639. * then we need to cancel it else the RXON below will fail. */
  5640. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5641. IWL_WARNING("Aborted scan still in progress "
  5642. "after 100ms\n");
  5643. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5644. mutex_unlock(&priv->mutex);
  5645. return -EAGAIN;
  5646. }
  5647. memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5648. /* TODO: Audit driver for usage of these members and see
  5649. * if mac80211 deprecates them (priv->bssid looks like it
  5650. * shouldn't be there, but I haven't scanned the IBSS code
  5651. * to verify) - jpk */
  5652. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5653. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5654. iwl3945_config_ap(priv);
  5655. else {
  5656. rc = iwl3945_commit_rxon(priv);
  5657. if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
  5658. iwl3945_add_station(priv,
  5659. priv->active_rxon.bssid_addr, 1, 0);
  5660. }
  5661. } else {
  5662. iwl3945_scan_cancel_timeout(priv, 100);
  5663. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5664. iwl3945_commit_rxon(priv);
  5665. }
  5666. done:
  5667. IWL_DEBUG_MAC80211("leave\n");
  5668. mutex_unlock(&priv->mutex);
  5669. return 0;
  5670. }
  5671. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5672. unsigned int changed_flags,
  5673. unsigned int *total_flags,
  5674. int mc_count, struct dev_addr_list *mc_list)
  5675. {
  5676. struct iwl3945_priv *priv = hw->priv;
  5677. __le32 *filter_flags = &priv->staging_rxon.filter_flags;
  5678. IWL_DEBUG_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
  5679. changed_flags, *total_flags);
  5680. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  5681. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  5682. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  5683. else
  5684. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  5685. }
  5686. if (changed_flags & FIF_ALLMULTI) {
  5687. if (*total_flags & FIF_ALLMULTI)
  5688. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  5689. else
  5690. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  5691. }
  5692. if (changed_flags & FIF_CONTROL) {
  5693. if (*total_flags & FIF_CONTROL)
  5694. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  5695. else
  5696. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  5697. }
  5698. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  5699. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  5700. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  5701. else
  5702. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  5703. }
  5704. /* We avoid iwl_commit_rxon here to commit the new filter flags
  5705. * since mac80211 will call ieee80211_hw_config immediately.
  5706. * (mc_list is not supported at this time). Otherwise, we need to
  5707. * queue a background iwl_commit_rxon work.
  5708. */
  5709. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  5710. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  5711. }
  5712. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5713. struct ieee80211_if_init_conf *conf)
  5714. {
  5715. struct iwl3945_priv *priv = hw->priv;
  5716. IWL_DEBUG_MAC80211("enter\n");
  5717. mutex_lock(&priv->mutex);
  5718. if (iwl3945_is_ready_rf(priv)) {
  5719. iwl3945_scan_cancel_timeout(priv, 100);
  5720. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5721. iwl3945_commit_rxon(priv);
  5722. }
  5723. if (priv->vif == conf->vif) {
  5724. priv->vif = NULL;
  5725. memset(priv->bssid, 0, ETH_ALEN);
  5726. }
  5727. mutex_unlock(&priv->mutex);
  5728. IWL_DEBUG_MAC80211("leave\n");
  5729. }
  5730. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  5731. static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
  5732. struct ieee80211_vif *vif,
  5733. struct ieee80211_bss_conf *bss_conf,
  5734. u32 changes)
  5735. {
  5736. struct iwl3945_priv *priv = hw->priv;
  5737. IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
  5738. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  5739. IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
  5740. bss_conf->use_short_preamble);
  5741. if (bss_conf->use_short_preamble)
  5742. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5743. else
  5744. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5745. }
  5746. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  5747. IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
  5748. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  5749. priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  5750. else
  5751. priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  5752. }
  5753. if (changes & BSS_CHANGED_ASSOC) {
  5754. IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
  5755. /* This should never happen as this function should
  5756. * never be called from interrupt context. */
  5757. if (WARN_ON_ONCE(in_interrupt()))
  5758. return;
  5759. if (bss_conf->assoc) {
  5760. priv->assoc_id = bss_conf->aid;
  5761. priv->beacon_int = bss_conf->beacon_int;
  5762. priv->timestamp0 = bss_conf->timestamp & 0xFFFFFFFF;
  5763. priv->timestamp1 = (bss_conf->timestamp >> 32) &
  5764. 0xFFFFFFFF;
  5765. priv->assoc_capability = bss_conf->assoc_capability;
  5766. priv->next_scan_jiffies = jiffies +
  5767. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  5768. mutex_lock(&priv->mutex);
  5769. iwl3945_post_associate(priv);
  5770. mutex_unlock(&priv->mutex);
  5771. } else {
  5772. priv->assoc_id = 0;
  5773. IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
  5774. }
  5775. } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
  5776. IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
  5777. iwl3945_send_rxon_assoc(priv);
  5778. }
  5779. }
  5780. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  5781. {
  5782. int rc = 0;
  5783. unsigned long flags;
  5784. struct iwl3945_priv *priv = hw->priv;
  5785. DECLARE_SSID_BUF(ssid_buf);
  5786. IWL_DEBUG_MAC80211("enter\n");
  5787. mutex_lock(&priv->mutex);
  5788. spin_lock_irqsave(&priv->lock, flags);
  5789. if (!iwl3945_is_ready_rf(priv)) {
  5790. rc = -EIO;
  5791. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  5792. goto out_unlock;
  5793. }
  5794. /* we don't schedule scan within next_scan_jiffies period */
  5795. if (priv->next_scan_jiffies &&
  5796. time_after(priv->next_scan_jiffies, jiffies)) {
  5797. rc = -EAGAIN;
  5798. goto out_unlock;
  5799. }
  5800. /* if we just finished scan ask for delay for a broadcast scan */
  5801. if ((len == 0) && priv->last_scan_jiffies &&
  5802. time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
  5803. jiffies)) {
  5804. rc = -EAGAIN;
  5805. goto out_unlock;
  5806. }
  5807. if (len) {
  5808. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  5809. print_ssid(ssid_buf, ssid, len), (int)len);
  5810. priv->one_direct_scan = 1;
  5811. priv->direct_ssid_len = (u8)
  5812. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  5813. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  5814. } else
  5815. priv->one_direct_scan = 0;
  5816. rc = iwl3945_scan_initiate(priv);
  5817. IWL_DEBUG_MAC80211("leave\n");
  5818. out_unlock:
  5819. spin_unlock_irqrestore(&priv->lock, flags);
  5820. mutex_unlock(&priv->mutex);
  5821. return rc;
  5822. }
  5823. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  5824. const u8 *local_addr, const u8 *addr,
  5825. struct ieee80211_key_conf *key)
  5826. {
  5827. struct iwl3945_priv *priv = hw->priv;
  5828. int rc = 0;
  5829. u8 sta_id;
  5830. IWL_DEBUG_MAC80211("enter\n");
  5831. if (!iwl3945_param_hwcrypto) {
  5832. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  5833. return -EOPNOTSUPP;
  5834. }
  5835. if (is_zero_ether_addr(addr))
  5836. /* only support pairwise keys */
  5837. return -EOPNOTSUPP;
  5838. sta_id = iwl3945_hw_find_station(priv, addr);
  5839. if (sta_id == IWL_INVALID_STATION) {
  5840. IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
  5841. addr);
  5842. return -EINVAL;
  5843. }
  5844. mutex_lock(&priv->mutex);
  5845. iwl3945_scan_cancel_timeout(priv, 100);
  5846. switch (cmd) {
  5847. case SET_KEY:
  5848. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  5849. if (!rc) {
  5850. iwl3945_set_rxon_hwcrypto(priv, 1);
  5851. iwl3945_commit_rxon(priv);
  5852. key->hw_key_idx = sta_id;
  5853. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  5854. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  5855. }
  5856. break;
  5857. case DISABLE_KEY:
  5858. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  5859. if (!rc) {
  5860. iwl3945_set_rxon_hwcrypto(priv, 0);
  5861. iwl3945_commit_rxon(priv);
  5862. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  5863. }
  5864. break;
  5865. default:
  5866. rc = -EINVAL;
  5867. }
  5868. IWL_DEBUG_MAC80211("leave\n");
  5869. mutex_unlock(&priv->mutex);
  5870. return rc;
  5871. }
  5872. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  5873. const struct ieee80211_tx_queue_params *params)
  5874. {
  5875. struct iwl3945_priv *priv = hw->priv;
  5876. unsigned long flags;
  5877. int q;
  5878. IWL_DEBUG_MAC80211("enter\n");
  5879. if (!iwl3945_is_ready_rf(priv)) {
  5880. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5881. return -EIO;
  5882. }
  5883. if (queue >= AC_NUM) {
  5884. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  5885. return 0;
  5886. }
  5887. q = AC_NUM - 1 - queue;
  5888. spin_lock_irqsave(&priv->lock, flags);
  5889. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  5890. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  5891. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  5892. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  5893. cpu_to_le16((params->txop * 32));
  5894. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  5895. priv->qos_data.qos_active = 1;
  5896. spin_unlock_irqrestore(&priv->lock, flags);
  5897. mutex_lock(&priv->mutex);
  5898. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5899. iwl3945_activate_qos(priv, 1);
  5900. else if (priv->assoc_id && iwl3945_is_associated(priv))
  5901. iwl3945_activate_qos(priv, 0);
  5902. mutex_unlock(&priv->mutex);
  5903. IWL_DEBUG_MAC80211("leave\n");
  5904. return 0;
  5905. }
  5906. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  5907. struct ieee80211_tx_queue_stats *stats)
  5908. {
  5909. struct iwl3945_priv *priv = hw->priv;
  5910. int i, avail;
  5911. struct iwl3945_tx_queue *txq;
  5912. struct iwl3945_queue *q;
  5913. unsigned long flags;
  5914. IWL_DEBUG_MAC80211("enter\n");
  5915. if (!iwl3945_is_ready_rf(priv)) {
  5916. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5917. return -EIO;
  5918. }
  5919. spin_lock_irqsave(&priv->lock, flags);
  5920. for (i = 0; i < AC_NUM; i++) {
  5921. txq = &priv->txq[i];
  5922. q = &txq->q;
  5923. avail = iwl3945_queue_space(q);
  5924. stats[i].len = q->n_window - avail;
  5925. stats[i].limit = q->n_window - q->high_mark;
  5926. stats[i].count = q->n_window;
  5927. }
  5928. spin_unlock_irqrestore(&priv->lock, flags);
  5929. IWL_DEBUG_MAC80211("leave\n");
  5930. return 0;
  5931. }
  5932. static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
  5933. struct ieee80211_low_level_stats *stats)
  5934. {
  5935. IWL_DEBUG_MAC80211("enter\n");
  5936. IWL_DEBUG_MAC80211("leave\n");
  5937. return 0;
  5938. }
  5939. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  5940. {
  5941. struct iwl3945_priv *priv = hw->priv;
  5942. unsigned long flags;
  5943. mutex_lock(&priv->mutex);
  5944. IWL_DEBUG_MAC80211("enter\n");
  5945. iwl3945_reset_qos(priv);
  5946. spin_lock_irqsave(&priv->lock, flags);
  5947. priv->assoc_id = 0;
  5948. priv->assoc_capability = 0;
  5949. priv->call_post_assoc_from_beacon = 0;
  5950. /* new association get rid of ibss beacon skb */
  5951. if (priv->ibss_beacon)
  5952. dev_kfree_skb(priv->ibss_beacon);
  5953. priv->ibss_beacon = NULL;
  5954. priv->beacon_int = priv->hw->conf.beacon_int;
  5955. priv->timestamp1 = 0;
  5956. priv->timestamp0 = 0;
  5957. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  5958. priv->beacon_int = 0;
  5959. spin_unlock_irqrestore(&priv->lock, flags);
  5960. if (!iwl3945_is_ready_rf(priv)) {
  5961. IWL_DEBUG_MAC80211("leave - not ready\n");
  5962. mutex_unlock(&priv->mutex);
  5963. return;
  5964. }
  5965. /* we are restarting association process
  5966. * clear RXON_FILTER_ASSOC_MSK bit
  5967. */
  5968. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  5969. iwl3945_scan_cancel_timeout(priv, 100);
  5970. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5971. iwl3945_commit_rxon(priv);
  5972. }
  5973. /* Per mac80211.h: This is only used in IBSS mode... */
  5974. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5975. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  5976. mutex_unlock(&priv->mutex);
  5977. return;
  5978. }
  5979. iwl3945_set_rate(priv);
  5980. mutex_unlock(&priv->mutex);
  5981. IWL_DEBUG_MAC80211("leave\n");
  5982. }
  5983. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  5984. {
  5985. struct iwl3945_priv *priv = hw->priv;
  5986. unsigned long flags;
  5987. IWL_DEBUG_MAC80211("enter\n");
  5988. if (!iwl3945_is_ready_rf(priv)) {
  5989. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5990. return -EIO;
  5991. }
  5992. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5993. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  5994. return -EIO;
  5995. }
  5996. spin_lock_irqsave(&priv->lock, flags);
  5997. if (priv->ibss_beacon)
  5998. dev_kfree_skb(priv->ibss_beacon);
  5999. priv->ibss_beacon = skb;
  6000. priv->assoc_id = 0;
  6001. IWL_DEBUG_MAC80211("leave\n");
  6002. spin_unlock_irqrestore(&priv->lock, flags);
  6003. iwl3945_reset_qos(priv);
  6004. iwl3945_post_associate(priv);
  6005. return 0;
  6006. }
  6007. /*****************************************************************************
  6008. *
  6009. * sysfs attributes
  6010. *
  6011. *****************************************************************************/
  6012. #ifdef CONFIG_IWL3945_DEBUG
  6013. /*
  6014. * The following adds a new attribute to the sysfs representation
  6015. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  6016. * used for controlling the debug level.
  6017. *
  6018. * See the level definitions in iwl for details.
  6019. */
  6020. static ssize_t show_debug_level(struct device_driver *d, char *buf)
  6021. {
  6022. return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
  6023. }
  6024. static ssize_t store_debug_level(struct device_driver *d,
  6025. const char *buf, size_t count)
  6026. {
  6027. char *p = (char *)buf;
  6028. u32 val;
  6029. val = simple_strtoul(p, &p, 0);
  6030. if (p == buf)
  6031. printk(KERN_INFO DRV_NAME
  6032. ": %s is not in hex or decimal form.\n", buf);
  6033. else
  6034. iwl3945_debug_level = val;
  6035. return strnlen(buf, count);
  6036. }
  6037. static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
  6038. show_debug_level, store_debug_level);
  6039. #endif /* CONFIG_IWL3945_DEBUG */
  6040. static ssize_t show_temperature(struct device *d,
  6041. struct device_attribute *attr, char *buf)
  6042. {
  6043. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6044. if (!iwl3945_is_alive(priv))
  6045. return -EAGAIN;
  6046. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  6047. }
  6048. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  6049. static ssize_t show_tx_power(struct device *d,
  6050. struct device_attribute *attr, char *buf)
  6051. {
  6052. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6053. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  6054. }
  6055. static ssize_t store_tx_power(struct device *d,
  6056. struct device_attribute *attr,
  6057. const char *buf, size_t count)
  6058. {
  6059. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6060. char *p = (char *)buf;
  6061. u32 val;
  6062. val = simple_strtoul(p, &p, 10);
  6063. if (p == buf)
  6064. printk(KERN_INFO DRV_NAME
  6065. ": %s is not in decimal form.\n", buf);
  6066. else
  6067. iwl3945_hw_reg_set_txpower(priv, val);
  6068. return count;
  6069. }
  6070. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  6071. static ssize_t show_flags(struct device *d,
  6072. struct device_attribute *attr, char *buf)
  6073. {
  6074. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6075. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  6076. }
  6077. static ssize_t store_flags(struct device *d,
  6078. struct device_attribute *attr,
  6079. const char *buf, size_t count)
  6080. {
  6081. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6082. u32 flags = simple_strtoul(buf, NULL, 0);
  6083. mutex_lock(&priv->mutex);
  6084. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  6085. /* Cancel any currently running scans... */
  6086. if (iwl3945_scan_cancel_timeout(priv, 100))
  6087. IWL_WARNING("Could not cancel scan.\n");
  6088. else {
  6089. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  6090. flags);
  6091. priv->staging_rxon.flags = cpu_to_le32(flags);
  6092. iwl3945_commit_rxon(priv);
  6093. }
  6094. }
  6095. mutex_unlock(&priv->mutex);
  6096. return count;
  6097. }
  6098. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  6099. static ssize_t show_filter_flags(struct device *d,
  6100. struct device_attribute *attr, char *buf)
  6101. {
  6102. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6103. return sprintf(buf, "0x%04X\n",
  6104. le32_to_cpu(priv->active_rxon.filter_flags));
  6105. }
  6106. static ssize_t store_filter_flags(struct device *d,
  6107. struct device_attribute *attr,
  6108. const char *buf, size_t count)
  6109. {
  6110. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6111. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  6112. mutex_lock(&priv->mutex);
  6113. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  6114. /* Cancel any currently running scans... */
  6115. if (iwl3945_scan_cancel_timeout(priv, 100))
  6116. IWL_WARNING("Could not cancel scan.\n");
  6117. else {
  6118. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  6119. "0x%04X\n", filter_flags);
  6120. priv->staging_rxon.filter_flags =
  6121. cpu_to_le32(filter_flags);
  6122. iwl3945_commit_rxon(priv);
  6123. }
  6124. }
  6125. mutex_unlock(&priv->mutex);
  6126. return count;
  6127. }
  6128. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  6129. store_filter_flags);
  6130. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6131. static ssize_t show_measurement(struct device *d,
  6132. struct device_attribute *attr, char *buf)
  6133. {
  6134. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6135. struct iwl3945_spectrum_notification measure_report;
  6136. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  6137. u8 *data = (u8 *)&measure_report;
  6138. unsigned long flags;
  6139. spin_lock_irqsave(&priv->lock, flags);
  6140. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  6141. spin_unlock_irqrestore(&priv->lock, flags);
  6142. return 0;
  6143. }
  6144. memcpy(&measure_report, &priv->measure_report, size);
  6145. priv->measurement_status = 0;
  6146. spin_unlock_irqrestore(&priv->lock, flags);
  6147. while (size && (PAGE_SIZE - len)) {
  6148. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6149. PAGE_SIZE - len, 1);
  6150. len = strlen(buf);
  6151. if (PAGE_SIZE - len)
  6152. buf[len++] = '\n';
  6153. ofs += 16;
  6154. size -= min(size, 16U);
  6155. }
  6156. return len;
  6157. }
  6158. static ssize_t store_measurement(struct device *d,
  6159. struct device_attribute *attr,
  6160. const char *buf, size_t count)
  6161. {
  6162. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6163. struct ieee80211_measurement_params params = {
  6164. .channel = le16_to_cpu(priv->active_rxon.channel),
  6165. .start_time = cpu_to_le64(priv->last_tsf),
  6166. .duration = cpu_to_le16(1),
  6167. };
  6168. u8 type = IWL_MEASURE_BASIC;
  6169. u8 buffer[32];
  6170. u8 channel;
  6171. if (count) {
  6172. char *p = buffer;
  6173. strncpy(buffer, buf, min(sizeof(buffer), count));
  6174. channel = simple_strtoul(p, NULL, 0);
  6175. if (channel)
  6176. params.channel = channel;
  6177. p = buffer;
  6178. while (*p && *p != ' ')
  6179. p++;
  6180. if (*p)
  6181. type = simple_strtoul(p + 1, NULL, 0);
  6182. }
  6183. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  6184. "channel %d (for '%s')\n", type, params.channel, buf);
  6185. iwl3945_get_measurement(priv, &params, type);
  6186. return count;
  6187. }
  6188. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  6189. show_measurement, store_measurement);
  6190. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  6191. static ssize_t store_retry_rate(struct device *d,
  6192. struct device_attribute *attr,
  6193. const char *buf, size_t count)
  6194. {
  6195. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6196. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  6197. if (priv->retry_rate <= 0)
  6198. priv->retry_rate = 1;
  6199. return count;
  6200. }
  6201. static ssize_t show_retry_rate(struct device *d,
  6202. struct device_attribute *attr, char *buf)
  6203. {
  6204. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6205. return sprintf(buf, "%d", priv->retry_rate);
  6206. }
  6207. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  6208. store_retry_rate);
  6209. static ssize_t store_power_level(struct device *d,
  6210. struct device_attribute *attr,
  6211. const char *buf, size_t count)
  6212. {
  6213. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6214. int rc;
  6215. int mode;
  6216. mode = simple_strtoul(buf, NULL, 0);
  6217. mutex_lock(&priv->mutex);
  6218. if (!iwl3945_is_ready(priv)) {
  6219. rc = -EAGAIN;
  6220. goto out;
  6221. }
  6222. if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
  6223. mode = IWL_POWER_AC;
  6224. else
  6225. mode |= IWL_POWER_ENABLED;
  6226. if (mode != priv->power_mode) {
  6227. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  6228. if (rc) {
  6229. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  6230. goto out;
  6231. }
  6232. priv->power_mode = mode;
  6233. }
  6234. rc = count;
  6235. out:
  6236. mutex_unlock(&priv->mutex);
  6237. return rc;
  6238. }
  6239. #define MAX_WX_STRING 80
  6240. /* Values are in microsecond */
  6241. static const s32 timeout_duration[] = {
  6242. 350000,
  6243. 250000,
  6244. 75000,
  6245. 37000,
  6246. 25000,
  6247. };
  6248. static const s32 period_duration[] = {
  6249. 400000,
  6250. 700000,
  6251. 1000000,
  6252. 1000000,
  6253. 1000000
  6254. };
  6255. static ssize_t show_power_level(struct device *d,
  6256. struct device_attribute *attr, char *buf)
  6257. {
  6258. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6259. int level = IWL_POWER_LEVEL(priv->power_mode);
  6260. char *p = buf;
  6261. p += sprintf(p, "%d ", level);
  6262. switch (level) {
  6263. case IWL_POWER_MODE_CAM:
  6264. case IWL_POWER_AC:
  6265. p += sprintf(p, "(AC)");
  6266. break;
  6267. case IWL_POWER_BATTERY:
  6268. p += sprintf(p, "(BATTERY)");
  6269. break;
  6270. default:
  6271. p += sprintf(p,
  6272. "(Timeout %dms, Period %dms)",
  6273. timeout_duration[level - 1] / 1000,
  6274. period_duration[level - 1] / 1000);
  6275. }
  6276. if (!(priv->power_mode & IWL_POWER_ENABLED))
  6277. p += sprintf(p, " OFF\n");
  6278. else
  6279. p += sprintf(p, " \n");
  6280. return p - buf + 1;
  6281. }
  6282. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  6283. store_power_level);
  6284. static ssize_t show_channels(struct device *d,
  6285. struct device_attribute *attr, char *buf)
  6286. {
  6287. /* all this shit doesn't belong into sysfs anyway */
  6288. return 0;
  6289. }
  6290. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  6291. static ssize_t show_statistics(struct device *d,
  6292. struct device_attribute *attr, char *buf)
  6293. {
  6294. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6295. u32 size = sizeof(struct iwl3945_notif_statistics);
  6296. u32 len = 0, ofs = 0;
  6297. u8 *data = (u8 *)&priv->statistics;
  6298. int rc = 0;
  6299. if (!iwl3945_is_alive(priv))
  6300. return -EAGAIN;
  6301. mutex_lock(&priv->mutex);
  6302. rc = iwl3945_send_statistics_request(priv);
  6303. mutex_unlock(&priv->mutex);
  6304. if (rc) {
  6305. len = sprintf(buf,
  6306. "Error sending statistics request: 0x%08X\n", rc);
  6307. return len;
  6308. }
  6309. while (size && (PAGE_SIZE - len)) {
  6310. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6311. PAGE_SIZE - len, 1);
  6312. len = strlen(buf);
  6313. if (PAGE_SIZE - len)
  6314. buf[len++] = '\n';
  6315. ofs += 16;
  6316. size -= min(size, 16U);
  6317. }
  6318. return len;
  6319. }
  6320. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  6321. static ssize_t show_antenna(struct device *d,
  6322. struct device_attribute *attr, char *buf)
  6323. {
  6324. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6325. if (!iwl3945_is_alive(priv))
  6326. return -EAGAIN;
  6327. return sprintf(buf, "%d\n", priv->antenna);
  6328. }
  6329. static ssize_t store_antenna(struct device *d,
  6330. struct device_attribute *attr,
  6331. const char *buf, size_t count)
  6332. {
  6333. int ant;
  6334. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6335. if (count == 0)
  6336. return 0;
  6337. if (sscanf(buf, "%1i", &ant) != 1) {
  6338. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6339. return count;
  6340. }
  6341. if ((ant >= 0) && (ant <= 2)) {
  6342. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6343. priv->antenna = (enum iwl3945_antenna)ant;
  6344. } else
  6345. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6346. return count;
  6347. }
  6348. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6349. static ssize_t show_status(struct device *d,
  6350. struct device_attribute *attr, char *buf)
  6351. {
  6352. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6353. if (!iwl3945_is_alive(priv))
  6354. return -EAGAIN;
  6355. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6356. }
  6357. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6358. static ssize_t dump_error_log(struct device *d,
  6359. struct device_attribute *attr,
  6360. const char *buf, size_t count)
  6361. {
  6362. char *p = (char *)buf;
  6363. if (p[0] == '1')
  6364. iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
  6365. return strnlen(buf, count);
  6366. }
  6367. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6368. static ssize_t dump_event_log(struct device *d,
  6369. struct device_attribute *attr,
  6370. const char *buf, size_t count)
  6371. {
  6372. char *p = (char *)buf;
  6373. if (p[0] == '1')
  6374. iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
  6375. return strnlen(buf, count);
  6376. }
  6377. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6378. /*****************************************************************************
  6379. *
  6380. * driver setup and tear down
  6381. *
  6382. *****************************************************************************/
  6383. static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
  6384. {
  6385. priv->workqueue = create_workqueue(DRV_NAME);
  6386. init_waitqueue_head(&priv->wait_command_queue);
  6387. INIT_WORK(&priv->up, iwl3945_bg_up);
  6388. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6389. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6390. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6391. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6392. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6393. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6394. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6395. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6396. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6397. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6398. iwl3945_hw_setup_deferred_work(priv);
  6399. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6400. iwl3945_irq_tasklet, (unsigned long)priv);
  6401. }
  6402. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
  6403. {
  6404. iwl3945_hw_cancel_deferred_work(priv);
  6405. cancel_delayed_work_sync(&priv->init_alive_start);
  6406. cancel_delayed_work(&priv->scan_check);
  6407. cancel_delayed_work(&priv->alive_start);
  6408. cancel_work_sync(&priv->beacon_update);
  6409. }
  6410. static struct attribute *iwl3945_sysfs_entries[] = {
  6411. &dev_attr_antenna.attr,
  6412. &dev_attr_channels.attr,
  6413. &dev_attr_dump_errors.attr,
  6414. &dev_attr_dump_events.attr,
  6415. &dev_attr_flags.attr,
  6416. &dev_attr_filter_flags.attr,
  6417. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6418. &dev_attr_measurement.attr,
  6419. #endif
  6420. &dev_attr_power_level.attr,
  6421. &dev_attr_retry_rate.attr,
  6422. &dev_attr_statistics.attr,
  6423. &dev_attr_status.attr,
  6424. &dev_attr_temperature.attr,
  6425. &dev_attr_tx_power.attr,
  6426. NULL
  6427. };
  6428. static struct attribute_group iwl3945_attribute_group = {
  6429. .name = NULL, /* put in device directory */
  6430. .attrs = iwl3945_sysfs_entries,
  6431. };
  6432. static struct ieee80211_ops iwl3945_hw_ops = {
  6433. .tx = iwl3945_mac_tx,
  6434. .start = iwl3945_mac_start,
  6435. .stop = iwl3945_mac_stop,
  6436. .add_interface = iwl3945_mac_add_interface,
  6437. .remove_interface = iwl3945_mac_remove_interface,
  6438. .config = iwl3945_mac_config,
  6439. .config_interface = iwl3945_mac_config_interface,
  6440. .configure_filter = iwl3945_configure_filter,
  6441. .set_key = iwl3945_mac_set_key,
  6442. .get_stats = iwl3945_mac_get_stats,
  6443. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6444. .conf_tx = iwl3945_mac_conf_tx,
  6445. .reset_tsf = iwl3945_mac_reset_tsf,
  6446. .bss_info_changed = iwl3945_bss_info_changed,
  6447. .hw_scan = iwl3945_mac_hw_scan
  6448. };
  6449. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6450. {
  6451. int err = 0;
  6452. struct iwl3945_priv *priv;
  6453. struct ieee80211_hw *hw;
  6454. struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
  6455. unsigned long flags;
  6456. /***********************
  6457. * 1. Allocating HW data
  6458. * ********************/
  6459. /* Disabling hardware scan means that mac80211 will perform scans
  6460. * "the hard way", rather than using device's scan. */
  6461. if (iwl3945_param_disable_hw_scan) {
  6462. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6463. iwl3945_hw_ops.hw_scan = NULL;
  6464. }
  6465. if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
  6466. (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
  6467. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  6468. IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
  6469. err = -EINVAL;
  6470. goto out;
  6471. }
  6472. /* mac80211 allocates memory for this device instance, including
  6473. * space for this driver's private structure */
  6474. hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
  6475. if (hw == NULL) {
  6476. IWL_ERROR("Can not allocate network device\n");
  6477. err = -ENOMEM;
  6478. goto out;
  6479. }
  6480. SET_IEEE80211_DEV(hw, &pdev->dev);
  6481. priv = hw->priv;
  6482. priv->hw = hw;
  6483. priv->pci_dev = pdev;
  6484. priv->cfg = cfg;
  6485. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6486. hw->rate_control_algorithm = "iwl-3945-rs";
  6487. hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
  6488. /* Select antenna (may be helpful if only one antenna is connected) */
  6489. priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
  6490. #ifdef CONFIG_IWL3945_DEBUG
  6491. iwl3945_debug_level = iwl3945_param_debug;
  6492. atomic_set(&priv->restrict_refcnt, 0);
  6493. #endif
  6494. /* Tell mac80211 our characteristics */
  6495. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  6496. IEEE80211_HW_NOISE_DBM;
  6497. hw->wiphy->interface_modes =
  6498. BIT(NL80211_IFTYPE_STATION) |
  6499. BIT(NL80211_IFTYPE_ADHOC);
  6500. hw->wiphy->fw_handles_regulatory = true;
  6501. /* 4 EDCA QOS priorities */
  6502. hw->queues = 4;
  6503. /***************************
  6504. * 2. Initializing PCI bus
  6505. * *************************/
  6506. if (pci_enable_device(pdev)) {
  6507. err = -ENODEV;
  6508. goto out_ieee80211_free_hw;
  6509. }
  6510. pci_set_master(pdev);
  6511. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6512. if (!err)
  6513. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6514. if (err) {
  6515. printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
  6516. goto out_pci_disable_device;
  6517. }
  6518. pci_set_drvdata(pdev, priv);
  6519. err = pci_request_regions(pdev, DRV_NAME);
  6520. if (err)
  6521. goto out_pci_disable_device;
  6522. /***********************
  6523. * 3. Read REV Register
  6524. * ********************/
  6525. priv->hw_base = pci_iomap(pdev, 0, 0);
  6526. if (!priv->hw_base) {
  6527. err = -ENODEV;
  6528. goto out_pci_release_regions;
  6529. }
  6530. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6531. (unsigned long long) pci_resource_len(pdev, 0));
  6532. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6533. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6534. * PCI Tx retries from interfering with C3 CPU state */
  6535. pci_write_config_byte(pdev, 0x41, 0x00);
  6536. /* nic init */
  6537. iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  6538. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  6539. iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  6540. err = iwl3945_poll_direct_bit(priv, CSR_GP_CNTRL,
  6541. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  6542. if (err < 0) {
  6543. IWL_DEBUG_INFO("Failed to init the card\n");
  6544. goto out_remove_sysfs;
  6545. }
  6546. /***********************
  6547. * 4. Read EEPROM
  6548. * ********************/
  6549. /* Read the EEPROM */
  6550. err = iwl3945_eeprom_init(priv);
  6551. if (err) {
  6552. IWL_ERROR("Unable to init EEPROM\n");
  6553. goto out_remove_sysfs;
  6554. }
  6555. /* MAC Address location in EEPROM same for 3945/4965 */
  6556. get_eeprom_mac(priv, priv->mac_addr);
  6557. IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
  6558. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6559. /***********************
  6560. * 5. Setup HW Constants
  6561. * ********************/
  6562. /* Device-specific setup */
  6563. if (iwl3945_hw_set_hw_setting(priv)) {
  6564. IWL_ERROR("failed to set hw settings\n");
  6565. goto out_iounmap;
  6566. }
  6567. /***********************
  6568. * 6. Setup priv
  6569. * ********************/
  6570. priv->retry_rate = 1;
  6571. priv->ibss_beacon = NULL;
  6572. spin_lock_init(&priv->lock);
  6573. spin_lock_init(&priv->power_data.lock);
  6574. spin_lock_init(&priv->sta_lock);
  6575. spin_lock_init(&priv->hcmd_lock);
  6576. INIT_LIST_HEAD(&priv->free_frames);
  6577. mutex_init(&priv->mutex);
  6578. /* Clear the driver's (not device's) station table */
  6579. iwl3945_clear_stations_table(priv);
  6580. priv->data_retry_limit = -1;
  6581. priv->ieee_channels = NULL;
  6582. priv->ieee_rates = NULL;
  6583. priv->band = IEEE80211_BAND_2GHZ;
  6584. priv->iw_mode = NL80211_IFTYPE_STATION;
  6585. iwl3945_reset_qos(priv);
  6586. priv->qos_data.qos_active = 0;
  6587. priv->qos_data.qos_cap.val = 0;
  6588. priv->rates_mask = IWL_RATES_MASK;
  6589. /* If power management is turned on, default to AC mode */
  6590. priv->power_mode = IWL_POWER_AC;
  6591. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6592. err = iwl3945_init_channel_map(priv);
  6593. if (err) {
  6594. IWL_ERROR("initializing regulatory failed: %d\n", err);
  6595. goto out_release_irq;
  6596. }
  6597. err = iwl3945_init_geos(priv);
  6598. if (err) {
  6599. IWL_ERROR("initializing geos failed: %d\n", err);
  6600. goto out_free_channel_map;
  6601. }
  6602. printk(KERN_INFO DRV_NAME
  6603. ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
  6604. /***********************************
  6605. * 7. Initialize Module Parameters
  6606. * **********************************/
  6607. /* Initialize module parameter values here */
  6608. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6609. if (iwl3945_param_disable) {
  6610. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6611. IWL_DEBUG_INFO("Radio disabled.\n");
  6612. }
  6613. /***********************
  6614. * 8. Setup Services
  6615. * ********************/
  6616. spin_lock_irqsave(&priv->lock, flags);
  6617. iwl3945_disable_interrupts(priv);
  6618. spin_unlock_irqrestore(&priv->lock, flags);
  6619. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6620. if (err) {
  6621. IWL_ERROR("failed to create sysfs device attributes\n");
  6622. goto out_free_geos;
  6623. }
  6624. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6625. iwl3945_setup_deferred_work(priv);
  6626. iwl3945_setup_rx_handlers(priv);
  6627. /***********************
  6628. * 9. Conclude
  6629. * ********************/
  6630. pci_save_state(pdev);
  6631. pci_disable_device(pdev);
  6632. /*********************************
  6633. * 10. Setup and Register mac80211
  6634. * *******************************/
  6635. err = ieee80211_register_hw(priv->hw);
  6636. if (err) {
  6637. IWL_ERROR("Failed to register network device (error %d)\n", err);
  6638. goto out_remove_sysfs;
  6639. }
  6640. priv->hw->conf.beacon_int = 100;
  6641. priv->mac80211_registered = 1;
  6642. err = iwl3945_rfkill_init(priv);
  6643. if (err)
  6644. IWL_ERROR("Unable to initialize RFKILL system. "
  6645. "Ignoring error: %d\n", err);
  6646. return 0;
  6647. out_remove_sysfs:
  6648. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6649. out_free_geos:
  6650. iwl3945_free_geos(priv);
  6651. out_free_channel_map:
  6652. iwl3945_free_channel_map(priv);
  6653. out_release_irq:
  6654. destroy_workqueue(priv->workqueue);
  6655. priv->workqueue = NULL;
  6656. iwl3945_unset_hw_setting(priv);
  6657. out_iounmap:
  6658. pci_iounmap(pdev, priv->hw_base);
  6659. out_pci_release_regions:
  6660. pci_release_regions(pdev);
  6661. out_pci_disable_device:
  6662. pci_disable_device(pdev);
  6663. pci_set_drvdata(pdev, NULL);
  6664. out_ieee80211_free_hw:
  6665. ieee80211_free_hw(priv->hw);
  6666. out:
  6667. return err;
  6668. }
  6669. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  6670. {
  6671. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6672. unsigned long flags;
  6673. if (!priv)
  6674. return;
  6675. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  6676. set_bit(STATUS_EXIT_PENDING, &priv->status);
  6677. iwl3945_down(priv);
  6678. /* make sure we flush any pending irq or
  6679. * tasklet for the driver
  6680. */
  6681. spin_lock_irqsave(&priv->lock, flags);
  6682. iwl3945_disable_interrupts(priv);
  6683. spin_unlock_irqrestore(&priv->lock, flags);
  6684. iwl_synchronize_irq(priv);
  6685. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6686. iwl3945_rfkill_unregister(priv);
  6687. iwl3945_dealloc_ucode_pci(priv);
  6688. if (priv->rxq.bd)
  6689. iwl3945_rx_queue_free(priv, &priv->rxq);
  6690. iwl3945_hw_txq_ctx_free(priv);
  6691. iwl3945_unset_hw_setting(priv);
  6692. iwl3945_clear_stations_table(priv);
  6693. if (priv->mac80211_registered)
  6694. ieee80211_unregister_hw(priv->hw);
  6695. /*netif_stop_queue(dev); */
  6696. flush_workqueue(priv->workqueue);
  6697. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  6698. * priv->workqueue... so we can't take down the workqueue
  6699. * until now... */
  6700. destroy_workqueue(priv->workqueue);
  6701. priv->workqueue = NULL;
  6702. pci_iounmap(pdev, priv->hw_base);
  6703. pci_release_regions(pdev);
  6704. pci_disable_device(pdev);
  6705. pci_set_drvdata(pdev, NULL);
  6706. iwl3945_free_channel_map(priv);
  6707. iwl3945_free_geos(priv);
  6708. kfree(priv->scan);
  6709. if (priv->ibss_beacon)
  6710. dev_kfree_skb(priv->ibss_beacon);
  6711. ieee80211_free_hw(priv->hw);
  6712. }
  6713. #ifdef CONFIG_PM
  6714. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  6715. {
  6716. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6717. if (priv->is_open) {
  6718. set_bit(STATUS_IN_SUSPEND, &priv->status);
  6719. iwl3945_mac_stop(priv->hw);
  6720. priv->is_open = 1;
  6721. }
  6722. pci_set_power_state(pdev, PCI_D3hot);
  6723. return 0;
  6724. }
  6725. static int iwl3945_pci_resume(struct pci_dev *pdev)
  6726. {
  6727. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6728. pci_set_power_state(pdev, PCI_D0);
  6729. if (priv->is_open)
  6730. iwl3945_mac_start(priv->hw);
  6731. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  6732. return 0;
  6733. }
  6734. #endif /* CONFIG_PM */
  6735. /*************** RFKILL FUNCTIONS **********/
  6736. #ifdef CONFIG_IWL3945_RFKILL
  6737. /* software rf-kill from user */
  6738. static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
  6739. {
  6740. struct iwl3945_priv *priv = data;
  6741. int err = 0;
  6742. if (!priv->rfkill)
  6743. return 0;
  6744. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  6745. return 0;
  6746. IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state);
  6747. mutex_lock(&priv->mutex);
  6748. switch (state) {
  6749. case RFKILL_STATE_UNBLOCKED:
  6750. if (iwl3945_is_rfkill_hw(priv)) {
  6751. err = -EBUSY;
  6752. goto out_unlock;
  6753. }
  6754. iwl3945_radio_kill_sw(priv, 0);
  6755. break;
  6756. case RFKILL_STATE_SOFT_BLOCKED:
  6757. iwl3945_radio_kill_sw(priv, 1);
  6758. break;
  6759. default:
  6760. IWL_WARNING("we received unexpected RFKILL state %d\n", state);
  6761. break;
  6762. }
  6763. out_unlock:
  6764. mutex_unlock(&priv->mutex);
  6765. return err;
  6766. }
  6767. int iwl3945_rfkill_init(struct iwl3945_priv *priv)
  6768. {
  6769. struct device *device = wiphy_dev(priv->hw->wiphy);
  6770. int ret = 0;
  6771. BUG_ON(device == NULL);
  6772. IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
  6773. priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
  6774. if (!priv->rfkill) {
  6775. IWL_ERROR("Unable to allocate rfkill device.\n");
  6776. ret = -ENOMEM;
  6777. goto error;
  6778. }
  6779. priv->rfkill->name = priv->cfg->name;
  6780. priv->rfkill->data = priv;
  6781. priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
  6782. priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
  6783. priv->rfkill->user_claim_unsupported = 1;
  6784. priv->rfkill->dev.class->suspend = NULL;
  6785. priv->rfkill->dev.class->resume = NULL;
  6786. ret = rfkill_register(priv->rfkill);
  6787. if (ret) {
  6788. IWL_ERROR("Unable to register rfkill: %d\n", ret);
  6789. goto freed_rfkill;
  6790. }
  6791. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6792. return ret;
  6793. freed_rfkill:
  6794. if (priv->rfkill != NULL)
  6795. rfkill_free(priv->rfkill);
  6796. priv->rfkill = NULL;
  6797. error:
  6798. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6799. return ret;
  6800. }
  6801. void iwl3945_rfkill_unregister(struct iwl3945_priv *priv)
  6802. {
  6803. if (priv->rfkill)
  6804. rfkill_unregister(priv->rfkill);
  6805. priv->rfkill = NULL;
  6806. }
  6807. /* set rf-kill to the right state. */
  6808. void iwl3945_rfkill_set_hw_state(struct iwl3945_priv *priv)
  6809. {
  6810. if (!priv->rfkill)
  6811. return;
  6812. if (iwl3945_is_rfkill_hw(priv)) {
  6813. rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
  6814. return;
  6815. }
  6816. if (!iwl3945_is_rfkill_sw(priv))
  6817. rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
  6818. else
  6819. rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
  6820. }
  6821. #endif
  6822. /*****************************************************************************
  6823. *
  6824. * driver and module entry point
  6825. *
  6826. *****************************************************************************/
  6827. static struct pci_driver iwl3945_driver = {
  6828. .name = DRV_NAME,
  6829. .id_table = iwl3945_hw_card_ids,
  6830. .probe = iwl3945_pci_probe,
  6831. .remove = __devexit_p(iwl3945_pci_remove),
  6832. #ifdef CONFIG_PM
  6833. .suspend = iwl3945_pci_suspend,
  6834. .resume = iwl3945_pci_resume,
  6835. #endif
  6836. };
  6837. static int __init iwl3945_init(void)
  6838. {
  6839. int ret;
  6840. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  6841. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  6842. ret = iwl3945_rate_control_register();
  6843. if (ret) {
  6844. IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
  6845. return ret;
  6846. }
  6847. ret = pci_register_driver(&iwl3945_driver);
  6848. if (ret) {
  6849. IWL_ERROR("Unable to initialize PCI module\n");
  6850. goto error_register;
  6851. }
  6852. #ifdef CONFIG_IWL3945_DEBUG
  6853. ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6854. if (ret) {
  6855. IWL_ERROR("Unable to create driver sysfs file\n");
  6856. goto error_debug;
  6857. }
  6858. #endif
  6859. return ret;
  6860. #ifdef CONFIG_IWL3945_DEBUG
  6861. error_debug:
  6862. pci_unregister_driver(&iwl3945_driver);
  6863. #endif
  6864. error_register:
  6865. iwl3945_rate_control_unregister();
  6866. return ret;
  6867. }
  6868. static void __exit iwl3945_exit(void)
  6869. {
  6870. #ifdef CONFIG_IWL3945_DEBUG
  6871. driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6872. #endif
  6873. pci_unregister_driver(&iwl3945_driver);
  6874. iwl3945_rate_control_unregister();
  6875. }
  6876. MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
  6877. module_param_named(antenna, iwl3945_param_antenna, int, 0444);
  6878. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  6879. module_param_named(disable, iwl3945_param_disable, int, 0444);
  6880. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  6881. module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
  6882. MODULE_PARM_DESC(hwcrypto,
  6883. "using hardware crypto engine (default 0 [software])\n");
  6884. module_param_named(debug, iwl3945_param_debug, uint, 0444);
  6885. MODULE_PARM_DESC(debug, "debug output mask");
  6886. module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
  6887. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  6888. module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
  6889. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  6890. module_exit(iwl3945_exit);
  6891. module_init(iwl3945_init);