phy_common.c 9.8 KB

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  1. /*
  2. Broadcom B43 wireless driver
  3. Common PHY routines
  4. Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
  5. Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
  6. Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
  7. Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
  8. Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  9. This program is free software; you can redistribute it and/or modify
  10. it under the terms of the GNU General Public License as published by
  11. the Free Software Foundation; either version 2 of the License, or
  12. (at your option) any later version.
  13. This program is distributed in the hope that it will be useful,
  14. but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. GNU General Public License for more details.
  17. You should have received a copy of the GNU General Public License
  18. along with this program; see the file COPYING. If not, write to
  19. the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  20. Boston, MA 02110-1301, USA.
  21. */
  22. #include "phy_common.h"
  23. #include "phy_g.h"
  24. #include "phy_a.h"
  25. #include "phy_n.h"
  26. #include "phy_lp.h"
  27. #include "b43.h"
  28. #include "main.h"
  29. int b43_phy_allocate(struct b43_wldev *dev)
  30. {
  31. struct b43_phy *phy = &(dev->phy);
  32. int err;
  33. phy->ops = NULL;
  34. switch (phy->type) {
  35. case B43_PHYTYPE_A:
  36. phy->ops = &b43_phyops_a;
  37. break;
  38. case B43_PHYTYPE_G:
  39. phy->ops = &b43_phyops_g;
  40. break;
  41. case B43_PHYTYPE_N:
  42. #ifdef CONFIG_B43_NPHY
  43. phy->ops = &b43_phyops_n;
  44. #endif
  45. break;
  46. case B43_PHYTYPE_LP:
  47. #ifdef CONFIG_B43_PHY_LP
  48. phy->ops = &b43_phyops_lp;
  49. #endif
  50. break;
  51. }
  52. if (B43_WARN_ON(!phy->ops))
  53. return -ENODEV;
  54. err = phy->ops->allocate(dev);
  55. if (err)
  56. phy->ops = NULL;
  57. return err;
  58. }
  59. void b43_phy_free(struct b43_wldev *dev)
  60. {
  61. dev->phy.ops->free(dev);
  62. dev->phy.ops = NULL;
  63. }
  64. int b43_phy_init(struct b43_wldev *dev)
  65. {
  66. struct b43_phy *phy = &dev->phy;
  67. const struct b43_phy_operations *ops = phy->ops;
  68. int err;
  69. phy->channel = ops->get_default_chan(dev);
  70. ops->software_rfkill(dev, RFKILL_STATE_UNBLOCKED);
  71. err = ops->init(dev);
  72. if (err) {
  73. b43err(dev->wl, "PHY init failed\n");
  74. goto err_block_rf;
  75. }
  76. /* Make sure to switch hardware and firmware (SHM) to
  77. * the default channel. */
  78. err = b43_switch_channel(dev, ops->get_default_chan(dev));
  79. if (err) {
  80. b43err(dev->wl, "PHY init: Channel switch to default failed\n");
  81. goto err_phy_exit;
  82. }
  83. return 0;
  84. err_phy_exit:
  85. if (ops->exit)
  86. ops->exit(dev);
  87. err_block_rf:
  88. ops->software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
  89. return err;
  90. }
  91. void b43_phy_exit(struct b43_wldev *dev)
  92. {
  93. const struct b43_phy_operations *ops = dev->phy.ops;
  94. ops->software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
  95. if (ops->exit)
  96. ops->exit(dev);
  97. }
  98. bool b43_has_hardware_pctl(struct b43_wldev *dev)
  99. {
  100. if (!dev->phy.hardware_power_control)
  101. return 0;
  102. if (!dev->phy.ops->supports_hwpctl)
  103. return 0;
  104. return dev->phy.ops->supports_hwpctl(dev);
  105. }
  106. void b43_radio_lock(struct b43_wldev *dev)
  107. {
  108. u32 macctl;
  109. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  110. B43_WARN_ON(macctl & B43_MACCTL_RADIOLOCK);
  111. macctl |= B43_MACCTL_RADIOLOCK;
  112. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  113. /* Commit the write and wait for the device
  114. * to exit any radio register access. */
  115. b43_read32(dev, B43_MMIO_MACCTL);
  116. udelay(10);
  117. }
  118. void b43_radio_unlock(struct b43_wldev *dev)
  119. {
  120. u32 macctl;
  121. /* Commit any write */
  122. b43_read16(dev, B43_MMIO_PHY_VER);
  123. /* unlock */
  124. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  125. B43_WARN_ON(!(macctl & B43_MACCTL_RADIOLOCK));
  126. macctl &= ~B43_MACCTL_RADIOLOCK;
  127. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  128. }
  129. void b43_phy_lock(struct b43_wldev *dev)
  130. {
  131. #if B43_DEBUG
  132. B43_WARN_ON(dev->phy.phy_locked);
  133. dev->phy.phy_locked = 1;
  134. #endif
  135. B43_WARN_ON(dev->dev->id.revision < 3);
  136. if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
  137. b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
  138. }
  139. void b43_phy_unlock(struct b43_wldev *dev)
  140. {
  141. #if B43_DEBUG
  142. B43_WARN_ON(!dev->phy.phy_locked);
  143. dev->phy.phy_locked = 0;
  144. #endif
  145. B43_WARN_ON(dev->dev->id.revision < 3);
  146. if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
  147. b43_power_saving_ctl_bits(dev, 0);
  148. }
  149. static inline void assert_mac_suspended(struct b43_wldev *dev)
  150. {
  151. if (!B43_DEBUG)
  152. return;
  153. if ((b43_status(dev) >= B43_STAT_INITIALIZED) &&
  154. (dev->mac_suspended <= 0)) {
  155. b43dbg(dev->wl, "PHY/RADIO register access with "
  156. "enabled MAC.\n");
  157. dump_stack();
  158. }
  159. }
  160. u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
  161. {
  162. assert_mac_suspended(dev);
  163. return dev->phy.ops->radio_read(dev, reg);
  164. }
  165. void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
  166. {
  167. assert_mac_suspended(dev);
  168. dev->phy.ops->radio_write(dev, reg, value);
  169. }
  170. void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
  171. {
  172. b43_radio_write16(dev, offset,
  173. b43_radio_read16(dev, offset) & mask);
  174. }
  175. void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
  176. {
  177. b43_radio_write16(dev, offset,
  178. b43_radio_read16(dev, offset) | set);
  179. }
  180. void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
  181. {
  182. b43_radio_write16(dev, offset,
  183. (b43_radio_read16(dev, offset) & mask) | set);
  184. }
  185. u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
  186. {
  187. assert_mac_suspended(dev);
  188. return dev->phy.ops->phy_read(dev, reg);
  189. }
  190. void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
  191. {
  192. assert_mac_suspended(dev);
  193. dev->phy.ops->phy_write(dev, reg, value);
  194. }
  195. void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
  196. {
  197. b43_phy_write(dev, offset,
  198. b43_phy_read(dev, offset) & mask);
  199. }
  200. void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
  201. {
  202. b43_phy_write(dev, offset,
  203. b43_phy_read(dev, offset) | set);
  204. }
  205. void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
  206. {
  207. b43_phy_write(dev, offset,
  208. (b43_phy_read(dev, offset) & mask) | set);
  209. }
  210. int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
  211. {
  212. struct b43_phy *phy = &(dev->phy);
  213. u16 channelcookie, savedcookie;
  214. int err;
  215. if (new_channel == B43_DEFAULT_CHANNEL)
  216. new_channel = phy->ops->get_default_chan(dev);
  217. /* First we set the channel radio code to prevent the
  218. * firmware from sending ghost packets.
  219. */
  220. channelcookie = new_channel;
  221. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
  222. channelcookie |= 0x100;
  223. //FIXME set 40Mhz flag if required
  224. savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
  225. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
  226. /* Now try to switch the PHY hardware channel. */
  227. err = phy->ops->switch_channel(dev, new_channel);
  228. if (err)
  229. goto err_restore_cookie;
  230. dev->phy.channel = new_channel;
  231. /* Wait for the radio to tune to the channel and stabilize. */
  232. msleep(8);
  233. return 0;
  234. err_restore_cookie:
  235. b43_shm_write16(dev, B43_SHM_SHARED,
  236. B43_SHM_SH_CHAN, savedcookie);
  237. return err;
  238. }
  239. void b43_software_rfkill(struct b43_wldev *dev, enum rfkill_state state)
  240. {
  241. struct b43_phy *phy = &dev->phy;
  242. if (state == RFKILL_STATE_HARD_BLOCKED) {
  243. /* We cannot hardware-block the device */
  244. state = RFKILL_STATE_SOFT_BLOCKED;
  245. }
  246. b43_mac_suspend(dev);
  247. phy->ops->software_rfkill(dev, state);
  248. phy->radio_on = (state == RFKILL_STATE_UNBLOCKED);
  249. b43_mac_enable(dev);
  250. }
  251. /**
  252. * b43_phy_txpower_adjust_work - TX power workqueue.
  253. *
  254. * Workqueue for updating the TX power parameters in hardware.
  255. */
  256. void b43_phy_txpower_adjust_work(struct work_struct *work)
  257. {
  258. struct b43_wl *wl = container_of(work, struct b43_wl,
  259. txpower_adjust_work);
  260. struct b43_wldev *dev;
  261. mutex_lock(&wl->mutex);
  262. dev = wl->current_dev;
  263. if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
  264. dev->phy.ops->adjust_txpower(dev);
  265. mutex_unlock(&wl->mutex);
  266. }
  267. /* Called with wl->irq_lock locked */
  268. void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
  269. {
  270. struct b43_phy *phy = &dev->phy;
  271. unsigned long now = jiffies;
  272. enum b43_txpwr_result result;
  273. if (!(flags & B43_TXPWR_IGNORE_TIME)) {
  274. /* Check if it's time for a TXpower check. */
  275. if (time_before(now, phy->next_txpwr_check_time))
  276. return; /* Not yet */
  277. }
  278. /* The next check will be needed in two seconds, or later. */
  279. phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));
  280. if ((dev->dev->bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
  281. (dev->dev->bus->boardinfo.type == SSB_BOARD_BU4306))
  282. return; /* No software txpower adjustment needed */
  283. result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
  284. if (result == B43_TXPWR_RES_DONE)
  285. return; /* We are done. */
  286. B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
  287. B43_WARN_ON(phy->ops->adjust_txpower == NULL);
  288. /* We must adjust the transmission power in hardware.
  289. * Schedule b43_phy_txpower_adjust_work(). */
  290. queue_work(dev->wl->hw->workqueue, &dev->wl->txpower_adjust_work);
  291. }
  292. int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
  293. {
  294. const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
  295. unsigned int a, b, c, d;
  296. unsigned int average;
  297. u32 tmp;
  298. tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
  299. a = tmp & 0xFF;
  300. b = (tmp >> 8) & 0xFF;
  301. c = (tmp >> 16) & 0xFF;
  302. d = (tmp >> 24) & 0xFF;
  303. if (a == 0 || a == B43_TSSI_MAX ||
  304. b == 0 || b == B43_TSSI_MAX ||
  305. c == 0 || c == B43_TSSI_MAX ||
  306. d == 0 || d == B43_TSSI_MAX)
  307. return -ENOENT;
  308. /* The values are OK. Clear them. */
  309. tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) |
  310. (B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24);
  311. b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);
  312. if (is_ofdm) {
  313. a = (a + 32) & 0x3F;
  314. b = (b + 32) & 0x3F;
  315. c = (c + 32) & 0x3F;
  316. d = (d + 32) & 0x3F;
  317. }
  318. /* Get the average of the values with 0.5 added to each value. */
  319. average = (a + b + c + d + 2) / 4;
  320. if (is_ofdm) {
  321. /* Adjust for CCK-boost */
  322. if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO)
  323. & B43_HF_CCKBOOST)
  324. average = (average >= 13) ? (average - 13) : 0;
  325. }
  326. return average;
  327. }
  328. void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
  329. {
  330. b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
  331. }