attach.c 10 KB

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  1. /*
  2. * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
  3. * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
  4. *
  5. * Permission to use, copy, modify, and distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. *
  17. */
  18. /*************************************\
  19. * Attach/Detach Functions and helpers *
  20. \*************************************/
  21. #include <linux/pci.h>
  22. #include "ath5k.h"
  23. #include "reg.h"
  24. #include "debug.h"
  25. #include "base.h"
  26. /**
  27. * ath5k_hw_post - Power On Self Test helper function
  28. *
  29. * @ah: The &struct ath5k_hw
  30. */
  31. static int ath5k_hw_post(struct ath5k_hw *ah)
  32. {
  33. int i, c;
  34. u16 cur_reg;
  35. u16 regs[2] = {AR5K_STA_ID0, AR5K_PHY(8)};
  36. u32 var_pattern;
  37. u32 static_pattern[4] = {
  38. 0x55555555, 0xaaaaaaaa,
  39. 0x66666666, 0x99999999
  40. };
  41. u32 init_val;
  42. u32 cur_val;
  43. for (c = 0; c < 2; c++) {
  44. cur_reg = regs[c];
  45. /* Save previous value */
  46. init_val = ath5k_hw_reg_read(ah, cur_reg);
  47. for (i = 0; i < 256; i++) {
  48. var_pattern = i << 16 | i;
  49. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  50. cur_val = ath5k_hw_reg_read(ah, cur_reg);
  51. if (cur_val != var_pattern) {
  52. ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
  53. return -EAGAIN;
  54. }
  55. /* Found on ndiswrapper dumps */
  56. var_pattern = 0x0039080f;
  57. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  58. }
  59. for (i = 0; i < 4; i++) {
  60. var_pattern = static_pattern[i];
  61. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  62. cur_val = ath5k_hw_reg_read(ah, cur_reg);
  63. if (cur_val != var_pattern) {
  64. ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
  65. return -EAGAIN;
  66. }
  67. /* Found on ndiswrapper dumps */
  68. var_pattern = 0x003b080f;
  69. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  70. }
  71. /* Restore previous value */
  72. ath5k_hw_reg_write(ah, init_val, cur_reg);
  73. }
  74. return 0;
  75. }
  76. /**
  77. * ath5k_hw_attach - Check if hw is supported and init the needed structs
  78. *
  79. * @sc: The &struct ath5k_softc we got from the driver's attach function
  80. * @mac_version: The mac version id (check out ath5k.h) based on pci id
  81. *
  82. * Check if the device is supported, perform a POST and initialize the needed
  83. * structs. Returns -ENOMEM if we don't have memory for the needed structs,
  84. * -ENODEV if the device is not supported or prints an error msg if something
  85. * else went wrong.
  86. */
  87. struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
  88. {
  89. struct ath5k_hw *ah;
  90. struct pci_dev *pdev = sc->pdev;
  91. u8 mac[ETH_ALEN] = {};
  92. int ret;
  93. u32 srev;
  94. /*If we passed the test malloc a ath5k_hw struct*/
  95. ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
  96. if (ah == NULL) {
  97. ret = -ENOMEM;
  98. ATH5K_ERR(sc, "out of memory\n");
  99. goto err;
  100. }
  101. ah->ah_sc = sc;
  102. ah->ah_iobase = sc->iobase;
  103. /*
  104. * HW information
  105. */
  106. ah->ah_op_mode = NL80211_IFTYPE_STATION;
  107. ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
  108. ah->ah_turbo = false;
  109. ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
  110. ah->ah_imr = 0;
  111. ah->ah_atim_window = 0;
  112. ah->ah_aifs = AR5K_TUNE_AIFS;
  113. ah->ah_cw_min = AR5K_TUNE_CWMIN;
  114. ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
  115. ah->ah_software_retry = false;
  116. ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
  117. /*
  118. * Set the mac version based on the pci id
  119. */
  120. ah->ah_version = mac_version;
  121. /*Fill the ath5k_hw struct with the needed functions*/
  122. ret = ath5k_hw_init_desc_functions(ah);
  123. if (ret)
  124. goto err_free;
  125. /* Bring device out of sleep and reset it's units */
  126. ret = ath5k_hw_nic_wakeup(ah, CHANNEL_B, true);
  127. if (ret)
  128. goto err_free;
  129. /* Get MAC, PHY and RADIO revisions */
  130. srev = ath5k_hw_reg_read(ah, AR5K_SREV);
  131. ah->ah_mac_srev = srev;
  132. ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
  133. ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
  134. ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
  135. 0xffffffff;
  136. ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
  137. CHANNEL_5GHZ);
  138. ah->ah_phy = AR5K_PHY(0);
  139. /* Try to identify radio chip based on it's srev */
  140. switch (ah->ah_radio_5ghz_revision & 0xf0) {
  141. case AR5K_SREV_RAD_5111:
  142. ah->ah_radio = AR5K_RF5111;
  143. ah->ah_single_chip = false;
  144. ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
  145. CHANNEL_2GHZ);
  146. ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111;
  147. break;
  148. case AR5K_SREV_RAD_5112:
  149. case AR5K_SREV_RAD_2112:
  150. ah->ah_radio = AR5K_RF5112;
  151. ah->ah_single_chip = false;
  152. ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
  153. CHANNEL_2GHZ);
  154. ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
  155. break;
  156. case AR5K_SREV_RAD_2413:
  157. ah->ah_radio = AR5K_RF2413;
  158. ah->ah_single_chip = true;
  159. ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
  160. break;
  161. case AR5K_SREV_RAD_5413:
  162. ah->ah_radio = AR5K_RF5413;
  163. ah->ah_single_chip = true;
  164. ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
  165. break;
  166. case AR5K_SREV_RAD_2316:
  167. ah->ah_radio = AR5K_RF2316;
  168. ah->ah_single_chip = true;
  169. ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2316;
  170. break;
  171. case AR5K_SREV_RAD_2317:
  172. ah->ah_radio = AR5K_RF2317;
  173. ah->ah_single_chip = true;
  174. ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2317;
  175. break;
  176. case AR5K_SREV_RAD_5424:
  177. if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
  178. ah->ah_mac_version == AR5K_SREV_AR2417){
  179. ah->ah_radio = AR5K_RF2425;
  180. ah->ah_single_chip = true;
  181. ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425;
  182. } else {
  183. ah->ah_radio = AR5K_RF5413;
  184. ah->ah_single_chip = true;
  185. ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
  186. }
  187. break;
  188. default:
  189. /* Identify radio based on mac/phy srev */
  190. if (ah->ah_version == AR5K_AR5210) {
  191. ah->ah_radio = AR5K_RF5110;
  192. ah->ah_single_chip = false;
  193. } else if (ah->ah_version == AR5K_AR5211) {
  194. ah->ah_radio = AR5K_RF5111;
  195. ah->ah_single_chip = false;
  196. ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
  197. CHANNEL_2GHZ);
  198. } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
  199. ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
  200. ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
  201. ah->ah_radio = AR5K_RF2425;
  202. ah->ah_single_chip = true;
  203. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
  204. ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425;
  205. } else if (srev == AR5K_SREV_AR5213A &&
  206. ah->ah_phy_revision == AR5K_SREV_PHY_2112B) {
  207. ah->ah_radio = AR5K_RF5112;
  208. ah->ah_single_chip = false;
  209. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2112B;
  210. } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
  211. ah->ah_radio = AR5K_RF2316;
  212. ah->ah_single_chip = true;
  213. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
  214. ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2316;
  215. } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
  216. ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
  217. ah->ah_radio = AR5K_RF5413;
  218. ah->ah_single_chip = true;
  219. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
  220. ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
  221. } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
  222. ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
  223. ah->ah_radio = AR5K_RF2413;
  224. ah->ah_single_chip = true;
  225. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
  226. ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
  227. } else {
  228. ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
  229. ret = -ENODEV;
  230. goto err_free;
  231. }
  232. }
  233. /* Return on unsuported chips (unsupported eeprom etc) */
  234. if ((srev >= AR5K_SREV_AR5416) &&
  235. (srev < AR5K_SREV_AR2425)) {
  236. ATH5K_ERR(sc, "Device not yet supported.\n");
  237. ret = -ENODEV;
  238. goto err_free;
  239. }
  240. /*
  241. * Write PCI-E power save settings
  242. */
  243. if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
  244. ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
  245. ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
  246. /* Shut off RX when elecidle is asserted */
  247. ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
  248. ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
  249. /* TODO: EEPROM work */
  250. ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
  251. /* Shut off PLL and CLKREQ active in L1 */
  252. ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
  253. /* Preserce other settings */
  254. ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
  255. ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
  256. ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
  257. /* Reset SERDES to load new settings */
  258. ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
  259. mdelay(1);
  260. }
  261. /*
  262. * POST
  263. */
  264. ret = ath5k_hw_post(ah);
  265. if (ret)
  266. goto err_free;
  267. /* Enable pci core retry fix on Hainan (5213A) and later chips */
  268. if (srev >= AR5K_SREV_AR5213A)
  269. ath5k_hw_reg_write(ah, AR5K_PCICFG_RETRY_FIX, AR5K_PCICFG);
  270. /*
  271. * Get card capabilities, calibration values etc
  272. * TODO: EEPROM work
  273. */
  274. ret = ath5k_eeprom_init(ah);
  275. if (ret) {
  276. ATH5K_ERR(sc, "unable to init EEPROM\n");
  277. goto err_free;
  278. }
  279. /* Get misc capabilities */
  280. ret = ath5k_hw_set_capabilities(ah);
  281. if (ret) {
  282. ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
  283. sc->pdev->device);
  284. goto err_free;
  285. }
  286. if (srev >= AR5K_SREV_AR2414) {
  287. ah->ah_combined_mic = true;
  288. AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
  289. AR5K_MISC_MODE_COMBINED_MIC);
  290. }
  291. /* MAC address is cleared until add_interface */
  292. ath5k_hw_set_lladdr(ah, mac);
  293. /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
  294. memset(ah->ah_bssid, 0xff, ETH_ALEN);
  295. ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
  296. ath5k_hw_set_opmode(ah);
  297. ath5k_hw_set_rfgain_opt(ah);
  298. return ah;
  299. err_free:
  300. kfree(ah);
  301. err:
  302. return ERR_PTR(ret);
  303. }
  304. /**
  305. * ath5k_hw_detach - Free the ath5k_hw struct
  306. *
  307. * @ah: The &struct ath5k_hw
  308. */
  309. void ath5k_hw_detach(struct ath5k_hw *ah)
  310. {
  311. ATH5K_TRACE(ah->ah_sc);
  312. __set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
  313. if (ah->ah_rf_banks != NULL)
  314. kfree(ah->ah_rf_banks);
  315. /* assume interrupts are down */
  316. kfree(ah);
  317. }