lmc_main.c 62 KB

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  1. /*
  2. * Copyright (c) 1997-2000 LAN Media Corporation (LMC)
  3. * All rights reserved. www.lanmedia.com
  4. * Generic HDLC port Copyright (C) 2008 Krzysztof Halasa <khc@pm.waw.pl>
  5. *
  6. * This code is written by:
  7. * Andrew Stanley-Jones (asj@cban.com)
  8. * Rob Braun (bbraun@vix.com),
  9. * Michael Graff (explorer@vix.com) and
  10. * Matt Thomas (matt@3am-software.com).
  11. *
  12. * With Help By:
  13. * David Boggs
  14. * Ron Crane
  15. * Alan Cox
  16. *
  17. * This software may be used and distributed according to the terms
  18. * of the GNU General Public License version 2, incorporated herein by reference.
  19. *
  20. * Driver for the LanMedia LMC5200, LMC5245, LMC1000, LMC1200 cards.
  21. *
  22. * To control link specific options lmcctl is required.
  23. * It can be obtained from ftp.lanmedia.com.
  24. *
  25. * Linux driver notes:
  26. * Linux uses the device struct lmc_private to pass private information
  27. * arround.
  28. *
  29. * The initialization portion of this driver (the lmc_reset() and the
  30. * lmc_dec_reset() functions, as well as the led controls and the
  31. * lmc_initcsrs() functions.
  32. *
  33. * The watchdog function runs every second and checks to see if
  34. * we still have link, and that the timing source is what we expected
  35. * it to be. If link is lost, the interface is marked down, and
  36. * we no longer can transmit.
  37. *
  38. */
  39. #include <linux/kernel.h>
  40. #include <linux/module.h>
  41. #include <linux/string.h>
  42. #include <linux/timer.h>
  43. #include <linux/ptrace.h>
  44. #include <linux/errno.h>
  45. #include <linux/ioport.h>
  46. #include <linux/slab.h>
  47. #include <linux/interrupt.h>
  48. #include <linux/pci.h>
  49. #include <linux/delay.h>
  50. #include <linux/hdlc.h>
  51. #include <linux/init.h>
  52. #include <linux/in.h>
  53. #include <linux/if_arp.h>
  54. #include <linux/netdevice.h>
  55. #include <linux/etherdevice.h>
  56. #include <linux/skbuff.h>
  57. #include <linux/inet.h>
  58. #include <linux/bitops.h>
  59. #include <asm/processor.h> /* Processor type for cache alignment. */
  60. #include <asm/io.h>
  61. #include <asm/dma.h>
  62. #include <asm/uaccess.h>
  63. //#include <asm/spinlock.h>
  64. #define DRIVER_MAJOR_VERSION 1
  65. #define DRIVER_MINOR_VERSION 34
  66. #define DRIVER_SUB_VERSION 0
  67. #define DRIVER_VERSION ((DRIVER_MAJOR_VERSION << 8) + DRIVER_MINOR_VERSION)
  68. #include "lmc.h"
  69. #include "lmc_var.h"
  70. #include "lmc_ioctl.h"
  71. #include "lmc_debug.h"
  72. #include "lmc_proto.h"
  73. static int LMC_PKT_BUF_SZ = 1542;
  74. static struct pci_device_id lmc_pci_tbl[] = {
  75. { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
  76. PCI_VENDOR_ID_LMC, PCI_ANY_ID },
  77. { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
  78. PCI_ANY_ID, PCI_VENDOR_ID_LMC },
  79. { 0 }
  80. };
  81. MODULE_DEVICE_TABLE(pci, lmc_pci_tbl);
  82. MODULE_LICENSE("GPL v2");
  83. static int lmc_start_xmit(struct sk_buff *skb, struct net_device *dev);
  84. static int lmc_rx (struct net_device *dev);
  85. static int lmc_open(struct net_device *dev);
  86. static int lmc_close(struct net_device *dev);
  87. static struct net_device_stats *lmc_get_stats(struct net_device *dev);
  88. static irqreturn_t lmc_interrupt(int irq, void *dev_instance);
  89. static void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, size_t csr_size);
  90. static void lmc_softreset(lmc_softc_t * const);
  91. static void lmc_running_reset(struct net_device *dev);
  92. static int lmc_ifdown(struct net_device * const);
  93. static void lmc_watchdog(unsigned long data);
  94. static void lmc_reset(lmc_softc_t * const sc);
  95. static void lmc_dec_reset(lmc_softc_t * const sc);
  96. static void lmc_driver_timeout(struct net_device *dev);
  97. /*
  98. * linux reserves 16 device specific IOCTLs. We call them
  99. * LMCIOC* to control various bits of our world.
  100. */
  101. int lmc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) /*fold00*/
  102. {
  103. lmc_softc_t *sc = dev_to_sc(dev);
  104. lmc_ctl_t ctl;
  105. int ret = -EOPNOTSUPP;
  106. u16 regVal;
  107. unsigned long flags;
  108. lmc_trace(dev, "lmc_ioctl in");
  109. /*
  110. * Most functions mess with the structure
  111. * Disable interrupts while we do the polling
  112. */
  113. switch (cmd) {
  114. /*
  115. * Return current driver state. Since we keep this up
  116. * To date internally, just copy this out to the user.
  117. */
  118. case LMCIOCGINFO: /*fold01*/
  119. if (copy_to_user(ifr->ifr_data, &sc->ictl, sizeof(lmc_ctl_t)))
  120. ret = -EFAULT;
  121. else
  122. ret = 0;
  123. break;
  124. case LMCIOCSINFO: /*fold01*/
  125. if (!capable(CAP_NET_ADMIN)) {
  126. ret = -EPERM;
  127. break;
  128. }
  129. if(dev->flags & IFF_UP){
  130. ret = -EBUSY;
  131. break;
  132. }
  133. if (copy_from_user(&ctl, ifr->ifr_data, sizeof(lmc_ctl_t))) {
  134. ret = -EFAULT;
  135. break;
  136. }
  137. spin_lock_irqsave(&sc->lmc_lock, flags);
  138. sc->lmc_media->set_status (sc, &ctl);
  139. if(ctl.crc_length != sc->ictl.crc_length) {
  140. sc->lmc_media->set_crc_length(sc, ctl.crc_length);
  141. if (sc->ictl.crc_length == LMC_CTL_CRC_LENGTH_16)
  142. sc->TxDescriptControlInit |= LMC_TDES_ADD_CRC_DISABLE;
  143. else
  144. sc->TxDescriptControlInit &= ~LMC_TDES_ADD_CRC_DISABLE;
  145. }
  146. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  147. ret = 0;
  148. break;
  149. case LMCIOCIFTYPE: /*fold01*/
  150. {
  151. u16 old_type = sc->if_type;
  152. u16 new_type;
  153. if (!capable(CAP_NET_ADMIN)) {
  154. ret = -EPERM;
  155. break;
  156. }
  157. if (copy_from_user(&new_type, ifr->ifr_data, sizeof(u16))) {
  158. ret = -EFAULT;
  159. break;
  160. }
  161. if (new_type == old_type)
  162. {
  163. ret = 0 ;
  164. break; /* no change */
  165. }
  166. spin_lock_irqsave(&sc->lmc_lock, flags);
  167. lmc_proto_close(sc);
  168. sc->if_type = new_type;
  169. lmc_proto_attach(sc);
  170. ret = lmc_proto_open(sc);
  171. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  172. break;
  173. }
  174. case LMCIOCGETXINFO: /*fold01*/
  175. spin_lock_irqsave(&sc->lmc_lock, flags);
  176. sc->lmc_xinfo.Magic0 = 0xBEEFCAFE;
  177. sc->lmc_xinfo.PciCardType = sc->lmc_cardtype;
  178. sc->lmc_xinfo.PciSlotNumber = 0;
  179. sc->lmc_xinfo.DriverMajorVersion = DRIVER_MAJOR_VERSION;
  180. sc->lmc_xinfo.DriverMinorVersion = DRIVER_MINOR_VERSION;
  181. sc->lmc_xinfo.DriverSubVersion = DRIVER_SUB_VERSION;
  182. sc->lmc_xinfo.XilinxRevisionNumber =
  183. lmc_mii_readreg (sc, 0, 3) & 0xf;
  184. sc->lmc_xinfo.MaxFrameSize = LMC_PKT_BUF_SZ;
  185. sc->lmc_xinfo.link_status = sc->lmc_media->get_link_status (sc);
  186. sc->lmc_xinfo.mii_reg16 = lmc_mii_readreg (sc, 0, 16);
  187. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  188. sc->lmc_xinfo.Magic1 = 0xDEADBEEF;
  189. if (copy_to_user(ifr->ifr_data, &sc->lmc_xinfo,
  190. sizeof(struct lmc_xinfo)))
  191. ret = -EFAULT;
  192. else
  193. ret = 0;
  194. break;
  195. case LMCIOCGETLMCSTATS:
  196. spin_lock_irqsave(&sc->lmc_lock, flags);
  197. if (sc->lmc_cardtype == LMC_CARDTYPE_T1) {
  198. lmc_mii_writereg(sc, 0, 17, T1FRAMER_FERR_LSB);
  199. sc->extra_stats.framingBitErrorCount +=
  200. lmc_mii_readreg(sc, 0, 18) & 0xff;
  201. lmc_mii_writereg(sc, 0, 17, T1FRAMER_FERR_MSB);
  202. sc->extra_stats.framingBitErrorCount +=
  203. (lmc_mii_readreg(sc, 0, 18) & 0xff) << 8;
  204. lmc_mii_writereg(sc, 0, 17, T1FRAMER_LCV_LSB);
  205. sc->extra_stats.lineCodeViolationCount +=
  206. lmc_mii_readreg(sc, 0, 18) & 0xff;
  207. lmc_mii_writereg(sc, 0, 17, T1FRAMER_LCV_MSB);
  208. sc->extra_stats.lineCodeViolationCount +=
  209. (lmc_mii_readreg(sc, 0, 18) & 0xff) << 8;
  210. lmc_mii_writereg(sc, 0, 17, T1FRAMER_AERR);
  211. regVal = lmc_mii_readreg(sc, 0, 18) & 0xff;
  212. sc->extra_stats.lossOfFrameCount +=
  213. (regVal & T1FRAMER_LOF_MASK) >> 4;
  214. sc->extra_stats.changeOfFrameAlignmentCount +=
  215. (regVal & T1FRAMER_COFA_MASK) >> 2;
  216. sc->extra_stats.severelyErroredFrameCount +=
  217. regVal & T1FRAMER_SEF_MASK;
  218. }
  219. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  220. if (copy_to_user(ifr->ifr_data, &sc->lmc_device->stats,
  221. sizeof(sc->lmc_device->stats)) ||
  222. copy_to_user(ifr->ifr_data + sizeof(sc->lmc_device->stats),
  223. &sc->extra_stats, sizeof(sc->extra_stats)))
  224. ret = -EFAULT;
  225. else
  226. ret = 0;
  227. break;
  228. case LMCIOCCLEARLMCSTATS:
  229. if (!capable(CAP_NET_ADMIN)) {
  230. ret = -EPERM;
  231. break;
  232. }
  233. spin_lock_irqsave(&sc->lmc_lock, flags);
  234. memset(&sc->lmc_device->stats, 0, sizeof(sc->lmc_device->stats));
  235. memset(&sc->extra_stats, 0, sizeof(sc->extra_stats));
  236. sc->extra_stats.check = STATCHECK;
  237. sc->extra_stats.version_size = (DRIVER_VERSION << 16) +
  238. sizeof(sc->lmc_device->stats) + sizeof(sc->extra_stats);
  239. sc->extra_stats.lmc_cardtype = sc->lmc_cardtype;
  240. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  241. ret = 0;
  242. break;
  243. case LMCIOCSETCIRCUIT: /*fold01*/
  244. if (!capable(CAP_NET_ADMIN)){
  245. ret = -EPERM;
  246. break;
  247. }
  248. if(dev->flags & IFF_UP){
  249. ret = -EBUSY;
  250. break;
  251. }
  252. if (copy_from_user(&ctl, ifr->ifr_data, sizeof(lmc_ctl_t))) {
  253. ret = -EFAULT;
  254. break;
  255. }
  256. spin_lock_irqsave(&sc->lmc_lock, flags);
  257. sc->lmc_media->set_circuit_type(sc, ctl.circuit_type);
  258. sc->ictl.circuit_type = ctl.circuit_type;
  259. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  260. ret = 0;
  261. break;
  262. case LMCIOCRESET: /*fold01*/
  263. if (!capable(CAP_NET_ADMIN)){
  264. ret = -EPERM;
  265. break;
  266. }
  267. spin_lock_irqsave(&sc->lmc_lock, flags);
  268. /* Reset driver and bring back to current state */
  269. printk (" REG16 before reset +%04x\n", lmc_mii_readreg (sc, 0, 16));
  270. lmc_running_reset (dev);
  271. printk (" REG16 after reset +%04x\n", lmc_mii_readreg (sc, 0, 16));
  272. LMC_EVENT_LOG(LMC_EVENT_FORCEDRESET, LMC_CSR_READ (sc, csr_status), lmc_mii_readreg (sc, 0, 16));
  273. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  274. ret = 0;
  275. break;
  276. #ifdef DEBUG
  277. case LMCIOCDUMPEVENTLOG:
  278. if (copy_to_user(ifr->ifr_data, &lmcEventLogIndex, sizeof(u32))) {
  279. ret = -EFAULT;
  280. break;
  281. }
  282. if (copy_to_user(ifr->ifr_data + sizeof(u32), lmcEventLogBuf,
  283. sizeof(lmcEventLogBuf)))
  284. ret = -EFAULT;
  285. else
  286. ret = 0;
  287. break;
  288. #endif /* end ifdef _DBG_EVENTLOG */
  289. case LMCIOCT1CONTROL: /*fold01*/
  290. if (sc->lmc_cardtype != LMC_CARDTYPE_T1){
  291. ret = -EOPNOTSUPP;
  292. break;
  293. }
  294. break;
  295. case LMCIOCXILINX: /*fold01*/
  296. {
  297. struct lmc_xilinx_control xc; /*fold02*/
  298. if (!capable(CAP_NET_ADMIN)){
  299. ret = -EPERM;
  300. break;
  301. }
  302. /*
  303. * Stop the xwitter whlie we restart the hardware
  304. */
  305. netif_stop_queue(dev);
  306. if (copy_from_user(&xc, ifr->ifr_data, sizeof(struct lmc_xilinx_control))) {
  307. ret = -EFAULT;
  308. break;
  309. }
  310. switch(xc.command){
  311. case lmc_xilinx_reset: /*fold02*/
  312. {
  313. u16 mii;
  314. spin_lock_irqsave(&sc->lmc_lock, flags);
  315. mii = lmc_mii_readreg (sc, 0, 16);
  316. /*
  317. * Make all of them 0 and make input
  318. */
  319. lmc_gpio_mkinput(sc, 0xff);
  320. /*
  321. * make the reset output
  322. */
  323. lmc_gpio_mkoutput(sc, LMC_GEP_RESET);
  324. /*
  325. * RESET low to force configuration. This also forces
  326. * the transmitter clock to be internal, but we expect to reset
  327. * that later anyway.
  328. */
  329. sc->lmc_gpio &= ~LMC_GEP_RESET;
  330. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  331. /*
  332. * hold for more than 10 microseconds
  333. */
  334. udelay(50);
  335. sc->lmc_gpio |= LMC_GEP_RESET;
  336. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  337. /*
  338. * stop driving Xilinx-related signals
  339. */
  340. lmc_gpio_mkinput(sc, 0xff);
  341. /* Reset the frammer hardware */
  342. sc->lmc_media->set_link_status (sc, 1);
  343. sc->lmc_media->set_status (sc, NULL);
  344. // lmc_softreset(sc);
  345. {
  346. int i;
  347. for(i = 0; i < 5; i++){
  348. lmc_led_on(sc, LMC_DS3_LED0);
  349. mdelay(100);
  350. lmc_led_off(sc, LMC_DS3_LED0);
  351. lmc_led_on(sc, LMC_DS3_LED1);
  352. mdelay(100);
  353. lmc_led_off(sc, LMC_DS3_LED1);
  354. lmc_led_on(sc, LMC_DS3_LED3);
  355. mdelay(100);
  356. lmc_led_off(sc, LMC_DS3_LED3);
  357. lmc_led_on(sc, LMC_DS3_LED2);
  358. mdelay(100);
  359. lmc_led_off(sc, LMC_DS3_LED2);
  360. }
  361. }
  362. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  363. ret = 0x0;
  364. }
  365. break;
  366. case lmc_xilinx_load_prom: /*fold02*/
  367. {
  368. u16 mii;
  369. int timeout = 500000;
  370. spin_lock_irqsave(&sc->lmc_lock, flags);
  371. mii = lmc_mii_readreg (sc, 0, 16);
  372. /*
  373. * Make all of them 0 and make input
  374. */
  375. lmc_gpio_mkinput(sc, 0xff);
  376. /*
  377. * make the reset output
  378. */
  379. lmc_gpio_mkoutput(sc, LMC_GEP_DP | LMC_GEP_RESET);
  380. /*
  381. * RESET low to force configuration. This also forces
  382. * the transmitter clock to be internal, but we expect to reset
  383. * that later anyway.
  384. */
  385. sc->lmc_gpio &= ~(LMC_GEP_RESET | LMC_GEP_DP);
  386. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  387. /*
  388. * hold for more than 10 microseconds
  389. */
  390. udelay(50);
  391. sc->lmc_gpio |= LMC_GEP_DP | LMC_GEP_RESET;
  392. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  393. /*
  394. * busy wait for the chip to reset
  395. */
  396. while( (LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0 &&
  397. (timeout-- > 0))
  398. cpu_relax();
  399. /*
  400. * stop driving Xilinx-related signals
  401. */
  402. lmc_gpio_mkinput(sc, 0xff);
  403. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  404. ret = 0x0;
  405. break;
  406. }
  407. case lmc_xilinx_load: /*fold02*/
  408. {
  409. char *data;
  410. int pos;
  411. int timeout = 500000;
  412. if (!xc.data) {
  413. ret = -EINVAL;
  414. break;
  415. }
  416. data = kmalloc(xc.len, GFP_KERNEL);
  417. if (!data) {
  418. printk(KERN_WARNING "%s: Failed to allocate memory for copy\n", dev->name);
  419. ret = -ENOMEM;
  420. break;
  421. }
  422. if(copy_from_user(data, xc.data, xc.len))
  423. {
  424. kfree(data);
  425. ret = -ENOMEM;
  426. break;
  427. }
  428. printk("%s: Starting load of data Len: %d at 0x%p == 0x%p\n", dev->name, xc.len, xc.data, data);
  429. spin_lock_irqsave(&sc->lmc_lock, flags);
  430. lmc_gpio_mkinput(sc, 0xff);
  431. /*
  432. * Clear the Xilinx and start prgramming from the DEC
  433. */
  434. /*
  435. * Set ouput as:
  436. * Reset: 0 (active)
  437. * DP: 0 (active)
  438. * Mode: 1
  439. *
  440. */
  441. sc->lmc_gpio = 0x00;
  442. sc->lmc_gpio &= ~LMC_GEP_DP;
  443. sc->lmc_gpio &= ~LMC_GEP_RESET;
  444. sc->lmc_gpio |= LMC_GEP_MODE;
  445. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  446. lmc_gpio_mkoutput(sc, LMC_GEP_MODE | LMC_GEP_DP | LMC_GEP_RESET);
  447. /*
  448. * Wait at least 10 us 20 to be safe
  449. */
  450. udelay(50);
  451. /*
  452. * Clear reset and activate programming lines
  453. * Reset: Input
  454. * DP: Input
  455. * Clock: Output
  456. * Data: Output
  457. * Mode: Output
  458. */
  459. lmc_gpio_mkinput(sc, LMC_GEP_DP | LMC_GEP_RESET);
  460. /*
  461. * Set LOAD, DATA, Clock to 1
  462. */
  463. sc->lmc_gpio = 0x00;
  464. sc->lmc_gpio |= LMC_GEP_MODE;
  465. sc->lmc_gpio |= LMC_GEP_DATA;
  466. sc->lmc_gpio |= LMC_GEP_CLK;
  467. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  468. lmc_gpio_mkoutput(sc, LMC_GEP_DATA | LMC_GEP_CLK | LMC_GEP_MODE );
  469. /*
  470. * busy wait for the chip to reset
  471. */
  472. while( (LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0 &&
  473. (timeout-- > 0))
  474. cpu_relax();
  475. printk(KERN_DEBUG "%s: Waited %d for the Xilinx to clear it's memory\n", dev->name, 500000-timeout);
  476. for(pos = 0; pos < xc.len; pos++){
  477. switch(data[pos]){
  478. case 0:
  479. sc->lmc_gpio &= ~LMC_GEP_DATA; /* Data is 0 */
  480. break;
  481. case 1:
  482. sc->lmc_gpio |= LMC_GEP_DATA; /* Data is 1 */
  483. break;
  484. default:
  485. printk(KERN_WARNING "%s Bad data in xilinx programming data at %d, got %d wanted 0 or 1\n", dev->name, pos, data[pos]);
  486. sc->lmc_gpio |= LMC_GEP_DATA; /* Assume it's 1 */
  487. }
  488. sc->lmc_gpio &= ~LMC_GEP_CLK; /* Clock to zero */
  489. sc->lmc_gpio |= LMC_GEP_MODE;
  490. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  491. udelay(1);
  492. sc->lmc_gpio |= LMC_GEP_CLK; /* Put the clack back to one */
  493. sc->lmc_gpio |= LMC_GEP_MODE;
  494. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  495. udelay(1);
  496. }
  497. if((LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0){
  498. printk(KERN_WARNING "%s: Reprogramming FAILED. Needs to be reprogrammed. (corrupted data)\n", dev->name);
  499. }
  500. else if((LMC_CSR_READ(sc, csr_gp) & LMC_GEP_DP) == 0){
  501. printk(KERN_WARNING "%s: Reprogramming FAILED. Needs to be reprogrammed. (done)\n", dev->name);
  502. }
  503. else {
  504. printk(KERN_DEBUG "%s: Done reprogramming Xilinx, %d bits, good luck!\n", dev->name, pos);
  505. }
  506. lmc_gpio_mkinput(sc, 0xff);
  507. sc->lmc_miireg16 |= LMC_MII16_FIFO_RESET;
  508. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  509. sc->lmc_miireg16 &= ~LMC_MII16_FIFO_RESET;
  510. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  511. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  512. kfree(data);
  513. ret = 0;
  514. break;
  515. }
  516. default: /*fold02*/
  517. ret = -EBADE;
  518. break;
  519. }
  520. netif_wake_queue(dev);
  521. sc->lmc_txfull = 0;
  522. }
  523. break;
  524. default: /*fold01*/
  525. /* If we don't know what to do, give the protocol a shot. */
  526. ret = lmc_proto_ioctl (sc, ifr, cmd);
  527. break;
  528. }
  529. lmc_trace(dev, "lmc_ioctl out");
  530. return ret;
  531. }
  532. /* the watchdog process that cruises around */
  533. static void lmc_watchdog (unsigned long data) /*fold00*/
  534. {
  535. struct net_device *dev = (struct net_device *)data;
  536. lmc_softc_t *sc = dev_to_sc(dev);
  537. int link_status;
  538. u32 ticks;
  539. unsigned long flags;
  540. lmc_trace(dev, "lmc_watchdog in");
  541. spin_lock_irqsave(&sc->lmc_lock, flags);
  542. if(sc->check != 0xBEAFCAFE){
  543. printk("LMC: Corrupt net_device struct, breaking out\n");
  544. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  545. return;
  546. }
  547. /* Make sure the tx jabber and rx watchdog are off,
  548. * and the transmit and receive processes are running.
  549. */
  550. LMC_CSR_WRITE (sc, csr_15, 0x00000011);
  551. sc->lmc_cmdmode |= TULIP_CMD_TXRUN | TULIP_CMD_RXRUN;
  552. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  553. if (sc->lmc_ok == 0)
  554. goto kick_timer;
  555. LMC_EVENT_LOG(LMC_EVENT_WATCHDOG, LMC_CSR_READ (sc, csr_status), lmc_mii_readreg (sc, 0, 16));
  556. /* --- begin time out check -----------------------------------
  557. * check for a transmit interrupt timeout
  558. * Has the packet xmt vs xmt serviced threshold been exceeded */
  559. if (sc->lmc_taint_tx == sc->lastlmc_taint_tx &&
  560. sc->lmc_device->stats.tx_packets > sc->lasttx_packets &&
  561. sc->tx_TimeoutInd == 0)
  562. {
  563. /* wait for the watchdog to come around again */
  564. sc->tx_TimeoutInd = 1;
  565. }
  566. else if (sc->lmc_taint_tx == sc->lastlmc_taint_tx &&
  567. sc->lmc_device->stats.tx_packets > sc->lasttx_packets &&
  568. sc->tx_TimeoutInd)
  569. {
  570. LMC_EVENT_LOG(LMC_EVENT_XMTINTTMO, LMC_CSR_READ (sc, csr_status), 0);
  571. sc->tx_TimeoutDisplay = 1;
  572. sc->extra_stats.tx_TimeoutCnt++;
  573. /* DEC chip is stuck, hit it with a RESET!!!! */
  574. lmc_running_reset (dev);
  575. /* look at receive & transmit process state to make sure they are running */
  576. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  577. /* look at: DSR - 02 for Reg 16
  578. * CTS - 08
  579. * DCD - 10
  580. * RI - 20
  581. * for Reg 17
  582. */
  583. LMC_EVENT_LOG(LMC_EVENT_RESET2, lmc_mii_readreg (sc, 0, 16), lmc_mii_readreg (sc, 0, 17));
  584. /* reset the transmit timeout detection flag */
  585. sc->tx_TimeoutInd = 0;
  586. sc->lastlmc_taint_tx = sc->lmc_taint_tx;
  587. sc->lasttx_packets = sc->lmc_device->stats.tx_packets;
  588. } else {
  589. sc->tx_TimeoutInd = 0;
  590. sc->lastlmc_taint_tx = sc->lmc_taint_tx;
  591. sc->lasttx_packets = sc->lmc_device->stats.tx_packets;
  592. }
  593. /* --- end time out check ----------------------------------- */
  594. link_status = sc->lmc_media->get_link_status (sc);
  595. /*
  596. * hardware level link lost, but the interface is marked as up.
  597. * Mark it as down.
  598. */
  599. if ((link_status == 0) && (sc->last_link_status != 0)) {
  600. printk(KERN_WARNING "%s: hardware/physical link down\n", dev->name);
  601. sc->last_link_status = 0;
  602. /* lmc_reset (sc); Why reset??? The link can go down ok */
  603. /* Inform the world that link has been lost */
  604. netif_carrier_off(dev);
  605. }
  606. /*
  607. * hardware link is up, but the interface is marked as down.
  608. * Bring it back up again.
  609. */
  610. if (link_status != 0 && sc->last_link_status == 0) {
  611. printk(KERN_WARNING "%s: hardware/physical link up\n", dev->name);
  612. sc->last_link_status = 1;
  613. /* lmc_reset (sc); Again why reset??? */
  614. netif_carrier_on(dev);
  615. }
  616. /* Call media specific watchdog functions */
  617. sc->lmc_media->watchdog(sc);
  618. /*
  619. * Poke the transmitter to make sure it
  620. * never stops, even if we run out of mem
  621. */
  622. LMC_CSR_WRITE(sc, csr_rxpoll, 0);
  623. /*
  624. * Check for code that failed
  625. * and try and fix it as appropriate
  626. */
  627. if(sc->failed_ring == 1){
  628. /*
  629. * Failed to setup the recv/xmit rin
  630. * Try again
  631. */
  632. sc->failed_ring = 0;
  633. lmc_softreset(sc);
  634. }
  635. if(sc->failed_recv_alloc == 1){
  636. /*
  637. * We failed to alloc mem in the
  638. * interrupt handler, go through the rings
  639. * and rebuild them
  640. */
  641. sc->failed_recv_alloc = 0;
  642. lmc_softreset(sc);
  643. }
  644. /*
  645. * remember the timer value
  646. */
  647. kick_timer:
  648. ticks = LMC_CSR_READ (sc, csr_gp_timer);
  649. LMC_CSR_WRITE (sc, csr_gp_timer, 0xffffffffUL);
  650. sc->ictl.ticks = 0x0000ffff - (ticks & 0x0000ffff);
  651. /*
  652. * restart this timer.
  653. */
  654. sc->timer.expires = jiffies + (HZ);
  655. add_timer (&sc->timer);
  656. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  657. lmc_trace(dev, "lmc_watchdog out");
  658. }
  659. static int lmc_attach(struct net_device *dev, unsigned short encoding,
  660. unsigned short parity)
  661. {
  662. if (encoding == ENCODING_NRZ && parity == PARITY_CRC16_PR1_CCITT)
  663. return 0;
  664. return -EINVAL;
  665. }
  666. static int __devinit lmc_init_one(struct pci_dev *pdev,
  667. const struct pci_device_id *ent)
  668. {
  669. lmc_softc_t *sc;
  670. struct net_device *dev;
  671. u16 subdevice;
  672. u16 AdapModelNum;
  673. int err;
  674. static int cards_found;
  675. /* lmc_trace(dev, "lmc_init_one in"); */
  676. err = pci_enable_device(pdev);
  677. if (err) {
  678. printk(KERN_ERR "lmc: pci enable failed: %d\n", err);
  679. return err;
  680. }
  681. err = pci_request_regions(pdev, "lmc");
  682. if (err) {
  683. printk(KERN_ERR "lmc: pci_request_region failed\n");
  684. goto err_req_io;
  685. }
  686. /*
  687. * Allocate our own device structure
  688. */
  689. sc = kzalloc(sizeof(lmc_softc_t), GFP_KERNEL);
  690. if (!sc) {
  691. err = -ENOMEM;
  692. goto err_kzalloc;
  693. }
  694. dev = alloc_hdlcdev(sc);
  695. if (!dev) {
  696. printk(KERN_ERR "lmc:alloc_netdev for device failed\n");
  697. goto err_hdlcdev;
  698. }
  699. dev->type = ARPHRD_HDLC;
  700. dev_to_hdlc(dev)->xmit = lmc_start_xmit;
  701. dev_to_hdlc(dev)->attach = lmc_attach;
  702. dev->open = lmc_open;
  703. dev->stop = lmc_close;
  704. dev->get_stats = lmc_get_stats;
  705. dev->do_ioctl = lmc_ioctl;
  706. dev->tx_timeout = lmc_driver_timeout;
  707. dev->watchdog_timeo = HZ; /* 1 second */
  708. dev->tx_queue_len = 100;
  709. sc->lmc_device = dev;
  710. sc->name = dev->name;
  711. sc->if_type = LMC_PPP;
  712. sc->check = 0xBEAFCAFE;
  713. dev->base_addr = pci_resource_start(pdev, 0);
  714. dev->irq = pdev->irq;
  715. pci_set_drvdata(pdev, dev);
  716. SET_NETDEV_DEV(dev, &pdev->dev);
  717. /*
  718. * This will get the protocol layer ready and do any 1 time init's
  719. * Must have a valid sc and dev structure
  720. */
  721. lmc_proto_attach(sc);
  722. /* Init the spin lock so can call it latter */
  723. spin_lock_init(&sc->lmc_lock);
  724. pci_set_master(pdev);
  725. printk(KERN_INFO "%s: detected at %lx, irq %d\n", dev->name,
  726. dev->base_addr, dev->irq);
  727. err = register_hdlc_device(dev);
  728. if (err) {
  729. printk(KERN_ERR "%s: register_netdev failed.\n", dev->name);
  730. free_netdev(dev);
  731. goto err_hdlcdev;
  732. }
  733. sc->lmc_cardtype = LMC_CARDTYPE_UNKNOWN;
  734. sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_EXT;
  735. /*
  736. *
  737. * Check either the subvendor or the subdevice, some systems reverse
  738. * the setting in the bois, seems to be version and arch dependent?
  739. * Fix the error, exchange the two values
  740. */
  741. if ((subdevice = pdev->subsystem_device) == PCI_VENDOR_ID_LMC)
  742. subdevice = pdev->subsystem_vendor;
  743. switch (subdevice) {
  744. case PCI_DEVICE_ID_LMC_HSSI:
  745. printk(KERN_INFO "%s: LMC HSSI\n", dev->name);
  746. sc->lmc_cardtype = LMC_CARDTYPE_HSSI;
  747. sc->lmc_media = &lmc_hssi_media;
  748. break;
  749. case PCI_DEVICE_ID_LMC_DS3:
  750. printk(KERN_INFO "%s: LMC DS3\n", dev->name);
  751. sc->lmc_cardtype = LMC_CARDTYPE_DS3;
  752. sc->lmc_media = &lmc_ds3_media;
  753. break;
  754. case PCI_DEVICE_ID_LMC_SSI:
  755. printk(KERN_INFO "%s: LMC SSI\n", dev->name);
  756. sc->lmc_cardtype = LMC_CARDTYPE_SSI;
  757. sc->lmc_media = &lmc_ssi_media;
  758. break;
  759. case PCI_DEVICE_ID_LMC_T1:
  760. printk(KERN_INFO "%s: LMC T1\n", dev->name);
  761. sc->lmc_cardtype = LMC_CARDTYPE_T1;
  762. sc->lmc_media = &lmc_t1_media;
  763. break;
  764. default:
  765. printk(KERN_WARNING "%s: LMC UNKOWN CARD!\n", dev->name);
  766. break;
  767. }
  768. lmc_initcsrs (sc, dev->base_addr, 8);
  769. lmc_gpio_mkinput (sc, 0xff);
  770. sc->lmc_gpio = 0; /* drive no signals yet */
  771. sc->lmc_media->defaults (sc);
  772. sc->lmc_media->set_link_status (sc, LMC_LINK_UP);
  773. /* verify that the PCI Sub System ID matches the Adapter Model number
  774. * from the MII register
  775. */
  776. AdapModelNum = (lmc_mii_readreg (sc, 0, 3) & 0x3f0) >> 4;
  777. if ((AdapModelNum != LMC_ADAP_T1 || /* detect LMC1200 */
  778. subdevice != PCI_DEVICE_ID_LMC_T1) &&
  779. (AdapModelNum != LMC_ADAP_SSI || /* detect LMC1000 */
  780. subdevice != PCI_DEVICE_ID_LMC_SSI) &&
  781. (AdapModelNum != LMC_ADAP_DS3 || /* detect LMC5245 */
  782. subdevice != PCI_DEVICE_ID_LMC_DS3) &&
  783. (AdapModelNum != LMC_ADAP_HSSI || /* detect LMC5200 */
  784. subdevice != PCI_DEVICE_ID_LMC_HSSI))
  785. printk(KERN_WARNING "%s: Model number (%d) miscompare for PCI"
  786. " Subsystem ID = 0x%04x\n",
  787. dev->name, AdapModelNum, subdevice);
  788. /*
  789. * reset clock
  790. */
  791. LMC_CSR_WRITE (sc, csr_gp_timer, 0xFFFFFFFFUL);
  792. sc->board_idx = cards_found++;
  793. sc->extra_stats.check = STATCHECK;
  794. sc->extra_stats.version_size = (DRIVER_VERSION << 16) +
  795. sizeof(sc->lmc_device->stats) + sizeof(sc->extra_stats);
  796. sc->extra_stats.lmc_cardtype = sc->lmc_cardtype;
  797. sc->lmc_ok = 0;
  798. sc->last_link_status = 0;
  799. lmc_trace(dev, "lmc_init_one out");
  800. return 0;
  801. err_hdlcdev:
  802. pci_set_drvdata(pdev, NULL);
  803. kfree(sc);
  804. err_kzalloc:
  805. pci_release_regions(pdev);
  806. err_req_io:
  807. pci_disable_device(pdev);
  808. return err;
  809. }
  810. /*
  811. * Called from pci when removing module.
  812. */
  813. static void __devexit lmc_remove_one(struct pci_dev *pdev)
  814. {
  815. struct net_device *dev = pci_get_drvdata(pdev);
  816. if (dev) {
  817. printk(KERN_DEBUG "%s: removing...\n", dev->name);
  818. unregister_hdlc_device(dev);
  819. free_netdev(dev);
  820. pci_release_regions(pdev);
  821. pci_disable_device(pdev);
  822. pci_set_drvdata(pdev, NULL);
  823. }
  824. }
  825. /* After this is called, packets can be sent.
  826. * Does not initialize the addresses
  827. */
  828. static int lmc_open(struct net_device *dev)
  829. {
  830. lmc_softc_t *sc = dev_to_sc(dev);
  831. int err;
  832. lmc_trace(dev, "lmc_open in");
  833. lmc_led_on(sc, LMC_DS3_LED0);
  834. lmc_dec_reset(sc);
  835. lmc_reset(sc);
  836. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ(sc, csr_status), 0);
  837. LMC_EVENT_LOG(LMC_EVENT_RESET2, lmc_mii_readreg(sc, 0, 16),
  838. lmc_mii_readreg(sc, 0, 17));
  839. if (sc->lmc_ok){
  840. lmc_trace(dev, "lmc_open lmc_ok out");
  841. return (0);
  842. }
  843. lmc_softreset (sc);
  844. /* Since we have to use PCI bus, this should work on x86,alpha,ppc */
  845. if (request_irq (dev->irq, &lmc_interrupt, IRQF_SHARED, dev->name, dev)){
  846. printk(KERN_WARNING "%s: could not get irq: %d\n", dev->name, dev->irq);
  847. lmc_trace(dev, "lmc_open irq failed out");
  848. return -EAGAIN;
  849. }
  850. sc->got_irq = 1;
  851. /* Assert Terminal Active */
  852. sc->lmc_miireg16 |= LMC_MII16_LED_ALL;
  853. sc->lmc_media->set_link_status (sc, LMC_LINK_UP);
  854. /*
  855. * reset to last state.
  856. */
  857. sc->lmc_media->set_status (sc, NULL);
  858. /* setup default bits to be used in tulip_desc_t transmit descriptor
  859. * -baz */
  860. sc->TxDescriptControlInit = (
  861. LMC_TDES_INTERRUPT_ON_COMPLETION
  862. | LMC_TDES_FIRST_SEGMENT
  863. | LMC_TDES_LAST_SEGMENT
  864. | LMC_TDES_SECOND_ADDR_CHAINED
  865. | LMC_TDES_DISABLE_PADDING
  866. );
  867. if (sc->ictl.crc_length == LMC_CTL_CRC_LENGTH_16) {
  868. /* disable 32 bit CRC generated by ASIC */
  869. sc->TxDescriptControlInit |= LMC_TDES_ADD_CRC_DISABLE;
  870. }
  871. sc->lmc_media->set_crc_length(sc, sc->ictl.crc_length);
  872. /* Acknoledge the Terminal Active and light LEDs */
  873. /* dev->flags |= IFF_UP; */
  874. if ((err = lmc_proto_open(sc)) != 0)
  875. return err;
  876. dev->do_ioctl = lmc_ioctl;
  877. netif_start_queue(dev);
  878. sc->extra_stats.tx_tbusy0++;
  879. /*
  880. * select what interrupts we want to get
  881. */
  882. sc->lmc_intrmask = 0;
  883. /* Should be using the default interrupt mask defined in the .h file. */
  884. sc->lmc_intrmask |= (TULIP_STS_NORMALINTR
  885. | TULIP_STS_RXINTR
  886. | TULIP_STS_TXINTR
  887. | TULIP_STS_ABNRMLINTR
  888. | TULIP_STS_SYSERROR
  889. | TULIP_STS_TXSTOPPED
  890. | TULIP_STS_TXUNDERFLOW
  891. | TULIP_STS_RXSTOPPED
  892. | TULIP_STS_RXNOBUF
  893. );
  894. LMC_CSR_WRITE (sc, csr_intr, sc->lmc_intrmask);
  895. sc->lmc_cmdmode |= TULIP_CMD_TXRUN;
  896. sc->lmc_cmdmode |= TULIP_CMD_RXRUN;
  897. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  898. sc->lmc_ok = 1; /* Run watchdog */
  899. /*
  900. * Set the if up now - pfb
  901. */
  902. sc->last_link_status = 1;
  903. /*
  904. * Setup a timer for the watchdog on probe, and start it running.
  905. * Since lmc_ok == 0, it will be a NOP for now.
  906. */
  907. init_timer (&sc->timer);
  908. sc->timer.expires = jiffies + HZ;
  909. sc->timer.data = (unsigned long) dev;
  910. sc->timer.function = &lmc_watchdog;
  911. add_timer (&sc->timer);
  912. lmc_trace(dev, "lmc_open out");
  913. return (0);
  914. }
  915. /* Total reset to compensate for the AdTran DSU doing bad things
  916. * under heavy load
  917. */
  918. static void lmc_running_reset (struct net_device *dev) /*fold00*/
  919. {
  920. lmc_softc_t *sc = dev_to_sc(dev);
  921. lmc_trace(dev, "lmc_runnig_reset in");
  922. /* stop interrupts */
  923. /* Clear the interrupt mask */
  924. LMC_CSR_WRITE (sc, csr_intr, 0x00000000);
  925. lmc_dec_reset (sc);
  926. lmc_reset (sc);
  927. lmc_softreset (sc);
  928. /* sc->lmc_miireg16 |= LMC_MII16_LED_ALL; */
  929. sc->lmc_media->set_link_status (sc, 1);
  930. sc->lmc_media->set_status (sc, NULL);
  931. netif_wake_queue(dev);
  932. sc->lmc_txfull = 0;
  933. sc->extra_stats.tx_tbusy0++;
  934. sc->lmc_intrmask = TULIP_DEFAULT_INTR_MASK;
  935. LMC_CSR_WRITE (sc, csr_intr, sc->lmc_intrmask);
  936. sc->lmc_cmdmode |= (TULIP_CMD_TXRUN | TULIP_CMD_RXRUN);
  937. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  938. lmc_trace(dev, "lmc_runnin_reset_out");
  939. }
  940. /* This is what is called when you ifconfig down a device.
  941. * This disables the timer for the watchdog and keepalives,
  942. * and disables the irq for dev.
  943. */
  944. static int lmc_close(struct net_device *dev)
  945. {
  946. /* not calling release_region() as we should */
  947. lmc_softc_t *sc = dev_to_sc(dev);
  948. lmc_trace(dev, "lmc_close in");
  949. sc->lmc_ok = 0;
  950. sc->lmc_media->set_link_status (sc, 0);
  951. del_timer (&sc->timer);
  952. lmc_proto_close(sc);
  953. lmc_ifdown (dev);
  954. lmc_trace(dev, "lmc_close out");
  955. return 0;
  956. }
  957. /* Ends the transfer of packets */
  958. /* When the interface goes down, this is called */
  959. static int lmc_ifdown (struct net_device *dev) /*fold00*/
  960. {
  961. lmc_softc_t *sc = dev_to_sc(dev);
  962. u32 csr6;
  963. int i;
  964. lmc_trace(dev, "lmc_ifdown in");
  965. /* Don't let anything else go on right now */
  966. // dev->start = 0;
  967. netif_stop_queue(dev);
  968. sc->extra_stats.tx_tbusy1++;
  969. /* stop interrupts */
  970. /* Clear the interrupt mask */
  971. LMC_CSR_WRITE (sc, csr_intr, 0x00000000);
  972. /* Stop Tx and Rx on the chip */
  973. csr6 = LMC_CSR_READ (sc, csr_command);
  974. csr6 &= ~LMC_DEC_ST; /* Turn off the Transmission bit */
  975. csr6 &= ~LMC_DEC_SR; /* Turn off the Receive bit */
  976. LMC_CSR_WRITE (sc, csr_command, csr6);
  977. sc->lmc_device->stats.rx_missed_errors +=
  978. LMC_CSR_READ(sc, csr_missed_frames) & 0xffff;
  979. /* release the interrupt */
  980. if(sc->got_irq == 1){
  981. free_irq (dev->irq, dev);
  982. sc->got_irq = 0;
  983. }
  984. /* free skbuffs in the Rx queue */
  985. for (i = 0; i < LMC_RXDESCS; i++)
  986. {
  987. struct sk_buff *skb = sc->lmc_rxq[i];
  988. sc->lmc_rxq[i] = NULL;
  989. sc->lmc_rxring[i].status = 0;
  990. sc->lmc_rxring[i].length = 0;
  991. sc->lmc_rxring[i].buffer1 = 0xDEADBEEF;
  992. if (skb != NULL)
  993. dev_kfree_skb(skb);
  994. sc->lmc_rxq[i] = NULL;
  995. }
  996. for (i = 0; i < LMC_TXDESCS; i++)
  997. {
  998. if (sc->lmc_txq[i] != NULL)
  999. dev_kfree_skb(sc->lmc_txq[i]);
  1000. sc->lmc_txq[i] = NULL;
  1001. }
  1002. lmc_led_off (sc, LMC_MII16_LED_ALL);
  1003. netif_wake_queue(dev);
  1004. sc->extra_stats.tx_tbusy0++;
  1005. lmc_trace(dev, "lmc_ifdown out");
  1006. return 0;
  1007. }
  1008. /* Interrupt handling routine. This will take an incoming packet, or clean
  1009. * up after a trasmit.
  1010. */
  1011. static irqreturn_t lmc_interrupt (int irq, void *dev_instance) /*fold00*/
  1012. {
  1013. struct net_device *dev = (struct net_device *) dev_instance;
  1014. lmc_softc_t *sc = dev_to_sc(dev);
  1015. u32 csr;
  1016. int i;
  1017. s32 stat;
  1018. unsigned int badtx;
  1019. u32 firstcsr;
  1020. int max_work = LMC_RXDESCS;
  1021. int handled = 0;
  1022. lmc_trace(dev, "lmc_interrupt in");
  1023. spin_lock(&sc->lmc_lock);
  1024. /*
  1025. * Read the csr to find what interrupts we have (if any)
  1026. */
  1027. csr = LMC_CSR_READ (sc, csr_status);
  1028. /*
  1029. * Make sure this is our interrupt
  1030. */
  1031. if ( ! (csr & sc->lmc_intrmask)) {
  1032. goto lmc_int_fail_out;
  1033. }
  1034. firstcsr = csr;
  1035. /* always go through this loop at least once */
  1036. while (csr & sc->lmc_intrmask) {
  1037. handled = 1;
  1038. /*
  1039. * Clear interrupt bits, we handle all case below
  1040. */
  1041. LMC_CSR_WRITE (sc, csr_status, csr);
  1042. /*
  1043. * One of
  1044. * - Transmit process timed out CSR5<1>
  1045. * - Transmit jabber timeout CSR5<3>
  1046. * - Transmit underflow CSR5<5>
  1047. * - Transmit Receiver buffer unavailable CSR5<7>
  1048. * - Receive process stopped CSR5<8>
  1049. * - Receive watchdog timeout CSR5<9>
  1050. * - Early transmit interrupt CSR5<10>
  1051. *
  1052. * Is this really right? Should we do a running reset for jabber?
  1053. * (being a WAN card and all)
  1054. */
  1055. if (csr & TULIP_STS_ABNRMLINTR){
  1056. lmc_running_reset (dev);
  1057. break;
  1058. }
  1059. if (csr & TULIP_STS_RXINTR){
  1060. lmc_trace(dev, "rx interrupt");
  1061. lmc_rx (dev);
  1062. }
  1063. if (csr & (TULIP_STS_TXINTR | TULIP_STS_TXNOBUF | TULIP_STS_TXSTOPPED)) {
  1064. int n_compl = 0 ;
  1065. /* reset the transmit timeout detection flag -baz */
  1066. sc->extra_stats.tx_NoCompleteCnt = 0;
  1067. badtx = sc->lmc_taint_tx;
  1068. i = badtx % LMC_TXDESCS;
  1069. while ((badtx < sc->lmc_next_tx)) {
  1070. stat = sc->lmc_txring[i].status;
  1071. LMC_EVENT_LOG (LMC_EVENT_XMTINT, stat,
  1072. sc->lmc_txring[i].length);
  1073. /*
  1074. * If bit 31 is 1 the tulip owns it break out of the loop
  1075. */
  1076. if (stat & 0x80000000)
  1077. break;
  1078. n_compl++ ; /* i.e., have an empty slot in ring */
  1079. /*
  1080. * If we have no skbuff or have cleared it
  1081. * Already continue to the next buffer
  1082. */
  1083. if (sc->lmc_txq[i] == NULL)
  1084. continue;
  1085. /*
  1086. * Check the total error summary to look for any errors
  1087. */
  1088. if (stat & 0x8000) {
  1089. sc->lmc_device->stats.tx_errors++;
  1090. if (stat & 0x4104)
  1091. sc->lmc_device->stats.tx_aborted_errors++;
  1092. if (stat & 0x0C00)
  1093. sc->lmc_device->stats.tx_carrier_errors++;
  1094. if (stat & 0x0200)
  1095. sc->lmc_device->stats.tx_window_errors++;
  1096. if (stat & 0x0002)
  1097. sc->lmc_device->stats.tx_fifo_errors++;
  1098. } else {
  1099. sc->lmc_device->stats.tx_bytes += sc->lmc_txring[i].length & 0x7ff;
  1100. sc->lmc_device->stats.tx_packets++;
  1101. }
  1102. // dev_kfree_skb(sc->lmc_txq[i]);
  1103. dev_kfree_skb_irq(sc->lmc_txq[i]);
  1104. sc->lmc_txq[i] = NULL;
  1105. badtx++;
  1106. i = badtx % LMC_TXDESCS;
  1107. }
  1108. if (sc->lmc_next_tx - badtx > LMC_TXDESCS)
  1109. {
  1110. printk ("%s: out of sync pointer\n", dev->name);
  1111. badtx += LMC_TXDESCS;
  1112. }
  1113. LMC_EVENT_LOG(LMC_EVENT_TBUSY0, n_compl, 0);
  1114. sc->lmc_txfull = 0;
  1115. netif_wake_queue(dev);
  1116. sc->extra_stats.tx_tbusy0++;
  1117. #ifdef DEBUG
  1118. sc->extra_stats.dirtyTx = badtx;
  1119. sc->extra_stats.lmc_next_tx = sc->lmc_next_tx;
  1120. sc->extra_stats.lmc_txfull = sc->lmc_txfull;
  1121. #endif
  1122. sc->lmc_taint_tx = badtx;
  1123. /*
  1124. * Why was there a break here???
  1125. */
  1126. } /* end handle transmit interrupt */
  1127. if (csr & TULIP_STS_SYSERROR) {
  1128. u32 error;
  1129. printk (KERN_WARNING "%s: system bus error csr: %#8.8x\n", dev->name, csr);
  1130. error = csr>>23 & 0x7;
  1131. switch(error){
  1132. case 0x000:
  1133. printk(KERN_WARNING "%s: Parity Fault (bad)\n", dev->name);
  1134. break;
  1135. case 0x001:
  1136. printk(KERN_WARNING "%s: Master Abort (naughty)\n", dev->name);
  1137. break;
  1138. case 0x010:
  1139. printk(KERN_WARNING "%s: Target Abort (not so naughty)\n", dev->name);
  1140. break;
  1141. default:
  1142. printk(KERN_WARNING "%s: This bus error code was supposed to be reserved!\n", dev->name);
  1143. }
  1144. lmc_dec_reset (sc);
  1145. lmc_reset (sc);
  1146. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  1147. LMC_EVENT_LOG(LMC_EVENT_RESET2,
  1148. lmc_mii_readreg (sc, 0, 16),
  1149. lmc_mii_readreg (sc, 0, 17));
  1150. }
  1151. if(max_work-- <= 0)
  1152. break;
  1153. /*
  1154. * Get current csr status to make sure
  1155. * we've cleared all interrupts
  1156. */
  1157. csr = LMC_CSR_READ (sc, csr_status);
  1158. } /* end interrupt loop */
  1159. LMC_EVENT_LOG(LMC_EVENT_INT, firstcsr, csr);
  1160. lmc_int_fail_out:
  1161. spin_unlock(&sc->lmc_lock);
  1162. lmc_trace(dev, "lmc_interrupt out");
  1163. return IRQ_RETVAL(handled);
  1164. }
  1165. static int lmc_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1166. {
  1167. lmc_softc_t *sc = dev_to_sc(dev);
  1168. u32 flag;
  1169. int entry;
  1170. int ret = 0;
  1171. unsigned long flags;
  1172. lmc_trace(dev, "lmc_start_xmit in");
  1173. spin_lock_irqsave(&sc->lmc_lock, flags);
  1174. /* normal path, tbusy known to be zero */
  1175. entry = sc->lmc_next_tx % LMC_TXDESCS;
  1176. sc->lmc_txq[entry] = skb;
  1177. sc->lmc_txring[entry].buffer1 = virt_to_bus (skb->data);
  1178. LMC_CONSOLE_LOG("xmit", skb->data, skb->len);
  1179. #ifndef GCOM
  1180. /* If the queue is less than half full, don't interrupt */
  1181. if (sc->lmc_next_tx - sc->lmc_taint_tx < LMC_TXDESCS / 2)
  1182. {
  1183. /* Do not interrupt on completion of this packet */
  1184. flag = 0x60000000;
  1185. netif_wake_queue(dev);
  1186. }
  1187. else if (sc->lmc_next_tx - sc->lmc_taint_tx == LMC_TXDESCS / 2)
  1188. {
  1189. /* This generates an interrupt on completion of this packet */
  1190. flag = 0xe0000000;
  1191. netif_wake_queue(dev);
  1192. }
  1193. else if (sc->lmc_next_tx - sc->lmc_taint_tx < LMC_TXDESCS - 1)
  1194. {
  1195. /* Do not interrupt on completion of this packet */
  1196. flag = 0x60000000;
  1197. netif_wake_queue(dev);
  1198. }
  1199. else
  1200. {
  1201. /* This generates an interrupt on completion of this packet */
  1202. flag = 0xe0000000;
  1203. sc->lmc_txfull = 1;
  1204. netif_stop_queue(dev);
  1205. }
  1206. #else
  1207. flag = LMC_TDES_INTERRUPT_ON_COMPLETION;
  1208. if (sc->lmc_next_tx - sc->lmc_taint_tx >= LMC_TXDESCS - 1)
  1209. { /* ring full, go busy */
  1210. sc->lmc_txfull = 1;
  1211. netif_stop_queue(dev);
  1212. sc->extra_stats.tx_tbusy1++;
  1213. LMC_EVENT_LOG(LMC_EVENT_TBUSY1, entry, 0);
  1214. }
  1215. #endif
  1216. if (entry == LMC_TXDESCS - 1) /* last descriptor in ring */
  1217. flag |= LMC_TDES_END_OF_RING; /* flag as such for Tulip */
  1218. /* don't pad small packets either */
  1219. flag = sc->lmc_txring[entry].length = (skb->len) | flag |
  1220. sc->TxDescriptControlInit;
  1221. /* set the transmit timeout flag to be checked in
  1222. * the watchdog timer handler. -baz
  1223. */
  1224. sc->extra_stats.tx_NoCompleteCnt++;
  1225. sc->lmc_next_tx++;
  1226. /* give ownership to the chip */
  1227. LMC_EVENT_LOG(LMC_EVENT_XMT, flag, entry);
  1228. sc->lmc_txring[entry].status = 0x80000000;
  1229. /* send now! */
  1230. LMC_CSR_WRITE (sc, csr_txpoll, 0);
  1231. dev->trans_start = jiffies;
  1232. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1233. lmc_trace(dev, "lmc_start_xmit_out");
  1234. return ret;
  1235. }
  1236. static int lmc_rx(struct net_device *dev)
  1237. {
  1238. lmc_softc_t *sc = dev_to_sc(dev);
  1239. int i;
  1240. int rx_work_limit = LMC_RXDESCS;
  1241. unsigned int next_rx;
  1242. int rxIntLoopCnt; /* debug -baz */
  1243. int localLengthErrCnt = 0;
  1244. long stat;
  1245. struct sk_buff *skb, *nsb;
  1246. u16 len;
  1247. lmc_trace(dev, "lmc_rx in");
  1248. lmc_led_on(sc, LMC_DS3_LED3);
  1249. rxIntLoopCnt = 0; /* debug -baz */
  1250. i = sc->lmc_next_rx % LMC_RXDESCS;
  1251. next_rx = sc->lmc_next_rx;
  1252. while (((stat = sc->lmc_rxring[i].status) & LMC_RDES_OWN_BIT) != DESC_OWNED_BY_DC21X4)
  1253. {
  1254. rxIntLoopCnt++; /* debug -baz */
  1255. len = ((stat & LMC_RDES_FRAME_LENGTH) >> RDES_FRAME_LENGTH_BIT_NUMBER);
  1256. if ((stat & 0x0300) != 0x0300) { /* Check first segment and last segment */
  1257. if ((stat & 0x0000ffff) != 0x7fff) {
  1258. /* Oversized frame */
  1259. sc->lmc_device->stats.rx_length_errors++;
  1260. goto skip_packet;
  1261. }
  1262. }
  1263. if (stat & 0x00000008) { /* Catch a dribbling bit error */
  1264. sc->lmc_device->stats.rx_errors++;
  1265. sc->lmc_device->stats.rx_frame_errors++;
  1266. goto skip_packet;
  1267. }
  1268. if (stat & 0x00000004) { /* Catch a CRC error by the Xilinx */
  1269. sc->lmc_device->stats.rx_errors++;
  1270. sc->lmc_device->stats.rx_crc_errors++;
  1271. goto skip_packet;
  1272. }
  1273. if (len > LMC_PKT_BUF_SZ) {
  1274. sc->lmc_device->stats.rx_length_errors++;
  1275. localLengthErrCnt++;
  1276. goto skip_packet;
  1277. }
  1278. if (len < sc->lmc_crcSize + 2) {
  1279. sc->lmc_device->stats.rx_length_errors++;
  1280. sc->extra_stats.rx_SmallPktCnt++;
  1281. localLengthErrCnt++;
  1282. goto skip_packet;
  1283. }
  1284. if(stat & 0x00004000){
  1285. printk(KERN_WARNING "%s: Receiver descriptor error, receiver out of sync?\n", dev->name);
  1286. }
  1287. len -= sc->lmc_crcSize;
  1288. skb = sc->lmc_rxq[i];
  1289. /*
  1290. * We ran out of memory at some point
  1291. * just allocate an skb buff and continue.
  1292. */
  1293. if (!skb) {
  1294. nsb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1295. if (nsb) {
  1296. sc->lmc_rxq[i] = nsb;
  1297. nsb->dev = dev;
  1298. sc->lmc_rxring[i].buffer1 = virt_to_bus(skb_tail_pointer(nsb));
  1299. }
  1300. sc->failed_recv_alloc = 1;
  1301. goto skip_packet;
  1302. }
  1303. sc->lmc_device->stats.rx_packets++;
  1304. sc->lmc_device->stats.rx_bytes += len;
  1305. LMC_CONSOLE_LOG("recv", skb->data, len);
  1306. /*
  1307. * I'm not sure of the sanity of this
  1308. * Packets could be arriving at a constant
  1309. * 44.210mbits/sec and we're going to copy
  1310. * them into a new buffer??
  1311. */
  1312. if(len > (LMC_MTU - (LMC_MTU>>2))){ /* len > LMC_MTU * 0.75 */
  1313. /*
  1314. * If it's a large packet don't copy it just hand it up
  1315. */
  1316. give_it_anyways:
  1317. sc->lmc_rxq[i] = NULL;
  1318. sc->lmc_rxring[i].buffer1 = 0x0;
  1319. skb_put (skb, len);
  1320. skb->protocol = lmc_proto_type(sc, skb);
  1321. skb_reset_mac_header(skb);
  1322. /* skb_reset_network_header(skb); */
  1323. skb->dev = dev;
  1324. lmc_proto_netif(sc, skb);
  1325. /*
  1326. * This skb will be destroyed by the upper layers, make a new one
  1327. */
  1328. nsb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1329. if (nsb) {
  1330. sc->lmc_rxq[i] = nsb;
  1331. nsb->dev = dev;
  1332. sc->lmc_rxring[i].buffer1 = virt_to_bus(skb_tail_pointer(nsb));
  1333. /* Transferred to 21140 below */
  1334. }
  1335. else {
  1336. /*
  1337. * We've run out of memory, stop trying to allocate
  1338. * memory and exit the interrupt handler
  1339. *
  1340. * The chip may run out of receivers and stop
  1341. * in which care we'll try to allocate the buffer
  1342. * again. (once a second)
  1343. */
  1344. sc->extra_stats.rx_BuffAllocErr++;
  1345. LMC_EVENT_LOG(LMC_EVENT_RCVINT, stat, len);
  1346. sc->failed_recv_alloc = 1;
  1347. goto skip_out_of_mem;
  1348. }
  1349. }
  1350. else {
  1351. nsb = dev_alloc_skb(len);
  1352. if(!nsb) {
  1353. goto give_it_anyways;
  1354. }
  1355. skb_copy_from_linear_data(skb, skb_put(nsb, len), len);
  1356. nsb->protocol = lmc_proto_type(sc, skb);
  1357. skb_reset_mac_header(nsb);
  1358. /* skb_reset_network_header(nsb); */
  1359. nsb->dev = dev;
  1360. lmc_proto_netif(sc, nsb);
  1361. }
  1362. skip_packet:
  1363. LMC_EVENT_LOG(LMC_EVENT_RCVINT, stat, len);
  1364. sc->lmc_rxring[i].status = DESC_OWNED_BY_DC21X4;
  1365. sc->lmc_next_rx++;
  1366. i = sc->lmc_next_rx % LMC_RXDESCS;
  1367. rx_work_limit--;
  1368. if (rx_work_limit < 0)
  1369. break;
  1370. }
  1371. /* detect condition for LMC1000 where DSU cable attaches and fills
  1372. * descriptors with bogus packets
  1373. *
  1374. if (localLengthErrCnt > LMC_RXDESCS - 3) {
  1375. sc->extra_stats.rx_BadPktSurgeCnt++;
  1376. LMC_EVENT_LOG(LMC_EVENT_BADPKTSURGE, localLengthErrCnt,
  1377. sc->extra_stats.rx_BadPktSurgeCnt);
  1378. } */
  1379. /* save max count of receive descriptors serviced */
  1380. if (rxIntLoopCnt > sc->extra_stats.rxIntLoopCnt)
  1381. sc->extra_stats.rxIntLoopCnt = rxIntLoopCnt; /* debug -baz */
  1382. #ifdef DEBUG
  1383. if (rxIntLoopCnt == 0)
  1384. {
  1385. for (i = 0; i < LMC_RXDESCS; i++)
  1386. {
  1387. if ((sc->lmc_rxring[i].status & LMC_RDES_OWN_BIT)
  1388. != DESC_OWNED_BY_DC21X4)
  1389. {
  1390. rxIntLoopCnt++;
  1391. }
  1392. }
  1393. LMC_EVENT_LOG(LMC_EVENT_RCVEND, rxIntLoopCnt, 0);
  1394. }
  1395. #endif
  1396. lmc_led_off(sc, LMC_DS3_LED3);
  1397. skip_out_of_mem:
  1398. lmc_trace(dev, "lmc_rx out");
  1399. return 0;
  1400. }
  1401. static struct net_device_stats *lmc_get_stats(struct net_device *dev)
  1402. {
  1403. lmc_softc_t *sc = dev_to_sc(dev);
  1404. unsigned long flags;
  1405. lmc_trace(dev, "lmc_get_stats in");
  1406. spin_lock_irqsave(&sc->lmc_lock, flags);
  1407. sc->lmc_device->stats.rx_missed_errors += LMC_CSR_READ(sc, csr_missed_frames) & 0xffff;
  1408. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1409. lmc_trace(dev, "lmc_get_stats out");
  1410. return &sc->lmc_device->stats;
  1411. }
  1412. static struct pci_driver lmc_driver = {
  1413. .name = "lmc",
  1414. .id_table = lmc_pci_tbl,
  1415. .probe = lmc_init_one,
  1416. .remove = __devexit_p(lmc_remove_one),
  1417. };
  1418. static int __init init_lmc(void)
  1419. {
  1420. return pci_register_driver(&lmc_driver);
  1421. }
  1422. static void __exit exit_lmc(void)
  1423. {
  1424. pci_unregister_driver(&lmc_driver);
  1425. }
  1426. module_init(init_lmc);
  1427. module_exit(exit_lmc);
  1428. unsigned lmc_mii_readreg (lmc_softc_t * const sc, unsigned devaddr, unsigned regno) /*fold00*/
  1429. {
  1430. int i;
  1431. int command = (0xf6 << 10) | (devaddr << 5) | regno;
  1432. int retval = 0;
  1433. lmc_trace(sc->lmc_device, "lmc_mii_readreg in");
  1434. LMC_MII_SYNC (sc);
  1435. lmc_trace(sc->lmc_device, "lmc_mii_readreg: done sync");
  1436. for (i = 15; i >= 0; i--)
  1437. {
  1438. int dataval = (command & (1 << i)) ? 0x20000 : 0;
  1439. LMC_CSR_WRITE (sc, csr_9, dataval);
  1440. lmc_delay ();
  1441. /* __SLOW_DOWN_IO; */
  1442. LMC_CSR_WRITE (sc, csr_9, dataval | 0x10000);
  1443. lmc_delay ();
  1444. /* __SLOW_DOWN_IO; */
  1445. }
  1446. lmc_trace(sc->lmc_device, "lmc_mii_readreg: done1");
  1447. for (i = 19; i > 0; i--)
  1448. {
  1449. LMC_CSR_WRITE (sc, csr_9, 0x40000);
  1450. lmc_delay ();
  1451. /* __SLOW_DOWN_IO; */
  1452. retval = (retval << 1) | ((LMC_CSR_READ (sc, csr_9) & 0x80000) ? 1 : 0);
  1453. LMC_CSR_WRITE (sc, csr_9, 0x40000 | 0x10000);
  1454. lmc_delay ();
  1455. /* __SLOW_DOWN_IO; */
  1456. }
  1457. lmc_trace(sc->lmc_device, "lmc_mii_readreg out");
  1458. return (retval >> 1) & 0xffff;
  1459. }
  1460. void lmc_mii_writereg (lmc_softc_t * const sc, unsigned devaddr, unsigned regno, unsigned data) /*fold00*/
  1461. {
  1462. int i = 32;
  1463. int command = (0x5002 << 16) | (devaddr << 23) | (regno << 18) | data;
  1464. lmc_trace(sc->lmc_device, "lmc_mii_writereg in");
  1465. LMC_MII_SYNC (sc);
  1466. i = 31;
  1467. while (i >= 0)
  1468. {
  1469. int datav;
  1470. if (command & (1 << i))
  1471. datav = 0x20000;
  1472. else
  1473. datav = 0x00000;
  1474. LMC_CSR_WRITE (sc, csr_9, datav);
  1475. lmc_delay ();
  1476. /* __SLOW_DOWN_IO; */
  1477. LMC_CSR_WRITE (sc, csr_9, (datav | 0x10000));
  1478. lmc_delay ();
  1479. /* __SLOW_DOWN_IO; */
  1480. i--;
  1481. }
  1482. i = 2;
  1483. while (i > 0)
  1484. {
  1485. LMC_CSR_WRITE (sc, csr_9, 0x40000);
  1486. lmc_delay ();
  1487. /* __SLOW_DOWN_IO; */
  1488. LMC_CSR_WRITE (sc, csr_9, 0x50000);
  1489. lmc_delay ();
  1490. /* __SLOW_DOWN_IO; */
  1491. i--;
  1492. }
  1493. lmc_trace(sc->lmc_device, "lmc_mii_writereg out");
  1494. }
  1495. static void lmc_softreset (lmc_softc_t * const sc) /*fold00*/
  1496. {
  1497. int i;
  1498. lmc_trace(sc->lmc_device, "lmc_softreset in");
  1499. /* Initialize the receive rings and buffers. */
  1500. sc->lmc_txfull = 0;
  1501. sc->lmc_next_rx = 0;
  1502. sc->lmc_next_tx = 0;
  1503. sc->lmc_taint_rx = 0;
  1504. sc->lmc_taint_tx = 0;
  1505. /*
  1506. * Setup each one of the receiver buffers
  1507. * allocate an skbuff for each one, setup the descriptor table
  1508. * and point each buffer at the next one
  1509. */
  1510. for (i = 0; i < LMC_RXDESCS; i++)
  1511. {
  1512. struct sk_buff *skb;
  1513. if (sc->lmc_rxq[i] == NULL)
  1514. {
  1515. skb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1516. if(skb == NULL){
  1517. printk(KERN_WARNING "%s: Failed to allocate receiver ring, will try again\n", sc->name);
  1518. sc->failed_ring = 1;
  1519. break;
  1520. }
  1521. else{
  1522. sc->lmc_rxq[i] = skb;
  1523. }
  1524. }
  1525. else
  1526. {
  1527. skb = sc->lmc_rxq[i];
  1528. }
  1529. skb->dev = sc->lmc_device;
  1530. /* owned by 21140 */
  1531. sc->lmc_rxring[i].status = 0x80000000;
  1532. /* used to be PKT_BUF_SZ now uses skb since we lose some to head room */
  1533. sc->lmc_rxring[i].length = skb_tailroom(skb);
  1534. /* use to be tail which is dumb since you're thinking why write
  1535. * to the end of the packj,et but since there's nothing there tail == data
  1536. */
  1537. sc->lmc_rxring[i].buffer1 = virt_to_bus (skb->data);
  1538. /* This is fair since the structure is static and we have the next address */
  1539. sc->lmc_rxring[i].buffer2 = virt_to_bus (&sc->lmc_rxring[i + 1]);
  1540. }
  1541. /*
  1542. * Sets end of ring
  1543. */
  1544. sc->lmc_rxring[i - 1].length |= 0x02000000; /* Set end of buffers flag */
  1545. sc->lmc_rxring[i - 1].buffer2 = virt_to_bus (&sc->lmc_rxring[0]); /* Point back to the start */
  1546. LMC_CSR_WRITE (sc, csr_rxlist, virt_to_bus (sc->lmc_rxring)); /* write base address */
  1547. /* Initialize the transmit rings and buffers */
  1548. for (i = 0; i < LMC_TXDESCS; i++)
  1549. {
  1550. if (sc->lmc_txq[i] != NULL){ /* have buffer */
  1551. dev_kfree_skb(sc->lmc_txq[i]); /* free it */
  1552. sc->lmc_device->stats.tx_dropped++; /* We just dropped a packet */
  1553. }
  1554. sc->lmc_txq[i] = NULL;
  1555. sc->lmc_txring[i].status = 0x00000000;
  1556. sc->lmc_txring[i].buffer2 = virt_to_bus (&sc->lmc_txring[i + 1]);
  1557. }
  1558. sc->lmc_txring[i - 1].buffer2 = virt_to_bus (&sc->lmc_txring[0]);
  1559. LMC_CSR_WRITE (sc, csr_txlist, virt_to_bus (sc->lmc_txring));
  1560. lmc_trace(sc->lmc_device, "lmc_softreset out");
  1561. }
  1562. void lmc_gpio_mkinput(lmc_softc_t * const sc, u32 bits) /*fold00*/
  1563. {
  1564. lmc_trace(sc->lmc_device, "lmc_gpio_mkinput in");
  1565. sc->lmc_gpio_io &= ~bits;
  1566. LMC_CSR_WRITE(sc, csr_gp, TULIP_GP_PINSET | (sc->lmc_gpio_io));
  1567. lmc_trace(sc->lmc_device, "lmc_gpio_mkinput out");
  1568. }
  1569. void lmc_gpio_mkoutput(lmc_softc_t * const sc, u32 bits) /*fold00*/
  1570. {
  1571. lmc_trace(sc->lmc_device, "lmc_gpio_mkoutput in");
  1572. sc->lmc_gpio_io |= bits;
  1573. LMC_CSR_WRITE(sc, csr_gp, TULIP_GP_PINSET | (sc->lmc_gpio_io));
  1574. lmc_trace(sc->lmc_device, "lmc_gpio_mkoutput out");
  1575. }
  1576. void lmc_led_on(lmc_softc_t * const sc, u32 led) /*fold00*/
  1577. {
  1578. lmc_trace(sc->lmc_device, "lmc_led_on in");
  1579. if((~sc->lmc_miireg16) & led){ /* Already on! */
  1580. lmc_trace(sc->lmc_device, "lmc_led_on aon out");
  1581. return;
  1582. }
  1583. sc->lmc_miireg16 &= ~led;
  1584. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1585. lmc_trace(sc->lmc_device, "lmc_led_on out");
  1586. }
  1587. void lmc_led_off(lmc_softc_t * const sc, u32 led) /*fold00*/
  1588. {
  1589. lmc_trace(sc->lmc_device, "lmc_led_off in");
  1590. if(sc->lmc_miireg16 & led){ /* Already set don't do anything */
  1591. lmc_trace(sc->lmc_device, "lmc_led_off aoff out");
  1592. return;
  1593. }
  1594. sc->lmc_miireg16 |= led;
  1595. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1596. lmc_trace(sc->lmc_device, "lmc_led_off out");
  1597. }
  1598. static void lmc_reset(lmc_softc_t * const sc) /*fold00*/
  1599. {
  1600. lmc_trace(sc->lmc_device, "lmc_reset in");
  1601. sc->lmc_miireg16 |= LMC_MII16_FIFO_RESET;
  1602. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1603. sc->lmc_miireg16 &= ~LMC_MII16_FIFO_RESET;
  1604. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1605. /*
  1606. * make some of the GPIO pins be outputs
  1607. */
  1608. lmc_gpio_mkoutput(sc, LMC_GEP_RESET);
  1609. /*
  1610. * RESET low to force state reset. This also forces
  1611. * the transmitter clock to be internal, but we expect to reset
  1612. * that later anyway.
  1613. */
  1614. sc->lmc_gpio &= ~(LMC_GEP_RESET);
  1615. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  1616. /*
  1617. * hold for more than 10 microseconds
  1618. */
  1619. udelay(50);
  1620. /*
  1621. * stop driving Xilinx-related signals
  1622. */
  1623. lmc_gpio_mkinput(sc, LMC_GEP_RESET);
  1624. /*
  1625. * Call media specific init routine
  1626. */
  1627. sc->lmc_media->init(sc);
  1628. sc->extra_stats.resetCount++;
  1629. lmc_trace(sc->lmc_device, "lmc_reset out");
  1630. }
  1631. static void lmc_dec_reset(lmc_softc_t * const sc) /*fold00*/
  1632. {
  1633. u32 val;
  1634. lmc_trace(sc->lmc_device, "lmc_dec_reset in");
  1635. /*
  1636. * disable all interrupts
  1637. */
  1638. sc->lmc_intrmask = 0;
  1639. LMC_CSR_WRITE(sc, csr_intr, sc->lmc_intrmask);
  1640. /*
  1641. * Reset the chip with a software reset command.
  1642. * Wait 10 microseconds (actually 50 PCI cycles but at
  1643. * 33MHz that comes to two microseconds but wait a
  1644. * bit longer anyways)
  1645. */
  1646. LMC_CSR_WRITE(sc, csr_busmode, TULIP_BUSMODE_SWRESET);
  1647. udelay(25);
  1648. #ifdef __sparc__
  1649. sc->lmc_busmode = LMC_CSR_READ(sc, csr_busmode);
  1650. sc->lmc_busmode = 0x00100000;
  1651. sc->lmc_busmode &= ~TULIP_BUSMODE_SWRESET;
  1652. LMC_CSR_WRITE(sc, csr_busmode, sc->lmc_busmode);
  1653. #endif
  1654. sc->lmc_cmdmode = LMC_CSR_READ(sc, csr_command);
  1655. /*
  1656. * We want:
  1657. * no ethernet address in frames we write
  1658. * disable padding (txdesc, padding disable)
  1659. * ignore runt frames (rdes0 bit 15)
  1660. * no receiver watchdog or transmitter jabber timer
  1661. * (csr15 bit 0,14 == 1)
  1662. * if using 16-bit CRC, turn off CRC (trans desc, crc disable)
  1663. */
  1664. sc->lmc_cmdmode |= ( TULIP_CMD_PROMISCUOUS
  1665. | TULIP_CMD_FULLDUPLEX
  1666. | TULIP_CMD_PASSBADPKT
  1667. | TULIP_CMD_NOHEARTBEAT
  1668. | TULIP_CMD_PORTSELECT
  1669. | TULIP_CMD_RECEIVEALL
  1670. | TULIP_CMD_MUSTBEONE
  1671. );
  1672. sc->lmc_cmdmode &= ~( TULIP_CMD_OPERMODE
  1673. | TULIP_CMD_THRESHOLDCTL
  1674. | TULIP_CMD_STOREFWD
  1675. | TULIP_CMD_TXTHRSHLDCTL
  1676. );
  1677. LMC_CSR_WRITE(sc, csr_command, sc->lmc_cmdmode);
  1678. /*
  1679. * disable receiver watchdog and transmit jabber
  1680. */
  1681. val = LMC_CSR_READ(sc, csr_sia_general);
  1682. val |= (TULIP_WATCHDOG_TXDISABLE | TULIP_WATCHDOG_RXDISABLE);
  1683. LMC_CSR_WRITE(sc, csr_sia_general, val);
  1684. lmc_trace(sc->lmc_device, "lmc_dec_reset out");
  1685. }
  1686. static void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, /*fold00*/
  1687. size_t csr_size)
  1688. {
  1689. lmc_trace(sc->lmc_device, "lmc_initcsrs in");
  1690. sc->lmc_csrs.csr_busmode = csr_base + 0 * csr_size;
  1691. sc->lmc_csrs.csr_txpoll = csr_base + 1 * csr_size;
  1692. sc->lmc_csrs.csr_rxpoll = csr_base + 2 * csr_size;
  1693. sc->lmc_csrs.csr_rxlist = csr_base + 3 * csr_size;
  1694. sc->lmc_csrs.csr_txlist = csr_base + 4 * csr_size;
  1695. sc->lmc_csrs.csr_status = csr_base + 5 * csr_size;
  1696. sc->lmc_csrs.csr_command = csr_base + 6 * csr_size;
  1697. sc->lmc_csrs.csr_intr = csr_base + 7 * csr_size;
  1698. sc->lmc_csrs.csr_missed_frames = csr_base + 8 * csr_size;
  1699. sc->lmc_csrs.csr_9 = csr_base + 9 * csr_size;
  1700. sc->lmc_csrs.csr_10 = csr_base + 10 * csr_size;
  1701. sc->lmc_csrs.csr_11 = csr_base + 11 * csr_size;
  1702. sc->lmc_csrs.csr_12 = csr_base + 12 * csr_size;
  1703. sc->lmc_csrs.csr_13 = csr_base + 13 * csr_size;
  1704. sc->lmc_csrs.csr_14 = csr_base + 14 * csr_size;
  1705. sc->lmc_csrs.csr_15 = csr_base + 15 * csr_size;
  1706. lmc_trace(sc->lmc_device, "lmc_initcsrs out");
  1707. }
  1708. static void lmc_driver_timeout(struct net_device *dev)
  1709. {
  1710. lmc_softc_t *sc = dev_to_sc(dev);
  1711. u32 csr6;
  1712. unsigned long flags;
  1713. lmc_trace(dev, "lmc_driver_timeout in");
  1714. spin_lock_irqsave(&sc->lmc_lock, flags);
  1715. printk("%s: Xmitter busy|\n", dev->name);
  1716. sc->extra_stats.tx_tbusy_calls++;
  1717. if (jiffies - dev->trans_start < TX_TIMEOUT)
  1718. goto bug_out;
  1719. /*
  1720. * Chip seems to have locked up
  1721. * Reset it
  1722. * This whips out all our decriptor
  1723. * table and starts from scartch
  1724. */
  1725. LMC_EVENT_LOG(LMC_EVENT_XMTPRCTMO,
  1726. LMC_CSR_READ (sc, csr_status),
  1727. sc->extra_stats.tx_ProcTimeout);
  1728. lmc_running_reset (dev);
  1729. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  1730. LMC_EVENT_LOG(LMC_EVENT_RESET2,
  1731. lmc_mii_readreg (sc, 0, 16),
  1732. lmc_mii_readreg (sc, 0, 17));
  1733. /* restart the tx processes */
  1734. csr6 = LMC_CSR_READ (sc, csr_command);
  1735. LMC_CSR_WRITE (sc, csr_command, csr6 | 0x0002);
  1736. LMC_CSR_WRITE (sc, csr_command, csr6 | 0x2002);
  1737. /* immediate transmit */
  1738. LMC_CSR_WRITE (sc, csr_txpoll, 0);
  1739. sc->lmc_device->stats.tx_errors++;
  1740. sc->extra_stats.tx_ProcTimeout++; /* -baz */
  1741. dev->trans_start = jiffies;
  1742. bug_out:
  1743. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1744. lmc_trace(dev, "lmc_driver_timout out");
  1745. }