smsc95xx.c 31 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2008 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. *
  19. *****************************************************************************/
  20. #include <linux/module.h>
  21. #include <linux/kmod.h>
  22. #include <linux/init.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/mii.h>
  27. #include <linux/usb.h>
  28. #include <linux/crc32.h>
  29. #include <linux/usb/usbnet.h>
  30. #include "smsc95xx.h"
  31. #define SMSC_CHIPNAME "smsc95xx"
  32. #define SMSC_DRIVER_VERSION "1.0.4"
  33. #define HS_USB_PKT_SIZE (512)
  34. #define FS_USB_PKT_SIZE (64)
  35. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  36. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  37. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  38. #define MAX_SINGLE_PACKET_SIZE (2048)
  39. #define LAN95XX_EEPROM_MAGIC (0x9500)
  40. #define EEPROM_MAC_OFFSET (0x01)
  41. #define DEFAULT_TX_CSUM_ENABLE (true)
  42. #define DEFAULT_RX_CSUM_ENABLE (true)
  43. #define SMSC95XX_INTERNAL_PHY_ID (1)
  44. #define SMSC95XX_TX_OVERHEAD (8)
  45. #define SMSC95XX_TX_OVERHEAD_CSUM (12)
  46. struct smsc95xx_priv {
  47. u32 mac_cr;
  48. spinlock_t mac_cr_lock;
  49. bool use_tx_csum;
  50. bool use_rx_csum;
  51. };
  52. struct usb_context {
  53. struct usb_ctrlrequest req;
  54. struct completion notify;
  55. struct usbnet *dev;
  56. };
  57. int turbo_mode = true;
  58. module_param(turbo_mode, bool, 0644);
  59. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  60. static int smsc95xx_read_reg(struct usbnet *dev, u32 index, u32 *data)
  61. {
  62. u32 *buf = kmalloc(4, GFP_KERNEL);
  63. int ret;
  64. BUG_ON(!dev);
  65. if (!buf)
  66. return -ENOMEM;
  67. ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
  68. USB_VENDOR_REQUEST_READ_REGISTER,
  69. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  70. 00, index, buf, 4, USB_CTRL_GET_TIMEOUT);
  71. if (unlikely(ret < 0))
  72. devwarn(dev, "Failed to read register index 0x%08x", index);
  73. le32_to_cpus(buf);
  74. *data = *buf;
  75. kfree(buf);
  76. return ret;
  77. }
  78. static int smsc95xx_write_reg(struct usbnet *dev, u32 index, u32 data)
  79. {
  80. u32 *buf = kmalloc(4, GFP_KERNEL);
  81. int ret;
  82. BUG_ON(!dev);
  83. if (!buf)
  84. return -ENOMEM;
  85. *buf = data;
  86. cpu_to_le32s(buf);
  87. ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
  88. USB_VENDOR_REQUEST_WRITE_REGISTER,
  89. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  90. 00, index, buf, 4, USB_CTRL_SET_TIMEOUT);
  91. if (unlikely(ret < 0))
  92. devwarn(dev, "Failed to write register index 0x%08x", index);
  93. kfree(buf);
  94. return ret;
  95. }
  96. /* Loop until the read is completed with timeout
  97. * called with phy_mutex held */
  98. static int smsc95xx_phy_wait_not_busy(struct usbnet *dev)
  99. {
  100. unsigned long start_time = jiffies;
  101. u32 val;
  102. do {
  103. smsc95xx_read_reg(dev, MII_ADDR, &val);
  104. if (!(val & MII_BUSY_))
  105. return 0;
  106. } while (!time_after(jiffies, start_time + HZ));
  107. return -EIO;
  108. }
  109. static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  110. {
  111. struct usbnet *dev = netdev_priv(netdev);
  112. u32 val, addr;
  113. mutex_lock(&dev->phy_mutex);
  114. /* confirm MII not busy */
  115. if (smsc95xx_phy_wait_not_busy(dev)) {
  116. devwarn(dev, "MII is busy in smsc95xx_mdio_read");
  117. mutex_unlock(&dev->phy_mutex);
  118. return -EIO;
  119. }
  120. /* set the address, index & direction (read from PHY) */
  121. phy_id &= dev->mii.phy_id_mask;
  122. idx &= dev->mii.reg_num_mask;
  123. addr = (phy_id << 11) | (idx << 6) | MII_READ_;
  124. smsc95xx_write_reg(dev, MII_ADDR, addr);
  125. if (smsc95xx_phy_wait_not_busy(dev)) {
  126. devwarn(dev, "Timed out reading MII reg %02X", idx);
  127. mutex_unlock(&dev->phy_mutex);
  128. return -EIO;
  129. }
  130. smsc95xx_read_reg(dev, MII_DATA, &val);
  131. mutex_unlock(&dev->phy_mutex);
  132. return (u16)(val & 0xFFFF);
  133. }
  134. static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  135. int regval)
  136. {
  137. struct usbnet *dev = netdev_priv(netdev);
  138. u32 val, addr;
  139. mutex_lock(&dev->phy_mutex);
  140. /* confirm MII not busy */
  141. if (smsc95xx_phy_wait_not_busy(dev)) {
  142. devwarn(dev, "MII is busy in smsc95xx_mdio_write");
  143. mutex_unlock(&dev->phy_mutex);
  144. return;
  145. }
  146. val = regval;
  147. smsc95xx_write_reg(dev, MII_DATA, val);
  148. /* set the address, index & direction (write to PHY) */
  149. phy_id &= dev->mii.phy_id_mask;
  150. idx &= dev->mii.reg_num_mask;
  151. addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
  152. smsc95xx_write_reg(dev, MII_ADDR, addr);
  153. if (smsc95xx_phy_wait_not_busy(dev))
  154. devwarn(dev, "Timed out writing MII reg %02X", idx);
  155. mutex_unlock(&dev->phy_mutex);
  156. }
  157. static int smsc95xx_wait_eeprom(struct usbnet *dev)
  158. {
  159. unsigned long start_time = jiffies;
  160. u32 val;
  161. do {
  162. smsc95xx_read_reg(dev, E2P_CMD, &val);
  163. if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
  164. break;
  165. udelay(40);
  166. } while (!time_after(jiffies, start_time + HZ));
  167. if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
  168. devwarn(dev, "EEPROM read operation timeout");
  169. return -EIO;
  170. }
  171. return 0;
  172. }
  173. static int smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev)
  174. {
  175. unsigned long start_time = jiffies;
  176. u32 val;
  177. do {
  178. smsc95xx_read_reg(dev, E2P_CMD, &val);
  179. if (!(val & E2P_CMD_LOADED_)) {
  180. devwarn(dev, "No EEPROM present");
  181. return -EIO;
  182. }
  183. if (!(val & E2P_CMD_BUSY_))
  184. return 0;
  185. udelay(40);
  186. } while (!time_after(jiffies, start_time + HZ));
  187. devwarn(dev, "EEPROM is busy");
  188. return -EIO;
  189. }
  190. static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  191. u8 *data)
  192. {
  193. u32 val;
  194. int i, ret;
  195. BUG_ON(!dev);
  196. BUG_ON(!data);
  197. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  198. if (ret)
  199. return ret;
  200. for (i = 0; i < length; i++) {
  201. val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
  202. smsc95xx_write_reg(dev, E2P_CMD, val);
  203. ret = smsc95xx_wait_eeprom(dev);
  204. if (ret < 0)
  205. return ret;
  206. smsc95xx_read_reg(dev, E2P_DATA, &val);
  207. data[i] = val & 0xFF;
  208. offset++;
  209. }
  210. return 0;
  211. }
  212. static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  213. u8 *data)
  214. {
  215. u32 val;
  216. int i, ret;
  217. BUG_ON(!dev);
  218. BUG_ON(!data);
  219. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  220. if (ret)
  221. return ret;
  222. /* Issue write/erase enable command */
  223. val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_;
  224. smsc95xx_write_reg(dev, E2P_CMD, val);
  225. ret = smsc95xx_wait_eeprom(dev);
  226. if (ret < 0)
  227. return ret;
  228. for (i = 0; i < length; i++) {
  229. /* Fill data register */
  230. val = data[i];
  231. smsc95xx_write_reg(dev, E2P_DATA, val);
  232. /* Send "write" command */
  233. val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_);
  234. smsc95xx_write_reg(dev, E2P_CMD, val);
  235. ret = smsc95xx_wait_eeprom(dev);
  236. if (ret < 0)
  237. return ret;
  238. offset++;
  239. }
  240. return 0;
  241. }
  242. static void smsc95xx_async_cmd_callback(struct urb *urb, struct pt_regs *regs)
  243. {
  244. struct usb_context *usb_context = urb->context;
  245. struct usbnet *dev = usb_context->dev;
  246. int status = urb->status;
  247. if (status < 0)
  248. devwarn(dev, "async callback failed with %d", status);
  249. complete(&usb_context->notify);
  250. kfree(usb_context);
  251. usb_free_urb(urb);
  252. }
  253. static int smsc95xx_write_reg_async(struct usbnet *dev, u16 index, u32 *data)
  254. {
  255. struct usb_context *usb_context;
  256. int status;
  257. struct urb *urb;
  258. const u16 size = 4;
  259. urb = usb_alloc_urb(0, GFP_ATOMIC);
  260. if (!urb) {
  261. devwarn(dev, "Error allocating URB");
  262. return -ENOMEM;
  263. }
  264. usb_context = kmalloc(sizeof(struct usb_context), GFP_ATOMIC);
  265. if (usb_context == NULL) {
  266. devwarn(dev, "Error allocating control msg");
  267. usb_free_urb(urb);
  268. return -ENOMEM;
  269. }
  270. usb_context->req.bRequestType =
  271. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE;
  272. usb_context->req.bRequest = USB_VENDOR_REQUEST_WRITE_REGISTER;
  273. usb_context->req.wValue = 00;
  274. usb_context->req.wIndex = cpu_to_le16(index);
  275. usb_context->req.wLength = cpu_to_le16(size);
  276. init_completion(&usb_context->notify);
  277. usb_fill_control_urb(urb, dev->udev, usb_sndctrlpipe(dev->udev, 0),
  278. (void *)&usb_context->req, data, size,
  279. (usb_complete_t)smsc95xx_async_cmd_callback,
  280. (void *)usb_context);
  281. status = usb_submit_urb(urb, GFP_ATOMIC);
  282. if (status < 0) {
  283. devwarn(dev, "Error submitting control msg, sts=%d", status);
  284. kfree(usb_context);
  285. usb_free_urb(urb);
  286. }
  287. return status;
  288. }
  289. /* returns hash bit number for given MAC address
  290. * example:
  291. * 01 00 5E 00 00 01 -> returns bit number 31 */
  292. static unsigned int smsc95xx_hash(char addr[ETH_ALEN])
  293. {
  294. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  295. }
  296. static void smsc95xx_set_multicast(struct net_device *netdev)
  297. {
  298. struct usbnet *dev = netdev_priv(netdev);
  299. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  300. u32 hash_hi = 0;
  301. u32 hash_lo = 0;
  302. unsigned long flags;
  303. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  304. if (dev->net->flags & IFF_PROMISC) {
  305. if (netif_msg_drv(dev))
  306. devdbg(dev, "promiscuous mode enabled");
  307. pdata->mac_cr |= MAC_CR_PRMS_;
  308. pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  309. } else if (dev->net->flags & IFF_ALLMULTI) {
  310. if (netif_msg_drv(dev))
  311. devdbg(dev, "receive all multicast enabled");
  312. pdata->mac_cr |= MAC_CR_MCPAS_;
  313. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  314. } else if (dev->net->mc_count > 0) {
  315. struct dev_mc_list *mc_list = dev->net->mc_list;
  316. int count = 0;
  317. pdata->mac_cr |= MAC_CR_HPFILT_;
  318. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  319. while (mc_list) {
  320. count++;
  321. if (mc_list->dmi_addrlen == ETH_ALEN) {
  322. u32 bitnum = smsc95xx_hash(mc_list->dmi_addr);
  323. u32 mask = 0x01 << (bitnum & 0x1F);
  324. if (bitnum & 0x20)
  325. hash_hi |= mask;
  326. else
  327. hash_lo |= mask;
  328. } else {
  329. devwarn(dev, "dmi_addrlen != 6");
  330. }
  331. mc_list = mc_list->next;
  332. }
  333. if (count != ((u32)dev->net->mc_count))
  334. devwarn(dev, "mc_count != dev->mc_count");
  335. if (netif_msg_drv(dev))
  336. devdbg(dev, "HASHH=0x%08X, HASHL=0x%08X", hash_hi,
  337. hash_lo);
  338. } else {
  339. if (netif_msg_drv(dev))
  340. devdbg(dev, "receive own packets only");
  341. pdata->mac_cr &=
  342. ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  343. }
  344. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  345. /* Initiate async writes, as we can't wait for completion here */
  346. smsc95xx_write_reg_async(dev, HASHH, &hash_hi);
  347. smsc95xx_write_reg_async(dev, HASHL, &hash_lo);
  348. smsc95xx_write_reg_async(dev, MAC_CR, &pdata->mac_cr);
  349. }
  350. static void smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex,
  351. u16 lcladv, u16 rmtadv)
  352. {
  353. u32 flow, afc_cfg = 0;
  354. int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg);
  355. if (ret < 0) {
  356. devwarn(dev, "error reading AFC_CFG");
  357. return;
  358. }
  359. if (duplex == DUPLEX_FULL) {
  360. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  361. if (cap & FLOW_CTRL_RX)
  362. flow = 0xFFFF0002;
  363. else
  364. flow = 0;
  365. if (cap & FLOW_CTRL_TX)
  366. afc_cfg |= 0xF;
  367. else
  368. afc_cfg &= ~0xF;
  369. if (netif_msg_link(dev))
  370. devdbg(dev, "rx pause %s, tx pause %s",
  371. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  372. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  373. } else {
  374. if (netif_msg_link(dev))
  375. devdbg(dev, "half duplex");
  376. flow = 0;
  377. afc_cfg |= 0xF;
  378. }
  379. smsc95xx_write_reg(dev, FLOW, flow);
  380. smsc95xx_write_reg(dev, AFC_CFG, afc_cfg);
  381. }
  382. static int smsc95xx_link_reset(struct usbnet *dev)
  383. {
  384. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  385. struct mii_if_info *mii = &dev->mii;
  386. struct ethtool_cmd ecmd;
  387. unsigned long flags;
  388. u16 lcladv, rmtadv;
  389. u32 intdata;
  390. /* clear interrupt status */
  391. smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC);
  392. intdata = 0xFFFFFFFF;
  393. smsc95xx_write_reg(dev, INT_STS, intdata);
  394. mii_check_media(mii, 1, 1);
  395. mii_ethtool_gset(&dev->mii, &ecmd);
  396. lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  397. rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  398. if (netif_msg_link(dev))
  399. devdbg(dev, "speed: %d duplex: %d lcladv: %04x rmtadv: %04x",
  400. ecmd.speed, ecmd.duplex, lcladv, rmtadv);
  401. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  402. if (ecmd.duplex != DUPLEX_FULL) {
  403. pdata->mac_cr &= ~MAC_CR_FDPX_;
  404. pdata->mac_cr |= MAC_CR_RCVOWN_;
  405. } else {
  406. pdata->mac_cr &= ~MAC_CR_RCVOWN_;
  407. pdata->mac_cr |= MAC_CR_FDPX_;
  408. }
  409. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  410. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  411. smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  412. return 0;
  413. }
  414. static void smsc95xx_status(struct usbnet *dev, struct urb *urb)
  415. {
  416. u32 intdata;
  417. if (urb->actual_length != 4) {
  418. devwarn(dev, "unexpected urb length %d", urb->actual_length);
  419. return;
  420. }
  421. memcpy(&intdata, urb->transfer_buffer, 4);
  422. le32_to_cpus(&intdata);
  423. if (netif_msg_link(dev))
  424. devdbg(dev, "intdata: 0x%08X", intdata);
  425. if (intdata & INT_ENP_PHY_INT_)
  426. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  427. else
  428. devwarn(dev, "unexpected interrupt, intdata=0x%08X", intdata);
  429. }
  430. /* Enable or disable Tx & Rx checksum offload engines */
  431. static int smsc95xx_set_csums(struct usbnet *dev)
  432. {
  433. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  434. u32 read_buf;
  435. int ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
  436. if (ret < 0) {
  437. devwarn(dev, "Failed to read COE_CR: %d", ret);
  438. return ret;
  439. }
  440. if (pdata->use_tx_csum)
  441. read_buf |= Tx_COE_EN_;
  442. else
  443. read_buf &= ~Tx_COE_EN_;
  444. if (pdata->use_rx_csum)
  445. read_buf |= Rx_COE_EN_;
  446. else
  447. read_buf &= ~Rx_COE_EN_;
  448. ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
  449. if (ret < 0) {
  450. devwarn(dev, "Failed to write COE_CR: %d", ret);
  451. return ret;
  452. }
  453. if (netif_msg_hw(dev))
  454. devdbg(dev, "COE_CR = 0x%08x", read_buf);
  455. return 0;
  456. }
  457. static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net)
  458. {
  459. return MAX_EEPROM_SIZE;
  460. }
  461. static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev,
  462. struct ethtool_eeprom *ee, u8 *data)
  463. {
  464. struct usbnet *dev = netdev_priv(netdev);
  465. ee->magic = LAN95XX_EEPROM_MAGIC;
  466. return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data);
  467. }
  468. static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev,
  469. struct ethtool_eeprom *ee, u8 *data)
  470. {
  471. struct usbnet *dev = netdev_priv(netdev);
  472. if (ee->magic != LAN95XX_EEPROM_MAGIC) {
  473. devwarn(dev, "EEPROM: magic value mismatch, magic = 0x%x",
  474. ee->magic);
  475. return -EINVAL;
  476. }
  477. return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data);
  478. }
  479. static u32 smsc95xx_ethtool_get_rx_csum(struct net_device *netdev)
  480. {
  481. struct usbnet *dev = netdev_priv(netdev);
  482. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  483. return pdata->use_rx_csum;
  484. }
  485. static int smsc95xx_ethtool_set_rx_csum(struct net_device *netdev, u32 val)
  486. {
  487. struct usbnet *dev = netdev_priv(netdev);
  488. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  489. pdata->use_rx_csum = !!val;
  490. return smsc95xx_set_csums(dev);
  491. }
  492. static u32 smsc95xx_ethtool_get_tx_csum(struct net_device *netdev)
  493. {
  494. struct usbnet *dev = netdev_priv(netdev);
  495. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  496. return pdata->use_tx_csum;
  497. }
  498. static int smsc95xx_ethtool_set_tx_csum(struct net_device *netdev, u32 val)
  499. {
  500. struct usbnet *dev = netdev_priv(netdev);
  501. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  502. pdata->use_tx_csum = !!val;
  503. ethtool_op_set_tx_hw_csum(netdev, pdata->use_tx_csum);
  504. return smsc95xx_set_csums(dev);
  505. }
  506. static struct ethtool_ops smsc95xx_ethtool_ops = {
  507. .get_link = usbnet_get_link,
  508. .nway_reset = usbnet_nway_reset,
  509. .get_drvinfo = usbnet_get_drvinfo,
  510. .get_msglevel = usbnet_get_msglevel,
  511. .set_msglevel = usbnet_set_msglevel,
  512. .get_settings = usbnet_get_settings,
  513. .set_settings = usbnet_set_settings,
  514. .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len,
  515. .get_eeprom = smsc95xx_ethtool_get_eeprom,
  516. .set_eeprom = smsc95xx_ethtool_set_eeprom,
  517. .get_tx_csum = smsc95xx_ethtool_get_tx_csum,
  518. .set_tx_csum = smsc95xx_ethtool_set_tx_csum,
  519. .get_rx_csum = smsc95xx_ethtool_get_rx_csum,
  520. .set_rx_csum = smsc95xx_ethtool_set_rx_csum,
  521. };
  522. static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  523. {
  524. struct usbnet *dev = netdev_priv(netdev);
  525. if (!netif_running(netdev))
  526. return -EINVAL;
  527. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  528. }
  529. static void smsc95xx_init_mac_address(struct usbnet *dev)
  530. {
  531. /* try reading mac address from EEPROM */
  532. if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  533. dev->net->dev_addr) == 0) {
  534. if (is_valid_ether_addr(dev->net->dev_addr)) {
  535. /* eeprom values are valid so use them */
  536. if (netif_msg_ifup(dev))
  537. devdbg(dev, "MAC address read from EEPROM");
  538. return;
  539. }
  540. }
  541. /* no eeprom, or eeprom values are invalid. generate random MAC */
  542. random_ether_addr(dev->net->dev_addr);
  543. if (netif_msg_ifup(dev))
  544. devdbg(dev, "MAC address set to random_ether_addr");
  545. }
  546. static int smsc95xx_set_mac_address(struct usbnet *dev)
  547. {
  548. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  549. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  550. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  551. int ret;
  552. ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
  553. if (ret < 0) {
  554. devwarn(dev, "Failed to write ADDRL: %d", ret);
  555. return ret;
  556. }
  557. ret = smsc95xx_write_reg(dev, ADDRH, addr_hi);
  558. if (ret < 0) {
  559. devwarn(dev, "Failed to write ADDRH: %d", ret);
  560. return ret;
  561. }
  562. return 0;
  563. }
  564. /* starts the TX path */
  565. static void smsc95xx_start_tx_path(struct usbnet *dev)
  566. {
  567. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  568. unsigned long flags;
  569. u32 reg_val;
  570. /* Enable Tx at MAC */
  571. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  572. pdata->mac_cr |= MAC_CR_TXEN_;
  573. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  574. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  575. /* Enable Tx at SCSRs */
  576. reg_val = TX_CFG_ON_;
  577. smsc95xx_write_reg(dev, TX_CFG, reg_val);
  578. }
  579. /* Starts the Receive path */
  580. static void smsc95xx_start_rx_path(struct usbnet *dev)
  581. {
  582. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  583. unsigned long flags;
  584. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  585. pdata->mac_cr |= MAC_CR_RXEN_;
  586. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  587. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  588. }
  589. static int smsc95xx_phy_initialize(struct usbnet *dev)
  590. {
  591. /* Initialize MII structure */
  592. dev->mii.dev = dev->net;
  593. dev->mii.mdio_read = smsc95xx_mdio_read;
  594. dev->mii.mdio_write = smsc95xx_mdio_write;
  595. dev->mii.phy_id_mask = 0x1f;
  596. dev->mii.reg_num_mask = 0x1f;
  597. dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID;
  598. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  599. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  600. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  601. ADVERTISE_PAUSE_ASYM);
  602. /* read to clear */
  603. smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  604. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  605. PHY_INT_MASK_DEFAULT_);
  606. mii_nway_restart(&dev->mii);
  607. if (netif_msg_ifup(dev))
  608. devdbg(dev, "phy initialised succesfully");
  609. return 0;
  610. }
  611. static int smsc95xx_reset(struct usbnet *dev)
  612. {
  613. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  614. struct net_device *netdev = dev->net;
  615. u32 read_buf, write_buf, burst_cap;
  616. int ret = 0, timeout;
  617. if (netif_msg_ifup(dev))
  618. devdbg(dev, "entering smsc95xx_reset");
  619. write_buf = HW_CFG_LRST_;
  620. ret = smsc95xx_write_reg(dev, HW_CFG, write_buf);
  621. if (ret < 0) {
  622. devwarn(dev, "Failed to write HW_CFG_LRST_ bit in HW_CFG "
  623. "register, ret = %d", ret);
  624. return ret;
  625. }
  626. timeout = 0;
  627. do {
  628. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  629. if (ret < 0) {
  630. devwarn(dev, "Failed to read HW_CFG: %d", ret);
  631. return ret;
  632. }
  633. msleep(10);
  634. timeout++;
  635. } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
  636. if (timeout >= 100) {
  637. devwarn(dev, "timeout waiting for completion of Lite Reset");
  638. return ret;
  639. }
  640. write_buf = PM_CTL_PHY_RST_;
  641. ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf);
  642. if (ret < 0) {
  643. devwarn(dev, "Failed to write PM_CTRL: %d", ret);
  644. return ret;
  645. }
  646. timeout = 0;
  647. do {
  648. ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
  649. if (ret < 0) {
  650. devwarn(dev, "Failed to read PM_CTRL: %d", ret);
  651. return ret;
  652. }
  653. msleep(10);
  654. timeout++;
  655. } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
  656. if (timeout >= 100) {
  657. devwarn(dev, "timeout waiting for PHY Reset");
  658. return ret;
  659. }
  660. smsc95xx_init_mac_address(dev);
  661. ret = smsc95xx_set_mac_address(dev);
  662. if (ret < 0)
  663. return ret;
  664. if (netif_msg_ifup(dev))
  665. devdbg(dev, "MAC Address: %pM", dev->net->dev_addr);
  666. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  667. if (ret < 0) {
  668. devwarn(dev, "Failed to read HW_CFG: %d", ret);
  669. return ret;
  670. }
  671. if (netif_msg_ifup(dev))
  672. devdbg(dev, "Read Value from HW_CFG : 0x%08x", read_buf);
  673. read_buf |= HW_CFG_BIR_;
  674. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  675. if (ret < 0) {
  676. devwarn(dev, "Failed to write HW_CFG_BIR_ bit in HW_CFG "
  677. "register, ret = %d", ret);
  678. return ret;
  679. }
  680. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  681. if (ret < 0) {
  682. devwarn(dev, "Failed to read HW_CFG: %d", ret);
  683. return ret;
  684. }
  685. if (netif_msg_ifup(dev))
  686. devdbg(dev, "Read Value from HW_CFG after writing "
  687. "HW_CFG_BIR_: 0x%08x", read_buf);
  688. if (!turbo_mode) {
  689. burst_cap = 0;
  690. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  691. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  692. burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  693. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  694. } else {
  695. burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  696. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  697. }
  698. if (netif_msg_ifup(dev))
  699. devdbg(dev, "rx_urb_size=%ld", (ulong)dev->rx_urb_size);
  700. ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
  701. if (ret < 0) {
  702. devwarn(dev, "Failed to write BURST_CAP: %d", ret);
  703. return ret;
  704. }
  705. ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
  706. if (ret < 0) {
  707. devwarn(dev, "Failed to read BURST_CAP: %d", ret);
  708. return ret;
  709. }
  710. if (netif_msg_ifup(dev))
  711. devdbg(dev, "Read Value from BURST_CAP after writing: 0x%08x",
  712. read_buf);
  713. read_buf = DEFAULT_BULK_IN_DELAY;
  714. ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf);
  715. if (ret < 0) {
  716. devwarn(dev, "ret = %d", ret);
  717. return ret;
  718. }
  719. ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
  720. if (ret < 0) {
  721. devwarn(dev, "Failed to read BULK_IN_DLY: %d", ret);
  722. return ret;
  723. }
  724. if (netif_msg_ifup(dev))
  725. devdbg(dev, "Read Value from BULK_IN_DLY after writing: "
  726. "0x%08x", read_buf);
  727. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  728. if (ret < 0) {
  729. devwarn(dev, "Failed to read HW_CFG: %d", ret);
  730. return ret;
  731. }
  732. if (netif_msg_ifup(dev))
  733. devdbg(dev, "Read Value from HW_CFG: 0x%08x", read_buf);
  734. if (turbo_mode)
  735. read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
  736. read_buf &= ~HW_CFG_RXDOFF_;
  737. /* set Rx data offset=2, Make IP header aligns on word boundary. */
  738. read_buf |= NET_IP_ALIGN << 9;
  739. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  740. if (ret < 0) {
  741. devwarn(dev, "Failed to write HW_CFG register, ret=%d", ret);
  742. return ret;
  743. }
  744. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  745. if (ret < 0) {
  746. devwarn(dev, "Failed to read HW_CFG: %d", ret);
  747. return ret;
  748. }
  749. if (netif_msg_ifup(dev))
  750. devdbg(dev, "Read Value from HW_CFG after writing: 0x%08x",
  751. read_buf);
  752. write_buf = 0xFFFFFFFF;
  753. ret = smsc95xx_write_reg(dev, INT_STS, write_buf);
  754. if (ret < 0) {
  755. devwarn(dev, "Failed to write INT_STS register, ret=%d", ret);
  756. return ret;
  757. }
  758. ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
  759. if (ret < 0) {
  760. devwarn(dev, "Failed to read ID_REV: %d", ret);
  761. return ret;
  762. }
  763. if (netif_msg_ifup(dev))
  764. devdbg(dev, "ID_REV = 0x%08x", read_buf);
  765. /* Init Tx */
  766. write_buf = 0;
  767. ret = smsc95xx_write_reg(dev, FLOW, write_buf);
  768. if (ret < 0) {
  769. devwarn(dev, "Failed to write FLOW: %d", ret);
  770. return ret;
  771. }
  772. read_buf = AFC_CFG_DEFAULT;
  773. ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf);
  774. if (ret < 0) {
  775. devwarn(dev, "Failed to write AFC_CFG: %d", ret);
  776. return ret;
  777. }
  778. /* Don't need mac_cr_lock during initialisation */
  779. ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr);
  780. if (ret < 0) {
  781. devwarn(dev, "Failed to read MAC_CR: %d", ret);
  782. return ret;
  783. }
  784. /* Init Rx */
  785. /* Set Vlan */
  786. write_buf = (u32)ETH_P_8021Q;
  787. ret = smsc95xx_write_reg(dev, VLAN1, write_buf);
  788. if (ret < 0) {
  789. devwarn(dev, "Failed to write VAN1: %d", ret);
  790. return ret;
  791. }
  792. /* Enable or disable checksum offload engines */
  793. ethtool_op_set_tx_hw_csum(netdev, pdata->use_tx_csum);
  794. ret = smsc95xx_set_csums(dev);
  795. if (ret < 0) {
  796. devwarn(dev, "Failed to set csum offload: %d", ret);
  797. return ret;
  798. }
  799. smsc95xx_set_multicast(dev->net);
  800. if (smsc95xx_phy_initialize(dev) < 0)
  801. return -EIO;
  802. ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
  803. if (ret < 0) {
  804. devwarn(dev, "Failed to read INT_EP_CTL: %d", ret);
  805. return ret;
  806. }
  807. /* enable PHY interrupts */
  808. read_buf |= INT_EP_CTL_PHY_INT_;
  809. ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
  810. if (ret < 0) {
  811. devwarn(dev, "Failed to write INT_EP_CTL: %d", ret);
  812. return ret;
  813. }
  814. smsc95xx_start_tx_path(dev);
  815. smsc95xx_start_rx_path(dev);
  816. if (netif_msg_ifup(dev))
  817. devdbg(dev, "smsc95xx_reset, return 0");
  818. return 0;
  819. }
  820. static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf)
  821. {
  822. struct smsc95xx_priv *pdata = NULL;
  823. int ret;
  824. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  825. ret = usbnet_get_endpoints(dev, intf);
  826. if (ret < 0) {
  827. devwarn(dev, "usbnet_get_endpoints failed: %d", ret);
  828. return ret;
  829. }
  830. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv),
  831. GFP_KERNEL);
  832. pdata = (struct smsc95xx_priv *)(dev->data[0]);
  833. if (!pdata) {
  834. devwarn(dev, "Unable to allocate struct smsc95xx_priv");
  835. return -ENOMEM;
  836. }
  837. spin_lock_init(&pdata->mac_cr_lock);
  838. pdata->use_tx_csum = DEFAULT_TX_CSUM_ENABLE;
  839. pdata->use_rx_csum = DEFAULT_RX_CSUM_ENABLE;
  840. /* Init all registers */
  841. ret = smsc95xx_reset(dev);
  842. dev->net->do_ioctl = smsc95xx_ioctl;
  843. dev->net->ethtool_ops = &smsc95xx_ethtool_ops;
  844. dev->net->set_multicast_list = smsc95xx_set_multicast;
  845. dev->net->flags |= IFF_MULTICAST;
  846. dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD;
  847. return 0;
  848. }
  849. static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  850. {
  851. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  852. if (pdata) {
  853. if (netif_msg_ifdown(dev))
  854. devdbg(dev, "free pdata");
  855. kfree(pdata);
  856. pdata = NULL;
  857. dev->data[0] = 0;
  858. }
  859. }
  860. static void smsc95xx_rx_csum_offload(struct sk_buff *skb)
  861. {
  862. skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2);
  863. skb->ip_summed = CHECKSUM_COMPLETE;
  864. skb_trim(skb, skb->len - 2);
  865. }
  866. static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  867. {
  868. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  869. while (skb->len > 0) {
  870. u32 header, align_count;
  871. struct sk_buff *ax_skb;
  872. unsigned char *packet;
  873. u16 size;
  874. memcpy(&header, skb->data, sizeof(header));
  875. le32_to_cpus(&header);
  876. skb_pull(skb, 4 + NET_IP_ALIGN);
  877. packet = skb->data;
  878. /* get the packet length */
  879. size = (u16)((header & RX_STS_FL_) >> 16);
  880. align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4;
  881. if (unlikely(header & RX_STS_ES_)) {
  882. if (netif_msg_rx_err(dev))
  883. devdbg(dev, "Error header=0x%08x", header);
  884. dev->stats.rx_errors++;
  885. dev->stats.rx_dropped++;
  886. if (header & RX_STS_CRC_) {
  887. dev->stats.rx_crc_errors++;
  888. } else {
  889. if (header & (RX_STS_TL_ | RX_STS_RF_))
  890. dev->stats.rx_frame_errors++;
  891. if ((header & RX_STS_LE_) &&
  892. (!(header & RX_STS_FT_)))
  893. dev->stats.rx_length_errors++;
  894. }
  895. } else {
  896. /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
  897. if (unlikely(size > (ETH_FRAME_LEN + 12))) {
  898. if (netif_msg_rx_err(dev))
  899. devdbg(dev, "size err header=0x%08x",
  900. header);
  901. return 0;
  902. }
  903. /* last frame in this batch */
  904. if (skb->len == size) {
  905. if (pdata->use_rx_csum)
  906. smsc95xx_rx_csum_offload(skb);
  907. skb->truesize = size + sizeof(struct sk_buff);
  908. return 1;
  909. }
  910. ax_skb = skb_clone(skb, GFP_ATOMIC);
  911. if (unlikely(!ax_skb)) {
  912. devwarn(dev, "Error allocating skb");
  913. return 0;
  914. }
  915. ax_skb->len = size;
  916. ax_skb->data = packet;
  917. skb_set_tail_pointer(ax_skb, size);
  918. if (pdata->use_rx_csum)
  919. smsc95xx_rx_csum_offload(ax_skb);
  920. ax_skb->truesize = size + sizeof(struct sk_buff);
  921. usbnet_skb_return(dev, ax_skb);
  922. }
  923. skb_pull(skb, size);
  924. /* padding bytes before the next frame starts */
  925. if (skb->len)
  926. skb_pull(skb, align_count);
  927. }
  928. if (unlikely(skb->len < 0)) {
  929. devwarn(dev, "invalid rx length<0 %d", skb->len);
  930. return 0;
  931. }
  932. return 1;
  933. }
  934. static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb)
  935. {
  936. int len = skb->data - skb->head;
  937. u16 high_16 = (u16)(skb->csum_offset + skb->csum_start - len);
  938. u16 low_16 = (u16)(skb->csum_start - len);
  939. return (high_16 << 16) | low_16;
  940. }
  941. static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev,
  942. struct sk_buff *skb, gfp_t flags)
  943. {
  944. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  945. bool csum = pdata->use_tx_csum && (skb->ip_summed == CHECKSUM_PARTIAL);
  946. int overhead = csum ? SMSC95XX_TX_OVERHEAD_CSUM : SMSC95XX_TX_OVERHEAD;
  947. u32 tx_cmd_a, tx_cmd_b;
  948. /* We do not advertise SG, so skbs should be already linearized */
  949. BUG_ON(skb_shinfo(skb)->nr_frags);
  950. if (skb_headroom(skb) < overhead) {
  951. struct sk_buff *skb2 = skb_copy_expand(skb,
  952. overhead, 0, flags);
  953. dev_kfree_skb_any(skb);
  954. skb = skb2;
  955. if (!skb)
  956. return NULL;
  957. }
  958. if (csum) {
  959. u32 csum_preamble = smsc95xx_calc_csum_preamble(skb);
  960. skb_push(skb, 4);
  961. memcpy(skb->data, &csum_preamble, 4);
  962. }
  963. skb_push(skb, 4);
  964. tx_cmd_b = (u32)(skb->len - 4);
  965. if (csum)
  966. tx_cmd_b |= TX_CMD_B_CSUM_ENABLE;
  967. cpu_to_le32s(&tx_cmd_b);
  968. memcpy(skb->data, &tx_cmd_b, 4);
  969. skb_push(skb, 4);
  970. tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ |
  971. TX_CMD_A_LAST_SEG_;
  972. cpu_to_le32s(&tx_cmd_a);
  973. memcpy(skb->data, &tx_cmd_a, 4);
  974. return skb;
  975. }
  976. static const struct driver_info smsc95xx_info = {
  977. .description = "smsc95xx USB 2.0 Ethernet",
  978. .bind = smsc95xx_bind,
  979. .unbind = smsc95xx_unbind,
  980. .link_reset = smsc95xx_link_reset,
  981. .reset = smsc95xx_reset,
  982. .rx_fixup = smsc95xx_rx_fixup,
  983. .tx_fixup = smsc95xx_tx_fixup,
  984. .status = smsc95xx_status,
  985. .flags = FLAG_ETHER,
  986. };
  987. static const struct usb_device_id products[] = {
  988. {
  989. /* SMSC9500 USB Ethernet Device */
  990. USB_DEVICE(0x0424, 0x9500),
  991. .driver_info = (unsigned long) &smsc95xx_info,
  992. },
  993. { }, /* END */
  994. };
  995. MODULE_DEVICE_TABLE(usb, products);
  996. static struct usb_driver smsc95xx_driver = {
  997. .name = "smsc95xx",
  998. .id_table = products,
  999. .probe = usbnet_probe,
  1000. .suspend = usbnet_suspend,
  1001. .resume = usbnet_resume,
  1002. .disconnect = usbnet_disconnect,
  1003. };
  1004. static int __init smsc95xx_init(void)
  1005. {
  1006. return usb_register(&smsc95xx_driver);
  1007. }
  1008. module_init(smsc95xx_init);
  1009. static void __exit smsc95xx_exit(void)
  1010. {
  1011. usb_deregister(&smsc95xx_driver);
  1012. }
  1013. module_exit(smsc95xx_exit);
  1014. MODULE_AUTHOR("Nancy Lin");
  1015. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@smsc.com>");
  1016. MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices");
  1017. MODULE_LICENSE("GPL");