tx.c 31 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2005-2008 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/pci.h>
  11. #include <linux/tcp.h>
  12. #include <linux/ip.h>
  13. #include <linux/in.h>
  14. #include <linux/if_ether.h>
  15. #include <linux/highmem.h>
  16. #include "net_driver.h"
  17. #include "tx.h"
  18. #include "efx.h"
  19. #include "falcon.h"
  20. #include "workarounds.h"
  21. /*
  22. * TX descriptor ring full threshold
  23. *
  24. * The tx_queue descriptor ring fill-level must fall below this value
  25. * before we restart the netif queue
  26. */
  27. #define EFX_NETDEV_TX_THRESHOLD(_tx_queue) \
  28. (_tx_queue->efx->type->txd_ring_mask / 2u)
  29. /* We want to be able to nest calls to netif_stop_queue(), since each
  30. * channel can have an individual stop on the queue.
  31. */
  32. void efx_stop_queue(struct efx_nic *efx)
  33. {
  34. spin_lock_bh(&efx->netif_stop_lock);
  35. EFX_TRACE(efx, "stop TX queue\n");
  36. atomic_inc(&efx->netif_stop_count);
  37. netif_stop_queue(efx->net_dev);
  38. spin_unlock_bh(&efx->netif_stop_lock);
  39. }
  40. /* Wake netif's TX queue
  41. * We want to be able to nest calls to netif_stop_queue(), since each
  42. * channel can have an individual stop on the queue.
  43. */
  44. void efx_wake_queue(struct efx_nic *efx)
  45. {
  46. local_bh_disable();
  47. if (atomic_dec_and_lock(&efx->netif_stop_count,
  48. &efx->netif_stop_lock)) {
  49. EFX_TRACE(efx, "waking TX queue\n");
  50. netif_wake_queue(efx->net_dev);
  51. spin_unlock(&efx->netif_stop_lock);
  52. }
  53. local_bh_enable();
  54. }
  55. static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
  56. struct efx_tx_buffer *buffer)
  57. {
  58. if (buffer->unmap_len) {
  59. struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
  60. dma_addr_t unmap_addr = (buffer->dma_addr + buffer->len -
  61. buffer->unmap_len);
  62. if (buffer->unmap_single)
  63. pci_unmap_single(pci_dev, unmap_addr, buffer->unmap_len,
  64. PCI_DMA_TODEVICE);
  65. else
  66. pci_unmap_page(pci_dev, unmap_addr, buffer->unmap_len,
  67. PCI_DMA_TODEVICE);
  68. buffer->unmap_len = 0;
  69. buffer->unmap_single = false;
  70. }
  71. if (buffer->skb) {
  72. dev_kfree_skb_any((struct sk_buff *) buffer->skb);
  73. buffer->skb = NULL;
  74. EFX_TRACE(tx_queue->efx, "TX queue %d transmission id %x "
  75. "complete\n", tx_queue->queue, read_ptr);
  76. }
  77. }
  78. /**
  79. * struct efx_tso_header - a DMA mapped buffer for packet headers
  80. * @next: Linked list of free ones.
  81. * The list is protected by the TX queue lock.
  82. * @dma_unmap_len: Length to unmap for an oversize buffer, or 0.
  83. * @dma_addr: The DMA address of the header below.
  84. *
  85. * This controls the memory used for a TSO header. Use TSOH_DATA()
  86. * to find the packet header data. Use TSOH_SIZE() to calculate the
  87. * total size required for a given packet header length. TSO headers
  88. * in the free list are exactly %TSOH_STD_SIZE bytes in size.
  89. */
  90. struct efx_tso_header {
  91. union {
  92. struct efx_tso_header *next;
  93. size_t unmap_len;
  94. };
  95. dma_addr_t dma_addr;
  96. };
  97. static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  98. struct sk_buff *skb);
  99. static void efx_fini_tso(struct efx_tx_queue *tx_queue);
  100. static void efx_tsoh_heap_free(struct efx_tx_queue *tx_queue,
  101. struct efx_tso_header *tsoh);
  102. static void efx_tsoh_free(struct efx_tx_queue *tx_queue,
  103. struct efx_tx_buffer *buffer)
  104. {
  105. if (buffer->tsoh) {
  106. if (likely(!buffer->tsoh->unmap_len)) {
  107. buffer->tsoh->next = tx_queue->tso_headers_free;
  108. tx_queue->tso_headers_free = buffer->tsoh;
  109. } else {
  110. efx_tsoh_heap_free(tx_queue, buffer->tsoh);
  111. }
  112. buffer->tsoh = NULL;
  113. }
  114. }
  115. /*
  116. * Add a socket buffer to a TX queue
  117. *
  118. * This maps all fragments of a socket buffer for DMA and adds them to
  119. * the TX queue. The queue's insert pointer will be incremented by
  120. * the number of fragments in the socket buffer.
  121. *
  122. * If any DMA mapping fails, any mapped fragments will be unmapped,
  123. * the queue's insert pointer will be restored to its original value.
  124. *
  125. * Returns NETDEV_TX_OK or NETDEV_TX_BUSY
  126. * You must hold netif_tx_lock() to call this function.
  127. */
  128. static int efx_enqueue_skb(struct efx_tx_queue *tx_queue,
  129. struct sk_buff *skb)
  130. {
  131. struct efx_nic *efx = tx_queue->efx;
  132. struct pci_dev *pci_dev = efx->pci_dev;
  133. struct efx_tx_buffer *buffer;
  134. skb_frag_t *fragment;
  135. struct page *page;
  136. int page_offset;
  137. unsigned int len, unmap_len = 0, fill_level, insert_ptr, misalign;
  138. dma_addr_t dma_addr, unmap_addr = 0;
  139. unsigned int dma_len;
  140. bool unmap_single;
  141. int q_space, i = 0;
  142. int rc = NETDEV_TX_OK;
  143. EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
  144. if (skb_shinfo((struct sk_buff *)skb)->gso_size)
  145. return efx_enqueue_skb_tso(tx_queue, skb);
  146. /* Get size of the initial fragment */
  147. len = skb_headlen(skb);
  148. fill_level = tx_queue->insert_count - tx_queue->old_read_count;
  149. q_space = efx->type->txd_ring_mask - 1 - fill_level;
  150. /* Map for DMA. Use pci_map_single rather than pci_map_page
  151. * since this is more efficient on machines with sparse
  152. * memory.
  153. */
  154. unmap_single = true;
  155. dma_addr = pci_map_single(pci_dev, skb->data, len, PCI_DMA_TODEVICE);
  156. /* Process all fragments */
  157. while (1) {
  158. if (unlikely(pci_dma_mapping_error(pci_dev, dma_addr)))
  159. goto pci_err;
  160. /* Store fields for marking in the per-fragment final
  161. * descriptor */
  162. unmap_len = len;
  163. unmap_addr = dma_addr;
  164. /* Add to TX queue, splitting across DMA boundaries */
  165. do {
  166. if (unlikely(q_space-- <= 0)) {
  167. /* It might be that completions have
  168. * happened since the xmit path last
  169. * checked. Update the xmit path's
  170. * copy of read_count.
  171. */
  172. ++tx_queue->stopped;
  173. /* This memory barrier protects the
  174. * change of stopped from the access
  175. * of read_count. */
  176. smp_mb();
  177. tx_queue->old_read_count =
  178. *(volatile unsigned *)
  179. &tx_queue->read_count;
  180. fill_level = (tx_queue->insert_count
  181. - tx_queue->old_read_count);
  182. q_space = (efx->type->txd_ring_mask - 1 -
  183. fill_level);
  184. if (unlikely(q_space-- <= 0))
  185. goto stop;
  186. smp_mb();
  187. --tx_queue->stopped;
  188. }
  189. insert_ptr = (tx_queue->insert_count &
  190. efx->type->txd_ring_mask);
  191. buffer = &tx_queue->buffer[insert_ptr];
  192. efx_tsoh_free(tx_queue, buffer);
  193. EFX_BUG_ON_PARANOID(buffer->tsoh);
  194. EFX_BUG_ON_PARANOID(buffer->skb);
  195. EFX_BUG_ON_PARANOID(buffer->len);
  196. EFX_BUG_ON_PARANOID(!buffer->continuation);
  197. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  198. dma_len = (((~dma_addr) & efx->type->tx_dma_mask) + 1);
  199. if (likely(dma_len > len))
  200. dma_len = len;
  201. misalign = (unsigned)dma_addr & efx->type->bug5391_mask;
  202. if (misalign && dma_len + misalign > 512)
  203. dma_len = 512 - misalign;
  204. /* Fill out per descriptor fields */
  205. buffer->len = dma_len;
  206. buffer->dma_addr = dma_addr;
  207. len -= dma_len;
  208. dma_addr += dma_len;
  209. ++tx_queue->insert_count;
  210. } while (len);
  211. /* Transfer ownership of the unmapping to the final buffer */
  212. buffer->unmap_single = unmap_single;
  213. buffer->unmap_len = unmap_len;
  214. unmap_len = 0;
  215. /* Get address and size of next fragment */
  216. if (i >= skb_shinfo(skb)->nr_frags)
  217. break;
  218. fragment = &skb_shinfo(skb)->frags[i];
  219. len = fragment->size;
  220. page = fragment->page;
  221. page_offset = fragment->page_offset;
  222. i++;
  223. /* Map for DMA */
  224. unmap_single = false;
  225. dma_addr = pci_map_page(pci_dev, page, page_offset, len,
  226. PCI_DMA_TODEVICE);
  227. }
  228. /* Transfer ownership of the skb to the final buffer */
  229. buffer->skb = skb;
  230. buffer->continuation = false;
  231. /* Pass off to hardware */
  232. falcon_push_buffers(tx_queue);
  233. return NETDEV_TX_OK;
  234. pci_err:
  235. EFX_ERR_RL(efx, " TX queue %d could not map skb with %d bytes %d "
  236. "fragments for DMA\n", tx_queue->queue, skb->len,
  237. skb_shinfo(skb)->nr_frags + 1);
  238. /* Mark the packet as transmitted, and free the SKB ourselves */
  239. dev_kfree_skb_any((struct sk_buff *)skb);
  240. goto unwind;
  241. stop:
  242. rc = NETDEV_TX_BUSY;
  243. if (tx_queue->stopped == 1)
  244. efx_stop_queue(efx);
  245. unwind:
  246. /* Work backwards until we hit the original insert pointer value */
  247. while (tx_queue->insert_count != tx_queue->write_count) {
  248. --tx_queue->insert_count;
  249. insert_ptr = tx_queue->insert_count & efx->type->txd_ring_mask;
  250. buffer = &tx_queue->buffer[insert_ptr];
  251. efx_dequeue_buffer(tx_queue, buffer);
  252. buffer->len = 0;
  253. }
  254. /* Free the fragment we were mid-way through pushing */
  255. if (unmap_len) {
  256. if (unmap_single)
  257. pci_unmap_single(pci_dev, unmap_addr, unmap_len,
  258. PCI_DMA_TODEVICE);
  259. else
  260. pci_unmap_page(pci_dev, unmap_addr, unmap_len,
  261. PCI_DMA_TODEVICE);
  262. }
  263. return rc;
  264. }
  265. /* Remove packets from the TX queue
  266. *
  267. * This removes packets from the TX queue, up to and including the
  268. * specified index.
  269. */
  270. static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
  271. unsigned int index)
  272. {
  273. struct efx_nic *efx = tx_queue->efx;
  274. unsigned int stop_index, read_ptr;
  275. unsigned int mask = tx_queue->efx->type->txd_ring_mask;
  276. stop_index = (index + 1) & mask;
  277. read_ptr = tx_queue->read_count & mask;
  278. while (read_ptr != stop_index) {
  279. struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
  280. if (unlikely(buffer->len == 0)) {
  281. EFX_ERR(tx_queue->efx, "TX queue %d spurious TX "
  282. "completion id %x\n", tx_queue->queue,
  283. read_ptr);
  284. efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
  285. return;
  286. }
  287. efx_dequeue_buffer(tx_queue, buffer);
  288. buffer->continuation = true;
  289. buffer->len = 0;
  290. ++tx_queue->read_count;
  291. read_ptr = tx_queue->read_count & mask;
  292. }
  293. }
  294. /* Initiate a packet transmission on the specified TX queue.
  295. * Note that returning anything other than NETDEV_TX_OK will cause the
  296. * OS to free the skb.
  297. *
  298. * This function is split out from efx_hard_start_xmit to allow the
  299. * loopback test to direct packets via specific TX queues. It is
  300. * therefore a non-static inline, so as not to penalise performance
  301. * for non-loopback transmissions.
  302. *
  303. * Context: netif_tx_lock held
  304. */
  305. inline int efx_xmit(struct efx_nic *efx,
  306. struct efx_tx_queue *tx_queue, struct sk_buff *skb)
  307. {
  308. int rc;
  309. /* Map fragments for DMA and add to TX queue */
  310. rc = efx_enqueue_skb(tx_queue, skb);
  311. if (unlikely(rc != NETDEV_TX_OK))
  312. goto out;
  313. /* Update last TX timer */
  314. efx->net_dev->trans_start = jiffies;
  315. out:
  316. return rc;
  317. }
  318. /* Initiate a packet transmission. We use one channel per CPU
  319. * (sharing when we have more CPUs than channels). On Falcon, the TX
  320. * completion events will be directed back to the CPU that transmitted
  321. * the packet, which should be cache-efficient.
  322. *
  323. * Context: non-blocking.
  324. * Note that returning anything other than NETDEV_TX_OK will cause the
  325. * OS to free the skb.
  326. */
  327. int efx_hard_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
  328. {
  329. struct efx_nic *efx = netdev_priv(net_dev);
  330. struct efx_tx_queue *tx_queue;
  331. if (likely(skb->ip_summed == CHECKSUM_PARTIAL))
  332. tx_queue = &efx->tx_queue[EFX_TX_QUEUE_OFFLOAD_CSUM];
  333. else
  334. tx_queue = &efx->tx_queue[EFX_TX_QUEUE_NO_CSUM];
  335. return efx_xmit(efx, tx_queue, skb);
  336. }
  337. void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
  338. {
  339. unsigned fill_level;
  340. struct efx_nic *efx = tx_queue->efx;
  341. EFX_BUG_ON_PARANOID(index > efx->type->txd_ring_mask);
  342. efx_dequeue_buffers(tx_queue, index);
  343. /* See if we need to restart the netif queue. This barrier
  344. * separates the update of read_count from the test of
  345. * stopped. */
  346. smp_mb();
  347. if (unlikely(tx_queue->stopped)) {
  348. fill_level = tx_queue->insert_count - tx_queue->read_count;
  349. if (fill_level < EFX_NETDEV_TX_THRESHOLD(tx_queue)) {
  350. EFX_BUG_ON_PARANOID(!efx_dev_registered(efx));
  351. /* Do this under netif_tx_lock(), to avoid racing
  352. * with efx_xmit(). */
  353. netif_tx_lock(efx->net_dev);
  354. if (tx_queue->stopped) {
  355. tx_queue->stopped = 0;
  356. efx_wake_queue(efx);
  357. }
  358. netif_tx_unlock(efx->net_dev);
  359. }
  360. }
  361. }
  362. int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
  363. {
  364. struct efx_nic *efx = tx_queue->efx;
  365. unsigned int txq_size;
  366. int i, rc;
  367. EFX_LOG(efx, "creating TX queue %d\n", tx_queue->queue);
  368. /* Allocate software ring */
  369. txq_size = (efx->type->txd_ring_mask + 1) * sizeof(*tx_queue->buffer);
  370. tx_queue->buffer = kzalloc(txq_size, GFP_KERNEL);
  371. if (!tx_queue->buffer)
  372. return -ENOMEM;
  373. for (i = 0; i <= efx->type->txd_ring_mask; ++i)
  374. tx_queue->buffer[i].continuation = true;
  375. /* Allocate hardware ring */
  376. rc = falcon_probe_tx(tx_queue);
  377. if (rc)
  378. goto fail;
  379. return 0;
  380. fail:
  381. kfree(tx_queue->buffer);
  382. tx_queue->buffer = NULL;
  383. return rc;
  384. }
  385. void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
  386. {
  387. EFX_LOG(tx_queue->efx, "initialising TX queue %d\n", tx_queue->queue);
  388. tx_queue->insert_count = 0;
  389. tx_queue->write_count = 0;
  390. tx_queue->read_count = 0;
  391. tx_queue->old_read_count = 0;
  392. BUG_ON(tx_queue->stopped);
  393. /* Set up TX descriptor ring */
  394. falcon_init_tx(tx_queue);
  395. }
  396. void efx_release_tx_buffers(struct efx_tx_queue *tx_queue)
  397. {
  398. struct efx_tx_buffer *buffer;
  399. if (!tx_queue->buffer)
  400. return;
  401. /* Free any buffers left in the ring */
  402. while (tx_queue->read_count != tx_queue->write_count) {
  403. buffer = &tx_queue->buffer[tx_queue->read_count &
  404. tx_queue->efx->type->txd_ring_mask];
  405. efx_dequeue_buffer(tx_queue, buffer);
  406. buffer->continuation = true;
  407. buffer->len = 0;
  408. ++tx_queue->read_count;
  409. }
  410. }
  411. void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
  412. {
  413. EFX_LOG(tx_queue->efx, "shutting down TX queue %d\n", tx_queue->queue);
  414. /* Flush TX queue, remove descriptor ring */
  415. falcon_fini_tx(tx_queue);
  416. efx_release_tx_buffers(tx_queue);
  417. /* Free up TSO header cache */
  418. efx_fini_tso(tx_queue);
  419. /* Release queue's stop on port, if any */
  420. if (tx_queue->stopped) {
  421. tx_queue->stopped = 0;
  422. efx_wake_queue(tx_queue->efx);
  423. }
  424. }
  425. void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
  426. {
  427. EFX_LOG(tx_queue->efx, "destroying TX queue %d\n", tx_queue->queue);
  428. falcon_remove_tx(tx_queue);
  429. kfree(tx_queue->buffer);
  430. tx_queue->buffer = NULL;
  431. }
  432. /* Efx TCP segmentation acceleration.
  433. *
  434. * Why? Because by doing it here in the driver we can go significantly
  435. * faster than the GSO.
  436. *
  437. * Requires TX checksum offload support.
  438. */
  439. /* Number of bytes inserted at the start of a TSO header buffer,
  440. * similar to NET_IP_ALIGN.
  441. */
  442. #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  443. #define TSOH_OFFSET 0
  444. #else
  445. #define TSOH_OFFSET NET_IP_ALIGN
  446. #endif
  447. #define TSOH_BUFFER(tsoh) ((u8 *)(tsoh + 1) + TSOH_OFFSET)
  448. /* Total size of struct efx_tso_header, buffer and padding */
  449. #define TSOH_SIZE(hdr_len) \
  450. (sizeof(struct efx_tso_header) + TSOH_OFFSET + hdr_len)
  451. /* Size of blocks on free list. Larger blocks must be allocated from
  452. * the heap.
  453. */
  454. #define TSOH_STD_SIZE 128
  455. #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2))
  456. #define ETH_HDR_LEN(skb) (skb_network_header(skb) - (skb)->data)
  457. #define SKB_TCP_OFF(skb) PTR_DIFF(tcp_hdr(skb), (skb)->data)
  458. #define SKB_IPV4_OFF(skb) PTR_DIFF(ip_hdr(skb), (skb)->data)
  459. /**
  460. * struct tso_state - TSO state for an SKB
  461. * @out_len: Remaining length in current segment
  462. * @seqnum: Current sequence number
  463. * @ipv4_id: Current IPv4 ID, host endian
  464. * @packet_space: Remaining space in current packet
  465. * @dma_addr: DMA address of current position
  466. * @in_len: Remaining length in current SKB fragment
  467. * @unmap_len: Length of SKB fragment
  468. * @unmap_addr: DMA address of SKB fragment
  469. * @unmap_single: DMA single vs page mapping flag
  470. * @header_len: Number of bytes of header
  471. * @full_packet_size: Number of bytes to put in each outgoing segment
  472. *
  473. * The state used during segmentation. It is put into this data structure
  474. * just to make it easy to pass into inline functions.
  475. */
  476. struct tso_state {
  477. /* Output position */
  478. unsigned out_len;
  479. unsigned seqnum;
  480. unsigned ipv4_id;
  481. unsigned packet_space;
  482. /* Input position */
  483. dma_addr_t dma_addr;
  484. unsigned in_len;
  485. unsigned unmap_len;
  486. dma_addr_t unmap_addr;
  487. bool unmap_single;
  488. unsigned header_len;
  489. int full_packet_size;
  490. };
  491. /*
  492. * Verify that our various assumptions about sk_buffs and the conditions
  493. * under which TSO will be attempted hold true.
  494. */
  495. static void efx_tso_check_safe(struct sk_buff *skb)
  496. {
  497. __be16 protocol = skb->protocol;
  498. EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto !=
  499. protocol);
  500. if (protocol == htons(ETH_P_8021Q)) {
  501. /* Find the encapsulated protocol; reset network header
  502. * and transport header based on that. */
  503. struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data;
  504. protocol = veh->h_vlan_encapsulated_proto;
  505. skb_set_network_header(skb, sizeof(*veh));
  506. if (protocol == htons(ETH_P_IP))
  507. skb_set_transport_header(skb, sizeof(*veh) +
  508. 4 * ip_hdr(skb)->ihl);
  509. }
  510. EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IP));
  511. EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP);
  512. EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data)
  513. + (tcp_hdr(skb)->doff << 2u)) >
  514. skb_headlen(skb));
  515. }
  516. /*
  517. * Allocate a page worth of efx_tso_header structures, and string them
  518. * into the tx_queue->tso_headers_free linked list. Return 0 or -ENOMEM.
  519. */
  520. static int efx_tsoh_block_alloc(struct efx_tx_queue *tx_queue)
  521. {
  522. struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
  523. struct efx_tso_header *tsoh;
  524. dma_addr_t dma_addr;
  525. u8 *base_kva, *kva;
  526. base_kva = pci_alloc_consistent(pci_dev, PAGE_SIZE, &dma_addr);
  527. if (base_kva == NULL) {
  528. EFX_ERR(tx_queue->efx, "Unable to allocate page for TSO"
  529. " headers\n");
  530. return -ENOMEM;
  531. }
  532. /* pci_alloc_consistent() allocates pages. */
  533. EFX_BUG_ON_PARANOID(dma_addr & (PAGE_SIZE - 1u));
  534. for (kva = base_kva; kva < base_kva + PAGE_SIZE; kva += TSOH_STD_SIZE) {
  535. tsoh = (struct efx_tso_header *)kva;
  536. tsoh->dma_addr = dma_addr + (TSOH_BUFFER(tsoh) - base_kva);
  537. tsoh->next = tx_queue->tso_headers_free;
  538. tx_queue->tso_headers_free = tsoh;
  539. }
  540. return 0;
  541. }
  542. /* Free up a TSO header, and all others in the same page. */
  543. static void efx_tsoh_block_free(struct efx_tx_queue *tx_queue,
  544. struct efx_tso_header *tsoh,
  545. struct pci_dev *pci_dev)
  546. {
  547. struct efx_tso_header **p;
  548. unsigned long base_kva;
  549. dma_addr_t base_dma;
  550. base_kva = (unsigned long)tsoh & PAGE_MASK;
  551. base_dma = tsoh->dma_addr & PAGE_MASK;
  552. p = &tx_queue->tso_headers_free;
  553. while (*p != NULL) {
  554. if (((unsigned long)*p & PAGE_MASK) == base_kva)
  555. *p = (*p)->next;
  556. else
  557. p = &(*p)->next;
  558. }
  559. pci_free_consistent(pci_dev, PAGE_SIZE, (void *)base_kva, base_dma);
  560. }
  561. static struct efx_tso_header *
  562. efx_tsoh_heap_alloc(struct efx_tx_queue *tx_queue, size_t header_len)
  563. {
  564. struct efx_tso_header *tsoh;
  565. tsoh = kmalloc(TSOH_SIZE(header_len), GFP_ATOMIC | GFP_DMA);
  566. if (unlikely(!tsoh))
  567. return NULL;
  568. tsoh->dma_addr = pci_map_single(tx_queue->efx->pci_dev,
  569. TSOH_BUFFER(tsoh), header_len,
  570. PCI_DMA_TODEVICE);
  571. if (unlikely(pci_dma_mapping_error(tx_queue->efx->pci_dev,
  572. tsoh->dma_addr))) {
  573. kfree(tsoh);
  574. return NULL;
  575. }
  576. tsoh->unmap_len = header_len;
  577. return tsoh;
  578. }
  579. static void
  580. efx_tsoh_heap_free(struct efx_tx_queue *tx_queue, struct efx_tso_header *tsoh)
  581. {
  582. pci_unmap_single(tx_queue->efx->pci_dev,
  583. tsoh->dma_addr, tsoh->unmap_len,
  584. PCI_DMA_TODEVICE);
  585. kfree(tsoh);
  586. }
  587. /**
  588. * efx_tx_queue_insert - push descriptors onto the TX queue
  589. * @tx_queue: Efx TX queue
  590. * @dma_addr: DMA address of fragment
  591. * @len: Length of fragment
  592. * @final_buffer: The final buffer inserted into the queue
  593. *
  594. * Push descriptors onto the TX queue. Return 0 on success or 1 if
  595. * @tx_queue full.
  596. */
  597. static int efx_tx_queue_insert(struct efx_tx_queue *tx_queue,
  598. dma_addr_t dma_addr, unsigned len,
  599. struct efx_tx_buffer **final_buffer)
  600. {
  601. struct efx_tx_buffer *buffer;
  602. struct efx_nic *efx = tx_queue->efx;
  603. unsigned dma_len, fill_level, insert_ptr, misalign;
  604. int q_space;
  605. EFX_BUG_ON_PARANOID(len <= 0);
  606. fill_level = tx_queue->insert_count - tx_queue->old_read_count;
  607. /* -1 as there is no way to represent all descriptors used */
  608. q_space = efx->type->txd_ring_mask - 1 - fill_level;
  609. while (1) {
  610. if (unlikely(q_space-- <= 0)) {
  611. /* It might be that completions have happened
  612. * since the xmit path last checked. Update
  613. * the xmit path's copy of read_count.
  614. */
  615. ++tx_queue->stopped;
  616. /* This memory barrier protects the change of
  617. * stopped from the access of read_count. */
  618. smp_mb();
  619. tx_queue->old_read_count =
  620. *(volatile unsigned *)&tx_queue->read_count;
  621. fill_level = (tx_queue->insert_count
  622. - tx_queue->old_read_count);
  623. q_space = efx->type->txd_ring_mask - 1 - fill_level;
  624. if (unlikely(q_space-- <= 0)) {
  625. *final_buffer = NULL;
  626. return 1;
  627. }
  628. smp_mb();
  629. --tx_queue->stopped;
  630. }
  631. insert_ptr = tx_queue->insert_count & efx->type->txd_ring_mask;
  632. buffer = &tx_queue->buffer[insert_ptr];
  633. ++tx_queue->insert_count;
  634. EFX_BUG_ON_PARANOID(tx_queue->insert_count -
  635. tx_queue->read_count >
  636. efx->type->txd_ring_mask);
  637. efx_tsoh_free(tx_queue, buffer);
  638. EFX_BUG_ON_PARANOID(buffer->len);
  639. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  640. EFX_BUG_ON_PARANOID(buffer->skb);
  641. EFX_BUG_ON_PARANOID(!buffer->continuation);
  642. EFX_BUG_ON_PARANOID(buffer->tsoh);
  643. buffer->dma_addr = dma_addr;
  644. /* Ensure we do not cross a boundary unsupported by H/W */
  645. dma_len = (~dma_addr & efx->type->tx_dma_mask) + 1;
  646. misalign = (unsigned)dma_addr & efx->type->bug5391_mask;
  647. if (misalign && dma_len + misalign > 512)
  648. dma_len = 512 - misalign;
  649. /* If there is enough space to send then do so */
  650. if (dma_len >= len)
  651. break;
  652. buffer->len = dma_len; /* Don't set the other members */
  653. dma_addr += dma_len;
  654. len -= dma_len;
  655. }
  656. EFX_BUG_ON_PARANOID(!len);
  657. buffer->len = len;
  658. *final_buffer = buffer;
  659. return 0;
  660. }
  661. /*
  662. * Put a TSO header into the TX queue.
  663. *
  664. * This is special-cased because we know that it is small enough to fit in
  665. * a single fragment, and we know it doesn't cross a page boundary. It
  666. * also allows us to not worry about end-of-packet etc.
  667. */
  668. static void efx_tso_put_header(struct efx_tx_queue *tx_queue,
  669. struct efx_tso_header *tsoh, unsigned len)
  670. {
  671. struct efx_tx_buffer *buffer;
  672. buffer = &tx_queue->buffer[tx_queue->insert_count &
  673. tx_queue->efx->type->txd_ring_mask];
  674. efx_tsoh_free(tx_queue, buffer);
  675. EFX_BUG_ON_PARANOID(buffer->len);
  676. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  677. EFX_BUG_ON_PARANOID(buffer->skb);
  678. EFX_BUG_ON_PARANOID(!buffer->continuation);
  679. EFX_BUG_ON_PARANOID(buffer->tsoh);
  680. buffer->len = len;
  681. buffer->dma_addr = tsoh->dma_addr;
  682. buffer->tsoh = tsoh;
  683. ++tx_queue->insert_count;
  684. }
  685. /* Remove descriptors put into a tx_queue. */
  686. static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue)
  687. {
  688. struct efx_tx_buffer *buffer;
  689. dma_addr_t unmap_addr;
  690. /* Work backwards until we hit the original insert pointer value */
  691. while (tx_queue->insert_count != tx_queue->write_count) {
  692. --tx_queue->insert_count;
  693. buffer = &tx_queue->buffer[tx_queue->insert_count &
  694. tx_queue->efx->type->txd_ring_mask];
  695. efx_tsoh_free(tx_queue, buffer);
  696. EFX_BUG_ON_PARANOID(buffer->skb);
  697. buffer->len = 0;
  698. buffer->continuation = true;
  699. if (buffer->unmap_len) {
  700. unmap_addr = (buffer->dma_addr + buffer->len -
  701. buffer->unmap_len);
  702. if (buffer->unmap_single)
  703. pci_unmap_single(tx_queue->efx->pci_dev,
  704. unmap_addr, buffer->unmap_len,
  705. PCI_DMA_TODEVICE);
  706. else
  707. pci_unmap_page(tx_queue->efx->pci_dev,
  708. unmap_addr, buffer->unmap_len,
  709. PCI_DMA_TODEVICE);
  710. buffer->unmap_len = 0;
  711. }
  712. }
  713. }
  714. /* Parse the SKB header and initialise state. */
  715. static void tso_start(struct tso_state *st, const struct sk_buff *skb)
  716. {
  717. /* All ethernet/IP/TCP headers combined size is TCP header size
  718. * plus offset of TCP header relative to start of packet.
  719. */
  720. st->header_len = ((tcp_hdr(skb)->doff << 2u)
  721. + PTR_DIFF(tcp_hdr(skb), skb->data));
  722. st->full_packet_size = st->header_len + skb_shinfo(skb)->gso_size;
  723. st->ipv4_id = ntohs(ip_hdr(skb)->id);
  724. st->seqnum = ntohl(tcp_hdr(skb)->seq);
  725. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg);
  726. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn);
  727. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst);
  728. st->packet_space = st->full_packet_size;
  729. st->out_len = skb->len - st->header_len;
  730. st->unmap_len = 0;
  731. st->unmap_single = false;
  732. }
  733. static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx,
  734. skb_frag_t *frag)
  735. {
  736. st->unmap_addr = pci_map_page(efx->pci_dev, frag->page,
  737. frag->page_offset, frag->size,
  738. PCI_DMA_TODEVICE);
  739. if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) {
  740. st->unmap_single = false;
  741. st->unmap_len = frag->size;
  742. st->in_len = frag->size;
  743. st->dma_addr = st->unmap_addr;
  744. return 0;
  745. }
  746. return -ENOMEM;
  747. }
  748. static int tso_get_head_fragment(struct tso_state *st, struct efx_nic *efx,
  749. const struct sk_buff *skb)
  750. {
  751. int hl = st->header_len;
  752. int len = skb_headlen(skb) - hl;
  753. st->unmap_addr = pci_map_single(efx->pci_dev, skb->data + hl,
  754. len, PCI_DMA_TODEVICE);
  755. if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) {
  756. st->unmap_single = true;
  757. st->unmap_len = len;
  758. st->in_len = len;
  759. st->dma_addr = st->unmap_addr;
  760. return 0;
  761. }
  762. return -ENOMEM;
  763. }
  764. /**
  765. * tso_fill_packet_with_fragment - form descriptors for the current fragment
  766. * @tx_queue: Efx TX queue
  767. * @skb: Socket buffer
  768. * @st: TSO state
  769. *
  770. * Form descriptors for the current fragment, until we reach the end
  771. * of fragment or end-of-packet. Return 0 on success, 1 if not enough
  772. * space in @tx_queue.
  773. */
  774. static int tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue,
  775. const struct sk_buff *skb,
  776. struct tso_state *st)
  777. {
  778. struct efx_tx_buffer *buffer;
  779. int n, end_of_packet, rc;
  780. if (st->in_len == 0)
  781. return 0;
  782. if (st->packet_space == 0)
  783. return 0;
  784. EFX_BUG_ON_PARANOID(st->in_len <= 0);
  785. EFX_BUG_ON_PARANOID(st->packet_space <= 0);
  786. n = min(st->in_len, st->packet_space);
  787. st->packet_space -= n;
  788. st->out_len -= n;
  789. st->in_len -= n;
  790. rc = efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer);
  791. if (likely(rc == 0)) {
  792. if (st->out_len == 0)
  793. /* Transfer ownership of the skb */
  794. buffer->skb = skb;
  795. end_of_packet = st->out_len == 0 || st->packet_space == 0;
  796. buffer->continuation = !end_of_packet;
  797. if (st->in_len == 0) {
  798. /* Transfer ownership of the pci mapping */
  799. buffer->unmap_len = st->unmap_len;
  800. buffer->unmap_single = st->unmap_single;
  801. st->unmap_len = 0;
  802. }
  803. }
  804. st->dma_addr += n;
  805. return rc;
  806. }
  807. /**
  808. * tso_start_new_packet - generate a new header and prepare for the new packet
  809. * @tx_queue: Efx TX queue
  810. * @skb: Socket buffer
  811. * @st: TSO state
  812. *
  813. * Generate a new header and prepare for the new packet. Return 0 on
  814. * success, or -1 if failed to alloc header.
  815. */
  816. static int tso_start_new_packet(struct efx_tx_queue *tx_queue,
  817. const struct sk_buff *skb,
  818. struct tso_state *st)
  819. {
  820. struct efx_tso_header *tsoh;
  821. struct iphdr *tsoh_iph;
  822. struct tcphdr *tsoh_th;
  823. unsigned ip_length;
  824. u8 *header;
  825. /* Allocate a DMA-mapped header buffer. */
  826. if (likely(TSOH_SIZE(st->header_len) <= TSOH_STD_SIZE)) {
  827. if (tx_queue->tso_headers_free == NULL) {
  828. if (efx_tsoh_block_alloc(tx_queue))
  829. return -1;
  830. }
  831. EFX_BUG_ON_PARANOID(!tx_queue->tso_headers_free);
  832. tsoh = tx_queue->tso_headers_free;
  833. tx_queue->tso_headers_free = tsoh->next;
  834. tsoh->unmap_len = 0;
  835. } else {
  836. tx_queue->tso_long_headers++;
  837. tsoh = efx_tsoh_heap_alloc(tx_queue, st->header_len);
  838. if (unlikely(!tsoh))
  839. return -1;
  840. }
  841. header = TSOH_BUFFER(tsoh);
  842. tsoh_th = (struct tcphdr *)(header + SKB_TCP_OFF(skb));
  843. tsoh_iph = (struct iphdr *)(header + SKB_IPV4_OFF(skb));
  844. /* Copy and update the headers. */
  845. memcpy(header, skb->data, st->header_len);
  846. tsoh_th->seq = htonl(st->seqnum);
  847. st->seqnum += skb_shinfo(skb)->gso_size;
  848. if (st->out_len > skb_shinfo(skb)->gso_size) {
  849. /* This packet will not finish the TSO burst. */
  850. ip_length = st->full_packet_size - ETH_HDR_LEN(skb);
  851. tsoh_th->fin = 0;
  852. tsoh_th->psh = 0;
  853. } else {
  854. /* This packet will be the last in the TSO burst. */
  855. ip_length = st->header_len - ETH_HDR_LEN(skb) + st->out_len;
  856. tsoh_th->fin = tcp_hdr(skb)->fin;
  857. tsoh_th->psh = tcp_hdr(skb)->psh;
  858. }
  859. tsoh_iph->tot_len = htons(ip_length);
  860. /* Linux leaves suitable gaps in the IP ID space for us to fill. */
  861. tsoh_iph->id = htons(st->ipv4_id);
  862. st->ipv4_id++;
  863. st->packet_space = skb_shinfo(skb)->gso_size;
  864. ++tx_queue->tso_packets;
  865. /* Form a descriptor for this header. */
  866. efx_tso_put_header(tx_queue, tsoh, st->header_len);
  867. return 0;
  868. }
  869. /**
  870. * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer
  871. * @tx_queue: Efx TX queue
  872. * @skb: Socket buffer
  873. *
  874. * Context: You must hold netif_tx_lock() to call this function.
  875. *
  876. * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if
  877. * @skb was not enqueued. In all cases @skb is consumed. Return
  878. * %NETDEV_TX_OK or %NETDEV_TX_BUSY.
  879. */
  880. static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  881. struct sk_buff *skb)
  882. {
  883. struct efx_nic *efx = tx_queue->efx;
  884. int frag_i, rc, rc2 = NETDEV_TX_OK;
  885. struct tso_state state;
  886. /* Verify TSO is safe - these checks should never fail. */
  887. efx_tso_check_safe(skb);
  888. EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
  889. tso_start(&state, skb);
  890. /* Assume that skb header area contains exactly the headers, and
  891. * all payload is in the frag list.
  892. */
  893. if (skb_headlen(skb) == state.header_len) {
  894. /* Grab the first payload fragment. */
  895. EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1);
  896. frag_i = 0;
  897. rc = tso_get_fragment(&state, efx,
  898. skb_shinfo(skb)->frags + frag_i);
  899. if (rc)
  900. goto mem_err;
  901. } else {
  902. rc = tso_get_head_fragment(&state, efx, skb);
  903. if (rc)
  904. goto mem_err;
  905. frag_i = -1;
  906. }
  907. if (tso_start_new_packet(tx_queue, skb, &state) < 0)
  908. goto mem_err;
  909. while (1) {
  910. rc = tso_fill_packet_with_fragment(tx_queue, skb, &state);
  911. if (unlikely(rc))
  912. goto stop;
  913. /* Move onto the next fragment? */
  914. if (state.in_len == 0) {
  915. if (++frag_i >= skb_shinfo(skb)->nr_frags)
  916. /* End of payload reached. */
  917. break;
  918. rc = tso_get_fragment(&state, efx,
  919. skb_shinfo(skb)->frags + frag_i);
  920. if (rc)
  921. goto mem_err;
  922. }
  923. /* Start at new packet? */
  924. if (state.packet_space == 0 &&
  925. tso_start_new_packet(tx_queue, skb, &state) < 0)
  926. goto mem_err;
  927. }
  928. /* Pass off to hardware */
  929. falcon_push_buffers(tx_queue);
  930. tx_queue->tso_bursts++;
  931. return NETDEV_TX_OK;
  932. mem_err:
  933. EFX_ERR(efx, "Out of memory for TSO headers, or PCI mapping error\n");
  934. dev_kfree_skb_any((struct sk_buff *)skb);
  935. goto unwind;
  936. stop:
  937. rc2 = NETDEV_TX_BUSY;
  938. /* Stop the queue if it wasn't stopped before. */
  939. if (tx_queue->stopped == 1)
  940. efx_stop_queue(efx);
  941. unwind:
  942. /* Free the DMA mapping we were in the process of writing out */
  943. if (state.unmap_len) {
  944. if (state.unmap_single)
  945. pci_unmap_single(efx->pci_dev, state.unmap_addr,
  946. state.unmap_len, PCI_DMA_TODEVICE);
  947. else
  948. pci_unmap_page(efx->pci_dev, state.unmap_addr,
  949. state.unmap_len, PCI_DMA_TODEVICE);
  950. }
  951. efx_enqueue_unwind(tx_queue);
  952. return rc2;
  953. }
  954. /*
  955. * Free up all TSO datastructures associated with tx_queue. This
  956. * routine should be called only once the tx_queue is both empty and
  957. * will no longer be used.
  958. */
  959. static void efx_fini_tso(struct efx_tx_queue *tx_queue)
  960. {
  961. unsigned i;
  962. if (tx_queue->buffer) {
  963. for (i = 0; i <= tx_queue->efx->type->txd_ring_mask; ++i)
  964. efx_tsoh_free(tx_queue, &tx_queue->buffer[i]);
  965. }
  966. while (tx_queue->tso_headers_free != NULL)
  967. efx_tsoh_block_free(tx_queue, tx_queue->tso_headers_free,
  968. tx_queue->efx->pci_dev);
  969. }