pxaficp_ir.c 22 KB

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  1. /*
  2. * linux/drivers/net/irda/pxaficp_ir.c
  3. *
  4. * Based on sa1100_ir.c by Russell King
  5. *
  6. * Changes copyright (C) 2003-2005 MontaVista Software, Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * Infra-red driver (SIR/FIR) for the PXA2xx embedded microprocessor
  13. *
  14. */
  15. #include <linux/module.h>
  16. #include <linux/netdevice.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/clk.h>
  19. #include <net/irda/irda.h>
  20. #include <net/irda/irmod.h>
  21. #include <net/irda/wrapper.h>
  22. #include <net/irda/irda_device.h>
  23. #include <mach/dma.h>
  24. #include <mach/irda.h>
  25. #include <mach/hardware.h>
  26. #include <mach/pxa-regs.h>
  27. #include <mach/regs-uart.h>
  28. #define FICP __REG(0x40800000) /* Start of FICP area */
  29. #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
  30. #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
  31. #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
  32. #define ICDR __REG(0x4080000c) /* ICP Data Register */
  33. #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
  34. #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
  35. #define ICCR0_AME (1 << 7) /* Address match enable */
  36. #define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */
  37. #define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */
  38. #define ICCR0_RXE (1 << 4) /* Receive enable */
  39. #define ICCR0_TXE (1 << 3) /* Transmit enable */
  40. #define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */
  41. #define ICCR0_LBM (1 << 1) /* Loopback mode */
  42. #define ICCR0_ITR (1 << 0) /* IrDA transmission */
  43. #define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
  44. #define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
  45. #define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
  46. #define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
  47. #define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
  48. #define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
  49. #ifdef CONFIG_PXA27x
  50. #define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */
  51. #endif
  52. #define ICSR0_FRE (1 << 5) /* Framing error */
  53. #define ICSR0_RFS (1 << 4) /* Receive FIFO service request */
  54. #define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */
  55. #define ICSR0_RAB (1 << 2) /* Receiver abort */
  56. #define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */
  57. #define ICSR0_EIF (1 << 0) /* End/Error in FIFO */
  58. #define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */
  59. #define ICSR1_CRE (1 << 5) /* CRC error */
  60. #define ICSR1_EOF (1 << 4) /* End of frame */
  61. #define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */
  62. #define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */
  63. #define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */
  64. #define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */
  65. #define IrSR_RXPL_NEG_IS_ZERO (1<<4)
  66. #define IrSR_RXPL_POS_IS_ZERO 0x0
  67. #define IrSR_TXPL_NEG_IS_ZERO (1<<3)
  68. #define IrSR_TXPL_POS_IS_ZERO 0x0
  69. #define IrSR_XMODE_PULSE_1_6 (1<<2)
  70. #define IrSR_XMODE_PULSE_3_16 0x0
  71. #define IrSR_RCVEIR_IR_MODE (1<<1)
  72. #define IrSR_RCVEIR_UART_MODE 0x0
  73. #define IrSR_XMITIR_IR_MODE (1<<0)
  74. #define IrSR_XMITIR_UART_MODE 0x0
  75. #define IrSR_IR_RECEIVE_ON (\
  76. IrSR_RXPL_NEG_IS_ZERO | \
  77. IrSR_TXPL_POS_IS_ZERO | \
  78. IrSR_XMODE_PULSE_3_16 | \
  79. IrSR_RCVEIR_IR_MODE | \
  80. IrSR_XMITIR_UART_MODE)
  81. #define IrSR_IR_TRANSMIT_ON (\
  82. IrSR_RXPL_NEG_IS_ZERO | \
  83. IrSR_TXPL_POS_IS_ZERO | \
  84. IrSR_XMODE_PULSE_3_16 | \
  85. IrSR_RCVEIR_UART_MODE | \
  86. IrSR_XMITIR_IR_MODE)
  87. struct pxa_irda {
  88. int speed;
  89. int newspeed;
  90. unsigned long last_oscr;
  91. unsigned char *dma_rx_buff;
  92. unsigned char *dma_tx_buff;
  93. dma_addr_t dma_rx_buff_phy;
  94. dma_addr_t dma_tx_buff_phy;
  95. unsigned int dma_tx_buff_len;
  96. int txdma;
  97. int rxdma;
  98. struct net_device_stats stats;
  99. struct irlap_cb *irlap;
  100. struct qos_info qos;
  101. iobuff_t tx_buff;
  102. iobuff_t rx_buff;
  103. struct device *dev;
  104. struct pxaficp_platform_data *pdata;
  105. struct clk *fir_clk;
  106. struct clk *sir_clk;
  107. struct clk *cur_clk;
  108. };
  109. static inline void pxa_irda_disable_clk(struct pxa_irda *si)
  110. {
  111. if (si->cur_clk)
  112. clk_disable(si->cur_clk);
  113. si->cur_clk = NULL;
  114. }
  115. static inline void pxa_irda_enable_firclk(struct pxa_irda *si)
  116. {
  117. si->cur_clk = si->fir_clk;
  118. clk_enable(si->fir_clk);
  119. }
  120. static inline void pxa_irda_enable_sirclk(struct pxa_irda *si)
  121. {
  122. si->cur_clk = si->sir_clk;
  123. clk_enable(si->sir_clk);
  124. }
  125. #define IS_FIR(si) ((si)->speed >= 4000000)
  126. #define IRDA_FRAME_SIZE_LIMIT 2047
  127. inline static void pxa_irda_fir_dma_rx_start(struct pxa_irda *si)
  128. {
  129. DCSR(si->rxdma) = DCSR_NODESC;
  130. DSADR(si->rxdma) = __PREG(ICDR);
  131. DTADR(si->rxdma) = si->dma_rx_buff_phy;
  132. DCMD(si->rxdma) = DCMD_INCTRGADDR | DCMD_FLOWSRC | DCMD_WIDTH1 | DCMD_BURST32 | IRDA_FRAME_SIZE_LIMIT;
  133. DCSR(si->rxdma) |= DCSR_RUN;
  134. }
  135. inline static void pxa_irda_fir_dma_tx_start(struct pxa_irda *si)
  136. {
  137. DCSR(si->txdma) = DCSR_NODESC;
  138. DSADR(si->txdma) = si->dma_tx_buff_phy;
  139. DTADR(si->txdma) = __PREG(ICDR);
  140. DCMD(si->txdma) = DCMD_INCSRCADDR | DCMD_FLOWTRG | DCMD_ENDIRQEN | DCMD_WIDTH1 | DCMD_BURST32 | si->dma_tx_buff_len;
  141. DCSR(si->txdma) |= DCSR_RUN;
  142. }
  143. /*
  144. * Set the IrDA communications speed.
  145. */
  146. static int pxa_irda_set_speed(struct pxa_irda *si, int speed)
  147. {
  148. unsigned long flags;
  149. unsigned int divisor;
  150. switch (speed) {
  151. case 9600: case 19200: case 38400:
  152. case 57600: case 115200:
  153. /* refer to PXA250/210 Developer's Manual 10-7 */
  154. /* BaudRate = 14.7456 MHz / (16*Divisor) */
  155. divisor = 14745600 / (16 * speed);
  156. local_irq_save(flags);
  157. if (IS_FIR(si)) {
  158. /* stop RX DMA */
  159. DCSR(si->rxdma) &= ~DCSR_RUN;
  160. /* disable FICP */
  161. ICCR0 = 0;
  162. pxa_irda_disable_clk(si);
  163. /* set board transceiver to SIR mode */
  164. si->pdata->transceiver_mode(si->dev, IR_SIRMODE);
  165. /* enable the STUART clock */
  166. pxa_irda_enable_sirclk(si);
  167. }
  168. /* disable STUART first */
  169. STIER = 0;
  170. /* access DLL & DLH */
  171. STLCR |= LCR_DLAB;
  172. STDLL = divisor & 0xff;
  173. STDLH = divisor >> 8;
  174. STLCR &= ~LCR_DLAB;
  175. si->speed = speed;
  176. STISR = IrSR_IR_RECEIVE_ON | IrSR_XMODE_PULSE_1_6;
  177. STIER = IER_UUE | IER_RLSE | IER_RAVIE | IER_RTIOE;
  178. local_irq_restore(flags);
  179. break;
  180. case 4000000:
  181. local_irq_save(flags);
  182. /* disable STUART */
  183. STIER = 0;
  184. STISR = 0;
  185. pxa_irda_disable_clk(si);
  186. /* disable FICP first */
  187. ICCR0 = 0;
  188. /* set board transceiver to FIR mode */
  189. si->pdata->transceiver_mode(si->dev, IR_FIRMODE);
  190. /* enable the FICP clock */
  191. pxa_irda_enable_firclk(si);
  192. si->speed = speed;
  193. pxa_irda_fir_dma_rx_start(si);
  194. ICCR0 = ICCR0_ITR | ICCR0_RXE;
  195. local_irq_restore(flags);
  196. break;
  197. default:
  198. return -EINVAL;
  199. }
  200. return 0;
  201. }
  202. /* SIR interrupt service routine. */
  203. static irqreturn_t pxa_irda_sir_irq(int irq, void *dev_id)
  204. {
  205. struct net_device *dev = dev_id;
  206. struct pxa_irda *si = netdev_priv(dev);
  207. int iir, lsr, data;
  208. iir = STIIR;
  209. switch (iir & 0x0F) {
  210. case 0x06: /* Receiver Line Status */
  211. lsr = STLSR;
  212. while (lsr & LSR_FIFOE) {
  213. data = STRBR;
  214. if (lsr & (LSR_OE | LSR_PE | LSR_FE | LSR_BI)) {
  215. printk(KERN_DEBUG "pxa_ir: sir receiving error\n");
  216. si->stats.rx_errors++;
  217. if (lsr & LSR_FE)
  218. si->stats.rx_frame_errors++;
  219. if (lsr & LSR_OE)
  220. si->stats.rx_fifo_errors++;
  221. } else {
  222. si->stats.rx_bytes++;
  223. async_unwrap_char(dev, &si->stats, &si->rx_buff, data);
  224. }
  225. lsr = STLSR;
  226. }
  227. si->last_oscr = OSCR;
  228. break;
  229. case 0x04: /* Received Data Available */
  230. /* forth through */
  231. case 0x0C: /* Character Timeout Indication */
  232. do {
  233. si->stats.rx_bytes++;
  234. async_unwrap_char(dev, &si->stats, &si->rx_buff, STRBR);
  235. } while (STLSR & LSR_DR);
  236. si->last_oscr = OSCR;
  237. break;
  238. case 0x02: /* Transmit FIFO Data Request */
  239. while ((si->tx_buff.len) && (STLSR & LSR_TDRQ)) {
  240. STTHR = *si->tx_buff.data++;
  241. si->tx_buff.len -= 1;
  242. }
  243. if (si->tx_buff.len == 0) {
  244. si->stats.tx_packets++;
  245. si->stats.tx_bytes += si->tx_buff.data -
  246. si->tx_buff.head;
  247. /* We need to ensure that the transmitter has finished. */
  248. while ((STLSR & LSR_TEMT) == 0)
  249. cpu_relax();
  250. si->last_oscr = OSCR;
  251. /*
  252. * Ok, we've finished transmitting. Now enable
  253. * the receiver. Sometimes we get a receive IRQ
  254. * immediately after a transmit...
  255. */
  256. if (si->newspeed) {
  257. pxa_irda_set_speed(si, si->newspeed);
  258. si->newspeed = 0;
  259. } else {
  260. /* enable IR Receiver, disable IR Transmitter */
  261. STISR = IrSR_IR_RECEIVE_ON | IrSR_XMODE_PULSE_1_6;
  262. /* enable STUART and receive interrupts */
  263. STIER = IER_UUE | IER_RLSE | IER_RAVIE | IER_RTIOE;
  264. }
  265. /* I'm hungry! */
  266. netif_wake_queue(dev);
  267. }
  268. break;
  269. }
  270. return IRQ_HANDLED;
  271. }
  272. /* FIR Receive DMA interrupt handler */
  273. static void pxa_irda_fir_dma_rx_irq(int channel, void *data)
  274. {
  275. int dcsr = DCSR(channel);
  276. DCSR(channel) = dcsr & ~DCSR_RUN;
  277. printk(KERN_DEBUG "pxa_ir: fir rx dma bus error %#x\n", dcsr);
  278. }
  279. /* FIR Transmit DMA interrupt handler */
  280. static void pxa_irda_fir_dma_tx_irq(int channel, void *data)
  281. {
  282. struct net_device *dev = data;
  283. struct pxa_irda *si = netdev_priv(dev);
  284. int dcsr;
  285. dcsr = DCSR(channel);
  286. DCSR(channel) = dcsr & ~DCSR_RUN;
  287. if (dcsr & DCSR_ENDINTR) {
  288. si->stats.tx_packets++;
  289. si->stats.tx_bytes += si->dma_tx_buff_len;
  290. } else {
  291. si->stats.tx_errors++;
  292. }
  293. while (ICSR1 & ICSR1_TBY)
  294. cpu_relax();
  295. si->last_oscr = OSCR;
  296. /*
  297. * HACK: It looks like the TBY bit is dropped too soon.
  298. * Without this delay things break.
  299. */
  300. udelay(120);
  301. if (si->newspeed) {
  302. pxa_irda_set_speed(si, si->newspeed);
  303. si->newspeed = 0;
  304. } else {
  305. int i = 64;
  306. ICCR0 = 0;
  307. pxa_irda_fir_dma_rx_start(si);
  308. while ((ICSR1 & ICSR1_RNE) && i--)
  309. (void)ICDR;
  310. ICCR0 = ICCR0_ITR | ICCR0_RXE;
  311. if (i < 0)
  312. printk(KERN_ERR "pxa_ir: cannot clear Rx FIFO!\n");
  313. }
  314. netif_wake_queue(dev);
  315. }
  316. /* EIF(Error in FIFO/End in Frame) handler for FIR */
  317. static void pxa_irda_fir_irq_eif(struct pxa_irda *si, struct net_device *dev, int icsr0)
  318. {
  319. unsigned int len, stat, data;
  320. /* Get the current data position. */
  321. len = DTADR(si->rxdma) - si->dma_rx_buff_phy;
  322. do {
  323. /* Read Status, and then Data. */
  324. stat = ICSR1;
  325. rmb();
  326. data = ICDR;
  327. if (stat & (ICSR1_CRE | ICSR1_ROR)) {
  328. si->stats.rx_errors++;
  329. if (stat & ICSR1_CRE) {
  330. printk(KERN_DEBUG "pxa_ir: fir receive CRC error\n");
  331. si->stats.rx_crc_errors++;
  332. }
  333. if (stat & ICSR1_ROR) {
  334. printk(KERN_DEBUG "pxa_ir: fir receive overrun\n");
  335. si->stats.rx_over_errors++;
  336. }
  337. } else {
  338. si->dma_rx_buff[len++] = data;
  339. }
  340. /* If we hit the end of frame, there's no point in continuing. */
  341. if (stat & ICSR1_EOF)
  342. break;
  343. } while (ICSR0 & ICSR0_EIF);
  344. if (stat & ICSR1_EOF) {
  345. /* end of frame. */
  346. struct sk_buff *skb;
  347. if (icsr0 & ICSR0_FRE) {
  348. printk(KERN_ERR "pxa_ir: dropping erroneous frame\n");
  349. si->stats.rx_dropped++;
  350. return;
  351. }
  352. skb = alloc_skb(len+1,GFP_ATOMIC);
  353. if (!skb) {
  354. printk(KERN_ERR "pxa_ir: fir out of memory for receive skb\n");
  355. si->stats.rx_dropped++;
  356. return;
  357. }
  358. /* Align IP header to 20 bytes */
  359. skb_reserve(skb, 1);
  360. skb_copy_to_linear_data(skb, si->dma_rx_buff, len);
  361. skb_put(skb, len);
  362. /* Feed it to IrLAP */
  363. skb->dev = dev;
  364. skb_reset_mac_header(skb);
  365. skb->protocol = htons(ETH_P_IRDA);
  366. netif_rx(skb);
  367. si->stats.rx_packets++;
  368. si->stats.rx_bytes += len;
  369. }
  370. }
  371. /* FIR interrupt handler */
  372. static irqreturn_t pxa_irda_fir_irq(int irq, void *dev_id)
  373. {
  374. struct net_device *dev = dev_id;
  375. struct pxa_irda *si = netdev_priv(dev);
  376. int icsr0, i = 64;
  377. /* stop RX DMA */
  378. DCSR(si->rxdma) &= ~DCSR_RUN;
  379. si->last_oscr = OSCR;
  380. icsr0 = ICSR0;
  381. if (icsr0 & (ICSR0_FRE | ICSR0_RAB)) {
  382. if (icsr0 & ICSR0_FRE) {
  383. printk(KERN_DEBUG "pxa_ir: fir receive frame error\n");
  384. si->stats.rx_frame_errors++;
  385. } else {
  386. printk(KERN_DEBUG "pxa_ir: fir receive abort\n");
  387. si->stats.rx_errors++;
  388. }
  389. ICSR0 = icsr0 & (ICSR0_FRE | ICSR0_RAB);
  390. }
  391. if (icsr0 & ICSR0_EIF) {
  392. /* An error in FIFO occured, or there is a end of frame */
  393. pxa_irda_fir_irq_eif(si, dev, icsr0);
  394. }
  395. ICCR0 = 0;
  396. pxa_irda_fir_dma_rx_start(si);
  397. while ((ICSR1 & ICSR1_RNE) && i--)
  398. (void)ICDR;
  399. ICCR0 = ICCR0_ITR | ICCR0_RXE;
  400. if (i < 0)
  401. printk(KERN_ERR "pxa_ir: cannot clear Rx FIFO!\n");
  402. return IRQ_HANDLED;
  403. }
  404. /* hard_xmit interface of irda device */
  405. static int pxa_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev)
  406. {
  407. struct pxa_irda *si = netdev_priv(dev);
  408. int speed = irda_get_next_speed(skb);
  409. /*
  410. * Does this packet contain a request to change the interface
  411. * speed? If so, remember it until we complete the transmission
  412. * of this frame.
  413. */
  414. if (speed != si->speed && speed != -1)
  415. si->newspeed = speed;
  416. /*
  417. * If this is an empty frame, we can bypass a lot.
  418. */
  419. if (skb->len == 0) {
  420. if (si->newspeed) {
  421. si->newspeed = 0;
  422. pxa_irda_set_speed(si, speed);
  423. }
  424. dev_kfree_skb(skb);
  425. return 0;
  426. }
  427. netif_stop_queue(dev);
  428. if (!IS_FIR(si)) {
  429. si->tx_buff.data = si->tx_buff.head;
  430. si->tx_buff.len = async_wrap_skb(skb, si->tx_buff.data, si->tx_buff.truesize);
  431. /* Disable STUART interrupts and switch to transmit mode. */
  432. STIER = 0;
  433. STISR = IrSR_IR_TRANSMIT_ON | IrSR_XMODE_PULSE_1_6;
  434. /* enable STUART and transmit interrupts */
  435. STIER = IER_UUE | IER_TIE;
  436. } else {
  437. unsigned long mtt = irda_get_mtt(skb);
  438. si->dma_tx_buff_len = skb->len;
  439. skb_copy_from_linear_data(skb, si->dma_tx_buff, skb->len);
  440. if (mtt)
  441. while ((unsigned)(OSCR - si->last_oscr)/4 < mtt)
  442. cpu_relax();
  443. /* stop RX DMA, disable FICP */
  444. DCSR(si->rxdma) &= ~DCSR_RUN;
  445. ICCR0 = 0;
  446. pxa_irda_fir_dma_tx_start(si);
  447. ICCR0 = ICCR0_ITR | ICCR0_TXE;
  448. }
  449. dev_kfree_skb(skb);
  450. dev->trans_start = jiffies;
  451. return 0;
  452. }
  453. static int pxa_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd)
  454. {
  455. struct if_irda_req *rq = (struct if_irda_req *)ifreq;
  456. struct pxa_irda *si = netdev_priv(dev);
  457. int ret;
  458. switch (cmd) {
  459. case SIOCSBANDWIDTH:
  460. ret = -EPERM;
  461. if (capable(CAP_NET_ADMIN)) {
  462. /*
  463. * We are unable to set the speed if the
  464. * device is not running.
  465. */
  466. if (netif_running(dev)) {
  467. ret = pxa_irda_set_speed(si,
  468. rq->ifr_baudrate);
  469. } else {
  470. printk(KERN_INFO "pxa_ir: SIOCSBANDWIDTH: !netif_running\n");
  471. ret = 0;
  472. }
  473. }
  474. break;
  475. case SIOCSMEDIABUSY:
  476. ret = -EPERM;
  477. if (capable(CAP_NET_ADMIN)) {
  478. irda_device_set_media_busy(dev, TRUE);
  479. ret = 0;
  480. }
  481. break;
  482. case SIOCGRECEIVING:
  483. ret = 0;
  484. rq->ifr_receiving = IS_FIR(si) ? 0
  485. : si->rx_buff.state != OUTSIDE_FRAME;
  486. break;
  487. default:
  488. ret = -EOPNOTSUPP;
  489. break;
  490. }
  491. return ret;
  492. }
  493. static struct net_device_stats *pxa_irda_stats(struct net_device *dev)
  494. {
  495. struct pxa_irda *si = netdev_priv(dev);
  496. return &si->stats;
  497. }
  498. static void pxa_irda_startup(struct pxa_irda *si)
  499. {
  500. /* Disable STUART interrupts */
  501. STIER = 0;
  502. /* enable STUART interrupt to the processor */
  503. STMCR = MCR_OUT2;
  504. /* configure SIR frame format: StartBit - Data 7 ... Data 0 - Stop Bit */
  505. STLCR = LCR_WLS0 | LCR_WLS1;
  506. /* enable FIFO, we use FIFO to improve performance */
  507. STFCR = FCR_TRFIFOE | FCR_ITL_32;
  508. /* disable FICP */
  509. ICCR0 = 0;
  510. /* configure FICP ICCR2 */
  511. ICCR2 = ICCR2_TXP | ICCR2_TRIG_32;
  512. /* configure DMAC */
  513. DRCMR(17) = si->rxdma | DRCMR_MAPVLD;
  514. DRCMR(18) = si->txdma | DRCMR_MAPVLD;
  515. /* force SIR reinitialization */
  516. si->speed = 4000000;
  517. pxa_irda_set_speed(si, 9600);
  518. printk(KERN_DEBUG "pxa_ir: irda startup\n");
  519. }
  520. static void pxa_irda_shutdown(struct pxa_irda *si)
  521. {
  522. unsigned long flags;
  523. local_irq_save(flags);
  524. /* disable STUART and interrupt */
  525. STIER = 0;
  526. /* disable STUART SIR mode */
  527. STISR = 0;
  528. /* disable DMA */
  529. DCSR(si->txdma) &= ~DCSR_RUN;
  530. DCSR(si->rxdma) &= ~DCSR_RUN;
  531. /* disable FICP */
  532. ICCR0 = 0;
  533. /* disable the STUART or FICP clocks */
  534. pxa_irda_disable_clk(si);
  535. DRCMR(17) = 0;
  536. DRCMR(18) = 0;
  537. local_irq_restore(flags);
  538. /* power off board transceiver */
  539. si->pdata->transceiver_mode(si->dev, IR_OFF);
  540. printk(KERN_DEBUG "pxa_ir: irda shutdown\n");
  541. }
  542. static int pxa_irda_start(struct net_device *dev)
  543. {
  544. struct pxa_irda *si = netdev_priv(dev);
  545. int err;
  546. si->speed = 9600;
  547. err = request_irq(IRQ_STUART, pxa_irda_sir_irq, 0, dev->name, dev);
  548. if (err)
  549. goto err_irq1;
  550. err = request_irq(IRQ_ICP, pxa_irda_fir_irq, 0, dev->name, dev);
  551. if (err)
  552. goto err_irq2;
  553. /*
  554. * The interrupt must remain disabled for now.
  555. */
  556. disable_irq(IRQ_STUART);
  557. disable_irq(IRQ_ICP);
  558. err = -EBUSY;
  559. si->rxdma = pxa_request_dma("FICP_RX",DMA_PRIO_LOW, pxa_irda_fir_dma_rx_irq, dev);
  560. if (si->rxdma < 0)
  561. goto err_rx_dma;
  562. si->txdma = pxa_request_dma("FICP_TX",DMA_PRIO_LOW, pxa_irda_fir_dma_tx_irq, dev);
  563. if (si->txdma < 0)
  564. goto err_tx_dma;
  565. err = -ENOMEM;
  566. si->dma_rx_buff = dma_alloc_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT,
  567. &si->dma_rx_buff_phy, GFP_KERNEL );
  568. if (!si->dma_rx_buff)
  569. goto err_dma_rx_buff;
  570. si->dma_tx_buff = dma_alloc_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT,
  571. &si->dma_tx_buff_phy, GFP_KERNEL );
  572. if (!si->dma_tx_buff)
  573. goto err_dma_tx_buff;
  574. /* Setup the serial port for the initial speed. */
  575. pxa_irda_startup(si);
  576. /*
  577. * Open a new IrLAP layer instance.
  578. */
  579. si->irlap = irlap_open(dev, &si->qos, "pxa");
  580. err = -ENOMEM;
  581. if (!si->irlap)
  582. goto err_irlap;
  583. /*
  584. * Now enable the interrupt and start the queue
  585. */
  586. enable_irq(IRQ_STUART);
  587. enable_irq(IRQ_ICP);
  588. netif_start_queue(dev);
  589. printk(KERN_DEBUG "pxa_ir: irda driver opened\n");
  590. return 0;
  591. err_irlap:
  592. pxa_irda_shutdown(si);
  593. dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_tx_buff, si->dma_tx_buff_phy);
  594. err_dma_tx_buff:
  595. dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_rx_buff, si->dma_rx_buff_phy);
  596. err_dma_rx_buff:
  597. pxa_free_dma(si->txdma);
  598. err_tx_dma:
  599. pxa_free_dma(si->rxdma);
  600. err_rx_dma:
  601. free_irq(IRQ_ICP, dev);
  602. err_irq2:
  603. free_irq(IRQ_STUART, dev);
  604. err_irq1:
  605. return err;
  606. }
  607. static int pxa_irda_stop(struct net_device *dev)
  608. {
  609. struct pxa_irda *si = netdev_priv(dev);
  610. netif_stop_queue(dev);
  611. pxa_irda_shutdown(si);
  612. /* Stop IrLAP */
  613. if (si->irlap) {
  614. irlap_close(si->irlap);
  615. si->irlap = NULL;
  616. }
  617. free_irq(IRQ_STUART, dev);
  618. free_irq(IRQ_ICP, dev);
  619. pxa_free_dma(si->rxdma);
  620. pxa_free_dma(si->txdma);
  621. if (si->dma_rx_buff)
  622. dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_tx_buff, si->dma_tx_buff_phy);
  623. if (si->dma_tx_buff)
  624. dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_rx_buff, si->dma_rx_buff_phy);
  625. printk(KERN_DEBUG "pxa_ir: irda driver closed\n");
  626. return 0;
  627. }
  628. static int pxa_irda_suspend(struct platform_device *_dev, pm_message_t state)
  629. {
  630. struct net_device *dev = platform_get_drvdata(_dev);
  631. struct pxa_irda *si;
  632. if (dev && netif_running(dev)) {
  633. si = netdev_priv(dev);
  634. netif_device_detach(dev);
  635. pxa_irda_shutdown(si);
  636. }
  637. return 0;
  638. }
  639. static int pxa_irda_resume(struct platform_device *_dev)
  640. {
  641. struct net_device *dev = platform_get_drvdata(_dev);
  642. struct pxa_irda *si;
  643. if (dev && netif_running(dev)) {
  644. si = netdev_priv(dev);
  645. pxa_irda_startup(si);
  646. netif_device_attach(dev);
  647. netif_wake_queue(dev);
  648. }
  649. return 0;
  650. }
  651. static int pxa_irda_init_iobuf(iobuff_t *io, int size)
  652. {
  653. io->head = kmalloc(size, GFP_KERNEL | GFP_DMA);
  654. if (io->head != NULL) {
  655. io->truesize = size;
  656. io->in_frame = FALSE;
  657. io->state = OUTSIDE_FRAME;
  658. io->data = io->head;
  659. }
  660. return io->head ? 0 : -ENOMEM;
  661. }
  662. static int pxa_irda_probe(struct platform_device *pdev)
  663. {
  664. struct net_device *dev;
  665. struct pxa_irda *si;
  666. unsigned int baudrate_mask;
  667. int err;
  668. if (!pdev->dev.platform_data)
  669. return -ENODEV;
  670. err = request_mem_region(__PREG(STUART), 0x24, "IrDA") ? 0 : -EBUSY;
  671. if (err)
  672. goto err_mem_1;
  673. err = request_mem_region(__PREG(FICP), 0x1c, "IrDA") ? 0 : -EBUSY;
  674. if (err)
  675. goto err_mem_2;
  676. dev = alloc_irdadev(sizeof(struct pxa_irda));
  677. if (!dev)
  678. goto err_mem_3;
  679. si = netdev_priv(dev);
  680. si->dev = &pdev->dev;
  681. si->pdata = pdev->dev.platform_data;
  682. si->sir_clk = clk_get(&pdev->dev, "UARTCLK");
  683. si->fir_clk = clk_get(&pdev->dev, "FICPCLK");
  684. if (IS_ERR(si->sir_clk) || IS_ERR(si->fir_clk)) {
  685. err = PTR_ERR(IS_ERR(si->sir_clk) ? si->sir_clk : si->fir_clk);
  686. goto err_mem_4;
  687. }
  688. /*
  689. * Initialise the SIR buffers
  690. */
  691. err = pxa_irda_init_iobuf(&si->rx_buff, 14384);
  692. if (err)
  693. goto err_mem_4;
  694. err = pxa_irda_init_iobuf(&si->tx_buff, 4000);
  695. if (err)
  696. goto err_mem_5;
  697. if (si->pdata->startup)
  698. err = si->pdata->startup(si->dev);
  699. if (err)
  700. goto err_startup;
  701. dev->hard_start_xmit = pxa_irda_hard_xmit;
  702. dev->open = pxa_irda_start;
  703. dev->stop = pxa_irda_stop;
  704. dev->do_ioctl = pxa_irda_ioctl;
  705. dev->get_stats = pxa_irda_stats;
  706. irda_init_max_qos_capabilies(&si->qos);
  707. baudrate_mask = 0;
  708. if (si->pdata->transceiver_cap & IR_SIRMODE)
  709. baudrate_mask |= IR_9600|IR_19200|IR_38400|IR_57600|IR_115200;
  710. if (si->pdata->transceiver_cap & IR_FIRMODE)
  711. baudrate_mask |= IR_4000000 << 8;
  712. si->qos.baud_rate.bits &= baudrate_mask;
  713. si->qos.min_turn_time.bits = 7; /* 1ms or more */
  714. irda_qos_bits_to_value(&si->qos);
  715. err = register_netdev(dev);
  716. if (err == 0)
  717. dev_set_drvdata(&pdev->dev, dev);
  718. if (err) {
  719. if (si->pdata->shutdown)
  720. si->pdata->shutdown(si->dev);
  721. err_startup:
  722. kfree(si->tx_buff.head);
  723. err_mem_5:
  724. kfree(si->rx_buff.head);
  725. err_mem_4:
  726. if (si->sir_clk && !IS_ERR(si->sir_clk))
  727. clk_put(si->sir_clk);
  728. if (si->fir_clk && !IS_ERR(si->fir_clk))
  729. clk_put(si->fir_clk);
  730. free_netdev(dev);
  731. err_mem_3:
  732. release_mem_region(__PREG(FICP), 0x1c);
  733. err_mem_2:
  734. release_mem_region(__PREG(STUART), 0x24);
  735. }
  736. err_mem_1:
  737. return err;
  738. }
  739. static int pxa_irda_remove(struct platform_device *_dev)
  740. {
  741. struct net_device *dev = platform_get_drvdata(_dev);
  742. if (dev) {
  743. struct pxa_irda *si = netdev_priv(dev);
  744. unregister_netdev(dev);
  745. if (si->pdata->shutdown)
  746. si->pdata->shutdown(si->dev);
  747. kfree(si->tx_buff.head);
  748. kfree(si->rx_buff.head);
  749. clk_put(si->fir_clk);
  750. clk_put(si->sir_clk);
  751. free_netdev(dev);
  752. }
  753. release_mem_region(__PREG(STUART), 0x24);
  754. release_mem_region(__PREG(FICP), 0x1c);
  755. return 0;
  756. }
  757. static struct platform_driver pxa_ir_driver = {
  758. .driver = {
  759. .name = "pxa2xx-ir",
  760. .owner = THIS_MODULE,
  761. },
  762. .probe = pxa_irda_probe,
  763. .remove = pxa_irda_remove,
  764. .suspend = pxa_irda_suspend,
  765. .resume = pxa_irda_resume,
  766. };
  767. static int __init pxa_irda_init(void)
  768. {
  769. return platform_driver_register(&pxa_ir_driver);
  770. }
  771. static void __exit pxa_irda_exit(void)
  772. {
  773. platform_driver_unregister(&pxa_ir_driver);
  774. }
  775. module_init(pxa_irda_init);
  776. module_exit(pxa_irda_exit);
  777. MODULE_LICENSE("GPL");
  778. MODULE_ALIAS("platform:pxa2xx-ir");