gru_instructions.h 19 KB

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  1. /*
  2. * Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU Lesser General Public License as published by
  6. * the Free Software Foundation; either version 2.1 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU Lesser General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU Lesser General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  17. */
  18. #ifndef __GRU_INSTRUCTIONS_H__
  19. #define __GRU_INSTRUCTIONS_H__
  20. #define gru_flush_cache_hook(p)
  21. #define gru_emulator_wait_hook(p, w)
  22. /*
  23. * Architecture dependent functions
  24. */
  25. #if defined(CONFIG_IA64)
  26. #include <linux/compiler.h>
  27. #include <asm/intrinsics.h>
  28. #define __flush_cache(p) ia64_fc(p)
  29. /* Use volatile on IA64 to ensure ordering via st4.rel */
  30. #define gru_ordered_store_int(p,v) \
  31. do { \
  32. barrier(); \
  33. *((volatile int *)(p)) = v; /* force st.rel */ \
  34. } while (0)
  35. #elif defined(CONFIG_X86_64)
  36. #define __flush_cache(p) clflush(p)
  37. #define gru_ordered_store_int(p,v) \
  38. do { \
  39. barrier(); \
  40. *(int *)p = v; \
  41. } while (0)
  42. #else
  43. #error "Unsupported architecture"
  44. #endif
  45. /*
  46. * Control block status and exception codes
  47. */
  48. #define CBS_IDLE 0
  49. #define CBS_EXCEPTION 1
  50. #define CBS_ACTIVE 2
  51. #define CBS_CALL_OS 3
  52. /* CB substatus bitmasks */
  53. #define CBSS_MSG_QUEUE_MASK 7
  54. #define CBSS_IMPLICIT_ABORT_ACTIVE_MASK 8
  55. /* CB substatus message queue values (low 3 bits of substatus) */
  56. #define CBSS_NO_ERROR 0
  57. #define CBSS_LB_OVERFLOWED 1
  58. #define CBSS_QLIMIT_REACHED 2
  59. #define CBSS_PAGE_OVERFLOW 3
  60. #define CBSS_AMO_NACKED 4
  61. #define CBSS_PUT_NACKED 5
  62. /*
  63. * Structure used to fetch exception detail for CBs that terminate with
  64. * CBS_EXCEPTION
  65. */
  66. struct control_block_extended_exc_detail {
  67. unsigned long cb;
  68. int opc;
  69. int ecause;
  70. int exopc;
  71. long exceptdet0;
  72. int exceptdet1;
  73. };
  74. /*
  75. * Instruction formats
  76. */
  77. /*
  78. * Generic instruction format.
  79. * This definition has precise bit field definitions.
  80. */
  81. struct gru_instruction_bits {
  82. /* DW 0 - low */
  83. unsigned int icmd: 1;
  84. unsigned char ima: 3; /* CB_DelRep, unmapped mode */
  85. unsigned char reserved0: 4;
  86. unsigned int xtype: 3;
  87. unsigned int iaa0: 2;
  88. unsigned int iaa1: 2;
  89. unsigned char reserved1: 1;
  90. unsigned char opc: 8; /* opcode */
  91. unsigned char exopc: 8; /* extended opcode */
  92. /* DW 0 - high */
  93. unsigned int idef2: 22; /* TRi0 */
  94. unsigned char reserved2: 2;
  95. unsigned char istatus: 2;
  96. unsigned char isubstatus:4;
  97. unsigned char reserved3: 2;
  98. /* DW 1 */
  99. unsigned long idef4; /* 42 bits: TRi1, BufSize */
  100. /* DW 2-6 */
  101. unsigned long idef1; /* BAddr0 */
  102. unsigned long idef5; /* Nelem */
  103. unsigned long idef6; /* Stride, Operand1 */
  104. unsigned long idef3; /* BAddr1, Value, Operand2 */
  105. unsigned long reserved4;
  106. /* DW 7 */
  107. unsigned long avalue; /* AValue */
  108. };
  109. /*
  110. * Generic instruction with friendlier names. This format is used
  111. * for inline instructions.
  112. */
  113. struct gru_instruction {
  114. /* DW 0 */
  115. unsigned int op32; /* icmd,xtype,iaa0,ima,opc */
  116. unsigned int tri0;
  117. unsigned long tri1_bufsize; /* DW 1 */
  118. unsigned long baddr0; /* DW 2 */
  119. unsigned long nelem; /* DW 3 */
  120. unsigned long op1_stride; /* DW 4 */
  121. unsigned long op2_value_baddr1; /* DW 5 */
  122. unsigned long reserved0; /* DW 6 */
  123. unsigned long avalue; /* DW 7 */
  124. };
  125. /* Some shifts and masks for the low 32 bits of a GRU command */
  126. #define GRU_CB_ICMD_SHFT 0
  127. #define GRU_CB_ICMD_MASK 0x1
  128. #define GRU_CB_XTYPE_SHFT 8
  129. #define GRU_CB_XTYPE_MASK 0x7
  130. #define GRU_CB_IAA0_SHFT 11
  131. #define GRU_CB_IAA0_MASK 0x3
  132. #define GRU_CB_IAA1_SHFT 13
  133. #define GRU_CB_IAA1_MASK 0x3
  134. #define GRU_CB_IMA_SHFT 1
  135. #define GRU_CB_IMA_MASK 0x3
  136. #define GRU_CB_OPC_SHFT 16
  137. #define GRU_CB_OPC_MASK 0xff
  138. #define GRU_CB_EXOPC_SHFT 24
  139. #define GRU_CB_EXOPC_MASK 0xff
  140. /* GRU instruction opcodes (opc field) */
  141. #define OP_NOP 0x00
  142. #define OP_BCOPY 0x01
  143. #define OP_VLOAD 0x02
  144. #define OP_IVLOAD 0x03
  145. #define OP_VSTORE 0x04
  146. #define OP_IVSTORE 0x05
  147. #define OP_VSET 0x06
  148. #define OP_IVSET 0x07
  149. #define OP_MESQ 0x08
  150. #define OP_GAMXR 0x09
  151. #define OP_GAMIR 0x0a
  152. #define OP_GAMIRR 0x0b
  153. #define OP_GAMER 0x0c
  154. #define OP_GAMERR 0x0d
  155. #define OP_BSTORE 0x0e
  156. #define OP_VFLUSH 0x0f
  157. /* Extended opcodes values (exopc field) */
  158. /* GAMIR - AMOs with implicit operands */
  159. #define EOP_IR_FETCH 0x01 /* Plain fetch of memory */
  160. #define EOP_IR_CLR 0x02 /* Fetch and clear */
  161. #define EOP_IR_INC 0x05 /* Fetch and increment */
  162. #define EOP_IR_DEC 0x07 /* Fetch and decrement */
  163. #define EOP_IR_QCHK1 0x0d /* Queue check, 64 byte msg */
  164. #define EOP_IR_QCHK2 0x0e /* Queue check, 128 byte msg */
  165. /* GAMIRR - Registered AMOs with implicit operands */
  166. #define EOP_IRR_FETCH 0x01 /* Registered fetch of memory */
  167. #define EOP_IRR_CLR 0x02 /* Registered fetch and clear */
  168. #define EOP_IRR_INC 0x05 /* Registered fetch and increment */
  169. #define EOP_IRR_DEC 0x07 /* Registered fetch and decrement */
  170. #define EOP_IRR_DECZ 0x0f /* Registered fetch and decrement, update on zero*/
  171. /* GAMER - AMOs with explicit operands */
  172. #define EOP_ER_SWAP 0x00 /* Exchange argument and memory */
  173. #define EOP_ER_OR 0x01 /* Logical OR with memory */
  174. #define EOP_ER_AND 0x02 /* Logical AND with memory */
  175. #define EOP_ER_XOR 0x03 /* Logical XOR with memory */
  176. #define EOP_ER_ADD 0x04 /* Add value to memory */
  177. #define EOP_ER_CSWAP 0x08 /* Compare with operand2, write operand1 if match*/
  178. #define EOP_ER_CADD 0x0c /* Queue check, operand1*64 byte msg */
  179. /* GAMERR - Registered AMOs with explicit operands */
  180. #define EOP_ERR_SWAP 0x00 /* Exchange argument and memory */
  181. #define EOP_ERR_OR 0x01 /* Logical OR with memory */
  182. #define EOP_ERR_AND 0x02 /* Logical AND with memory */
  183. #define EOP_ERR_XOR 0x03 /* Logical XOR with memory */
  184. #define EOP_ERR_ADD 0x04 /* Add value to memory */
  185. #define EOP_ERR_CSWAP 0x08 /* Compare with operand2, write operand1 if match*/
  186. #define EOP_ERR_EPOLL 0x09 /* Poll for equality */
  187. #define EOP_ERR_NPOLL 0x0a /* Poll for inequality */
  188. /* GAMXR - SGI Arithmetic unit */
  189. #define EOP_XR_CSWAP 0x0b /* Masked compare exchange */
  190. /* Transfer types (xtype field) */
  191. #define XTYPE_B 0x0 /* byte */
  192. #define XTYPE_S 0x1 /* short (2-byte) */
  193. #define XTYPE_W 0x2 /* word (4-byte) */
  194. #define XTYPE_DW 0x3 /* doubleword (8-byte) */
  195. #define XTYPE_CL 0x6 /* cacheline (64-byte) */
  196. /* Instruction access attributes (iaa0, iaa1 fields) */
  197. #define IAA_RAM 0x0 /* normal cached RAM access */
  198. #define IAA_NCRAM 0x2 /* noncoherent RAM access */
  199. #define IAA_MMIO 0x1 /* noncoherent memory-mapped I/O space */
  200. #define IAA_REGISTER 0x3 /* memory-mapped registers, etc. */
  201. /* Instruction mode attributes (ima field) */
  202. #define IMA_MAPPED 0x0 /* Virtual mode */
  203. #define IMA_CB_DELAY 0x1 /* hold read responses until status changes */
  204. #define IMA_UNMAPPED 0x2 /* bypass the TLBs (OS only) */
  205. #define IMA_INTERRUPT 0x4 /* Interrupt when instruction completes */
  206. /* CBE ecause bits */
  207. #define CBE_CAUSE_RI (1 << 0)
  208. #define CBE_CAUSE_INVALID_INSTRUCTION (1 << 1)
  209. #define CBE_CAUSE_UNMAPPED_MODE_FORBIDDEN (1 << 2)
  210. #define CBE_CAUSE_PE_CHECK_DATA_ERROR (1 << 3)
  211. #define CBE_CAUSE_IAA_GAA_MISMATCH (1 << 4)
  212. #define CBE_CAUSE_DATA_SEGMENT_LIMIT_EXCEPTION (1 << 5)
  213. #define CBE_CAUSE_OS_FATAL_TLB_FAULT (1 << 6)
  214. #define CBE_CAUSE_EXECUTION_HW_ERROR (1 << 7)
  215. #define CBE_CAUSE_TLBHW_ERROR (1 << 8)
  216. #define CBE_CAUSE_RA_REQUEST_TIMEOUT (1 << 9)
  217. #define CBE_CAUSE_HA_REQUEST_TIMEOUT (1 << 10)
  218. #define CBE_CAUSE_RA_RESPONSE_FATAL (1 << 11)
  219. #define CBE_CAUSE_RA_RESPONSE_NON_FATAL (1 << 12)
  220. #define CBE_CAUSE_HA_RESPONSE_FATAL (1 << 13)
  221. #define CBE_CAUSE_HA_RESPONSE_NON_FATAL (1 << 14)
  222. #define CBE_CAUSE_ADDRESS_SPACE_DECODE_ERROR (1 << 15)
  223. #define CBE_CAUSE_RESPONSE_DATA_ERROR (1 << 16)
  224. #define CBE_CAUSE_PROTOCOL_STATE_DATA_ERROR (1 << 17)
  225. /*
  226. * Exceptions are retried for the following cases. If any OTHER bits are set
  227. * in ecause, the exception is not retryable.
  228. */
  229. #define EXCEPTION_RETRY_BITS (CBE_CAUSE_RESPONSE_DATA_ERROR | \
  230. CBE_CAUSE_RA_REQUEST_TIMEOUT | \
  231. CBE_CAUSE_TLBHW_ERROR | \
  232. CBE_CAUSE_HA_REQUEST_TIMEOUT)
  233. /* Message queue head structure */
  234. union gru_mesqhead {
  235. unsigned long val;
  236. struct {
  237. unsigned int head;
  238. unsigned int limit;
  239. };
  240. };
  241. /* Generate the low word of a GRU instruction */
  242. static inline unsigned int
  243. __opword(unsigned char opcode, unsigned char exopc, unsigned char xtype,
  244. unsigned char iaa0, unsigned char iaa1,
  245. unsigned char ima)
  246. {
  247. return (1 << GRU_CB_ICMD_SHFT) |
  248. (iaa0 << GRU_CB_IAA0_SHFT) |
  249. (iaa1 << GRU_CB_IAA1_SHFT) |
  250. (ima << GRU_CB_IMA_SHFT) |
  251. (xtype << GRU_CB_XTYPE_SHFT) |
  252. (opcode << GRU_CB_OPC_SHFT) |
  253. (exopc << GRU_CB_EXOPC_SHFT);
  254. }
  255. /*
  256. * Architecture specific intrinsics
  257. */
  258. static inline void gru_flush_cache(void *p)
  259. {
  260. __flush_cache(p);
  261. }
  262. /*
  263. * Store the lower 32 bits of the command including the "start" bit. Then
  264. * start the instruction executing.
  265. */
  266. static inline void gru_start_instruction(struct gru_instruction *ins, int op32)
  267. {
  268. gru_ordered_store_int(ins, op32);
  269. gru_flush_cache(ins);
  270. }
  271. /* Convert "hints" to IMA */
  272. #define CB_IMA(h) ((h) | IMA_UNMAPPED)
  273. /* Convert data segment cache line index into TRI0 / TRI1 value */
  274. #define GRU_DINDEX(i) ((i) * GRU_CACHE_LINE_BYTES)
  275. /* Inline functions for GRU instructions.
  276. * Note:
  277. * - nelem and stride are in elements
  278. * - tri0/tri1 is in bytes for the beginning of the data segment.
  279. */
  280. static inline void gru_vload(void *cb, unsigned long mem_addr,
  281. unsigned int tri0, unsigned char xtype, unsigned long nelem,
  282. unsigned long stride, unsigned long hints)
  283. {
  284. struct gru_instruction *ins = (struct gru_instruction *)cb;
  285. ins->baddr0 = (long)mem_addr;
  286. ins->nelem = nelem;
  287. ins->tri0 = tri0;
  288. ins->op1_stride = stride;
  289. gru_start_instruction(ins, __opword(OP_VLOAD, 0, xtype, IAA_RAM, 0,
  290. CB_IMA(hints)));
  291. }
  292. static inline void gru_vstore(void *cb, unsigned long mem_addr,
  293. unsigned int tri0, unsigned char xtype, unsigned long nelem,
  294. unsigned long stride, unsigned long hints)
  295. {
  296. struct gru_instruction *ins = (void *)cb;
  297. ins->baddr0 = (long)mem_addr;
  298. ins->nelem = nelem;
  299. ins->tri0 = tri0;
  300. ins->op1_stride = stride;
  301. gru_start_instruction(ins, __opword(OP_VSTORE, 0, xtype, IAA_RAM, 0,
  302. CB_IMA(hints)));
  303. }
  304. static inline void gru_ivload(void *cb, unsigned long mem_addr,
  305. unsigned int tri0, unsigned int tri1, unsigned char xtype,
  306. unsigned long nelem, unsigned long hints)
  307. {
  308. struct gru_instruction *ins = (void *)cb;
  309. ins->baddr0 = (long)mem_addr;
  310. ins->nelem = nelem;
  311. ins->tri0 = tri0;
  312. ins->tri1_bufsize = tri1;
  313. gru_start_instruction(ins, __opword(OP_IVLOAD, 0, xtype, IAA_RAM, 0,
  314. CB_IMA(hints)));
  315. }
  316. static inline void gru_ivstore(void *cb, unsigned long mem_addr,
  317. unsigned int tri0, unsigned int tri1,
  318. unsigned char xtype, unsigned long nelem, unsigned long hints)
  319. {
  320. struct gru_instruction *ins = (void *)cb;
  321. ins->baddr0 = (long)mem_addr;
  322. ins->nelem = nelem;
  323. ins->tri0 = tri0;
  324. ins->tri1_bufsize = tri1;
  325. gru_start_instruction(ins, __opword(OP_IVSTORE, 0, xtype, IAA_RAM, 0,
  326. CB_IMA(hints)));
  327. }
  328. static inline void gru_vset(void *cb, unsigned long mem_addr,
  329. unsigned long value, unsigned char xtype, unsigned long nelem,
  330. unsigned long stride, unsigned long hints)
  331. {
  332. struct gru_instruction *ins = (void *)cb;
  333. ins->baddr0 = (long)mem_addr;
  334. ins->op2_value_baddr1 = value;
  335. ins->nelem = nelem;
  336. ins->op1_stride = stride;
  337. gru_start_instruction(ins, __opword(OP_VSET, 0, xtype, IAA_RAM, 0,
  338. CB_IMA(hints)));
  339. }
  340. static inline void gru_ivset(void *cb, unsigned long mem_addr,
  341. unsigned int tri1, unsigned long value, unsigned char xtype,
  342. unsigned long nelem, unsigned long hints)
  343. {
  344. struct gru_instruction *ins = (void *)cb;
  345. ins->baddr0 = (long)mem_addr;
  346. ins->op2_value_baddr1 = value;
  347. ins->nelem = nelem;
  348. ins->tri1_bufsize = tri1;
  349. gru_start_instruction(ins, __opword(OP_IVSET, 0, xtype, IAA_RAM, 0,
  350. CB_IMA(hints)));
  351. }
  352. static inline void gru_vflush(void *cb, unsigned long mem_addr,
  353. unsigned long nelem, unsigned char xtype, unsigned long stride,
  354. unsigned long hints)
  355. {
  356. struct gru_instruction *ins = (void *)cb;
  357. ins->baddr0 = (long)mem_addr;
  358. ins->op1_stride = stride;
  359. ins->nelem = nelem;
  360. gru_start_instruction(ins, __opword(OP_VFLUSH, 0, xtype, IAA_RAM, 0,
  361. CB_IMA(hints)));
  362. }
  363. static inline void gru_nop(void *cb, int hints)
  364. {
  365. struct gru_instruction *ins = (void *)cb;
  366. gru_start_instruction(ins, __opword(OP_NOP, 0, 0, 0, 0, CB_IMA(hints)));
  367. }
  368. static inline void gru_bcopy(void *cb, const unsigned long src,
  369. unsigned long dest,
  370. unsigned int tri0, unsigned int xtype, unsigned long nelem,
  371. unsigned int bufsize, unsigned long hints)
  372. {
  373. struct gru_instruction *ins = (void *)cb;
  374. ins->baddr0 = (long)src;
  375. ins->op2_value_baddr1 = (long)dest;
  376. ins->nelem = nelem;
  377. ins->tri0 = tri0;
  378. ins->tri1_bufsize = bufsize;
  379. gru_start_instruction(ins, __opword(OP_BCOPY, 0, xtype, IAA_RAM,
  380. IAA_RAM, CB_IMA(hints)));
  381. }
  382. static inline void gru_bstore(void *cb, const unsigned long src,
  383. unsigned long dest, unsigned int tri0, unsigned int xtype,
  384. unsigned long nelem, unsigned long hints)
  385. {
  386. struct gru_instruction *ins = (void *)cb;
  387. ins->baddr0 = (long)src;
  388. ins->op2_value_baddr1 = (long)dest;
  389. ins->nelem = nelem;
  390. ins->tri0 = tri0;
  391. gru_start_instruction(ins, __opword(OP_BSTORE, 0, xtype, 0, IAA_RAM,
  392. CB_IMA(hints)));
  393. }
  394. static inline void gru_gamir(void *cb, int exopc, unsigned long src,
  395. unsigned int xtype, unsigned long hints)
  396. {
  397. struct gru_instruction *ins = (void *)cb;
  398. ins->baddr0 = (long)src;
  399. gru_start_instruction(ins, __opword(OP_GAMIR, exopc, xtype, IAA_RAM, 0,
  400. CB_IMA(hints)));
  401. }
  402. static inline void gru_gamirr(void *cb, int exopc, unsigned long src,
  403. unsigned int xtype, unsigned long hints)
  404. {
  405. struct gru_instruction *ins = (void *)cb;
  406. ins->baddr0 = (long)src;
  407. gru_start_instruction(ins, __opword(OP_GAMIRR, exopc, xtype, IAA_RAM, 0,
  408. CB_IMA(hints)));
  409. }
  410. static inline void gru_gamer(void *cb, int exopc, unsigned long src,
  411. unsigned int xtype,
  412. unsigned long operand1, unsigned long operand2,
  413. unsigned long hints)
  414. {
  415. struct gru_instruction *ins = (void *)cb;
  416. ins->baddr0 = (long)src;
  417. ins->op1_stride = operand1;
  418. ins->op2_value_baddr1 = operand2;
  419. gru_start_instruction(ins, __opword(OP_GAMER, exopc, xtype, IAA_RAM, 0,
  420. CB_IMA(hints)));
  421. }
  422. static inline void gru_gamerr(void *cb, int exopc, unsigned long src,
  423. unsigned int xtype, unsigned long operand1,
  424. unsigned long operand2, unsigned long hints)
  425. {
  426. struct gru_instruction *ins = (void *)cb;
  427. ins->baddr0 = (long)src;
  428. ins->op1_stride = operand1;
  429. ins->op2_value_baddr1 = operand2;
  430. gru_start_instruction(ins, __opword(OP_GAMERR, exopc, xtype, IAA_RAM, 0,
  431. CB_IMA(hints)));
  432. }
  433. static inline void gru_gamxr(void *cb, unsigned long src,
  434. unsigned int tri0, unsigned long hints)
  435. {
  436. struct gru_instruction *ins = (void *)cb;
  437. ins->baddr0 = (long)src;
  438. ins->nelem = 4;
  439. gru_start_instruction(ins, __opword(OP_GAMXR, EOP_XR_CSWAP, XTYPE_DW,
  440. IAA_RAM, 0, CB_IMA(hints)));
  441. }
  442. static inline void gru_mesq(void *cb, unsigned long queue,
  443. unsigned long tri0, unsigned long nelem,
  444. unsigned long hints)
  445. {
  446. struct gru_instruction *ins = (void *)cb;
  447. ins->baddr0 = (long)queue;
  448. ins->nelem = nelem;
  449. ins->tri0 = tri0;
  450. gru_start_instruction(ins, __opword(OP_MESQ, 0, XTYPE_CL, IAA_RAM, 0,
  451. CB_IMA(hints)));
  452. }
  453. static inline unsigned long gru_get_amo_value(void *cb)
  454. {
  455. struct gru_instruction *ins = (void *)cb;
  456. return ins->avalue;
  457. }
  458. static inline int gru_get_amo_value_head(void *cb)
  459. {
  460. struct gru_instruction *ins = (void *)cb;
  461. return ins->avalue & 0xffffffff;
  462. }
  463. static inline int gru_get_amo_value_limit(void *cb)
  464. {
  465. struct gru_instruction *ins = (void *)cb;
  466. return ins->avalue >> 32;
  467. }
  468. static inline union gru_mesqhead gru_mesq_head(int head, int limit)
  469. {
  470. union gru_mesqhead mqh;
  471. mqh.head = head;
  472. mqh.limit = limit;
  473. return mqh;
  474. }
  475. /*
  476. * Get struct control_block_extended_exc_detail for CB.
  477. */
  478. extern int gru_get_cb_exception_detail(void *cb,
  479. struct control_block_extended_exc_detail *excdet);
  480. #define GRU_EXC_STR_SIZE 256
  481. extern int gru_check_status_proc(void *cb);
  482. extern int gru_wait_proc(void *cb);
  483. extern void gru_wait_abort_proc(void *cb);
  484. /*
  485. * Control block definition for checking status
  486. */
  487. struct gru_control_block_status {
  488. unsigned int icmd :1;
  489. unsigned int unused1 :31;
  490. unsigned int unused2 :24;
  491. unsigned int istatus :2;
  492. unsigned int isubstatus :4;
  493. unsigned int inused3 :2;
  494. };
  495. /* Get CB status */
  496. static inline int gru_get_cb_status(void *cb)
  497. {
  498. struct gru_control_block_status *cbs = (void *)cb;
  499. return cbs->istatus;
  500. }
  501. /* Get CB message queue substatus */
  502. static inline int gru_get_cb_message_queue_substatus(void *cb)
  503. {
  504. struct gru_control_block_status *cbs = (void *)cb;
  505. return cbs->isubstatus & CBSS_MSG_QUEUE_MASK;
  506. }
  507. /* Get CB substatus */
  508. static inline int gru_get_cb_substatus(void *cb)
  509. {
  510. struct gru_control_block_status *cbs = (void *)cb;
  511. return cbs->isubstatus;
  512. }
  513. /* Check the status of a CB. If the CB is in UPM mode, call the
  514. * OS to handle the UPM status.
  515. * Returns the CB status field value (0 for normal completion)
  516. */
  517. static inline int gru_check_status(void *cb)
  518. {
  519. struct gru_control_block_status *cbs = (void *)cb;
  520. int ret;
  521. ret = cbs->istatus;
  522. if (ret == CBS_CALL_OS)
  523. ret = gru_check_status_proc(cb);
  524. return ret;
  525. }
  526. /* Wait for CB to complete.
  527. * Returns the CB status field value (0 for normal completion)
  528. */
  529. static inline int gru_wait(void *cb)
  530. {
  531. struct gru_control_block_status *cbs = (void *)cb;
  532. int ret = cbs->istatus;
  533. if (ret != CBS_IDLE)
  534. ret = gru_wait_proc(cb);
  535. return ret;
  536. }
  537. /* Wait for CB to complete. Aborts program if error. (Note: error does NOT
  538. * mean TLB mis - only fatal errors such as memory parity error or user
  539. * bugs will cause termination.
  540. */
  541. static inline void gru_wait_abort(void *cb)
  542. {
  543. struct gru_control_block_status *cbs = (void *)cb;
  544. if (cbs->istatus != CBS_IDLE)
  545. gru_wait_abort_proc(cb);
  546. }
  547. /*
  548. * Get a pointer to a control block
  549. * gseg - GSeg address returned from gru_get_thread_gru_segment()
  550. * index - index of desired CB
  551. */
  552. static inline void *gru_get_cb_pointer(void *gseg,
  553. int index)
  554. {
  555. return gseg + GRU_CB_BASE + index * GRU_HANDLE_STRIDE;
  556. }
  557. /*
  558. * Get a pointer to a cacheline in the data segment portion of a GSeg
  559. * gseg - GSeg address returned from gru_get_thread_gru_segment()
  560. * index - index of desired cache line
  561. */
  562. static inline void *gru_get_data_pointer(void *gseg, int index)
  563. {
  564. return gseg + GRU_DS_BASE + index * GRU_CACHE_LINE_BYTES;
  565. }
  566. /*
  567. * Convert a vaddr into the tri index within the GSEG
  568. * vaddr - virtual address of within gseg
  569. */
  570. static inline int gru_get_tri(void *vaddr)
  571. {
  572. return ((unsigned long)vaddr & (GRU_GSEG_PAGESIZE - 1)) - GRU_DS_BASE;
  573. }
  574. #endif /* __GRU_INSTRUCTIONS_H__ */