wm8350-core.c 38 KB

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  1. /*
  2. * wm8350-core.c -- Device access for Wolfson WM8350
  3. *
  4. * Copyright 2007, 2008 Wolfson Microelectronics PLC.
  5. *
  6. * Author: Liam Girdwood, Mark Brown
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/init.h>
  17. #include <linux/bug.h>
  18. #include <linux/device.h>
  19. #include <linux/delay.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/workqueue.h>
  22. #include <linux/mfd/wm8350/core.h>
  23. #include <linux/mfd/wm8350/audio.h>
  24. #include <linux/mfd/wm8350/comparator.h>
  25. #include <linux/mfd/wm8350/gpio.h>
  26. #include <linux/mfd/wm8350/pmic.h>
  27. #include <linux/mfd/wm8350/rtc.h>
  28. #include <linux/mfd/wm8350/supply.h>
  29. #include <linux/mfd/wm8350/wdt.h>
  30. #define WM8350_UNLOCK_KEY 0x0013
  31. #define WM8350_LOCK_KEY 0x0000
  32. #define WM8350_CLOCK_CONTROL_1 0x28
  33. #define WM8350_AIF_TEST 0x74
  34. /* debug */
  35. #define WM8350_BUS_DEBUG 0
  36. #if WM8350_BUS_DEBUG
  37. #define dump(regs, src) do { \
  38. int i_; \
  39. u16 *src_ = src; \
  40. printk(KERN_DEBUG); \
  41. for (i_ = 0; i_ < regs; i_++) \
  42. printk(" 0x%4.4x", *src_++); \
  43. printk("\n"); \
  44. } while (0);
  45. #else
  46. #define dump(bytes, src)
  47. #endif
  48. #define WM8350_LOCK_DEBUG 0
  49. #if WM8350_LOCK_DEBUG
  50. #define ldbg(format, arg...) printk(format, ## arg)
  51. #else
  52. #define ldbg(format, arg...)
  53. #endif
  54. /*
  55. * WM8350 Device IO
  56. */
  57. static DEFINE_MUTEX(io_mutex);
  58. static DEFINE_MUTEX(reg_lock_mutex);
  59. static DEFINE_MUTEX(auxadc_mutex);
  60. /* Perform a physical read from the device.
  61. */
  62. static int wm8350_phys_read(struct wm8350 *wm8350, u8 reg, int num_regs,
  63. u16 *dest)
  64. {
  65. int i, ret;
  66. int bytes = num_regs * 2;
  67. dev_dbg(wm8350->dev, "volatile read\n");
  68. ret = wm8350->read_dev(wm8350, reg, bytes, (char *)dest);
  69. for (i = reg; i < reg + num_regs; i++) {
  70. /* Cache is CPU endian */
  71. dest[i - reg] = be16_to_cpu(dest[i - reg]);
  72. /* Satisfy non-volatile bits from cache */
  73. dest[i - reg] &= wm8350_reg_io_map[i].vol;
  74. dest[i - reg] |= wm8350->reg_cache[i];
  75. /* Mask out non-readable bits */
  76. dest[i - reg] &= wm8350_reg_io_map[i].readable;
  77. }
  78. dump(num_regs, dest);
  79. return ret;
  80. }
  81. static int wm8350_read(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *dest)
  82. {
  83. int i;
  84. int end = reg + num_regs;
  85. int ret = 0;
  86. int bytes = num_regs * 2;
  87. if (wm8350->read_dev == NULL)
  88. return -ENODEV;
  89. if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
  90. dev_err(wm8350->dev, "invalid reg %x\n",
  91. reg + num_regs - 1);
  92. return -EINVAL;
  93. }
  94. dev_dbg(wm8350->dev,
  95. "%s R%d(0x%2.2x) %d regs\n", __func__, reg, reg, num_regs);
  96. #if WM8350_BUS_DEBUG
  97. /* we can _safely_ read any register, but warn if read not supported */
  98. for (i = reg; i < end; i++) {
  99. if (!wm8350_reg_io_map[i].readable)
  100. dev_warn(wm8350->dev,
  101. "reg R%d is not readable\n", i);
  102. }
  103. #endif
  104. /* if any volatile registers are required, then read back all */
  105. for (i = reg; i < end; i++)
  106. if (wm8350_reg_io_map[i].vol)
  107. return wm8350_phys_read(wm8350, reg, num_regs, dest);
  108. /* no volatiles, then cache is good */
  109. dev_dbg(wm8350->dev, "cache read\n");
  110. memcpy(dest, &wm8350->reg_cache[reg], bytes);
  111. dump(num_regs, dest);
  112. return ret;
  113. }
  114. static inline int is_reg_locked(struct wm8350 *wm8350, u8 reg)
  115. {
  116. if (reg == WM8350_SECURITY ||
  117. wm8350->reg_cache[WM8350_SECURITY] == WM8350_UNLOCK_KEY)
  118. return 0;
  119. if ((reg == WM8350_GPIO_CONFIGURATION_I_O) ||
  120. (reg >= WM8350_GPIO_FUNCTION_SELECT_1 &&
  121. reg <= WM8350_GPIO_FUNCTION_SELECT_4) ||
  122. (reg >= WM8350_BATTERY_CHARGER_CONTROL_1 &&
  123. reg <= WM8350_BATTERY_CHARGER_CONTROL_3))
  124. return 1;
  125. return 0;
  126. }
  127. static int wm8350_write(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *src)
  128. {
  129. int i;
  130. int end = reg + num_regs;
  131. int bytes = num_regs * 2;
  132. if (wm8350->write_dev == NULL)
  133. return -ENODEV;
  134. if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
  135. dev_err(wm8350->dev, "invalid reg %x\n",
  136. reg + num_regs - 1);
  137. return -EINVAL;
  138. }
  139. /* it's generally not a good idea to write to RO or locked registers */
  140. for (i = reg; i < end; i++) {
  141. if (!wm8350_reg_io_map[i].writable) {
  142. dev_err(wm8350->dev,
  143. "attempted write to read only reg R%d\n", i);
  144. return -EINVAL;
  145. }
  146. if (is_reg_locked(wm8350, i)) {
  147. dev_err(wm8350->dev,
  148. "attempted write to locked reg R%d\n", i);
  149. return -EINVAL;
  150. }
  151. src[i - reg] &= wm8350_reg_io_map[i].writable;
  152. wm8350->reg_cache[i] =
  153. (wm8350->reg_cache[i] & ~wm8350_reg_io_map[i].writable)
  154. | src[i - reg];
  155. /* Don't store volatile bits */
  156. wm8350->reg_cache[i] &= ~wm8350_reg_io_map[i].vol;
  157. src[i - reg] = cpu_to_be16(src[i - reg]);
  158. }
  159. /* Actually write it out */
  160. return wm8350->write_dev(wm8350, reg, bytes, (char *)src);
  161. }
  162. /*
  163. * Safe read, modify, write methods
  164. */
  165. int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
  166. {
  167. u16 data;
  168. int err;
  169. mutex_lock(&io_mutex);
  170. err = wm8350_read(wm8350, reg, 1, &data);
  171. if (err) {
  172. dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
  173. goto out;
  174. }
  175. data &= ~mask;
  176. err = wm8350_write(wm8350, reg, 1, &data);
  177. if (err)
  178. dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
  179. out:
  180. mutex_unlock(&io_mutex);
  181. return err;
  182. }
  183. EXPORT_SYMBOL_GPL(wm8350_clear_bits);
  184. int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
  185. {
  186. u16 data;
  187. int err;
  188. mutex_lock(&io_mutex);
  189. err = wm8350_read(wm8350, reg, 1, &data);
  190. if (err) {
  191. dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
  192. goto out;
  193. }
  194. data |= mask;
  195. err = wm8350_write(wm8350, reg, 1, &data);
  196. if (err)
  197. dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
  198. out:
  199. mutex_unlock(&io_mutex);
  200. return err;
  201. }
  202. EXPORT_SYMBOL_GPL(wm8350_set_bits);
  203. u16 wm8350_reg_read(struct wm8350 *wm8350, int reg)
  204. {
  205. u16 data;
  206. int err;
  207. mutex_lock(&io_mutex);
  208. err = wm8350_read(wm8350, reg, 1, &data);
  209. if (err)
  210. dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
  211. mutex_unlock(&io_mutex);
  212. return data;
  213. }
  214. EXPORT_SYMBOL_GPL(wm8350_reg_read);
  215. int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val)
  216. {
  217. int ret;
  218. u16 data = val;
  219. mutex_lock(&io_mutex);
  220. ret = wm8350_write(wm8350, reg, 1, &data);
  221. if (ret)
  222. dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
  223. mutex_unlock(&io_mutex);
  224. return ret;
  225. }
  226. EXPORT_SYMBOL_GPL(wm8350_reg_write);
  227. int wm8350_block_read(struct wm8350 *wm8350, int start_reg, int regs,
  228. u16 *dest)
  229. {
  230. int err = 0;
  231. mutex_lock(&io_mutex);
  232. err = wm8350_read(wm8350, start_reg, regs, dest);
  233. if (err)
  234. dev_err(wm8350->dev, "block read starting from R%d failed\n",
  235. start_reg);
  236. mutex_unlock(&io_mutex);
  237. return err;
  238. }
  239. EXPORT_SYMBOL_GPL(wm8350_block_read);
  240. int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs,
  241. u16 *src)
  242. {
  243. int ret = 0;
  244. mutex_lock(&io_mutex);
  245. ret = wm8350_write(wm8350, start_reg, regs, src);
  246. if (ret)
  247. dev_err(wm8350->dev, "block write starting at R%d failed\n",
  248. start_reg);
  249. mutex_unlock(&io_mutex);
  250. return ret;
  251. }
  252. EXPORT_SYMBOL_GPL(wm8350_block_write);
  253. int wm8350_reg_lock(struct wm8350 *wm8350)
  254. {
  255. u16 key = WM8350_LOCK_KEY;
  256. int ret;
  257. ldbg(__func__);
  258. mutex_lock(&io_mutex);
  259. ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
  260. if (ret)
  261. dev_err(wm8350->dev, "lock failed\n");
  262. mutex_unlock(&io_mutex);
  263. return ret;
  264. }
  265. EXPORT_SYMBOL_GPL(wm8350_reg_lock);
  266. int wm8350_reg_unlock(struct wm8350 *wm8350)
  267. {
  268. u16 key = WM8350_UNLOCK_KEY;
  269. int ret;
  270. ldbg(__func__);
  271. mutex_lock(&io_mutex);
  272. ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
  273. if (ret)
  274. dev_err(wm8350->dev, "unlock failed\n");
  275. mutex_unlock(&io_mutex);
  276. return ret;
  277. }
  278. EXPORT_SYMBOL_GPL(wm8350_reg_unlock);
  279. static void wm8350_irq_call_handler(struct wm8350 *wm8350, int irq)
  280. {
  281. mutex_lock(&wm8350->irq_mutex);
  282. if (wm8350->irq[irq].handler)
  283. wm8350->irq[irq].handler(wm8350, irq, wm8350->irq[irq].data);
  284. else {
  285. dev_err(wm8350->dev, "irq %d nobody cared. now masked.\n",
  286. irq);
  287. wm8350_mask_irq(wm8350, irq);
  288. }
  289. mutex_unlock(&wm8350->irq_mutex);
  290. }
  291. /*
  292. * wm8350_irq_worker actually handles the interrupts. Since all
  293. * interrupts are clear on read the IRQ line will be reasserted and
  294. * the physical IRQ will be handled again if another interrupt is
  295. * asserted while we run - in the normal course of events this is a
  296. * rare occurrence so we save I2C/SPI reads.
  297. */
  298. static void wm8350_irq_worker(struct work_struct *work)
  299. {
  300. struct wm8350 *wm8350 = container_of(work, struct wm8350, irq_work);
  301. u16 level_one, status1, status2, comp;
  302. /* TODO: Use block reads to improve performance? */
  303. level_one = wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS)
  304. & ~wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK);
  305. status1 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_1)
  306. & ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_1_MASK);
  307. status2 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_2)
  308. & ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_2_MASK);
  309. comp = wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS)
  310. & ~wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS_MASK);
  311. /* over current */
  312. if (level_one & WM8350_OC_INT) {
  313. u16 oc;
  314. oc = wm8350_reg_read(wm8350, WM8350_OVER_CURRENT_INT_STATUS);
  315. oc &= ~wm8350_reg_read(wm8350,
  316. WM8350_OVER_CURRENT_INT_STATUS_MASK);
  317. if (oc & WM8350_OC_LS_EINT) /* limit switch */
  318. wm8350_irq_call_handler(wm8350, WM8350_IRQ_OC_LS);
  319. }
  320. /* under voltage */
  321. if (level_one & WM8350_UV_INT) {
  322. u16 uv;
  323. uv = wm8350_reg_read(wm8350, WM8350_UNDER_VOLTAGE_INT_STATUS);
  324. uv &= ~wm8350_reg_read(wm8350,
  325. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK);
  326. if (uv & WM8350_UV_DC1_EINT)
  327. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC1);
  328. if (uv & WM8350_UV_DC2_EINT)
  329. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC2);
  330. if (uv & WM8350_UV_DC3_EINT)
  331. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC3);
  332. if (uv & WM8350_UV_DC4_EINT)
  333. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC4);
  334. if (uv & WM8350_UV_DC5_EINT)
  335. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC5);
  336. if (uv & WM8350_UV_DC6_EINT)
  337. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC6);
  338. if (uv & WM8350_UV_LDO1_EINT)
  339. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO1);
  340. if (uv & WM8350_UV_LDO2_EINT)
  341. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO2);
  342. if (uv & WM8350_UV_LDO3_EINT)
  343. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO3);
  344. if (uv & WM8350_UV_LDO4_EINT)
  345. wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO4);
  346. }
  347. /* charger, RTC */
  348. if (status1) {
  349. if (status1 & WM8350_CHG_BAT_HOT_EINT)
  350. wm8350_irq_call_handler(wm8350,
  351. WM8350_IRQ_CHG_BAT_HOT);
  352. if (status1 & WM8350_CHG_BAT_COLD_EINT)
  353. wm8350_irq_call_handler(wm8350,
  354. WM8350_IRQ_CHG_BAT_COLD);
  355. if (status1 & WM8350_CHG_BAT_FAIL_EINT)
  356. wm8350_irq_call_handler(wm8350,
  357. WM8350_IRQ_CHG_BAT_FAIL);
  358. if (status1 & WM8350_CHG_TO_EINT)
  359. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_TO);
  360. if (status1 & WM8350_CHG_END_EINT)
  361. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_END);
  362. if (status1 & WM8350_CHG_START_EINT)
  363. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_START);
  364. if (status1 & WM8350_CHG_FAST_RDY_EINT)
  365. wm8350_irq_call_handler(wm8350,
  366. WM8350_IRQ_CHG_FAST_RDY);
  367. if (status1 & WM8350_CHG_VBATT_LT_3P9_EINT)
  368. wm8350_irq_call_handler(wm8350,
  369. WM8350_IRQ_CHG_VBATT_LT_3P9);
  370. if (status1 & WM8350_CHG_VBATT_LT_3P1_EINT)
  371. wm8350_irq_call_handler(wm8350,
  372. WM8350_IRQ_CHG_VBATT_LT_3P1);
  373. if (status1 & WM8350_CHG_VBATT_LT_2P85_EINT)
  374. wm8350_irq_call_handler(wm8350,
  375. WM8350_IRQ_CHG_VBATT_LT_2P85);
  376. if (status1 & WM8350_RTC_ALM_EINT)
  377. wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_ALM);
  378. if (status1 & WM8350_RTC_SEC_EINT)
  379. wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_SEC);
  380. if (status1 & WM8350_RTC_PER_EINT)
  381. wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_PER);
  382. }
  383. /* current sink, system, aux adc */
  384. if (status2) {
  385. if (status2 & WM8350_CS1_EINT)
  386. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS1);
  387. if (status2 & WM8350_CS2_EINT)
  388. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS2);
  389. if (status2 & WM8350_SYS_HYST_COMP_FAIL_EINT)
  390. wm8350_irq_call_handler(wm8350,
  391. WM8350_IRQ_SYS_HYST_COMP_FAIL);
  392. if (status2 & WM8350_SYS_CHIP_GT115_EINT)
  393. wm8350_irq_call_handler(wm8350,
  394. WM8350_IRQ_SYS_CHIP_GT115);
  395. if (status2 & WM8350_SYS_CHIP_GT140_EINT)
  396. wm8350_irq_call_handler(wm8350,
  397. WM8350_IRQ_SYS_CHIP_GT140);
  398. if (status2 & WM8350_SYS_WDOG_TO_EINT)
  399. wm8350_irq_call_handler(wm8350,
  400. WM8350_IRQ_SYS_WDOG_TO);
  401. if (status2 & WM8350_AUXADC_DATARDY_EINT)
  402. wm8350_irq_call_handler(wm8350,
  403. WM8350_IRQ_AUXADC_DATARDY);
  404. if (status2 & WM8350_AUXADC_DCOMP4_EINT)
  405. wm8350_irq_call_handler(wm8350,
  406. WM8350_IRQ_AUXADC_DCOMP4);
  407. if (status2 & WM8350_AUXADC_DCOMP3_EINT)
  408. wm8350_irq_call_handler(wm8350,
  409. WM8350_IRQ_AUXADC_DCOMP3);
  410. if (status2 & WM8350_AUXADC_DCOMP2_EINT)
  411. wm8350_irq_call_handler(wm8350,
  412. WM8350_IRQ_AUXADC_DCOMP2);
  413. if (status2 & WM8350_AUXADC_DCOMP1_EINT)
  414. wm8350_irq_call_handler(wm8350,
  415. WM8350_IRQ_AUXADC_DCOMP1);
  416. if (status2 & WM8350_USB_LIMIT_EINT)
  417. wm8350_irq_call_handler(wm8350, WM8350_IRQ_USB_LIMIT);
  418. }
  419. /* wake, codec, ext */
  420. if (comp) {
  421. if (comp & WM8350_WKUP_OFF_STATE_EINT)
  422. wm8350_irq_call_handler(wm8350,
  423. WM8350_IRQ_WKUP_OFF_STATE);
  424. if (comp & WM8350_WKUP_HIB_STATE_EINT)
  425. wm8350_irq_call_handler(wm8350,
  426. WM8350_IRQ_WKUP_HIB_STATE);
  427. if (comp & WM8350_WKUP_CONV_FAULT_EINT)
  428. wm8350_irq_call_handler(wm8350,
  429. WM8350_IRQ_WKUP_CONV_FAULT);
  430. if (comp & WM8350_WKUP_WDOG_RST_EINT)
  431. wm8350_irq_call_handler(wm8350,
  432. WM8350_IRQ_WKUP_WDOG_RST);
  433. if (comp & WM8350_WKUP_GP_PWR_ON_EINT)
  434. wm8350_irq_call_handler(wm8350,
  435. WM8350_IRQ_WKUP_GP_PWR_ON);
  436. if (comp & WM8350_WKUP_ONKEY_EINT)
  437. wm8350_irq_call_handler(wm8350, WM8350_IRQ_WKUP_ONKEY);
  438. if (comp & WM8350_WKUP_GP_WAKEUP_EINT)
  439. wm8350_irq_call_handler(wm8350,
  440. WM8350_IRQ_WKUP_GP_WAKEUP);
  441. if (comp & WM8350_CODEC_JCK_DET_L_EINT)
  442. wm8350_irq_call_handler(wm8350,
  443. WM8350_IRQ_CODEC_JCK_DET_L);
  444. if (comp & WM8350_CODEC_JCK_DET_R_EINT)
  445. wm8350_irq_call_handler(wm8350,
  446. WM8350_IRQ_CODEC_JCK_DET_R);
  447. if (comp & WM8350_CODEC_MICSCD_EINT)
  448. wm8350_irq_call_handler(wm8350,
  449. WM8350_IRQ_CODEC_MICSCD);
  450. if (comp & WM8350_CODEC_MICD_EINT)
  451. wm8350_irq_call_handler(wm8350, WM8350_IRQ_CODEC_MICD);
  452. if (comp & WM8350_EXT_USB_FB_EINT)
  453. wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_USB_FB);
  454. if (comp & WM8350_EXT_WALL_FB_EINT)
  455. wm8350_irq_call_handler(wm8350,
  456. WM8350_IRQ_EXT_WALL_FB);
  457. if (comp & WM8350_EXT_BAT_FB_EINT)
  458. wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_BAT_FB);
  459. }
  460. if (level_one & WM8350_GP_INT) {
  461. int i;
  462. u16 gpio;
  463. gpio = wm8350_reg_read(wm8350, WM8350_GPIO_INT_STATUS);
  464. gpio &= ~wm8350_reg_read(wm8350,
  465. WM8350_GPIO_INT_STATUS_MASK);
  466. for (i = 0; i < 12; i++) {
  467. if (gpio & (1 << i))
  468. wm8350_irq_call_handler(wm8350,
  469. WM8350_IRQ_GPIO(i));
  470. }
  471. }
  472. enable_irq(wm8350->chip_irq);
  473. }
  474. static irqreturn_t wm8350_irq(int irq, void *data)
  475. {
  476. struct wm8350 *wm8350 = data;
  477. disable_irq_nosync(irq);
  478. schedule_work(&wm8350->irq_work);
  479. return IRQ_HANDLED;
  480. }
  481. int wm8350_register_irq(struct wm8350 *wm8350, int irq,
  482. void (*handler) (struct wm8350 *, int, void *),
  483. void *data)
  484. {
  485. if (irq < 0 || irq > WM8350_NUM_IRQ || !handler)
  486. return -EINVAL;
  487. if (wm8350->irq[irq].handler)
  488. return -EBUSY;
  489. mutex_lock(&wm8350->irq_mutex);
  490. wm8350->irq[irq].handler = handler;
  491. wm8350->irq[irq].data = data;
  492. mutex_unlock(&wm8350->irq_mutex);
  493. return 0;
  494. }
  495. EXPORT_SYMBOL_GPL(wm8350_register_irq);
  496. int wm8350_free_irq(struct wm8350 *wm8350, int irq)
  497. {
  498. if (irq < 0 || irq > WM8350_NUM_IRQ)
  499. return -EINVAL;
  500. mutex_lock(&wm8350->irq_mutex);
  501. wm8350->irq[irq].handler = NULL;
  502. mutex_unlock(&wm8350->irq_mutex);
  503. return 0;
  504. }
  505. EXPORT_SYMBOL_GPL(wm8350_free_irq);
  506. int wm8350_mask_irq(struct wm8350 *wm8350, int irq)
  507. {
  508. switch (irq) {
  509. case WM8350_IRQ_CHG_BAT_HOT:
  510. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  511. WM8350_IM_CHG_BAT_HOT_EINT);
  512. case WM8350_IRQ_CHG_BAT_COLD:
  513. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  514. WM8350_IM_CHG_BAT_COLD_EINT);
  515. case WM8350_IRQ_CHG_BAT_FAIL:
  516. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  517. WM8350_IM_CHG_BAT_FAIL_EINT);
  518. case WM8350_IRQ_CHG_TO:
  519. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  520. WM8350_IM_CHG_TO_EINT);
  521. case WM8350_IRQ_CHG_END:
  522. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  523. WM8350_IM_CHG_END_EINT);
  524. case WM8350_IRQ_CHG_START:
  525. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  526. WM8350_IM_CHG_START_EINT);
  527. case WM8350_IRQ_CHG_FAST_RDY:
  528. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  529. WM8350_IM_CHG_FAST_RDY_EINT);
  530. case WM8350_IRQ_RTC_PER:
  531. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  532. WM8350_IM_RTC_PER_EINT);
  533. case WM8350_IRQ_RTC_SEC:
  534. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  535. WM8350_IM_RTC_SEC_EINT);
  536. case WM8350_IRQ_RTC_ALM:
  537. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  538. WM8350_IM_RTC_ALM_EINT);
  539. case WM8350_IRQ_CHG_VBATT_LT_3P9:
  540. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  541. WM8350_IM_CHG_VBATT_LT_3P9_EINT);
  542. case WM8350_IRQ_CHG_VBATT_LT_3P1:
  543. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  544. WM8350_IM_CHG_VBATT_LT_3P1_EINT);
  545. case WM8350_IRQ_CHG_VBATT_LT_2P85:
  546. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  547. WM8350_IM_CHG_VBATT_LT_2P85_EINT);
  548. case WM8350_IRQ_CS1:
  549. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  550. WM8350_IM_CS1_EINT);
  551. case WM8350_IRQ_CS2:
  552. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  553. WM8350_IM_CS2_EINT);
  554. case WM8350_IRQ_USB_LIMIT:
  555. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  556. WM8350_IM_USB_LIMIT_EINT);
  557. case WM8350_IRQ_AUXADC_DATARDY:
  558. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  559. WM8350_IM_AUXADC_DATARDY_EINT);
  560. case WM8350_IRQ_AUXADC_DCOMP4:
  561. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  562. WM8350_IM_AUXADC_DCOMP4_EINT);
  563. case WM8350_IRQ_AUXADC_DCOMP3:
  564. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  565. WM8350_IM_AUXADC_DCOMP3_EINT);
  566. case WM8350_IRQ_AUXADC_DCOMP2:
  567. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  568. WM8350_IM_AUXADC_DCOMP2_EINT);
  569. case WM8350_IRQ_AUXADC_DCOMP1:
  570. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  571. WM8350_IM_AUXADC_DCOMP1_EINT);
  572. case WM8350_IRQ_SYS_HYST_COMP_FAIL:
  573. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  574. WM8350_IM_SYS_HYST_COMP_FAIL_EINT);
  575. case WM8350_IRQ_SYS_CHIP_GT115:
  576. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  577. WM8350_IM_SYS_CHIP_GT115_EINT);
  578. case WM8350_IRQ_SYS_CHIP_GT140:
  579. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  580. WM8350_IM_SYS_CHIP_GT140_EINT);
  581. case WM8350_IRQ_SYS_WDOG_TO:
  582. return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  583. WM8350_IM_SYS_WDOG_TO_EINT);
  584. case WM8350_IRQ_UV_LDO4:
  585. return wm8350_set_bits(wm8350,
  586. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  587. WM8350_IM_UV_LDO4_EINT);
  588. case WM8350_IRQ_UV_LDO3:
  589. return wm8350_set_bits(wm8350,
  590. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  591. WM8350_IM_UV_LDO3_EINT);
  592. case WM8350_IRQ_UV_LDO2:
  593. return wm8350_set_bits(wm8350,
  594. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  595. WM8350_IM_UV_LDO2_EINT);
  596. case WM8350_IRQ_UV_LDO1:
  597. return wm8350_set_bits(wm8350,
  598. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  599. WM8350_IM_UV_LDO1_EINT);
  600. case WM8350_IRQ_UV_DC6:
  601. return wm8350_set_bits(wm8350,
  602. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  603. WM8350_IM_UV_DC6_EINT);
  604. case WM8350_IRQ_UV_DC5:
  605. return wm8350_set_bits(wm8350,
  606. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  607. WM8350_IM_UV_DC5_EINT);
  608. case WM8350_IRQ_UV_DC4:
  609. return wm8350_set_bits(wm8350,
  610. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  611. WM8350_IM_UV_DC4_EINT);
  612. case WM8350_IRQ_UV_DC3:
  613. return wm8350_set_bits(wm8350,
  614. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  615. WM8350_IM_UV_DC3_EINT);
  616. case WM8350_IRQ_UV_DC2:
  617. return wm8350_set_bits(wm8350,
  618. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  619. WM8350_IM_UV_DC2_EINT);
  620. case WM8350_IRQ_UV_DC1:
  621. return wm8350_set_bits(wm8350,
  622. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  623. WM8350_IM_UV_DC1_EINT);
  624. case WM8350_IRQ_OC_LS:
  625. return wm8350_set_bits(wm8350,
  626. WM8350_OVER_CURRENT_INT_STATUS_MASK,
  627. WM8350_IM_OC_LS_EINT);
  628. case WM8350_IRQ_EXT_USB_FB:
  629. return wm8350_set_bits(wm8350,
  630. WM8350_COMPARATOR_INT_STATUS_MASK,
  631. WM8350_IM_EXT_USB_FB_EINT);
  632. case WM8350_IRQ_EXT_WALL_FB:
  633. return wm8350_set_bits(wm8350,
  634. WM8350_COMPARATOR_INT_STATUS_MASK,
  635. WM8350_IM_EXT_WALL_FB_EINT);
  636. case WM8350_IRQ_EXT_BAT_FB:
  637. return wm8350_set_bits(wm8350,
  638. WM8350_COMPARATOR_INT_STATUS_MASK,
  639. WM8350_IM_EXT_BAT_FB_EINT);
  640. case WM8350_IRQ_CODEC_JCK_DET_L:
  641. return wm8350_set_bits(wm8350,
  642. WM8350_COMPARATOR_INT_STATUS_MASK,
  643. WM8350_IM_CODEC_JCK_DET_L_EINT);
  644. case WM8350_IRQ_CODEC_JCK_DET_R:
  645. return wm8350_set_bits(wm8350,
  646. WM8350_COMPARATOR_INT_STATUS_MASK,
  647. WM8350_IM_CODEC_JCK_DET_R_EINT);
  648. case WM8350_IRQ_CODEC_MICSCD:
  649. return wm8350_set_bits(wm8350,
  650. WM8350_COMPARATOR_INT_STATUS_MASK,
  651. WM8350_IM_CODEC_MICSCD_EINT);
  652. case WM8350_IRQ_CODEC_MICD:
  653. return wm8350_set_bits(wm8350,
  654. WM8350_COMPARATOR_INT_STATUS_MASK,
  655. WM8350_IM_CODEC_MICD_EINT);
  656. case WM8350_IRQ_WKUP_OFF_STATE:
  657. return wm8350_set_bits(wm8350,
  658. WM8350_COMPARATOR_INT_STATUS_MASK,
  659. WM8350_IM_WKUP_OFF_STATE_EINT);
  660. case WM8350_IRQ_WKUP_HIB_STATE:
  661. return wm8350_set_bits(wm8350,
  662. WM8350_COMPARATOR_INT_STATUS_MASK,
  663. WM8350_IM_WKUP_HIB_STATE_EINT);
  664. case WM8350_IRQ_WKUP_CONV_FAULT:
  665. return wm8350_set_bits(wm8350,
  666. WM8350_COMPARATOR_INT_STATUS_MASK,
  667. WM8350_IM_WKUP_CONV_FAULT_EINT);
  668. case WM8350_IRQ_WKUP_WDOG_RST:
  669. return wm8350_set_bits(wm8350,
  670. WM8350_COMPARATOR_INT_STATUS_MASK,
  671. WM8350_IM_WKUP_OFF_STATE_EINT);
  672. case WM8350_IRQ_WKUP_GP_PWR_ON:
  673. return wm8350_set_bits(wm8350,
  674. WM8350_COMPARATOR_INT_STATUS_MASK,
  675. WM8350_IM_WKUP_GP_PWR_ON_EINT);
  676. case WM8350_IRQ_WKUP_ONKEY:
  677. return wm8350_set_bits(wm8350,
  678. WM8350_COMPARATOR_INT_STATUS_MASK,
  679. WM8350_IM_WKUP_ONKEY_EINT);
  680. case WM8350_IRQ_WKUP_GP_WAKEUP:
  681. return wm8350_set_bits(wm8350,
  682. WM8350_COMPARATOR_INT_STATUS_MASK,
  683. WM8350_IM_WKUP_GP_WAKEUP_EINT);
  684. case WM8350_IRQ_GPIO(0):
  685. return wm8350_set_bits(wm8350,
  686. WM8350_GPIO_INT_STATUS_MASK,
  687. WM8350_IM_GP0_EINT);
  688. case WM8350_IRQ_GPIO(1):
  689. return wm8350_set_bits(wm8350,
  690. WM8350_GPIO_INT_STATUS_MASK,
  691. WM8350_IM_GP1_EINT);
  692. case WM8350_IRQ_GPIO(2):
  693. return wm8350_set_bits(wm8350,
  694. WM8350_GPIO_INT_STATUS_MASK,
  695. WM8350_IM_GP2_EINT);
  696. case WM8350_IRQ_GPIO(3):
  697. return wm8350_set_bits(wm8350,
  698. WM8350_GPIO_INT_STATUS_MASK,
  699. WM8350_IM_GP3_EINT);
  700. case WM8350_IRQ_GPIO(4):
  701. return wm8350_set_bits(wm8350,
  702. WM8350_GPIO_INT_STATUS_MASK,
  703. WM8350_IM_GP4_EINT);
  704. case WM8350_IRQ_GPIO(5):
  705. return wm8350_set_bits(wm8350,
  706. WM8350_GPIO_INT_STATUS_MASK,
  707. WM8350_IM_GP5_EINT);
  708. case WM8350_IRQ_GPIO(6):
  709. return wm8350_set_bits(wm8350,
  710. WM8350_GPIO_INT_STATUS_MASK,
  711. WM8350_IM_GP6_EINT);
  712. case WM8350_IRQ_GPIO(7):
  713. return wm8350_set_bits(wm8350,
  714. WM8350_GPIO_INT_STATUS_MASK,
  715. WM8350_IM_GP7_EINT);
  716. case WM8350_IRQ_GPIO(8):
  717. return wm8350_set_bits(wm8350,
  718. WM8350_GPIO_INT_STATUS_MASK,
  719. WM8350_IM_GP8_EINT);
  720. case WM8350_IRQ_GPIO(9):
  721. return wm8350_set_bits(wm8350,
  722. WM8350_GPIO_INT_STATUS_MASK,
  723. WM8350_IM_GP9_EINT);
  724. case WM8350_IRQ_GPIO(10):
  725. return wm8350_set_bits(wm8350,
  726. WM8350_GPIO_INT_STATUS_MASK,
  727. WM8350_IM_GP10_EINT);
  728. case WM8350_IRQ_GPIO(11):
  729. return wm8350_set_bits(wm8350,
  730. WM8350_GPIO_INT_STATUS_MASK,
  731. WM8350_IM_GP11_EINT);
  732. case WM8350_IRQ_GPIO(12):
  733. return wm8350_set_bits(wm8350,
  734. WM8350_GPIO_INT_STATUS_MASK,
  735. WM8350_IM_GP12_EINT);
  736. default:
  737. dev_warn(wm8350->dev, "Attempting to mask unknown IRQ %d\n",
  738. irq);
  739. return -EINVAL;
  740. }
  741. return 0;
  742. }
  743. EXPORT_SYMBOL_GPL(wm8350_mask_irq);
  744. int wm8350_unmask_irq(struct wm8350 *wm8350, int irq)
  745. {
  746. switch (irq) {
  747. case WM8350_IRQ_CHG_BAT_HOT:
  748. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  749. WM8350_IM_CHG_BAT_HOT_EINT);
  750. case WM8350_IRQ_CHG_BAT_COLD:
  751. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  752. WM8350_IM_CHG_BAT_COLD_EINT);
  753. case WM8350_IRQ_CHG_BAT_FAIL:
  754. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  755. WM8350_IM_CHG_BAT_FAIL_EINT);
  756. case WM8350_IRQ_CHG_TO:
  757. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  758. WM8350_IM_CHG_TO_EINT);
  759. case WM8350_IRQ_CHG_END:
  760. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  761. WM8350_IM_CHG_END_EINT);
  762. case WM8350_IRQ_CHG_START:
  763. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  764. WM8350_IM_CHG_START_EINT);
  765. case WM8350_IRQ_CHG_FAST_RDY:
  766. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  767. WM8350_IM_CHG_FAST_RDY_EINT);
  768. case WM8350_IRQ_RTC_PER:
  769. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  770. WM8350_IM_RTC_PER_EINT);
  771. case WM8350_IRQ_RTC_SEC:
  772. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  773. WM8350_IM_RTC_SEC_EINT);
  774. case WM8350_IRQ_RTC_ALM:
  775. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  776. WM8350_IM_RTC_ALM_EINT);
  777. case WM8350_IRQ_CHG_VBATT_LT_3P9:
  778. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  779. WM8350_IM_CHG_VBATT_LT_3P9_EINT);
  780. case WM8350_IRQ_CHG_VBATT_LT_3P1:
  781. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  782. WM8350_IM_CHG_VBATT_LT_3P1_EINT);
  783. case WM8350_IRQ_CHG_VBATT_LT_2P85:
  784. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
  785. WM8350_IM_CHG_VBATT_LT_2P85_EINT);
  786. case WM8350_IRQ_CS1:
  787. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  788. WM8350_IM_CS1_EINT);
  789. case WM8350_IRQ_CS2:
  790. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  791. WM8350_IM_CS2_EINT);
  792. case WM8350_IRQ_USB_LIMIT:
  793. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  794. WM8350_IM_USB_LIMIT_EINT);
  795. case WM8350_IRQ_AUXADC_DATARDY:
  796. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  797. WM8350_IM_AUXADC_DATARDY_EINT);
  798. case WM8350_IRQ_AUXADC_DCOMP4:
  799. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  800. WM8350_IM_AUXADC_DCOMP4_EINT);
  801. case WM8350_IRQ_AUXADC_DCOMP3:
  802. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  803. WM8350_IM_AUXADC_DCOMP3_EINT);
  804. case WM8350_IRQ_AUXADC_DCOMP2:
  805. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  806. WM8350_IM_AUXADC_DCOMP2_EINT);
  807. case WM8350_IRQ_AUXADC_DCOMP1:
  808. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  809. WM8350_IM_AUXADC_DCOMP1_EINT);
  810. case WM8350_IRQ_SYS_HYST_COMP_FAIL:
  811. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  812. WM8350_IM_SYS_HYST_COMP_FAIL_EINT);
  813. case WM8350_IRQ_SYS_CHIP_GT115:
  814. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  815. WM8350_IM_SYS_CHIP_GT115_EINT);
  816. case WM8350_IRQ_SYS_CHIP_GT140:
  817. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  818. WM8350_IM_SYS_CHIP_GT140_EINT);
  819. case WM8350_IRQ_SYS_WDOG_TO:
  820. return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
  821. WM8350_IM_SYS_WDOG_TO_EINT);
  822. case WM8350_IRQ_UV_LDO4:
  823. return wm8350_clear_bits(wm8350,
  824. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  825. WM8350_IM_UV_LDO4_EINT);
  826. case WM8350_IRQ_UV_LDO3:
  827. return wm8350_clear_bits(wm8350,
  828. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  829. WM8350_IM_UV_LDO3_EINT);
  830. case WM8350_IRQ_UV_LDO2:
  831. return wm8350_clear_bits(wm8350,
  832. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  833. WM8350_IM_UV_LDO2_EINT);
  834. case WM8350_IRQ_UV_LDO1:
  835. return wm8350_clear_bits(wm8350,
  836. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  837. WM8350_IM_UV_LDO1_EINT);
  838. case WM8350_IRQ_UV_DC6:
  839. return wm8350_clear_bits(wm8350,
  840. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  841. WM8350_IM_UV_DC6_EINT);
  842. case WM8350_IRQ_UV_DC5:
  843. return wm8350_clear_bits(wm8350,
  844. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  845. WM8350_IM_UV_DC5_EINT);
  846. case WM8350_IRQ_UV_DC4:
  847. return wm8350_clear_bits(wm8350,
  848. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  849. WM8350_IM_UV_DC4_EINT);
  850. case WM8350_IRQ_UV_DC3:
  851. return wm8350_clear_bits(wm8350,
  852. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  853. WM8350_IM_UV_DC3_EINT);
  854. case WM8350_IRQ_UV_DC2:
  855. return wm8350_clear_bits(wm8350,
  856. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  857. WM8350_IM_UV_DC2_EINT);
  858. case WM8350_IRQ_UV_DC1:
  859. return wm8350_clear_bits(wm8350,
  860. WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
  861. WM8350_IM_UV_DC1_EINT);
  862. case WM8350_IRQ_OC_LS:
  863. return wm8350_clear_bits(wm8350,
  864. WM8350_OVER_CURRENT_INT_STATUS_MASK,
  865. WM8350_IM_OC_LS_EINT);
  866. case WM8350_IRQ_EXT_USB_FB:
  867. return wm8350_clear_bits(wm8350,
  868. WM8350_COMPARATOR_INT_STATUS_MASK,
  869. WM8350_IM_EXT_USB_FB_EINT);
  870. case WM8350_IRQ_EXT_WALL_FB:
  871. return wm8350_clear_bits(wm8350,
  872. WM8350_COMPARATOR_INT_STATUS_MASK,
  873. WM8350_IM_EXT_WALL_FB_EINT);
  874. case WM8350_IRQ_EXT_BAT_FB:
  875. return wm8350_clear_bits(wm8350,
  876. WM8350_COMPARATOR_INT_STATUS_MASK,
  877. WM8350_IM_EXT_BAT_FB_EINT);
  878. case WM8350_IRQ_CODEC_JCK_DET_L:
  879. return wm8350_clear_bits(wm8350,
  880. WM8350_COMPARATOR_INT_STATUS_MASK,
  881. WM8350_IM_CODEC_JCK_DET_L_EINT);
  882. case WM8350_IRQ_CODEC_JCK_DET_R:
  883. return wm8350_clear_bits(wm8350,
  884. WM8350_COMPARATOR_INT_STATUS_MASK,
  885. WM8350_IM_CODEC_JCK_DET_R_EINT);
  886. case WM8350_IRQ_CODEC_MICSCD:
  887. return wm8350_clear_bits(wm8350,
  888. WM8350_COMPARATOR_INT_STATUS_MASK,
  889. WM8350_IM_CODEC_MICSCD_EINT);
  890. case WM8350_IRQ_CODEC_MICD:
  891. return wm8350_clear_bits(wm8350,
  892. WM8350_COMPARATOR_INT_STATUS_MASK,
  893. WM8350_IM_CODEC_MICD_EINT);
  894. case WM8350_IRQ_WKUP_OFF_STATE:
  895. return wm8350_clear_bits(wm8350,
  896. WM8350_COMPARATOR_INT_STATUS_MASK,
  897. WM8350_IM_WKUP_OFF_STATE_EINT);
  898. case WM8350_IRQ_WKUP_HIB_STATE:
  899. return wm8350_clear_bits(wm8350,
  900. WM8350_COMPARATOR_INT_STATUS_MASK,
  901. WM8350_IM_WKUP_HIB_STATE_EINT);
  902. case WM8350_IRQ_WKUP_CONV_FAULT:
  903. return wm8350_clear_bits(wm8350,
  904. WM8350_COMPARATOR_INT_STATUS_MASK,
  905. WM8350_IM_WKUP_CONV_FAULT_EINT);
  906. case WM8350_IRQ_WKUP_WDOG_RST:
  907. return wm8350_clear_bits(wm8350,
  908. WM8350_COMPARATOR_INT_STATUS_MASK,
  909. WM8350_IM_WKUP_OFF_STATE_EINT);
  910. case WM8350_IRQ_WKUP_GP_PWR_ON:
  911. return wm8350_clear_bits(wm8350,
  912. WM8350_COMPARATOR_INT_STATUS_MASK,
  913. WM8350_IM_WKUP_GP_PWR_ON_EINT);
  914. case WM8350_IRQ_WKUP_ONKEY:
  915. return wm8350_clear_bits(wm8350,
  916. WM8350_COMPARATOR_INT_STATUS_MASK,
  917. WM8350_IM_WKUP_ONKEY_EINT);
  918. case WM8350_IRQ_WKUP_GP_WAKEUP:
  919. return wm8350_clear_bits(wm8350,
  920. WM8350_COMPARATOR_INT_STATUS_MASK,
  921. WM8350_IM_WKUP_GP_WAKEUP_EINT);
  922. case WM8350_IRQ_GPIO(0):
  923. return wm8350_clear_bits(wm8350,
  924. WM8350_GPIO_INT_STATUS_MASK,
  925. WM8350_IM_GP0_EINT);
  926. case WM8350_IRQ_GPIO(1):
  927. return wm8350_clear_bits(wm8350,
  928. WM8350_GPIO_INT_STATUS_MASK,
  929. WM8350_IM_GP1_EINT);
  930. case WM8350_IRQ_GPIO(2):
  931. return wm8350_clear_bits(wm8350,
  932. WM8350_GPIO_INT_STATUS_MASK,
  933. WM8350_IM_GP2_EINT);
  934. case WM8350_IRQ_GPIO(3):
  935. return wm8350_clear_bits(wm8350,
  936. WM8350_GPIO_INT_STATUS_MASK,
  937. WM8350_IM_GP3_EINT);
  938. case WM8350_IRQ_GPIO(4):
  939. return wm8350_clear_bits(wm8350,
  940. WM8350_GPIO_INT_STATUS_MASK,
  941. WM8350_IM_GP4_EINT);
  942. case WM8350_IRQ_GPIO(5):
  943. return wm8350_clear_bits(wm8350,
  944. WM8350_GPIO_INT_STATUS_MASK,
  945. WM8350_IM_GP5_EINT);
  946. case WM8350_IRQ_GPIO(6):
  947. return wm8350_clear_bits(wm8350,
  948. WM8350_GPIO_INT_STATUS_MASK,
  949. WM8350_IM_GP6_EINT);
  950. case WM8350_IRQ_GPIO(7):
  951. return wm8350_clear_bits(wm8350,
  952. WM8350_GPIO_INT_STATUS_MASK,
  953. WM8350_IM_GP7_EINT);
  954. case WM8350_IRQ_GPIO(8):
  955. return wm8350_clear_bits(wm8350,
  956. WM8350_GPIO_INT_STATUS_MASK,
  957. WM8350_IM_GP8_EINT);
  958. case WM8350_IRQ_GPIO(9):
  959. return wm8350_clear_bits(wm8350,
  960. WM8350_GPIO_INT_STATUS_MASK,
  961. WM8350_IM_GP9_EINT);
  962. case WM8350_IRQ_GPIO(10):
  963. return wm8350_clear_bits(wm8350,
  964. WM8350_GPIO_INT_STATUS_MASK,
  965. WM8350_IM_GP10_EINT);
  966. case WM8350_IRQ_GPIO(11):
  967. return wm8350_clear_bits(wm8350,
  968. WM8350_GPIO_INT_STATUS_MASK,
  969. WM8350_IM_GP11_EINT);
  970. case WM8350_IRQ_GPIO(12):
  971. return wm8350_clear_bits(wm8350,
  972. WM8350_GPIO_INT_STATUS_MASK,
  973. WM8350_IM_GP12_EINT);
  974. default:
  975. dev_warn(wm8350->dev, "Attempting to unmask unknown IRQ %d\n",
  976. irq);
  977. return -EINVAL;
  978. }
  979. return 0;
  980. }
  981. EXPORT_SYMBOL_GPL(wm8350_unmask_irq);
  982. /*
  983. * Cache is always host endian.
  984. */
  985. static int wm8350_create_cache(struct wm8350 *wm8350, int mode)
  986. {
  987. int i, ret = 0;
  988. u16 value;
  989. const u16 *reg_map;
  990. switch (mode) {
  991. #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0
  992. case 0:
  993. reg_map = wm8350_mode0_defaults;
  994. break;
  995. #endif
  996. #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1
  997. case 1:
  998. reg_map = wm8350_mode1_defaults;
  999. break;
  1000. #endif
  1001. #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2
  1002. case 2:
  1003. reg_map = wm8350_mode2_defaults;
  1004. break;
  1005. #endif
  1006. #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3
  1007. case 3:
  1008. reg_map = wm8350_mode3_defaults;
  1009. break;
  1010. #endif
  1011. default:
  1012. dev_err(wm8350->dev, "Configuration mode %d not supported\n",
  1013. mode);
  1014. return -EINVAL;
  1015. }
  1016. wm8350->reg_cache =
  1017. kzalloc(sizeof(u16) * (WM8350_MAX_REGISTER + 1), GFP_KERNEL);
  1018. if (wm8350->reg_cache == NULL)
  1019. return -ENOMEM;
  1020. /* Read the initial cache state back from the device - this is
  1021. * a PMIC so the device many not be in a virgin state and we
  1022. * can't rely on the silicon values.
  1023. */
  1024. for (i = 0; i < WM8350_MAX_REGISTER; i++) {
  1025. /* audio register range */
  1026. if (wm8350_reg_io_map[i].readable &&
  1027. (i < WM8350_CLOCK_CONTROL_1 || i > WM8350_AIF_TEST)) {
  1028. ret = wm8350->read_dev(wm8350, i, 2, (char *)&value);
  1029. if (ret < 0) {
  1030. dev_err(wm8350->dev,
  1031. "failed to read initial cache value\n");
  1032. goto out;
  1033. }
  1034. value = be16_to_cpu(value);
  1035. value &= wm8350_reg_io_map[i].readable;
  1036. value &= ~wm8350_reg_io_map[i].vol;
  1037. wm8350->reg_cache[i] = value;
  1038. } else
  1039. wm8350->reg_cache[i] = reg_map[i];
  1040. }
  1041. out:
  1042. return ret;
  1043. }
  1044. /*
  1045. * Register a client device. This is non-fatal since there is no need to
  1046. * fail the entire device init due to a single platform device failing.
  1047. */
  1048. static void wm8350_client_dev_register(struct wm8350 *wm8350,
  1049. const char *name,
  1050. struct platform_device **pdev)
  1051. {
  1052. int ret;
  1053. *pdev = platform_device_alloc(name, -1);
  1054. if (pdev == NULL) {
  1055. dev_err(wm8350->dev, "Failed to allocate %s\n", name);
  1056. return;
  1057. }
  1058. (*pdev)->dev.parent = wm8350->dev;
  1059. platform_set_drvdata(*pdev, wm8350);
  1060. ret = platform_device_add(*pdev);
  1061. if (ret != 0) {
  1062. dev_err(wm8350->dev, "Failed to register %s: %d\n", name, ret);
  1063. platform_device_put(*pdev);
  1064. *pdev = NULL;
  1065. }
  1066. }
  1067. int wm8350_device_init(struct wm8350 *wm8350, int irq,
  1068. struct wm8350_platform_data *pdata)
  1069. {
  1070. int ret = -EINVAL;
  1071. u16 id1, id2, mask, mode;
  1072. /* get WM8350 revision and config mode */
  1073. wm8350->read_dev(wm8350, WM8350_RESET_ID, sizeof(id1), &id1);
  1074. wm8350->read_dev(wm8350, WM8350_ID, sizeof(id2), &id2);
  1075. id1 = be16_to_cpu(id1);
  1076. id2 = be16_to_cpu(id2);
  1077. if (id1 == 0x6143) {
  1078. switch ((id2 & WM8350_CHIP_REV_MASK) >> 12) {
  1079. case WM8350_REV_E:
  1080. dev_info(wm8350->dev, "Found Rev E device\n");
  1081. wm8350->rev = WM8350_REV_E;
  1082. break;
  1083. case WM8350_REV_F:
  1084. dev_info(wm8350->dev, "Found Rev F device\n");
  1085. wm8350->rev = WM8350_REV_F;
  1086. break;
  1087. case WM8350_REV_G:
  1088. dev_info(wm8350->dev, "Found Rev G device\n");
  1089. wm8350->rev = WM8350_REV_G;
  1090. break;
  1091. default:
  1092. /* For safety we refuse to run on unknown hardware */
  1093. dev_info(wm8350->dev, "Found unknown rev\n");
  1094. ret = -ENODEV;
  1095. goto err;
  1096. }
  1097. } else {
  1098. dev_info(wm8350->dev, "Device with ID %x is not a WM8350\n",
  1099. id1);
  1100. ret = -ENODEV;
  1101. goto err;
  1102. }
  1103. mode = id2 & WM8350_CONF_STS_MASK >> 10;
  1104. mask = id2 & WM8350_CUST_ID_MASK;
  1105. dev_info(wm8350->dev, "Config mode %d, ROM mask %d\n", mode, mask);
  1106. ret = wm8350_create_cache(wm8350, mode);
  1107. if (ret < 0) {
  1108. printk(KERN_ERR "wm8350: failed to create register cache\n");
  1109. return ret;
  1110. }
  1111. if (pdata->init) {
  1112. ret = pdata->init(wm8350);
  1113. if (ret != 0) {
  1114. dev_err(wm8350->dev, "Platform init() failed: %d\n",
  1115. ret);
  1116. goto err;
  1117. }
  1118. }
  1119. mutex_init(&wm8350->irq_mutex);
  1120. INIT_WORK(&wm8350->irq_work, wm8350_irq_worker);
  1121. if (irq) {
  1122. ret = request_irq(irq, wm8350_irq, 0,
  1123. "wm8350", wm8350);
  1124. if (ret != 0) {
  1125. dev_err(wm8350->dev, "Failed to request IRQ: %d\n",
  1126. ret);
  1127. goto err;
  1128. }
  1129. } else {
  1130. dev_err(wm8350->dev, "No IRQ configured\n");
  1131. goto err;
  1132. }
  1133. wm8350->chip_irq = irq;
  1134. wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x0);
  1135. wm8350_client_dev_register(wm8350, "wm8350-codec",
  1136. &(wm8350->codec.pdev));
  1137. wm8350_client_dev_register(wm8350, "wm8350-gpio",
  1138. &(wm8350->gpio.pdev));
  1139. wm8350_client_dev_register(wm8350, "wm8350-power",
  1140. &(wm8350->power.pdev));
  1141. wm8350_client_dev_register(wm8350, "wm8350-rtc", &(wm8350->rtc.pdev));
  1142. wm8350_client_dev_register(wm8350, "wm8350-wdt", &(wm8350->wdt.pdev));
  1143. return 0;
  1144. err:
  1145. kfree(wm8350->reg_cache);
  1146. return ret;
  1147. }
  1148. EXPORT_SYMBOL_GPL(wm8350_device_init);
  1149. void wm8350_device_exit(struct wm8350 *wm8350)
  1150. {
  1151. int i;
  1152. for (i = 0; i < ARRAY_SIZE(wm8350->pmic.pdev); i++)
  1153. platform_device_unregister(wm8350->pmic.pdev[i]);
  1154. platform_device_unregister(wm8350->wdt.pdev);
  1155. platform_device_unregister(wm8350->rtc.pdev);
  1156. platform_device_unregister(wm8350->power.pdev);
  1157. platform_device_unregister(wm8350->gpio.pdev);
  1158. platform_device_unregister(wm8350->codec.pdev);
  1159. free_irq(wm8350->chip_irq, wm8350);
  1160. flush_work(&wm8350->irq_work);
  1161. kfree(wm8350->reg_cache);
  1162. }
  1163. EXPORT_SYMBOL_GPL(wm8350_device_exit);
  1164. MODULE_DESCRIPTION("WM8350 AudioPlus PMIC core driver");
  1165. MODULE_LICENSE("GPL");