dib0070.c 13 KB

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  1. /*
  2. * Linux-DVB Driver for DiBcom's DiB0070 base-band RF Tuner.
  3. *
  4. * Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/)
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation, version 2.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/i2c.h>
  12. #include "dvb_frontend.h"
  13. #include "dib0070.h"
  14. #include "dibx000_common.h"
  15. static int debug;
  16. module_param(debug, int, 0644);
  17. MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
  18. #define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB0070: "); printk(args); printk("\n"); } } while (0)
  19. #define DIB0070_P1D 0x00
  20. #define DIB0070_P1F 0x01
  21. #define DIB0070_P1G 0x03
  22. #define DIB0070S_P1A 0x02
  23. struct dib0070_state {
  24. struct i2c_adapter *i2c;
  25. struct dvb_frontend *fe;
  26. const struct dib0070_config *cfg;
  27. u16 wbd_ff_offset;
  28. u8 revision;
  29. };
  30. static uint16_t dib0070_read_reg(struct dib0070_state *state, u8 reg)
  31. {
  32. u8 b[2];
  33. struct i2c_msg msg[2] = {
  34. { .addr = state->cfg->i2c_address, .flags = 0, .buf = &reg, .len = 1 },
  35. { .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = b, .len = 2 },
  36. };
  37. if (i2c_transfer(state->i2c, msg, 2) != 2) {
  38. printk(KERN_WARNING "DiB0070 I2C read failed\n");
  39. return 0;
  40. }
  41. return (b[0] << 8) | b[1];
  42. }
  43. static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val)
  44. {
  45. u8 b[3] = { reg, val >> 8, val & 0xff };
  46. struct i2c_msg msg = { .addr = state->cfg->i2c_address, .flags = 0, .buf = b, .len = 3 };
  47. if (i2c_transfer(state->i2c, &msg, 1) != 1) {
  48. printk(KERN_WARNING "DiB0070 I2C write failed\n");
  49. return -EREMOTEIO;
  50. }
  51. return 0;
  52. }
  53. #define HARD_RESET(state) do { if (state->cfg->reset) { state->cfg->reset(state->fe,1); msleep(10); state->cfg->reset(state->fe,0); msleep(10); } } while (0)
  54. static int dib0070_set_bandwidth(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch)
  55. {
  56. struct dib0070_state *st = fe->tuner_priv;
  57. u16 tmp = 0;
  58. tmp = dib0070_read_reg(st, 0x02) & 0x3fff;
  59. switch(BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth)) {
  60. case 8000:
  61. tmp |= (0 << 14);
  62. break;
  63. case 7000:
  64. tmp |= (1 << 14);
  65. break;
  66. case 6000:
  67. tmp |= (2 << 14);
  68. break;
  69. case 5000:
  70. default:
  71. tmp |= (3 << 14);
  72. break;
  73. }
  74. dib0070_write_reg(st, 0x02, tmp);
  75. return 0;
  76. }
  77. static void dib0070_captrim(struct dib0070_state *st, u16 LO4)
  78. {
  79. int8_t captrim, fcaptrim, step_sign, step;
  80. u16 adc, adc_diff = 3000;
  81. dib0070_write_reg(st, 0x0f, 0xed10);
  82. dib0070_write_reg(st, 0x17, 0x0034);
  83. dib0070_write_reg(st, 0x18, 0x0032);
  84. msleep(2);
  85. step = captrim = fcaptrim = 64;
  86. do {
  87. step /= 2;
  88. dib0070_write_reg(st, 0x14, LO4 | captrim);
  89. msleep(1);
  90. adc = dib0070_read_reg(st, 0x19);
  91. dprintk( "CAPTRIM=%hd; ADC = %hd (ADC) & %dmV", captrim, adc, (u32) adc*(u32)1800/(u32)1024);
  92. if (adc >= 400) {
  93. adc -= 400;
  94. step_sign = -1;
  95. } else {
  96. adc = 400 - adc;
  97. step_sign = 1;
  98. }
  99. if (adc < adc_diff) {
  100. dprintk( "CAPTRIM=%hd is closer to target (%hd/%hd)", captrim, adc, adc_diff);
  101. adc_diff = adc;
  102. fcaptrim = captrim;
  103. }
  104. captrim += (step_sign * step);
  105. } while (step >= 1);
  106. dib0070_write_reg(st, 0x14, LO4 | fcaptrim);
  107. dib0070_write_reg(st, 0x18, 0x07ff);
  108. }
  109. #define LPF 100 // define for the loop filter 100kHz by default 16-07-06
  110. #define LO4_SET_VCO_HFDIV(l, v, h) l |= ((v) << 11) | ((h) << 7)
  111. #define LO4_SET_SD(l, s) l |= ((s) << 14) | ((s) << 12)
  112. #define LO4_SET_CTRIM(l, c) l |= (c) << 10
  113. static int dib0070_tune_digital(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch)
  114. {
  115. struct dib0070_state *st = fe->tuner_priv;
  116. u32 freq = ch->frequency/1000 + (BAND_OF_FREQUENCY(ch->frequency/1000) == BAND_VHF ? st->cfg->freq_offset_khz_vhf : st->cfg->freq_offset_khz_uhf);
  117. u8 band = BAND_OF_FREQUENCY(freq), c;
  118. /*******************VCO***********************************/
  119. u16 lo4 = 0;
  120. u8 REFDIV, PRESC = 2;
  121. u32 FBDiv, Rest, FREF, VCOF_kHz;
  122. u16 Num, Den;
  123. /*******************FrontEnd******************************/
  124. u16 value = 0;
  125. dprintk( "Tuning for Band: %hd (%d kHz)", band, freq);
  126. dib0070_write_reg(st, 0x17, 0x30);
  127. dib0070_set_bandwidth(fe, ch); /* c is used as HF */
  128. switch (st->revision) {
  129. case DIB0070S_P1A:
  130. switch (band) {
  131. case BAND_LBAND:
  132. LO4_SET_VCO_HFDIV(lo4, 1, 1);
  133. c = 2;
  134. break;
  135. case BAND_SBAND:
  136. LO4_SET_VCO_HFDIV(lo4, 0, 0);
  137. LO4_SET_CTRIM(lo4, 1);;
  138. c = 1;
  139. break;
  140. case BAND_UHF:
  141. default:
  142. if (freq < 570000) {
  143. LO4_SET_VCO_HFDIV(lo4, 1, 3);
  144. PRESC = 6; c = 6;
  145. } else if (freq < 680000) {
  146. LO4_SET_VCO_HFDIV(lo4, 0, 2);
  147. c = 4;
  148. } else {
  149. LO4_SET_VCO_HFDIV(lo4, 1, 2);
  150. c = 4;
  151. }
  152. break;
  153. } break;
  154. case DIB0070_P1G:
  155. case DIB0070_P1F:
  156. default:
  157. switch (band) {
  158. case BAND_FM:
  159. LO4_SET_VCO_HFDIV(lo4, 0, 7);
  160. c = 24;
  161. break;
  162. case BAND_LBAND:
  163. LO4_SET_VCO_HFDIV(lo4, 1, 0);
  164. c = 2;
  165. break;
  166. case BAND_VHF:
  167. if (freq < 180000) {
  168. LO4_SET_VCO_HFDIV(lo4, 0, 3);
  169. c = 16;
  170. } else if (freq < 190000) {
  171. LO4_SET_VCO_HFDIV(lo4, 1, 3);
  172. c = 16;
  173. } else {
  174. LO4_SET_VCO_HFDIV(lo4, 0, 6);
  175. c = 12;
  176. }
  177. break;
  178. case BAND_UHF:
  179. default:
  180. if (freq < 570000) {
  181. LO4_SET_VCO_HFDIV(lo4, 1, 5);
  182. c = 6;
  183. } else if (freq < 700000) {
  184. LO4_SET_VCO_HFDIV(lo4, 0, 1);
  185. c = 4;
  186. } else {
  187. LO4_SET_VCO_HFDIV(lo4, 1, 1);
  188. c = 4;
  189. }
  190. break;
  191. }
  192. break;
  193. }
  194. dprintk( "HFDIV code: %hd", (lo4 >> 7) & 0xf);
  195. dprintk( "VCO = %hd", (lo4 >> 11) & 0x3);
  196. VCOF_kHz = (c * freq) * 2;
  197. dprintk( "VCOF in kHz: %d ((%hd*%d) << 1))",VCOF_kHz, c, freq);
  198. switch (band) {
  199. case BAND_VHF:
  200. REFDIV = (u8) ((st->cfg->clock_khz + 9999) / 10000);
  201. break;
  202. case BAND_FM:
  203. REFDIV = (u8) ((st->cfg->clock_khz) / 1000);
  204. break;
  205. default:
  206. REFDIV = (u8) ( st->cfg->clock_khz / 10000);
  207. break;
  208. }
  209. FREF = st->cfg->clock_khz / REFDIV;
  210. dprintk( "REFDIV: %hd, FREF: %d", REFDIV, FREF);
  211. switch (st->revision) {
  212. case DIB0070S_P1A:
  213. FBDiv = (VCOF_kHz / PRESC / FREF);
  214. Rest = (VCOF_kHz / PRESC) - FBDiv * FREF;
  215. break;
  216. case DIB0070_P1G:
  217. case DIB0070_P1F:
  218. default:
  219. FBDiv = (freq / (FREF / 2));
  220. Rest = 2 * freq - FBDiv * FREF;
  221. break;
  222. }
  223. if (Rest < LPF) Rest = 0;
  224. else if (Rest < 2 * LPF) Rest = 2 * LPF;
  225. else if (Rest > (FREF - LPF)) { Rest = 0 ; FBDiv += 1; }
  226. else if (Rest > (FREF - 2 * LPF)) Rest = FREF - 2 * LPF;
  227. Rest = (Rest * 6528) / (FREF / 10);
  228. dprintk( "FBDIV: %d, Rest: %d", FBDiv, Rest);
  229. Num = 0;
  230. Den = 1;
  231. if (Rest > 0) {
  232. LO4_SET_SD(lo4, 1);
  233. Den = 255;
  234. Num = (u16)Rest;
  235. }
  236. dprintk( "Num: %hd, Den: %hd, SD: %hd",Num, Den, (lo4 >> 12) & 0x1);
  237. dib0070_write_reg(st, 0x11, (u16)FBDiv);
  238. dib0070_write_reg(st, 0x12, (Den << 8) | REFDIV);
  239. dib0070_write_reg(st, 0x13, Num);
  240. value = 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001;
  241. switch (band) {
  242. case BAND_UHF: value |= 0x4000 | 0x0800; break;
  243. case BAND_LBAND: value |= 0x2000 | 0x0400; break;
  244. default: value |= 0x8000 | 0x1000; break;
  245. }
  246. dib0070_write_reg(st, 0x20, value);
  247. dib0070_captrim(st, lo4);
  248. if (st->revision == DIB0070S_P1A) {
  249. if (band == BAND_SBAND)
  250. dib0070_write_reg(st, 0x15, 0x16e2);
  251. else
  252. dib0070_write_reg(st, 0x15, 0x56e5);
  253. }
  254. switch (band) {
  255. case BAND_UHF: value = 0x7c82; break;
  256. case BAND_LBAND: value = 0x7c84; break;
  257. default: value = 0x7c81; break;
  258. }
  259. dib0070_write_reg(st, 0x0f, value);
  260. dib0070_write_reg(st, 0x06, 0x3fff);
  261. /* Front End */
  262. /* c == TUNE, value = SWITCH */
  263. c = 0;
  264. value = 0;
  265. switch (band) {
  266. case BAND_FM:
  267. c = 0; value = 1;
  268. break;
  269. case BAND_VHF:
  270. if (freq <= 180000) c = 0;
  271. else if (freq <= 188200) c = 1;
  272. else if (freq <= 196400) c = 2;
  273. else c = 3;
  274. value = 1;
  275. break;
  276. case BAND_LBAND:
  277. if (freq <= 1500000) c = 0;
  278. else if (freq <= 1600000) c = 1;
  279. else c = 3;
  280. break;
  281. case BAND_SBAND:
  282. c = 7;
  283. dib0070_write_reg(st, 0x1d,0xFFFF);
  284. break;
  285. case BAND_UHF:
  286. default:
  287. if (st->cfg->flip_chip) {
  288. if (freq <= 550000) c = 0;
  289. else if (freq <= 590000) c = 1;
  290. else if (freq <= 666000) c = 3;
  291. else c = 5;
  292. } else {
  293. if (freq <= 550000) c = 2;
  294. else if (freq <= 650000) c = 3;
  295. else if (freq <= 750000) c = 5;
  296. else if (freq <= 850000) c = 6;
  297. else c = 7;
  298. }
  299. value = 2;
  300. break;
  301. }
  302. /* default: LNA_MATCH=7, BIAS=3 */
  303. dib0070_write_reg(st, 0x07, (value << 11) | (7 << 8) | (c << 3) | (3 << 0));
  304. dib0070_write_reg(st, 0x08, (c << 10) | (3 << 7) | (127));
  305. dib0070_write_reg(st, 0x0d, 0x0d80);
  306. dib0070_write_reg(st, 0x18, 0x07ff);
  307. dib0070_write_reg(st, 0x17, 0x0033);
  308. return 0;
  309. }
  310. static int dib0070_wakeup(struct dvb_frontend *fe)
  311. {
  312. struct dib0070_state *st = fe->tuner_priv;
  313. if (st->cfg->sleep)
  314. st->cfg->sleep(fe, 0);
  315. return 0;
  316. }
  317. static int dib0070_sleep(struct dvb_frontend *fe)
  318. {
  319. struct dib0070_state *st = fe->tuner_priv;
  320. if (st->cfg->sleep)
  321. st->cfg->sleep(fe, 1);
  322. return 0;
  323. }
  324. static u16 dib0070_p1f_defaults[] =
  325. {
  326. 7, 0x02,
  327. 0x0008,
  328. 0x0000,
  329. 0x0000,
  330. 0x0000,
  331. 0x0000,
  332. 0x0002,
  333. 0x0100,
  334. 3, 0x0d,
  335. 0x0d80,
  336. 0x0001,
  337. 0x0000,
  338. 4, 0x11,
  339. 0x0000,
  340. 0x0103,
  341. 0x0000,
  342. 0x0000,
  343. 3, 0x16,
  344. 0x0004 | 0x0040,
  345. 0x0030,
  346. 0x07ff,
  347. 6, 0x1b,
  348. 0x4112,
  349. 0xff00,
  350. 0xc07f,
  351. 0x0000,
  352. 0x0180,
  353. 0x4000 | 0x0800 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001,
  354. 0,
  355. };
  356. static void dib0070_wbd_calibration(struct dvb_frontend *fe)
  357. {
  358. u16 wbd_offs;
  359. struct dib0070_state *state = fe->tuner_priv;
  360. if (state->cfg->sleep)
  361. state->cfg->sleep(fe, 0);
  362. dib0070_write_reg(state, 0x0f, 0x6d81);
  363. dib0070_write_reg(state, 0x20, 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001);
  364. msleep(9);
  365. wbd_offs = dib0070_read_reg(state, 0x19);
  366. dib0070_write_reg(state, 0x20, 0);
  367. state->wbd_ff_offset = ((wbd_offs * 8 * 18 / 33 + 1) / 2);
  368. dprintk( "WBDStart = %d (Vargen) - FF = %hd", (u32) wbd_offs * 1800/1024, state->wbd_ff_offset);
  369. if (state->cfg->sleep)
  370. state->cfg->sleep(fe, 1);
  371. }
  372. u16 dib0070_wbd_offset(struct dvb_frontend *fe)
  373. {
  374. struct dib0070_state *st = fe->tuner_priv;
  375. return st->wbd_ff_offset;
  376. }
  377. EXPORT_SYMBOL(dib0070_wbd_offset);
  378. static int dib0070_set_ctrl_lo5(struct dvb_frontend *fe, u8 vco_bias_trim, u8 hf_div_trim, u8 cp_current, u8 third_order_filt)
  379. {
  380. struct dib0070_state *state = fe->tuner_priv;
  381. u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0);
  382. dprintk( "CTRL_LO5: 0x%x", lo5);
  383. return dib0070_write_reg(state, 0x15, lo5);
  384. }
  385. #define pgm_read_word(w) (*w)
  386. static int dib0070_reset(struct dib0070_state *state)
  387. {
  388. u16 l, r, *n;
  389. HARD_RESET(state);
  390. #ifndef FORCE_SBAND_TUNER
  391. if ((dib0070_read_reg(state, 0x22) >> 9) & 0x1)
  392. state->revision = (dib0070_read_reg(state, 0x1f) >> 8) & 0xff;
  393. else
  394. #endif
  395. state->revision = DIB0070S_P1A;
  396. /* P1F or not */
  397. dprintk( "Revision: %x", state->revision);
  398. if (state->revision == DIB0070_P1D) {
  399. dprintk( "Error: this driver is not to be used meant for P1D or earlier");
  400. return -EINVAL;
  401. }
  402. n = (u16 *) dib0070_p1f_defaults;
  403. l = pgm_read_word(n++);
  404. while (l) {
  405. r = pgm_read_word(n++);
  406. do {
  407. dib0070_write_reg(state, (u8)r, pgm_read_word(n++));
  408. r++;
  409. } while (--l);
  410. l = pgm_read_word(n++);
  411. }
  412. if (state->cfg->force_crystal_mode != 0)
  413. r = state->cfg->force_crystal_mode;
  414. else if (state->cfg->clock_khz >= 24000)
  415. r = 1;
  416. else
  417. r = 2;
  418. r |= state->cfg->osc_buffer_state << 3;
  419. dib0070_write_reg(state, 0x10, r);
  420. dib0070_write_reg(state, 0x1f, (1 << 8) | ((state->cfg->clock_pad_drive & 0xf) << 4));
  421. if (state->cfg->invert_iq) {
  422. r = dib0070_read_reg(state, 0x02) & 0xffdf;
  423. dib0070_write_reg(state, 0x02, r | (1 << 5));
  424. }
  425. if (state->revision == DIB0070S_P1A)
  426. dib0070_set_ctrl_lo5(state->fe, 4, 7, 3, 1);
  427. else
  428. dib0070_set_ctrl_lo5(state->fe, 4, 4, 2, 0);
  429. dib0070_write_reg(state, 0x01, (54 << 9) | 0xc8);
  430. return 0;
  431. }
  432. static int dib0070_release(struct dvb_frontend *fe)
  433. {
  434. kfree(fe->tuner_priv);
  435. fe->tuner_priv = NULL;
  436. return 0;
  437. }
  438. static struct dvb_tuner_ops dib0070_ops = {
  439. .info = {
  440. .name = "DiBcom DiB0070",
  441. .frequency_min = 45000000,
  442. .frequency_max = 860000000,
  443. .frequency_step = 1000,
  444. },
  445. .release = dib0070_release,
  446. .init = dib0070_wakeup,
  447. .sleep = dib0070_sleep,
  448. .set_params = dib0070_tune_digital,
  449. // .get_frequency = dib0070_get_frequency,
  450. // .get_bandwidth = dib0070_get_bandwidth
  451. };
  452. struct dvb_frontend * dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg)
  453. {
  454. struct dib0070_state *state = kzalloc(sizeof(struct dib0070_state), GFP_KERNEL);
  455. if (state == NULL)
  456. return NULL;
  457. state->cfg = cfg;
  458. state->i2c = i2c;
  459. state->fe = fe;
  460. fe->tuner_priv = state;
  461. if (dib0070_reset(state) != 0)
  462. goto free_mem;
  463. dib0070_wbd_calibration(fe);
  464. printk(KERN_INFO "DiB0070: successfully identified\n");
  465. memcpy(&fe->ops.tuner_ops, &dib0070_ops, sizeof(struct dvb_tuner_ops));
  466. fe->tuner_priv = state;
  467. return fe;
  468. free_mem:
  469. kfree(state);
  470. fe->tuner_priv = NULL;
  471. return NULL;
  472. }
  473. EXPORT_SYMBOL(dib0070_attach);
  474. MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
  475. MODULE_DESCRIPTION("Driver for the DiBcom 0070 base-band RF Tuner");
  476. MODULE_LICENSE("GPL");