hp_sdc.c 28 KB

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  1. /*
  2. * HP i8042-based System Device Controller driver.
  3. *
  4. * Copyright (c) 2001 Brian S. Julin
  5. * All rights reserved.
  6. *
  7. * Redistribution and use in source and binary forms, with or without
  8. * modification, are permitted provided that the following conditions
  9. * are met:
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions, and the following disclaimer,
  12. * without modification.
  13. * 2. The name of the author may not be used to endorse or promote products
  14. * derived from this software without specific prior written permission.
  15. *
  16. * Alternatively, this software may be distributed under the terms of the
  17. * GNU General Public License ("GPL").
  18. *
  19. * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22. * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  23. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28. *
  29. * References:
  30. * System Device Controller Microprocessor Firmware Theory of Operation
  31. * for Part Number 1820-4784 Revision B. Dwg No. A-1820-4784-2
  32. * Helge Deller's original hilkbd.c port for PA-RISC.
  33. *
  34. *
  35. * Driver theory of operation:
  36. *
  37. * hp_sdc_put does all writing to the SDC. ISR can run on a different
  38. * CPU than hp_sdc_put, but only one CPU runs hp_sdc_put at a time
  39. * (it cannot really benefit from SMP anyway.) A tasket fit this perfectly.
  40. *
  41. * All data coming back from the SDC is sent via interrupt and can be read
  42. * fully in the ISR, so there are no latency/throughput problems there.
  43. * The problem is with output, due to the slow clock speed of the SDC
  44. * compared to the CPU. This should not be too horrible most of the time,
  45. * but if used with HIL devices that support the multibyte transfer command,
  46. * keeping outbound throughput flowing at the 6500KBps that the HIL is
  47. * capable of is more than can be done at HZ=100.
  48. *
  49. * Busy polling for IBF clear wastes CPU cycles and bus cycles. hp_sdc.ibf
  50. * is set to 0 when the IBF flag in the status register has cleared. ISR
  51. * may do this, and may also access the parts of queued transactions related
  52. * to reading data back from the SDC, but otherwise will not touch the
  53. * hp_sdc state. Whenever a register is written hp_sdc.ibf is set to 1.
  54. *
  55. * The i8042 write index and the values in the 4-byte input buffer
  56. * starting at 0x70 are kept track of in hp_sdc.wi, and .r7[], respectively,
  57. * to minimize the amount of IO needed to the SDC. However these values
  58. * do not need to be locked since they are only ever accessed by hp_sdc_put.
  59. *
  60. * A timer task schedules the tasklet once per second just to make
  61. * sure it doesn't freeze up and to allow for bad reads to time out.
  62. */
  63. #include <linux/hp_sdc.h>
  64. #include <linux/errno.h>
  65. #include <linux/init.h>
  66. #include <linux/module.h>
  67. #include <linux/ioport.h>
  68. #include <linux/time.h>
  69. #include <linux/semaphore.h>
  70. #include <linux/slab.h>
  71. #include <linux/hil.h>
  72. #include <asm/io.h>
  73. #include <asm/system.h>
  74. /* Machine-specific abstraction */
  75. #if defined(__hppa__)
  76. # include <asm/parisc-device.h>
  77. # define sdc_readb(p) gsc_readb(p)
  78. # define sdc_writeb(v,p) gsc_writeb((v),(p))
  79. #elif defined(__mc68000__)
  80. # include <asm/uaccess.h>
  81. # define sdc_readb(p) in_8(p)
  82. # define sdc_writeb(v,p) out_8((p),(v))
  83. #else
  84. # error "HIL is not supported on this platform"
  85. #endif
  86. #define PREFIX "HP SDC: "
  87. MODULE_AUTHOR("Brian S. Julin <bri@calyx.com>");
  88. MODULE_DESCRIPTION("HP i8042-based SDC Driver");
  89. MODULE_LICENSE("Dual BSD/GPL");
  90. EXPORT_SYMBOL(hp_sdc_request_timer_irq);
  91. EXPORT_SYMBOL(hp_sdc_request_hil_irq);
  92. EXPORT_SYMBOL(hp_sdc_request_cooked_irq);
  93. EXPORT_SYMBOL(hp_sdc_release_timer_irq);
  94. EXPORT_SYMBOL(hp_sdc_release_hil_irq);
  95. EXPORT_SYMBOL(hp_sdc_release_cooked_irq);
  96. EXPORT_SYMBOL(__hp_sdc_enqueue_transaction);
  97. EXPORT_SYMBOL(hp_sdc_enqueue_transaction);
  98. EXPORT_SYMBOL(hp_sdc_dequeue_transaction);
  99. static unsigned int hp_sdc_disabled;
  100. module_param_named(no_hpsdc, hp_sdc_disabled, bool, 0);
  101. MODULE_PARM_DESC(no_hpsdc, "Do not enable HP SDC driver.");
  102. static hp_i8042_sdc hp_sdc; /* All driver state is kept in here. */
  103. /*************** primitives for use in any context *********************/
  104. static inline uint8_t hp_sdc_status_in8(void)
  105. {
  106. uint8_t status;
  107. unsigned long flags;
  108. write_lock_irqsave(&hp_sdc.ibf_lock, flags);
  109. status = sdc_readb(hp_sdc.status_io);
  110. if (!(status & HP_SDC_STATUS_IBF))
  111. hp_sdc.ibf = 0;
  112. write_unlock_irqrestore(&hp_sdc.ibf_lock, flags);
  113. return status;
  114. }
  115. static inline uint8_t hp_sdc_data_in8(void)
  116. {
  117. return sdc_readb(hp_sdc.data_io);
  118. }
  119. static inline void hp_sdc_status_out8(uint8_t val)
  120. {
  121. unsigned long flags;
  122. write_lock_irqsave(&hp_sdc.ibf_lock, flags);
  123. hp_sdc.ibf = 1;
  124. if ((val & 0xf0) == 0xe0)
  125. hp_sdc.wi = 0xff;
  126. sdc_writeb(val, hp_sdc.status_io);
  127. write_unlock_irqrestore(&hp_sdc.ibf_lock, flags);
  128. }
  129. static inline void hp_sdc_data_out8(uint8_t val)
  130. {
  131. unsigned long flags;
  132. write_lock_irqsave(&hp_sdc.ibf_lock, flags);
  133. hp_sdc.ibf = 1;
  134. sdc_writeb(val, hp_sdc.data_io);
  135. write_unlock_irqrestore(&hp_sdc.ibf_lock, flags);
  136. }
  137. /* Care must be taken to only invoke hp_sdc_spin_ibf when
  138. * absolutely needed, or in rarely invoked subroutines.
  139. * Not only does it waste CPU cycles, it also wastes bus cycles.
  140. */
  141. static inline void hp_sdc_spin_ibf(void)
  142. {
  143. unsigned long flags;
  144. rwlock_t *lock;
  145. lock = &hp_sdc.ibf_lock;
  146. read_lock_irqsave(lock, flags);
  147. if (!hp_sdc.ibf) {
  148. read_unlock_irqrestore(lock, flags);
  149. return;
  150. }
  151. read_unlock(lock);
  152. write_lock(lock);
  153. while (sdc_readb(hp_sdc.status_io) & HP_SDC_STATUS_IBF)
  154. { }
  155. hp_sdc.ibf = 0;
  156. write_unlock_irqrestore(lock, flags);
  157. }
  158. /************************ Interrupt context functions ************************/
  159. static void hp_sdc_take(int irq, void *dev_id, uint8_t status, uint8_t data)
  160. {
  161. hp_sdc_transaction *curr;
  162. read_lock(&hp_sdc.rtq_lock);
  163. if (hp_sdc.rcurr < 0) {
  164. read_unlock(&hp_sdc.rtq_lock);
  165. return;
  166. }
  167. curr = hp_sdc.tq[hp_sdc.rcurr];
  168. read_unlock(&hp_sdc.rtq_lock);
  169. curr->seq[curr->idx++] = status;
  170. curr->seq[curr->idx++] = data;
  171. hp_sdc.rqty -= 2;
  172. do_gettimeofday(&hp_sdc.rtv);
  173. if (hp_sdc.rqty <= 0) {
  174. /* All data has been gathered. */
  175. if (curr->seq[curr->actidx] & HP_SDC_ACT_SEMAPHORE)
  176. if (curr->act.semaphore)
  177. up(curr->act.semaphore);
  178. if (curr->seq[curr->actidx] & HP_SDC_ACT_CALLBACK)
  179. if (curr->act.irqhook)
  180. curr->act.irqhook(irq, dev_id, status, data);
  181. curr->actidx = curr->idx;
  182. curr->idx++;
  183. /* Return control of this transaction */
  184. write_lock(&hp_sdc.rtq_lock);
  185. hp_sdc.rcurr = -1;
  186. hp_sdc.rqty = 0;
  187. write_unlock(&hp_sdc.rtq_lock);
  188. tasklet_schedule(&hp_sdc.task);
  189. }
  190. }
  191. static irqreturn_t hp_sdc_isr(int irq, void *dev_id)
  192. {
  193. uint8_t status, data;
  194. status = hp_sdc_status_in8();
  195. /* Read data unconditionally to advance i8042. */
  196. data = hp_sdc_data_in8();
  197. /* For now we are ignoring these until we get the SDC to behave. */
  198. if (((status & 0xf1) == 0x51) && data == 0x82)
  199. return IRQ_HANDLED;
  200. switch (status & HP_SDC_STATUS_IRQMASK) {
  201. case 0: /* This case is not documented. */
  202. break;
  203. case HP_SDC_STATUS_USERTIMER:
  204. case HP_SDC_STATUS_PERIODIC:
  205. case HP_SDC_STATUS_TIMER:
  206. read_lock(&hp_sdc.hook_lock);
  207. if (hp_sdc.timer != NULL)
  208. hp_sdc.timer(irq, dev_id, status, data);
  209. read_unlock(&hp_sdc.hook_lock);
  210. break;
  211. case HP_SDC_STATUS_REG:
  212. hp_sdc_take(irq, dev_id, status, data);
  213. break;
  214. case HP_SDC_STATUS_HILCMD:
  215. case HP_SDC_STATUS_HILDATA:
  216. read_lock(&hp_sdc.hook_lock);
  217. if (hp_sdc.hil != NULL)
  218. hp_sdc.hil(irq, dev_id, status, data);
  219. read_unlock(&hp_sdc.hook_lock);
  220. break;
  221. case HP_SDC_STATUS_PUP:
  222. read_lock(&hp_sdc.hook_lock);
  223. if (hp_sdc.pup != NULL)
  224. hp_sdc.pup(irq, dev_id, status, data);
  225. else
  226. printk(KERN_INFO PREFIX "HP SDC reports successful PUP.\n");
  227. read_unlock(&hp_sdc.hook_lock);
  228. break;
  229. default:
  230. read_lock(&hp_sdc.hook_lock);
  231. if (hp_sdc.cooked != NULL)
  232. hp_sdc.cooked(irq, dev_id, status, data);
  233. read_unlock(&hp_sdc.hook_lock);
  234. break;
  235. }
  236. return IRQ_HANDLED;
  237. }
  238. static irqreturn_t hp_sdc_nmisr(int irq, void *dev_id)
  239. {
  240. int status;
  241. status = hp_sdc_status_in8();
  242. printk(KERN_WARNING PREFIX "NMI !\n");
  243. #if 0
  244. if (status & HP_SDC_NMISTATUS_FHS) {
  245. read_lock(&hp_sdc.hook_lock);
  246. if (hp_sdc.timer != NULL)
  247. hp_sdc.timer(irq, dev_id, status, 0);
  248. read_unlock(&hp_sdc.hook_lock);
  249. } else {
  250. /* TODO: pass this on to the HIL handler, or do SAK here? */
  251. printk(KERN_WARNING PREFIX "HIL NMI\n");
  252. }
  253. #endif
  254. return IRQ_HANDLED;
  255. }
  256. /***************** Kernel (tasklet) context functions ****************/
  257. unsigned long hp_sdc_put(void);
  258. static void hp_sdc_tasklet(unsigned long foo)
  259. {
  260. write_lock_irq(&hp_sdc.rtq_lock);
  261. if (hp_sdc.rcurr >= 0) {
  262. struct timeval tv;
  263. do_gettimeofday(&tv);
  264. if (tv.tv_sec > hp_sdc.rtv.tv_sec)
  265. tv.tv_usec += USEC_PER_SEC;
  266. if (tv.tv_usec - hp_sdc.rtv.tv_usec > HP_SDC_MAX_REG_DELAY) {
  267. hp_sdc_transaction *curr;
  268. uint8_t tmp;
  269. curr = hp_sdc.tq[hp_sdc.rcurr];
  270. /* If this turns out to be a normal failure mode
  271. * we'll need to figure out a way to communicate
  272. * it back to the application. and be less verbose.
  273. */
  274. printk(KERN_WARNING PREFIX "read timeout (%ius)!\n",
  275. (int)(tv.tv_usec - hp_sdc.rtv.tv_usec));
  276. curr->idx += hp_sdc.rqty;
  277. hp_sdc.rqty = 0;
  278. tmp = curr->seq[curr->actidx];
  279. curr->seq[curr->actidx] |= HP_SDC_ACT_DEAD;
  280. if (tmp & HP_SDC_ACT_SEMAPHORE)
  281. if (curr->act.semaphore)
  282. up(curr->act.semaphore);
  283. if (tmp & HP_SDC_ACT_CALLBACK) {
  284. /* Note this means that irqhooks may be called
  285. * in tasklet/bh context.
  286. */
  287. if (curr->act.irqhook)
  288. curr->act.irqhook(0, NULL, 0, 0);
  289. }
  290. curr->actidx = curr->idx;
  291. curr->idx++;
  292. hp_sdc.rcurr = -1;
  293. }
  294. }
  295. write_unlock_irq(&hp_sdc.rtq_lock);
  296. hp_sdc_put();
  297. }
  298. unsigned long hp_sdc_put(void)
  299. {
  300. hp_sdc_transaction *curr;
  301. uint8_t act;
  302. int idx, curridx;
  303. int limit = 0;
  304. write_lock(&hp_sdc.lock);
  305. /* If i8042 buffers are full, we cannot do anything that
  306. requires output, so we skip to the administrativa. */
  307. if (hp_sdc.ibf) {
  308. hp_sdc_status_in8();
  309. if (hp_sdc.ibf)
  310. goto finish;
  311. }
  312. anew:
  313. /* See if we are in the middle of a sequence. */
  314. if (hp_sdc.wcurr < 0)
  315. hp_sdc.wcurr = 0;
  316. read_lock_irq(&hp_sdc.rtq_lock);
  317. if (hp_sdc.rcurr == hp_sdc.wcurr)
  318. hp_sdc.wcurr++;
  319. read_unlock_irq(&hp_sdc.rtq_lock);
  320. if (hp_sdc.wcurr >= HP_SDC_QUEUE_LEN)
  321. hp_sdc.wcurr = 0;
  322. curridx = hp_sdc.wcurr;
  323. if (hp_sdc.tq[curridx] != NULL)
  324. goto start;
  325. while (++curridx != hp_sdc.wcurr) {
  326. if (curridx >= HP_SDC_QUEUE_LEN) {
  327. curridx = -1; /* Wrap to top */
  328. continue;
  329. }
  330. read_lock_irq(&hp_sdc.rtq_lock);
  331. if (hp_sdc.rcurr == curridx) {
  332. read_unlock_irq(&hp_sdc.rtq_lock);
  333. continue;
  334. }
  335. read_unlock_irq(&hp_sdc.rtq_lock);
  336. if (hp_sdc.tq[curridx] != NULL)
  337. break; /* Found one. */
  338. }
  339. if (curridx == hp_sdc.wcurr) { /* There's nothing queued to do. */
  340. curridx = -1;
  341. }
  342. hp_sdc.wcurr = curridx;
  343. start:
  344. /* Check to see if the interrupt mask needs to be set. */
  345. if (hp_sdc.set_im) {
  346. hp_sdc_status_out8(hp_sdc.im | HP_SDC_CMD_SET_IM);
  347. hp_sdc.set_im = 0;
  348. goto finish;
  349. }
  350. if (hp_sdc.wcurr == -1)
  351. goto done;
  352. curr = hp_sdc.tq[curridx];
  353. idx = curr->actidx;
  354. if (curr->actidx >= curr->endidx) {
  355. hp_sdc.tq[curridx] = NULL;
  356. /* Interleave outbound data between the transactions. */
  357. hp_sdc.wcurr++;
  358. if (hp_sdc.wcurr >= HP_SDC_QUEUE_LEN)
  359. hp_sdc.wcurr = 0;
  360. goto finish;
  361. }
  362. act = curr->seq[idx];
  363. idx++;
  364. if (curr->idx >= curr->endidx) {
  365. if (act & HP_SDC_ACT_DEALLOC)
  366. kfree(curr);
  367. hp_sdc.tq[curridx] = NULL;
  368. /* Interleave outbound data between the transactions. */
  369. hp_sdc.wcurr++;
  370. if (hp_sdc.wcurr >= HP_SDC_QUEUE_LEN)
  371. hp_sdc.wcurr = 0;
  372. goto finish;
  373. }
  374. while (act & HP_SDC_ACT_PRECMD) {
  375. if (curr->idx != idx) {
  376. idx++;
  377. act &= ~HP_SDC_ACT_PRECMD;
  378. break;
  379. }
  380. hp_sdc_status_out8(curr->seq[idx]);
  381. curr->idx++;
  382. /* act finished? */
  383. if ((act & HP_SDC_ACT_DURING) == HP_SDC_ACT_PRECMD)
  384. goto actdone;
  385. /* skip quantity field if data-out sequence follows. */
  386. if (act & HP_SDC_ACT_DATAOUT)
  387. curr->idx++;
  388. goto finish;
  389. }
  390. if (act & HP_SDC_ACT_DATAOUT) {
  391. int qty;
  392. qty = curr->seq[idx];
  393. idx++;
  394. if (curr->idx - idx < qty) {
  395. hp_sdc_data_out8(curr->seq[curr->idx]);
  396. curr->idx++;
  397. /* act finished? */
  398. if (curr->idx - idx >= qty &&
  399. (act & HP_SDC_ACT_DURING) == HP_SDC_ACT_DATAOUT)
  400. goto actdone;
  401. goto finish;
  402. }
  403. idx += qty;
  404. act &= ~HP_SDC_ACT_DATAOUT;
  405. } else
  406. while (act & HP_SDC_ACT_DATAREG) {
  407. int mask;
  408. uint8_t w7[4];
  409. mask = curr->seq[idx];
  410. if (idx != curr->idx) {
  411. idx++;
  412. idx += !!(mask & 1);
  413. idx += !!(mask & 2);
  414. idx += !!(mask & 4);
  415. idx += !!(mask & 8);
  416. act &= ~HP_SDC_ACT_DATAREG;
  417. break;
  418. }
  419. w7[0] = (mask & 1) ? curr->seq[++idx] : hp_sdc.r7[0];
  420. w7[1] = (mask & 2) ? curr->seq[++idx] : hp_sdc.r7[1];
  421. w7[2] = (mask & 4) ? curr->seq[++idx] : hp_sdc.r7[2];
  422. w7[3] = (mask & 8) ? curr->seq[++idx] : hp_sdc.r7[3];
  423. if (hp_sdc.wi > 0x73 || hp_sdc.wi < 0x70 ||
  424. w7[hp_sdc.wi - 0x70] == hp_sdc.r7[hp_sdc.wi - 0x70]) {
  425. int i = 0;
  426. /* Need to point the write index register */
  427. while (i < 4 && w7[i] == hp_sdc.r7[i])
  428. i++;
  429. if (i < 4) {
  430. hp_sdc_status_out8(HP_SDC_CMD_SET_D0 + i);
  431. hp_sdc.wi = 0x70 + i;
  432. goto finish;
  433. }
  434. idx++;
  435. if ((act & HP_SDC_ACT_DURING) == HP_SDC_ACT_DATAREG)
  436. goto actdone;
  437. curr->idx = idx;
  438. act &= ~HP_SDC_ACT_DATAREG;
  439. break;
  440. }
  441. hp_sdc_data_out8(w7[hp_sdc.wi - 0x70]);
  442. hp_sdc.r7[hp_sdc.wi - 0x70] = w7[hp_sdc.wi - 0x70];
  443. hp_sdc.wi++; /* write index register autoincrements */
  444. {
  445. int i = 0;
  446. while ((i < 4) && w7[i] == hp_sdc.r7[i])
  447. i++;
  448. if (i >= 4) {
  449. curr->idx = idx + 1;
  450. if ((act & HP_SDC_ACT_DURING) ==
  451. HP_SDC_ACT_DATAREG)
  452. goto actdone;
  453. }
  454. }
  455. goto finish;
  456. }
  457. /* We don't go any further in the command if there is a pending read,
  458. because we don't want interleaved results. */
  459. read_lock_irq(&hp_sdc.rtq_lock);
  460. if (hp_sdc.rcurr >= 0) {
  461. read_unlock_irq(&hp_sdc.rtq_lock);
  462. goto finish;
  463. }
  464. read_unlock_irq(&hp_sdc.rtq_lock);
  465. if (act & HP_SDC_ACT_POSTCMD) {
  466. uint8_t postcmd;
  467. /* curr->idx should == idx at this point. */
  468. postcmd = curr->seq[idx];
  469. curr->idx++;
  470. if (act & HP_SDC_ACT_DATAIN) {
  471. /* Start a new read */
  472. hp_sdc.rqty = curr->seq[curr->idx];
  473. do_gettimeofday(&hp_sdc.rtv);
  474. curr->idx++;
  475. /* Still need to lock here in case of spurious irq. */
  476. write_lock_irq(&hp_sdc.rtq_lock);
  477. hp_sdc.rcurr = curridx;
  478. write_unlock_irq(&hp_sdc.rtq_lock);
  479. hp_sdc_status_out8(postcmd);
  480. goto finish;
  481. }
  482. hp_sdc_status_out8(postcmd);
  483. goto actdone;
  484. }
  485. actdone:
  486. if (act & HP_SDC_ACT_SEMAPHORE)
  487. up(curr->act.semaphore);
  488. else if (act & HP_SDC_ACT_CALLBACK)
  489. curr->act.irqhook(0,NULL,0,0);
  490. if (curr->idx >= curr->endidx) { /* This transaction is over. */
  491. if (act & HP_SDC_ACT_DEALLOC)
  492. kfree(curr);
  493. hp_sdc.tq[curridx] = NULL;
  494. } else {
  495. curr->actidx = idx + 1;
  496. curr->idx = idx + 2;
  497. }
  498. /* Interleave outbound data between the transactions. */
  499. hp_sdc.wcurr++;
  500. if (hp_sdc.wcurr >= HP_SDC_QUEUE_LEN)
  501. hp_sdc.wcurr = 0;
  502. finish:
  503. /* If by some quirk IBF has cleared and our ISR has run to
  504. see that that has happened, do it all again. */
  505. if (!hp_sdc.ibf && limit++ < 20)
  506. goto anew;
  507. done:
  508. if (hp_sdc.wcurr >= 0)
  509. tasklet_schedule(&hp_sdc.task);
  510. write_unlock(&hp_sdc.lock);
  511. return 0;
  512. }
  513. /******* Functions called in either user or kernel context ****/
  514. int __hp_sdc_enqueue_transaction(hp_sdc_transaction *this)
  515. {
  516. int i;
  517. if (this == NULL) {
  518. BUG();
  519. return -EINVAL;
  520. }
  521. /* Can't have same transaction on queue twice */
  522. for (i = 0; i < HP_SDC_QUEUE_LEN; i++)
  523. if (hp_sdc.tq[i] == this)
  524. goto fail;
  525. this->actidx = 0;
  526. this->idx = 1;
  527. /* Search for empty slot */
  528. for (i = 0; i < HP_SDC_QUEUE_LEN; i++)
  529. if (hp_sdc.tq[i] == NULL) {
  530. hp_sdc.tq[i] = this;
  531. tasklet_schedule(&hp_sdc.task);
  532. return 0;
  533. }
  534. printk(KERN_WARNING PREFIX "No free slot to add transaction.\n");
  535. return -EBUSY;
  536. fail:
  537. printk(KERN_WARNING PREFIX "Transaction add failed: transaction already queued?\n");
  538. return -EINVAL;
  539. }
  540. int hp_sdc_enqueue_transaction(hp_sdc_transaction *this) {
  541. unsigned long flags;
  542. int ret;
  543. write_lock_irqsave(&hp_sdc.lock, flags);
  544. ret = __hp_sdc_enqueue_transaction(this);
  545. write_unlock_irqrestore(&hp_sdc.lock,flags);
  546. return ret;
  547. }
  548. int hp_sdc_dequeue_transaction(hp_sdc_transaction *this)
  549. {
  550. unsigned long flags;
  551. int i;
  552. write_lock_irqsave(&hp_sdc.lock, flags);
  553. /* TODO: don't remove it if it's not done. */
  554. for (i = 0; i < HP_SDC_QUEUE_LEN; i++)
  555. if (hp_sdc.tq[i] == this)
  556. hp_sdc.tq[i] = NULL;
  557. write_unlock_irqrestore(&hp_sdc.lock, flags);
  558. return 0;
  559. }
  560. /********************** User context functions **************************/
  561. int hp_sdc_request_timer_irq(hp_sdc_irqhook *callback)
  562. {
  563. if (callback == NULL || hp_sdc.dev == NULL)
  564. return -EINVAL;
  565. write_lock_irq(&hp_sdc.hook_lock);
  566. if (hp_sdc.timer != NULL) {
  567. write_unlock_irq(&hp_sdc.hook_lock);
  568. return -EBUSY;
  569. }
  570. hp_sdc.timer = callback;
  571. /* Enable interrupts from the timers */
  572. hp_sdc.im &= ~HP_SDC_IM_FH;
  573. hp_sdc.im &= ~HP_SDC_IM_PT;
  574. hp_sdc.im &= ~HP_SDC_IM_TIMERS;
  575. hp_sdc.set_im = 1;
  576. write_unlock_irq(&hp_sdc.hook_lock);
  577. tasklet_schedule(&hp_sdc.task);
  578. return 0;
  579. }
  580. int hp_sdc_request_hil_irq(hp_sdc_irqhook *callback)
  581. {
  582. if (callback == NULL || hp_sdc.dev == NULL)
  583. return -EINVAL;
  584. write_lock_irq(&hp_sdc.hook_lock);
  585. if (hp_sdc.hil != NULL) {
  586. write_unlock_irq(&hp_sdc.hook_lock);
  587. return -EBUSY;
  588. }
  589. hp_sdc.hil = callback;
  590. hp_sdc.im &= ~(HP_SDC_IM_HIL | HP_SDC_IM_RESET);
  591. hp_sdc.set_im = 1;
  592. write_unlock_irq(&hp_sdc.hook_lock);
  593. tasklet_schedule(&hp_sdc.task);
  594. return 0;
  595. }
  596. int hp_sdc_request_cooked_irq(hp_sdc_irqhook *callback)
  597. {
  598. if (callback == NULL || hp_sdc.dev == NULL)
  599. return -EINVAL;
  600. write_lock_irq(&hp_sdc.hook_lock);
  601. if (hp_sdc.cooked != NULL) {
  602. write_unlock_irq(&hp_sdc.hook_lock);
  603. return -EBUSY;
  604. }
  605. /* Enable interrupts from the HIL MLC */
  606. hp_sdc.cooked = callback;
  607. hp_sdc.im &= ~(HP_SDC_IM_HIL | HP_SDC_IM_RESET);
  608. hp_sdc.set_im = 1;
  609. write_unlock_irq(&hp_sdc.hook_lock);
  610. tasklet_schedule(&hp_sdc.task);
  611. return 0;
  612. }
  613. int hp_sdc_release_timer_irq(hp_sdc_irqhook *callback)
  614. {
  615. write_lock_irq(&hp_sdc.hook_lock);
  616. if ((callback != hp_sdc.timer) ||
  617. (hp_sdc.timer == NULL)) {
  618. write_unlock_irq(&hp_sdc.hook_lock);
  619. return -EINVAL;
  620. }
  621. /* Disable interrupts from the timers */
  622. hp_sdc.timer = NULL;
  623. hp_sdc.im |= HP_SDC_IM_TIMERS;
  624. hp_sdc.im |= HP_SDC_IM_FH;
  625. hp_sdc.im |= HP_SDC_IM_PT;
  626. hp_sdc.set_im = 1;
  627. write_unlock_irq(&hp_sdc.hook_lock);
  628. tasklet_schedule(&hp_sdc.task);
  629. return 0;
  630. }
  631. int hp_sdc_release_hil_irq(hp_sdc_irqhook *callback)
  632. {
  633. write_lock_irq(&hp_sdc.hook_lock);
  634. if ((callback != hp_sdc.hil) ||
  635. (hp_sdc.hil == NULL)) {
  636. write_unlock_irq(&hp_sdc.hook_lock);
  637. return -EINVAL;
  638. }
  639. hp_sdc.hil = NULL;
  640. /* Disable interrupts from HIL only if there is no cooked driver. */
  641. if(hp_sdc.cooked == NULL) {
  642. hp_sdc.im |= (HP_SDC_IM_HIL | HP_SDC_IM_RESET);
  643. hp_sdc.set_im = 1;
  644. }
  645. write_unlock_irq(&hp_sdc.hook_lock);
  646. tasklet_schedule(&hp_sdc.task);
  647. return 0;
  648. }
  649. int hp_sdc_release_cooked_irq(hp_sdc_irqhook *callback)
  650. {
  651. write_lock_irq(&hp_sdc.hook_lock);
  652. if ((callback != hp_sdc.cooked) ||
  653. (hp_sdc.cooked == NULL)) {
  654. write_unlock_irq(&hp_sdc.hook_lock);
  655. return -EINVAL;
  656. }
  657. hp_sdc.cooked = NULL;
  658. /* Disable interrupts from HIL only if there is no raw HIL driver. */
  659. if(hp_sdc.hil == NULL) {
  660. hp_sdc.im |= (HP_SDC_IM_HIL | HP_SDC_IM_RESET);
  661. hp_sdc.set_im = 1;
  662. }
  663. write_unlock_irq(&hp_sdc.hook_lock);
  664. tasklet_schedule(&hp_sdc.task);
  665. return 0;
  666. }
  667. /************************* Keepalive timer task *********************/
  668. void hp_sdc_kicker (unsigned long data)
  669. {
  670. tasklet_schedule(&hp_sdc.task);
  671. /* Re-insert the periodic task. */
  672. mod_timer(&hp_sdc.kicker, jiffies + HZ);
  673. }
  674. /************************** Module Initialization ***************************/
  675. #if defined(__hppa__)
  676. static const struct parisc_device_id hp_sdc_tbl[] = {
  677. {
  678. .hw_type = HPHW_FIO,
  679. .hversion_rev = HVERSION_REV_ANY_ID,
  680. .hversion = HVERSION_ANY_ID,
  681. .sversion = 0x73,
  682. },
  683. { 0, }
  684. };
  685. MODULE_DEVICE_TABLE(parisc, hp_sdc_tbl);
  686. static int __init hp_sdc_init_hppa(struct parisc_device *d);
  687. static struct parisc_driver hp_sdc_driver = {
  688. .name = "hp_sdc",
  689. .id_table = hp_sdc_tbl,
  690. .probe = hp_sdc_init_hppa,
  691. };
  692. #endif /* __hppa__ */
  693. static int __init hp_sdc_init(void)
  694. {
  695. char *errstr;
  696. hp_sdc_transaction t_sync;
  697. uint8_t ts_sync[6];
  698. struct semaphore s_sync;
  699. rwlock_init(&hp_sdc.lock);
  700. rwlock_init(&hp_sdc.ibf_lock);
  701. rwlock_init(&hp_sdc.rtq_lock);
  702. rwlock_init(&hp_sdc.hook_lock);
  703. hp_sdc.timer = NULL;
  704. hp_sdc.hil = NULL;
  705. hp_sdc.pup = NULL;
  706. hp_sdc.cooked = NULL;
  707. hp_sdc.im = HP_SDC_IM_MASK; /* Mask maskable irqs */
  708. hp_sdc.set_im = 1;
  709. hp_sdc.wi = 0xff;
  710. hp_sdc.r7[0] = 0xff;
  711. hp_sdc.r7[1] = 0xff;
  712. hp_sdc.r7[2] = 0xff;
  713. hp_sdc.r7[3] = 0xff;
  714. hp_sdc.ibf = 1;
  715. memset(&hp_sdc.tq, 0, sizeof(hp_sdc.tq));
  716. hp_sdc.wcurr = -1;
  717. hp_sdc.rcurr = -1;
  718. hp_sdc.rqty = 0;
  719. hp_sdc.dev_err = -ENODEV;
  720. errstr = "IO not found for";
  721. if (!hp_sdc.base_io)
  722. goto err0;
  723. errstr = "IRQ not found for";
  724. if (!hp_sdc.irq)
  725. goto err0;
  726. hp_sdc.dev_err = -EBUSY;
  727. #if defined(__hppa__)
  728. errstr = "IO not available for";
  729. if (request_region(hp_sdc.data_io, 2, hp_sdc_driver.name))
  730. goto err0;
  731. #endif
  732. errstr = "IRQ not available for";
  733. if (request_irq(hp_sdc.irq, &hp_sdc_isr, IRQF_SHARED|IRQF_SAMPLE_RANDOM,
  734. "HP SDC", &hp_sdc))
  735. goto err1;
  736. errstr = "NMI not available for";
  737. if (request_irq(hp_sdc.nmi, &hp_sdc_nmisr, IRQF_SHARED,
  738. "HP SDC NMI", &hp_sdc))
  739. goto err2;
  740. printk(KERN_INFO PREFIX "HP SDC at 0x%p, IRQ %d (NMI IRQ %d)\n",
  741. (void *)hp_sdc.base_io, hp_sdc.irq, hp_sdc.nmi);
  742. hp_sdc_status_in8();
  743. hp_sdc_data_in8();
  744. tasklet_init(&hp_sdc.task, hp_sdc_tasklet, 0);
  745. /* Sync the output buffer registers, thus scheduling hp_sdc_tasklet. */
  746. t_sync.actidx = 0;
  747. t_sync.idx = 1;
  748. t_sync.endidx = 6;
  749. t_sync.seq = ts_sync;
  750. ts_sync[0] = HP_SDC_ACT_DATAREG | HP_SDC_ACT_SEMAPHORE;
  751. ts_sync[1] = 0x0f;
  752. ts_sync[2] = ts_sync[3] = ts_sync[4] = ts_sync[5] = 0;
  753. t_sync.act.semaphore = &s_sync;
  754. init_MUTEX_LOCKED(&s_sync);
  755. hp_sdc_enqueue_transaction(&t_sync);
  756. down(&s_sync); /* Wait for t_sync to complete */
  757. /* Create the keepalive task */
  758. init_timer(&hp_sdc.kicker);
  759. hp_sdc.kicker.expires = jiffies + HZ;
  760. hp_sdc.kicker.function = &hp_sdc_kicker;
  761. add_timer(&hp_sdc.kicker);
  762. hp_sdc.dev_err = 0;
  763. return 0;
  764. err2:
  765. free_irq(hp_sdc.irq, &hp_sdc);
  766. err1:
  767. release_region(hp_sdc.data_io, 2);
  768. err0:
  769. printk(KERN_WARNING PREFIX ": %s SDC IO=0x%p IRQ=0x%x NMI=0x%x\n",
  770. errstr, (void *)hp_sdc.base_io, hp_sdc.irq, hp_sdc.nmi);
  771. hp_sdc.dev = NULL;
  772. return hp_sdc.dev_err;
  773. }
  774. #if defined(__hppa__)
  775. static int __init hp_sdc_init_hppa(struct parisc_device *d)
  776. {
  777. if (!d)
  778. return 1;
  779. if (hp_sdc.dev != NULL)
  780. return 1; /* We only expect one SDC */
  781. hp_sdc.dev = d;
  782. hp_sdc.irq = d->irq;
  783. hp_sdc.nmi = d->aux_irq;
  784. hp_sdc.base_io = d->hpa.start;
  785. hp_sdc.data_io = d->hpa.start + 0x800;
  786. hp_sdc.status_io = d->hpa.start + 0x801;
  787. return hp_sdc_init();
  788. }
  789. #endif /* __hppa__ */
  790. static void hp_sdc_exit(void)
  791. {
  792. write_lock_irq(&hp_sdc.lock);
  793. /* Turn off all maskable "sub-function" irq's. */
  794. hp_sdc_spin_ibf();
  795. sdc_writeb(HP_SDC_CMD_SET_IM | HP_SDC_IM_MASK, hp_sdc.status_io);
  796. /* Wait until we know this has been processed by the i8042 */
  797. hp_sdc_spin_ibf();
  798. free_irq(hp_sdc.nmi, &hp_sdc);
  799. free_irq(hp_sdc.irq, &hp_sdc);
  800. write_unlock_irq(&hp_sdc.lock);
  801. del_timer(&hp_sdc.kicker);
  802. tasklet_kill(&hp_sdc.task);
  803. #if defined(__hppa__)
  804. if (unregister_parisc_driver(&hp_sdc_driver))
  805. printk(KERN_WARNING PREFIX "Error unregistering HP SDC");
  806. #endif
  807. }
  808. static int __init hp_sdc_register(void)
  809. {
  810. hp_sdc_transaction tq_init;
  811. uint8_t tq_init_seq[5];
  812. struct semaphore tq_init_sem;
  813. #if defined(__mc68000__)
  814. mm_segment_t fs;
  815. unsigned char i;
  816. #endif
  817. if (hp_sdc_disabled) {
  818. printk(KERN_WARNING PREFIX "HP SDC driver disabled by no_hpsdc=1.\n");
  819. return -ENODEV;
  820. }
  821. hp_sdc.dev = NULL;
  822. hp_sdc.dev_err = 0;
  823. #if defined(__hppa__)
  824. if (register_parisc_driver(&hp_sdc_driver)) {
  825. printk(KERN_WARNING PREFIX "Error registering SDC with system bus tree.\n");
  826. return -ENODEV;
  827. }
  828. #elif defined(__mc68000__)
  829. if (!MACH_IS_HP300)
  830. return -ENODEV;
  831. hp_sdc.irq = 1;
  832. hp_sdc.nmi = 7;
  833. hp_sdc.base_io = (unsigned long) 0xf0428000;
  834. hp_sdc.data_io = (unsigned long) hp_sdc.base_io + 1;
  835. hp_sdc.status_io = (unsigned long) hp_sdc.base_io + 3;
  836. fs = get_fs();
  837. set_fs(KERNEL_DS);
  838. if (!get_user(i, (unsigned char *)hp_sdc.data_io))
  839. hp_sdc.dev = (void *)1;
  840. set_fs(fs);
  841. hp_sdc.dev_err = hp_sdc_init();
  842. #endif
  843. if (hp_sdc.dev == NULL) {
  844. printk(KERN_WARNING PREFIX "No SDC found.\n");
  845. return hp_sdc.dev_err;
  846. }
  847. init_MUTEX_LOCKED(&tq_init_sem);
  848. tq_init.actidx = 0;
  849. tq_init.idx = 1;
  850. tq_init.endidx = 5;
  851. tq_init.seq = tq_init_seq;
  852. tq_init.act.semaphore = &tq_init_sem;
  853. tq_init_seq[0] =
  854. HP_SDC_ACT_POSTCMD | HP_SDC_ACT_DATAIN | HP_SDC_ACT_SEMAPHORE;
  855. tq_init_seq[1] = HP_SDC_CMD_READ_KCC;
  856. tq_init_seq[2] = 1;
  857. tq_init_seq[3] = 0;
  858. tq_init_seq[4] = 0;
  859. hp_sdc_enqueue_transaction(&tq_init);
  860. down(&tq_init_sem);
  861. up(&tq_init_sem);
  862. if ((tq_init_seq[0] & HP_SDC_ACT_DEAD) == HP_SDC_ACT_DEAD) {
  863. printk(KERN_WARNING PREFIX "Error reading config byte.\n");
  864. hp_sdc_exit();
  865. return -ENODEV;
  866. }
  867. hp_sdc.r11 = tq_init_seq[4];
  868. if (hp_sdc.r11 & HP_SDC_CFG_NEW) {
  869. const char *str;
  870. printk(KERN_INFO PREFIX "New style SDC\n");
  871. tq_init_seq[1] = HP_SDC_CMD_READ_XTD;
  872. tq_init.actidx = 0;
  873. tq_init.idx = 1;
  874. down(&tq_init_sem);
  875. hp_sdc_enqueue_transaction(&tq_init);
  876. down(&tq_init_sem);
  877. up(&tq_init_sem);
  878. if ((tq_init_seq[0] & HP_SDC_ACT_DEAD) == HP_SDC_ACT_DEAD) {
  879. printk(KERN_WARNING PREFIX "Error reading extended config byte.\n");
  880. return -ENODEV;
  881. }
  882. hp_sdc.r7e = tq_init_seq[4];
  883. HP_SDC_XTD_REV_STRINGS(hp_sdc.r7e & HP_SDC_XTD_REV, str)
  884. printk(KERN_INFO PREFIX "Revision: %s\n", str);
  885. if (hp_sdc.r7e & HP_SDC_XTD_BEEPER)
  886. printk(KERN_INFO PREFIX "TI SN76494 beeper present\n");
  887. if (hp_sdc.r7e & HP_SDC_XTD_BBRTC)
  888. printk(KERN_INFO PREFIX "OKI MSM-58321 BBRTC present\n");
  889. printk(KERN_INFO PREFIX "Spunking the self test register to force PUP "
  890. "on next firmware reset.\n");
  891. tq_init_seq[0] = HP_SDC_ACT_PRECMD |
  892. HP_SDC_ACT_DATAOUT | HP_SDC_ACT_SEMAPHORE;
  893. tq_init_seq[1] = HP_SDC_CMD_SET_STR;
  894. tq_init_seq[2] = 1;
  895. tq_init_seq[3] = 0;
  896. tq_init.actidx = 0;
  897. tq_init.idx = 1;
  898. tq_init.endidx = 4;
  899. down(&tq_init_sem);
  900. hp_sdc_enqueue_transaction(&tq_init);
  901. down(&tq_init_sem);
  902. up(&tq_init_sem);
  903. } else
  904. printk(KERN_INFO PREFIX "Old style SDC (1820-%s).\n",
  905. (hp_sdc.r11 & HP_SDC_CFG_REV) ? "3300" : "2564/3087");
  906. return 0;
  907. }
  908. module_init(hp_sdc_register);
  909. module_exit(hp_sdc_exit);
  910. /* Timing notes: These measurements taken on my 64MHz 7100-LC (715/64)
  911. * cycles cycles-adj time
  912. * between two consecutive mfctl(16)'s: 4 n/a 63ns
  913. * hp_sdc_spin_ibf when idle: 119 115 1.7us
  914. * gsc_writeb status register: 83 79 1.2us
  915. * IBF to clear after sending SET_IM: 6204 6006 93us
  916. * IBF to clear after sending LOAD_RT: 4467 4352 68us
  917. * IBF to clear after sending two LOAD_RTs: 18974 18859 295us
  918. * READ_T1, read status/data, IRQ, call handler: 35564 n/a 556us
  919. * cmd to ~IBF READ_T1 2nd time right after: 5158403 n/a 81ms
  920. * between IRQ received and ~IBF for above: 2578877 n/a 40ms
  921. *
  922. * Performance stats after a run of this module configuring HIL and
  923. * receiving a few mouse events:
  924. *
  925. * status in8 282508 cycles 7128 calls
  926. * status out8 8404 cycles 341 calls
  927. * data out8 1734 cycles 78 calls
  928. * isr 174324 cycles 617 calls (includes take)
  929. * take 1241 cycles 2 calls
  930. * put 1411504 cycles 6937 calls
  931. * task 1655209 cycles 6937 calls (includes put)
  932. *
  933. */