q40ide.c 4.0 KB

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  1. /*
  2. * Q40 I/O port IDE Driver
  3. *
  4. * (c) Richard Zidlicky
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file COPYING in the main directory of this archive for
  8. * more details.
  9. *
  10. *
  11. */
  12. #include <linux/types.h>
  13. #include <linux/mm.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/blkdev.h>
  16. #include <linux/ide.h>
  17. /*
  18. * Bases of the IDE interfaces
  19. */
  20. #define Q40IDE_NUM_HWIFS 2
  21. #define PCIDE_BASE1 0x1f0
  22. #define PCIDE_BASE2 0x170
  23. #define PCIDE_BASE3 0x1e8
  24. #define PCIDE_BASE4 0x168
  25. #define PCIDE_BASE5 0x1e0
  26. #define PCIDE_BASE6 0x160
  27. static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = {
  28. PCIDE_BASE1, PCIDE_BASE2, /* PCIDE_BASE3, PCIDE_BASE4 , PCIDE_BASE5,
  29. PCIDE_BASE6 */
  30. };
  31. static int q40ide_default_irq(unsigned long base)
  32. {
  33. switch (base) {
  34. case 0x1f0: return 14;
  35. case 0x170: return 15;
  36. case 0x1e8: return 11;
  37. default:
  38. return 0;
  39. }
  40. }
  41. /*
  42. * Addresses are pretranslated for Q40 ISA access.
  43. */
  44. static void q40_ide_setup_ports(hw_regs_t *hw, unsigned long base,
  45. ide_ack_intr_t *ack_intr,
  46. int irq)
  47. {
  48. memset(hw, 0, sizeof(hw_regs_t));
  49. /* BIG FAT WARNING:
  50. assumption: only DATA port is ever used in 16 bit mode */
  51. hw->io_ports.data_addr = Q40_ISA_IO_W(base);
  52. hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1);
  53. hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2);
  54. hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3);
  55. hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4);
  56. hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5);
  57. hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6);
  58. hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7);
  59. hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206);
  60. hw->irq = irq;
  61. hw->ack_intr = ack_intr;
  62. hw->chipset = ide_generic;
  63. }
  64. static void q40ide_input_data(ide_drive_t *drive, struct request *rq,
  65. void *buf, unsigned int len)
  66. {
  67. unsigned long data_addr = drive->hwif->io_ports.data_addr;
  68. if (drive->media == ide_disk && rq && rq->cmd_type == REQ_TYPE_FS)
  69. return insw(data_addr, buf, (len + 1) / 2);
  70. insw_swapw(data_addr, buf, (len + 1) / 2);
  71. }
  72. static void q40ide_output_data(ide_drive_t *drive, struct request *rq,
  73. void *buf, unsigned int len)
  74. {
  75. unsigned long data_addr = drive->hwif->io_ports.data_addr;
  76. if (drive->media == ide_disk && rq && rq->cmd_type == REQ_TYPE_FS)
  77. return outsw(data_addr, buf, (len + 1) / 2);
  78. outsw_swapw(data_addr, buf, (len + 1) / 2);
  79. }
  80. /* Q40 has a byte-swapped IDE interface */
  81. static const struct ide_tp_ops q40ide_tp_ops = {
  82. .exec_command = ide_exec_command,
  83. .read_status = ide_read_status,
  84. .read_altstatus = ide_read_altstatus,
  85. .read_sff_dma_status = ide_read_sff_dma_status,
  86. .set_irq = ide_set_irq,
  87. .tf_load = ide_tf_load,
  88. .tf_read = ide_tf_read,
  89. .input_data = q40ide_input_data,
  90. .output_data = q40ide_output_data,
  91. };
  92. static const struct ide_port_info q40ide_port_info = {
  93. .tp_ops = &q40ide_tp_ops,
  94. .host_flags = IDE_HFLAG_NO_DMA,
  95. };
  96. /*
  97. * the static array is needed to have the name reported in /proc/ioports,
  98. * hwif->name unfortunately isn't available yet
  99. */
  100. static const char *q40_ide_names[Q40IDE_NUM_HWIFS]={
  101. "ide0", "ide1"
  102. };
  103. /*
  104. * Probe for Q40 IDE interfaces
  105. */
  106. static int __init q40ide_init(void)
  107. {
  108. int i;
  109. hw_regs_t hw[Q40IDE_NUM_HWIFS], *hws[] = { NULL, NULL, NULL, NULL };
  110. if (!MACH_IS_Q40)
  111. return -ENODEV;
  112. printk(KERN_INFO "ide: Q40 IDE controller\n");
  113. for (i = 0; i < Q40IDE_NUM_HWIFS; i++) {
  114. const char *name = q40_ide_names[i];
  115. if (!request_region(pcide_bases[i], 8, name)) {
  116. printk("could not reserve ports %lx-%lx for %s\n",
  117. pcide_bases[i],pcide_bases[i]+8,name);
  118. continue;
  119. }
  120. if (!request_region(pcide_bases[i]+0x206, 1, name)) {
  121. printk("could not reserve port %lx for %s\n",
  122. pcide_bases[i]+0x206,name);
  123. release_region(pcide_bases[i], 8);
  124. continue;
  125. }
  126. q40_ide_setup_ports(&hw[i], pcide_bases[i], NULL,
  127. q40ide_default_irq(pcide_bases[i]));
  128. hws[i] = &hw[i];
  129. }
  130. return ide_host_add(&q40ide_port_info, hws, NULL);
  131. }
  132. module_init(q40ide_init);
  133. MODULE_LICENSE("GPL");