i2c-ocores.c 8.4 KB

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  1. /*
  2. * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
  3. * (http://www.opencores.org/projects.cgi/web/i2c/overview).
  4. *
  5. * Peter Korsgaard <jacmet@sunsite.dk>
  6. *
  7. * This file is licensed under the terms of the GNU General Public License
  8. * version 2. This program is licensed "as is" without any warranty of any
  9. * kind, whether express or implied.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/init.h>
  14. #include <linux/errno.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/i2c.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/wait.h>
  19. #include <linux/i2c-ocores.h>
  20. #include <asm/io.h>
  21. struct ocores_i2c {
  22. void __iomem *base;
  23. int regstep;
  24. wait_queue_head_t wait;
  25. struct i2c_adapter adap;
  26. struct i2c_msg *msg;
  27. int pos;
  28. int nmsgs;
  29. int state; /* see STATE_ */
  30. int clock_khz;
  31. };
  32. /* registers */
  33. #define OCI2C_PRELOW 0
  34. #define OCI2C_PREHIGH 1
  35. #define OCI2C_CONTROL 2
  36. #define OCI2C_DATA 3
  37. #define OCI2C_CMD 4 /* write only */
  38. #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
  39. #define OCI2C_CTRL_IEN 0x40
  40. #define OCI2C_CTRL_EN 0x80
  41. #define OCI2C_CMD_START 0x91
  42. #define OCI2C_CMD_STOP 0x41
  43. #define OCI2C_CMD_READ 0x21
  44. #define OCI2C_CMD_WRITE 0x11
  45. #define OCI2C_CMD_READ_ACK 0x21
  46. #define OCI2C_CMD_READ_NACK 0x29
  47. #define OCI2C_CMD_IACK 0x01
  48. #define OCI2C_STAT_IF 0x01
  49. #define OCI2C_STAT_TIP 0x02
  50. #define OCI2C_STAT_ARBLOST 0x20
  51. #define OCI2C_STAT_BUSY 0x40
  52. #define OCI2C_STAT_NACK 0x80
  53. #define STATE_DONE 0
  54. #define STATE_START 1
  55. #define STATE_WRITE 2
  56. #define STATE_READ 3
  57. #define STATE_ERROR 4
  58. static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
  59. {
  60. iowrite8(value, i2c->base + reg * i2c->regstep);
  61. }
  62. static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
  63. {
  64. return ioread8(i2c->base + reg * i2c->regstep);
  65. }
  66. static void ocores_process(struct ocores_i2c *i2c)
  67. {
  68. struct i2c_msg *msg = i2c->msg;
  69. u8 stat = oc_getreg(i2c, OCI2C_STATUS);
  70. if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
  71. /* stop has been sent */
  72. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
  73. wake_up(&i2c->wait);
  74. return;
  75. }
  76. /* error? */
  77. if (stat & OCI2C_STAT_ARBLOST) {
  78. i2c->state = STATE_ERROR;
  79. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
  80. return;
  81. }
  82. if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
  83. i2c->state =
  84. (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
  85. if (stat & OCI2C_STAT_NACK) {
  86. i2c->state = STATE_ERROR;
  87. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
  88. return;
  89. }
  90. } else
  91. msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
  92. /* end of msg? */
  93. if (i2c->pos == msg->len) {
  94. i2c->nmsgs--;
  95. i2c->msg++;
  96. i2c->pos = 0;
  97. msg = i2c->msg;
  98. if (i2c->nmsgs) { /* end? */
  99. /* send start? */
  100. if (!(msg->flags & I2C_M_NOSTART)) {
  101. u8 addr = (msg->addr << 1);
  102. if (msg->flags & I2C_M_RD)
  103. addr |= 1;
  104. i2c->state = STATE_START;
  105. oc_setreg(i2c, OCI2C_DATA, addr);
  106. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
  107. return;
  108. } else
  109. i2c->state = (msg->flags & I2C_M_RD)
  110. ? STATE_READ : STATE_WRITE;
  111. } else {
  112. i2c->state = STATE_DONE;
  113. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
  114. return;
  115. }
  116. }
  117. if (i2c->state == STATE_READ) {
  118. oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
  119. OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
  120. } else {
  121. oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
  122. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
  123. }
  124. }
  125. static irqreturn_t ocores_isr(int irq, void *dev_id)
  126. {
  127. struct ocores_i2c *i2c = dev_id;
  128. ocores_process(i2c);
  129. return IRQ_HANDLED;
  130. }
  131. static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
  132. {
  133. struct ocores_i2c *i2c = i2c_get_adapdata(adap);
  134. i2c->msg = msgs;
  135. i2c->pos = 0;
  136. i2c->nmsgs = num;
  137. i2c->state = STATE_START;
  138. oc_setreg(i2c, OCI2C_DATA,
  139. (i2c->msg->addr << 1) |
  140. ((i2c->msg->flags & I2C_M_RD) ? 1:0));
  141. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
  142. if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
  143. (i2c->state == STATE_DONE), HZ))
  144. return (i2c->state == STATE_DONE) ? num : -EIO;
  145. else
  146. return -ETIMEDOUT;
  147. }
  148. static void ocores_init(struct ocores_i2c *i2c)
  149. {
  150. int prescale;
  151. u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
  152. /* make sure the device is disabled */
  153. oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
  154. prescale = (i2c->clock_khz / (5*100)) - 1;
  155. oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
  156. oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
  157. /* Init the device */
  158. oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
  159. oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN);
  160. }
  161. static u32 ocores_func(struct i2c_adapter *adap)
  162. {
  163. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  164. }
  165. static const struct i2c_algorithm ocores_algorithm = {
  166. .master_xfer = ocores_xfer,
  167. .functionality = ocores_func,
  168. };
  169. static struct i2c_adapter ocores_adapter = {
  170. .owner = THIS_MODULE,
  171. .name = "i2c-ocores",
  172. .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
  173. .algo = &ocores_algorithm,
  174. };
  175. static int __devinit ocores_i2c_probe(struct platform_device *pdev)
  176. {
  177. struct ocores_i2c *i2c;
  178. struct ocores_i2c_platform_data *pdata;
  179. struct resource *res, *res2;
  180. int ret;
  181. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  182. if (!res)
  183. return -ENODEV;
  184. res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  185. if (!res2)
  186. return -ENODEV;
  187. pdata = (struct ocores_i2c_platform_data*) pdev->dev.platform_data;
  188. if (!pdata)
  189. return -ENODEV;
  190. i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
  191. if (!i2c)
  192. return -ENOMEM;
  193. if (!request_mem_region(res->start, res->end - res->start + 1,
  194. pdev->name)) {
  195. dev_err(&pdev->dev, "Memory region busy\n");
  196. ret = -EBUSY;
  197. goto request_mem_failed;
  198. }
  199. i2c->base = ioremap(res->start, res->end - res->start + 1);
  200. if (!i2c->base) {
  201. dev_err(&pdev->dev, "Unable to map registers\n");
  202. ret = -EIO;
  203. goto map_failed;
  204. }
  205. i2c->regstep = pdata->regstep;
  206. i2c->clock_khz = pdata->clock_khz;
  207. ocores_init(i2c);
  208. init_waitqueue_head(&i2c->wait);
  209. ret = request_irq(res2->start, ocores_isr, 0, pdev->name, i2c);
  210. if (ret) {
  211. dev_err(&pdev->dev, "Cannot claim IRQ\n");
  212. goto request_irq_failed;
  213. }
  214. /* hook up driver to tree */
  215. platform_set_drvdata(pdev, i2c);
  216. i2c->adap = ocores_adapter;
  217. i2c_set_adapdata(&i2c->adap, i2c);
  218. i2c->adap.dev.parent = &pdev->dev;
  219. /* add i2c adapter to i2c tree */
  220. ret = i2c_add_adapter(&i2c->adap);
  221. if (ret) {
  222. dev_err(&pdev->dev, "Failed to add adapter\n");
  223. goto add_adapter_failed;
  224. }
  225. return 0;
  226. add_adapter_failed:
  227. free_irq(res2->start, i2c);
  228. request_irq_failed:
  229. iounmap(i2c->base);
  230. map_failed:
  231. release_mem_region(res->start, res->end - res->start + 1);
  232. request_mem_failed:
  233. kfree(i2c);
  234. return ret;
  235. }
  236. static int __devexit ocores_i2c_remove(struct platform_device* pdev)
  237. {
  238. struct ocores_i2c *i2c = platform_get_drvdata(pdev);
  239. struct resource *res;
  240. /* disable i2c logic */
  241. oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
  242. & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
  243. /* remove adapter & data */
  244. i2c_del_adapter(&i2c->adap);
  245. platform_set_drvdata(pdev, NULL);
  246. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  247. if (res)
  248. free_irq(res->start, i2c);
  249. iounmap(i2c->base);
  250. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  251. if (res)
  252. release_mem_region(res->start, res->end - res->start + 1);
  253. kfree(i2c);
  254. return 0;
  255. }
  256. #ifdef CONFIG_PM
  257. static int ocores_i2c_suspend(struct platform_device *pdev, pm_message_t state)
  258. {
  259. struct ocores_i2c *i2c = platform_get_drvdata(pdev);
  260. u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
  261. /* make sure the device is disabled */
  262. oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
  263. return 0;
  264. }
  265. static int ocores_i2c_resume(struct platform_device *pdev)
  266. {
  267. struct ocores_i2c *i2c = platform_get_drvdata(pdev);
  268. ocores_init(i2c);
  269. return 0;
  270. }
  271. #else
  272. #define ocores_i2c_suspend NULL
  273. #define ocores_i2c_resume NULL
  274. #endif
  275. /* work with hotplug and coldplug */
  276. MODULE_ALIAS("platform:ocores-i2c");
  277. static struct platform_driver ocores_i2c_driver = {
  278. .probe = ocores_i2c_probe,
  279. .remove = __devexit_p(ocores_i2c_remove),
  280. .suspend = ocores_i2c_suspend,
  281. .resume = ocores_i2c_resume,
  282. .driver = {
  283. .owner = THIS_MODULE,
  284. .name = "ocores-i2c",
  285. },
  286. };
  287. static int __init ocores_i2c_init(void)
  288. {
  289. return platform_driver_register(&ocores_i2c_driver);
  290. }
  291. static void __exit ocores_i2c_exit(void)
  292. {
  293. platform_driver_unregister(&ocores_i2c_driver);
  294. }
  295. module_init(ocores_i2c_init);
  296. module_exit(ocores_i2c_exit);
  297. MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
  298. MODULE_DESCRIPTION("OpenCores I2C bus driver");
  299. MODULE_LICENSE("GPL");