tlb_nohash_low.S 3.7 KB

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  1. /*
  2. * This file contains low-level functions for performing various
  3. * types of TLB invalidations on various processors with no hash
  4. * table.
  5. *
  6. * This file implements the following functions for all no-hash
  7. * processors. Some aren't implemented for some variants. Some
  8. * are inline in tlbflush.h
  9. *
  10. * - tlbil_va
  11. * - tlbil_pid
  12. * - tlbil_all
  13. * - tlbivax_bcast (not yet)
  14. *
  15. * Code mostly moved over from misc_32.S
  16. *
  17. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  18. *
  19. * Partially rewritten by Cort Dougan (cort@cs.nmt.edu)
  20. * Paul Mackerras, Kumar Gala and Benjamin Herrenschmidt.
  21. *
  22. * This program is free software; you can redistribute it and/or
  23. * modify it under the terms of the GNU General Public License
  24. * as published by the Free Software Foundation; either version
  25. * 2 of the License, or (at your option) any later version.
  26. *
  27. */
  28. #include <asm/reg.h>
  29. #include <asm/page.h>
  30. #include <asm/cputable.h>
  31. #include <asm/mmu.h>
  32. #include <asm/ppc_asm.h>
  33. #include <asm/asm-offsets.h>
  34. #include <asm/processor.h>
  35. #if defined(CONFIG_40x)
  36. /*
  37. * 40x implementation needs only tlbil_va
  38. */
  39. _GLOBAL(_tlbil_va)
  40. /* We run the search with interrupts disabled because we have to change
  41. * the PID and I don't want to preempt when that happens.
  42. */
  43. mfmsr r5
  44. mfspr r6,SPRN_PID
  45. wrteei 0
  46. mtspr SPRN_PID,r4
  47. tlbsx. r3, 0, r3
  48. mtspr SPRN_PID,r6
  49. wrtee r5
  50. bne 1f
  51. sync
  52. /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is
  53. * clear. Since 25 is the V bit in the TLB_TAG, loading this value
  54. * will invalidate the TLB entry. */
  55. tlbwe r3, r3, TLB_TAG
  56. isync
  57. 1: blr
  58. #elif defined(CONFIG_8xx)
  59. /*
  60. * Nothing to do for 8xx, everything is inline
  61. */
  62. #elif defined(CONFIG_44x)
  63. /*
  64. * 440 implementation uses tlbsx/we for tlbil_va and a full sweep
  65. * of the TLB for everything else.
  66. */
  67. _GLOBAL(_tlbil_va)
  68. mfspr r5,SPRN_MMUCR
  69. rlwimi r5,r4,0,24,31 /* Set TID */
  70. /* We have to run the search with interrupts disabled, otherwise
  71. * an interrupt which causes a TLB miss can clobber the MMUCR
  72. * between the mtspr and the tlbsx.
  73. *
  74. * Critical and Machine Check interrupts take care of saving
  75. * and restoring MMUCR, so only normal interrupts have to be
  76. * taken care of.
  77. */
  78. mfmsr r4
  79. wrteei 0
  80. mtspr SPRN_MMUCR,r5
  81. tlbsx. r3, 0, r3
  82. wrtee r4
  83. bne 1f
  84. sync
  85. /* There are only 64 TLB entries, so r3 < 64,
  86. * which means bit 22, is clear. Since 22 is
  87. * the V bit in the TLB_PAGEID, loading this
  88. * value will invalidate the TLB entry.
  89. */
  90. tlbwe r3, r3, PPC44x_TLB_PAGEID
  91. isync
  92. 1: blr
  93. _GLOBAL(_tlbil_all)
  94. _GLOBAL(_tlbil_pid)
  95. li r3,0
  96. sync
  97. /* Load high watermark */
  98. lis r4,tlb_44x_hwater@ha
  99. lwz r5,tlb_44x_hwater@l(r4)
  100. 1: tlbwe r3,r3,PPC44x_TLB_PAGEID
  101. addi r3,r3,1
  102. cmpw 0,r3,r5
  103. ble 1b
  104. isync
  105. blr
  106. #elif defined(CONFIG_FSL_BOOKE)
  107. /*
  108. * FSL BookE implementations. Currently _pid and _all are the
  109. * same. This will change when tlbilx is actually supported and
  110. * performs invalidate-by-PID. This change will be driven by
  111. * mmu_features conditional
  112. */
  113. /*
  114. * Flush MMU TLB on the local processor
  115. */
  116. _GLOBAL(_tlbil_pid)
  117. _GLOBAL(_tlbil_all)
  118. #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
  119. MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
  120. li r3,(MMUCSR0_TLBFI)@l
  121. mtspr SPRN_MMUCSR0, r3
  122. 1:
  123. mfspr r3,SPRN_MMUCSR0
  124. andi. r3,r3,MMUCSR0_TLBFI@l
  125. bne 1b
  126. msync
  127. isync
  128. blr
  129. /*
  130. * Flush MMU TLB for a particular address, but only on the local processor
  131. * (no broadcast)
  132. */
  133. _GLOBAL(_tlbil_va)
  134. mfmsr r10
  135. wrteei 0
  136. slwi r4,r4,16
  137. mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
  138. tlbsx 0,r3
  139. mfspr r4,SPRN_MAS1 /* check valid */
  140. andis. r3,r4,MAS1_VALID@h
  141. beq 1f
  142. rlwinm r4,r4,0,1,31
  143. mtspr SPRN_MAS1,r4
  144. tlbwe
  145. msync
  146. isync
  147. 1: wrtee r10
  148. blr
  149. #elif
  150. #error Unsupported processor type !
  151. #endif